| Commit message (Collapse) | Author | Age | Files | Lines |
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in the chipset tag for establishing interrupts now takes a struct cpu_info *.
The normal pci_intr_establish() macro passes NULL as ci, which indicates that
the primary CPU is to be used.
The PCI controller drivers can then simply pass the ci on to our arm64/armv7
interrupt establish "framework".
Prompted by dlg@
ok kettenis@
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accessing PCI config space on some cards. okay kettenis@
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* Enable gen2 link training when the dtb is configured with
max-link-speed = <2>;
* Workaround a rockchip bug where Target Link Speed is not set when
PCIE_CLIENT_PCIE_GEN_SEL_2 is configured
* Wait for LTSSM L0 state after initial link training to ensure gen2
link training does not start too early
okay kettenis@
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implements mapping of MSI and MSI-X interrupts with new generic functions.
Fixes a use-after-free in sone PCI device drivers that call pci_intr_string(9)
after pci_intr_establish(9).
ok deraadt@
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ok patrick@
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ok kettenis@
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arm_intr_* prefix with fdt_intr_*.
ok kettenis@
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rkpcie(4).
ok patrick@
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Linux kernel.
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bus numbers on the "bus-range" property. Create outbound translations based
on the "ranges" property.
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now it cheats when setting up an interrupt handler. This cheat only works
because it currently effectively only supports a single device. But the
cheat works well enough to support the Firefly SATA adapter board.
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