| Commit message (Collapse) | Author | Age | Files | Lines |
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Pointed out by Artturi Alm.
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arm_intr_* prefix with fdt_intr_*.
ok kettenis@
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ok patrick@
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Marvell controller. The difference is essentially register offsets
and a clock divider calculation based on a power of two. Also this
particular hardware needs a delay after sending a stop and before
reading the status register since apparently the data doesn't
propagate fast enough. This makes sxitwi(4) work on the Marvell
Armada 38x.
ok kettenis@
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the rate of the parent clock. If the "clock-frequency" property isn't
present, use the default standard mode clock of 100kHz.
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read or write to aregister. There is also no reason to wait after
transmitting a STOP since the controller will wait until the bus is free
when transmitting the next START. Based on a diff by Stephen Graf.
Also remove the interrupt code; it doesn't work on the newer variants of
the device. The functionality will be put back in a future commit.
ok patrick@
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From Artturi Alm
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above and enable the driver on arm64.
From Artturi Alm. Tested by Stephen Graf.
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it a logical OR intead of a binary OR.
From Artturi Alm
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several Allwinner SoCs. From Artturi Alm, based on code from NetBSD.
Also add axppmic(4), a driver for the AXP209 i2c PMIC, which provides
power down support. Written by Artturi Alm.
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