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* set the scsi status to SCSI_OKdlg2016-04-141-1/+2
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* allocate dma memory for ccbs to use as prpe listsdlg2016-04-141-2/+19
| | | | | | prpe is short for Physical Region Page Entry. this is where long lists of dma regions go when they wont fit into a submission queue entry.
* dont attach if the min nvme page size is bigger than the cpu page sizedlg2016-04-141-4/+8
| | | | | | | | | | | nvme and the host cpu need to agree on the page size because its the implicit size of the elements in the chips scatter gather lists. if the min nvme size is greater than the cpus page size then we cant guarantee that io buffers are contig for nvme pages. nvme 1.1 provides an alternative sgl mechanism, so if this really becomes a problem in the future we can fix it on 1.1 and later devices.
* dont complete scsi writes twicedlg2016-04-141-2/+2
| | | | it ends up being a use after free, which disagrees with the midlayer.
* WAITOK for the dmamap create for ccbs toodlg2016-04-141-2/+2
| | | | again, only called during autoconf which is a kind of process context.
* cut the memory for io buffers up into page sized chunksdlg2016-04-141-2/+2
| | | | | | | | | | | nvme 1.0 does not use conventional scatter gather lists of address+length pairs. instead, it simply expects a list of page addresses. this should be ok if we only feed it single VA chunks which map directly to only whole physical pages. nvme 1.1 introduced another scather format, but still accepts the 1.0 format too. we'll stick to the 1.0 format so we can support 1.0 devs.
* check both the admin and io queue for completions in the interrupt handlerdlg2016-04-141-2/+8
| | | | this means we'll notice io completions.
* dont put names in arguments.dlg2016-04-141-2/+2
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* implement handling of scsi reads and writesdlg2016-04-131-1/+126
| | | | | | | | | | | | ive only tested reads, and not very big ones. nvme 1.0 has a very stupid/naive idea about what constitutes a scatter gather list. it assumes io is in whole pages in memory, but i dont know if that is true in our kernel. this could be cleaned up a bit, and it currently runs with a single opening for the whole scsi layer and a bunch of magic values for the size and number of the io queues.
* enable interrupts before attaching the scsibusdlg2016-04-131-1/+3
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* allocate a queue for io commands and tell the chip about it.dlg2016-04-131-1/+14
| | | | this is necessary to run reads and writes against the device.
* nvme_q_create() issues the commands to tell the chip about io queuesdlg2016-04-131-1/+46
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* stub out handling of TEST_UNIT_READY, PREVENT_ALLOW, and START_STOPdlg2016-04-131-1/+8
| | | | at the moment this just pretends the commands completed fine.
* implement handling of scsi read capacity commandsdlg2016-04-131-2/+78
| | | | read cap 16 claims the devices are thin.
* implement basic scsi inquiry handlingdlg2016-04-131-1/+59
| | | | | most values are as per the nvm to scsi mapping guide. this doesnt do vpd at all, so no devids or serial numbers just yet.
* implement the guts of the scsi probe and free functiondlg2016-04-131-2/+52
| | | | | | | | probe issues a namespace identify against the "target". if it works it stashes a copy of the info, otherwise it tells the midlayer to avoid it. free gets rid of the stashed info.
* wire up the scsi midlayer. scsibus should appear after this.dlg2016-04-131-1/+16
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* allocate an array of things to hold info about namespacesdlg2016-04-131-1/+4
| | | | so far the only useful info is namespace identify info
* stash the controller identify and number of namespaces in the softc.dlg2016-04-131-3/+7
| | | | | the nn is used to size the scsi bus, and the controller identify is used to build responses for various scsi commands.
* provide an scsi_adapter and stub functions for emulation to sit indlg2016-04-131-1/+33
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* nvme_sqe_fill will post a copy of an sqe from a callerdlg2016-04-131-1/+11
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* poll for command completion on the cqe itll be of calling nvme_intrdlg2016-04-131-2/+2
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* make nvme_poll return the flags from the completion queue entrydlg2016-04-131-2/+2
| | | | it's still 0 on success, but is the actual bits rather than a mashup of it
* keep track of the queue id in nvme_queue.dlg2016-04-131-1/+2
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* rename idx to id in nvme_q_allocdlg2016-04-131-5/+5
| | | | make it a u_int16_t like the hw while here.
* nvme_dmamem_alloc runs in autoconf or process context, so it can sleepdlg2016-04-131-6/+6
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* shuffle attach so we read chip capabilities before operating on itdlg2016-04-121-9/+10
| | | | most importantly this gets the proper timeout for chip enables/disables.
* when enabling the controller, wait till CSTS.RDY lights up.dlg2016-01-151-6/+6
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* feng shui.dlg2016-01-151-44/+36
| | | | | dont need a billion tabs for the function prototypes. just some akward line wrappings.
* handle the version register like ahci.dlg2016-01-151-5/+18
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* wrap up dma syncs for the whole mapping.dlg2016-01-151-13/+19
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* shuffle when the cid is set on submission queue entries so its afterdlg2014-11-041-3/+2
| | | | when the caller fills the entry.
* when reading the completion queue, it helps to write where we've read updlg2014-11-041-2/+2
| | | | | | | to to the completion queue head doorbell instead of the submission queue tail doorbell. this lets us submit more than one command to the chip.
* dont leak a ccb in identifydlg2014-09-121-1/+3
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* fix some format string issuesdlg2014-09-121-6/+6
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* Some reallocarray() use; review Jean-Philippe Ouellet, patrick keshishianderaadt2014-07-131-2/+2
| | | | ok tedu
* add a size argument to free. will be used soon, but for now default to 0.tedu2014-07-121-6/+6
| | | | after discussions with beck deraadt kettenis.
* set ourselves up to respect the max data transfer size.dlg2014-04-161-4/+11
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* have nvme_poll return the status bigs from the completion ringdlg2014-04-161-31/+34
| | | | | | | | | | | entry. if i ever implement timeouts ill use high bits in the int or the phase bit to indicate non chip related errors. a successful chip status conveniently maps to 0. how handy. this lets me move the completion handling for the controller identification commands back into the caller. at the moment im just printing out controller and firmware details like we do on mfi/mpii/mfii.
* i wanted to work on this in the tree so i could commit lots of smalldlg2014-04-151-28/+335
| | | | | | | | | | | steps, but unfortunately the next step after "talk to the chips registers" was "get command queues working" which ended up being a huge amount of plumbing. anyway, this lets me successfully run an identify controller command against the chip and should be cut up the right way to be usable for io command submissions. will need to think about how to avoid overflowing rings though.
* start working on a driver for non volatile memory express controllers.dlg2014-04-121-0/+377
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