wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add hibernate support for nvme(4). This creates a separate IO queue that is	jmatthew	2017-05-29	1	-1/+5
\| \| \| \| \| \| \| \|	only active during hibernation, preallocating the the submission and completion queues during attach as they need to be page-aligned. tested on an x270 that successfully hibernates now. ok dlg@
*	nvme: Add suspend/resume code	sf	2017-05-27	1	-1/+3
\| \| \| \| \| \| \|	Based on an initial patch by ehrhardt@ . Thanks to claudio@ for testing and deraadt@ for advice. "go ahead" deraadt@
*	mask and unmask the interrupt source in an intx specific intr handler.	dlg	2016-10-25	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	it seems devices using levelled intx interrupts need to explicitely ack interrupts by masking and unmasking the source around the completion ring handling. without this completions can be lost, which in turn causes long (permanent?) stalls in the block layer under heavy write load. ive experienced this problem with an intel nvme part that only has intx and msix support. because we dont support msix yet we only use intx on it. it appeared to lock up before this fix. this has been tested on both that intel board and a samsung with msi. this fix was based on work found in code by nonaka
*	provide a shutdown hook that follows the procedure in the docs	dlg	2016-04-14	1	-1/+7
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*	tabs, not spaces	dlg	2016-04-14	1	-3/+3
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*	wire up the scsi midlayer. scsibus should appear after this.	dlg	2016-04-13	1	-1/+4
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*	allocate an array of things to hold info about namespaces	dlg	2016-04-13	1	-1/+6
\| \| \| \|	so far the only useful info is namespace identify info
*	stash the controller identify and number of namespaces in the softc.	dlg	2016-04-13	1	-1/+6
\| \| \| \| \|	the nn is used to size the scsi bus, and the controller identify is used to build responses for various scsi commands.
*	make a place for q_id to go	dlg	2016-04-13	1	-1/+2
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*	i wanted to work on this in the tree so i could commit lots of small	dlg	2014-04-15	1	-4/+32
\| \| \| \| \| \| \| \| \| \| \|	steps, but unfortunately the next step after "talk to the chips registers" was "get command queues working" which ended up being a huge amount of plumbing. anyway, this lets me successfully run an identify controller command against the chip and should be cut up the right way to be usable for io command submissions. will need to think about how to avoid overflowing rings though.
*	start working on a driver for non volatile memory express controllers.	dlg	2014-04-12	1	-0/+58