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* Nuke unused struct scsi_link members of adapter softc's where thekrw2020-07-221-3/+1
| | | | driver successfully compiles on one or more of amd64, i386, hppa.
* False alarm, back it goes. Managed to mangle my kernel build directorykrw2020-07-121-2/+1
| | | | | somehow. Cleaning it out and config/compile from scratch and all seems well.
* Revert previous. Broke something somehow.krw2020-07-111-1/+2
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* Garbage collect unused nvme_softc member "sc_scsibus".krw2020-07-111-2/+1
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* sparc64 issue being identified and removed, reapply r1.73:krw2020-03-151-1/+2
| | | | "Bump nvme(4) max physio() i/o size to 128K"
* Revert nvme back to last working commit for sparc64.kmos2020-03-151-2/+1
| | | | | | The coverity-related diff breaks sparc64's ability to read the disk. ok deraadt
* Bump nvme(4) max physio() i/o size to 128K.krw2020-03-131-1/+2
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* Ooops. Need both files.krw2020-03-101-2/+2
| | | | | | | | | sgl (scatter gather list) and prpl (physical region page list) are two different things in the NVMe world. Only the latter is currently implemented in nvme(4) so rename sc_max_sgl to sc_max_prpl to reflect this. No functional change.
* Use ffs() on sc_mps, removing need for sc_mps_bits. Replace ffs(64)-1krw2020-03-011-2/+1
| | | | | | | | | and ffs(16)-1 with the constant results (i.e. 6 and 4). Add comments to clarify use of these constants. Net result, one less invocation of ffs(), softc smaller by one u_int, and less potential confusion over 'mps'. No functional change.
* Add hibernate support for nvme(4). This creates a separate IO queue that isjmatthew2017-05-291-1/+5
| | | | | | | | only active during hibernation, preallocating the the submission and completion queues during attach as they need to be page-aligned. tested on an x270 that successfully hibernates now. ok dlg@
* nvme: Add suspend/resume codesf2017-05-271-1/+3
| | | | | | | Based on an initial patch by ehrhardt@ . Thanks to claudio@ for testing and deraadt@ for advice. "go ahead" deraadt@
* mask and unmask the interrupt source in an intx specific intr handler.dlg2016-10-251-1/+2
| | | | | | | | | | | | | | | it seems devices using levelled intx interrupts need to explicitely ack interrupts by masking and unmasking the source around the completion ring handling. without this completions can be lost, which in turn causes long (permanent?) stalls in the block layer under heavy write load. ive experienced this problem with an intel nvme part that only has intx and msix support. because we dont support msix yet we only use intx on it. it appeared to lock up before this fix. this has been tested on both that intel board and a samsung with msi. this fix was based on work found in code by nonaka
* provide a shutdown hook that follows the procedure in the docsdlg2016-04-141-1/+7
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* tabs, not spacesdlg2016-04-141-3/+3
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* wire up the scsi midlayer. scsibus should appear after this.dlg2016-04-131-1/+4
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* allocate an array of things to hold info about namespacesdlg2016-04-131-1/+6
| | | | so far the only useful info is namespace identify info
* stash the controller identify and number of namespaces in the softc.dlg2016-04-131-1/+6
| | | | | the nn is used to size the scsi bus, and the controller identify is used to build responses for various scsi commands.
* make a place for q_id to godlg2016-04-131-1/+2
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* i wanted to work on this in the tree so i could commit lots of smalldlg2014-04-151-4/+32
| | | | | | | | | | | steps, but unfortunately the next step after "talk to the chips registers" was "get command queues working" which ended up being a huge amount of plumbing. anyway, this lets me successfully run an identify controller command against the chip and should be cut up the right way to be usable for io command submissions. will need to think about how to avoid overflowing rings though.
* start working on a driver for non volatile memory express controllers.dlg2014-04-121-0/+58
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