| Commit message (Collapse) | Author | Age | Files | Lines |
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e1000e driver (which enables MSI as well), leaving everything handled by the
old Linux e1000 driver (which doesn't enable MSI) use legacy interrupts.
tested by many; ok jsg@
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make em_write_pci_cfg() do a proper read/modify/write cycle, to avoid changing
the neighbouring 16 bits. Also remove the comment in em_pci_set_mwi() and
em_pci_clear_mwi(); writting 0 to the status bits in the command/status word
is the right thing to do. Fixes a panic on sparc64 and other strict alignment
architectures.
ok deraadt@
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From Laurence Tratt.
ok claudio@ deraadt@
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ok claudio@
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rather than looping over them until it runs out of work to do.
looping in the isr is bad for several reasons:
firstly, the chip does interrupt mitigation so you have a
decent/predictable amount of work to do in the isr. your first loop
will do that chunk of work (ie, it pulls off 50ish packets), and
then the successive looping aggressively pull one or two packets
off the rx ring. these extra loops work against the benefit that
interrupt mitigation provides.
bus space reads are slow. we should avoid doing them where possible
(but we should always do them when necessary).
doing the loop 5 times per isr works against the mclgeti semantics.
it knows a nic is busy and therefore needs more rx descriptors by
watching to see when the nic uses all of its descriptors between
interrupts. if we're aggressively pulling packets off by looping
in the isr then we're skewing this check.
ok deraadt@ claudio@
this is like src/sys/dev/pci/if_ix.c r1.50.
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and it does not exist at all on newer hardware so only map
it on those types we are interested in.
Fixes "PRO/1000 PT (82575EB)" for Sylvain Desveaux and will
also be required for at least 82580.
ok claudio@
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ok claudio krw
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ok claudio@
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a global em_display_debug_stats variable.
OK mcbride, matthew, deraadt, henning.
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RAMDISKA breathe a bit better.
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ok jsg@
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traversal code to suspend/resume
ok oga kettenis blambert
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DVACT_SUSPEND, therefore DVACT_QUIECE can do standard sleeping operations
to get ready.
Discussed quite a while back with kettenis and jakemsr, oga suddenly needed
it as well and wrote half of it, so it was time to finish it.
proofread by miod.
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job of taking the chip up and down.
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and move it back to the location where it was before rev. 1.239, while
keeping the horrible override for em_pchlan. From Holger Mikolon.
ok jsg@, deraadt@
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a bug in the initial EP80579 commit from dms that was exposed by gcc4.
Lots of help tracking down the block of code at fault from
Mike Belopuhov, but I spotted the problem in the end :)
ok kettenis@ deraadt@
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stripping works insertion seems to have trouble in certain conditions,
which needs to be fixed before we want to enable hardware support for this.
ok deraadt@
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we do upon resume and failing to cope with the fact that the state has changed
under our feet. Fixes watchdog timeout issues in at least one case.
ok deraadt@, tested by thib@
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ok claudio@
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all the workarounds but is enough to make things run at
faster than 10 Mbit speeds, though these aren't always
reflecting in ifmedia properly just yet.
ok claudio@
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from Laurence Tratt based on FreeBSD code. Confirmed to
work on lenovo t410i/t410s/x201.
Desktop machines with PCH tend to be paired with a 82578 PHY,
these will at some point be supported but not yet.
ok claudio@
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in the FreeBSD driver.
ok claudio@
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based on information in the linux driver.
ok claudio@
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effectively lose receive descriptors each time we reset the interface, until
we run out of descriptors and panic. Should fix the "em_rxeof: NULL mbuf in
slot 0 (nrx 256, filled 255)" panic on em(4).
ok jsing@ (for the em(4) bits), jsg@
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recieved packets.
fix from intel drivers, via Brad
ok claudio@, deraadt@
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ok deraadt@
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ok deraadt@
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tested by deraadt@ and me
ok deraadt@
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basicly 82545, but the PHY's are separated form the chip and they are accessed
through a special PCI device called GCU which has the MDIO interface. Since
there is no direct relationship between MAC and PHY, so for the moment they
are assigned to each other the way its done on Axiomtek NA-200, that was
danted to us by them.
This also adds a device driver for the GCU.
tested by me on Axiomtek board
reviewed by claudio@, kettenis@, deraadt@
'commit that as is' deraadt@
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No other functional change expected. ok dms
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introduced in rev. 1.204. from brad
ok by claudio@
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ok by claudio@
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go messing with the maps. Only affects my disconnectable em(4).
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seems to be fixed, thanks to tests done by mpf at mailq dot de.
Also support for older fiber cards that have no PHY seems to be working,
thanks to claudio@
The code includes all the changes that i backed out, plus two tweaks:
1. em_detect_gig_phy() gets called in em_setup_link() instead of
em_copper_link_preconfig(), this enables phy detection on fiber cards.
2. em_detect_gig_phy() gets a condition to look for old fiber cards, that
have no PHY.
ok by claudio@, prodded by deraadt@
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It seems that new phy detection code breaks
some of the newer fiber cards.
found by Brad, ok by claudio@
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ok dlg@
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running out of mbufs for rx rings.
if the system low watermark is lower than a rx rings low watermark,
we'll never send a packet up the stack, we'll always recycle it.
found by thib@ on a bge
sadface
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to free some for use on the rx rings on network cards.
this modifies m_cluncount to advise callers when we're in such a
situation, and makes them responsible for freeing up the cluster
for allocation by MCLGETI later.
fixes an awesome lockup with sis(4) henning has been experiencing.
this is not the best fix, but it is better than the current situation.
yep deraadt@ tested by henning@
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we now know the interface has already been stopped
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reducing the amount of splnet/splx dancing required.. especially in the
worst case (of m_cldrop)
ok dlg kettenis damien
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with help from Brad. OK deraadt@
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some newer ICH* chips. All the hard work done by Dariusz Swiderski
sfires (at) sfires.net, tested by myself, sthen@ and many more.
Eyeballed and OK dlg@ kettenis@
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same. Not sure if the 82576 is 100% compatible to the 82575 but only when
enabled it will be possible to test them. OK jsg@
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or less out of the box if one explicitly enables the TX DMA engine.
Only tested with 82575, people with 82576 cards may contact me for a diff.
OK kettenis@
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