wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix support for additional I2C busses in piixpm(4) for older SB800 SMBus	claudio	2020-01-21	1	-2/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	controllers. Devices where SB800_PMREG_SMB0SELEN returns 0 will only use the first port. Also clean up the PCI_PRODUCT_AMD_HUDSON2_SMB detection a bit more. The PCI ID 1022:780b is used by AMD Bolton FCH and AMD Family 16h model 30h-3fh. The problem is the former uses old register layout while the latter uses the new FCH layout. Make sure AMD Bolton FCH uses the old code path. Finally fix a confusion about the IRQ / SMI detection. The logic was reversed since if the bit is 0 then SMI is used. This should fix attaching sensors 4 times on old AMD machines. OK kettenis@
*	Update piixpm(4) to support newer AMD chips like some Hudson-2 and	claudio	2019-12-16	1	-1/+10
\| \| \| \| \| \|	especially KERNCZ (AMD FCH SMBus). Additionally this also implements multi-bus support for SB800, Hudson-2 and KERNCZ. Tested by many. Input & OK kettenis@
*	Add support for AMD SB800, where the SMBus control registers have been hidden	kettenis	2011-05-28	1	-1/+14
\| \| \| \| \| \|	away. Based on a diff from Bryan Steele. ok deraadt@
*	Correct interrupt type check. Pointed out by kettenis@, thanks.	grange	2006-01-03	1	-1/+4
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*	Use corrent size for io mapping. Problem reported by	grange	2005-12-28	1	-1/+3
\| \| \| \|	steve.shockley@shockley.net.
*	Move all PIIX register definitions to a separate file.	grange	2005-12-25	1	-0/+62