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path: root/sys/dev/usb/xhci.c (follow)
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* Do not consider the pipe as halted if the device is gone.mpi2019-06-131-1/+3
| | | | Analysed by and ok claudio@
* Fix NULL check with wrong pointer in xhci_event_xfer_isoc(); CID 1480287stsp2019-05-211-2/+2
| | | | ok ratchov@
* Decrease verbosity when XHCI_DEBUG is defined.ratchov2019-04-301-3/+3
| | | | ok mpi
* Handle missed service errors, specific to isochronous transfers.ratchov2019-04-101-1/+52
| | | | | | | | | After each MSE, ensuire usbd_complete_transfer() is called for each missed transfer, for which there's no transfer completion event. Fixes crashes and deadlocks in upper layers caused by the missing completion. ok deraadt, patrick; help from mpi, patrick, gmlocker
* Since an isoc endpoint never halts, move to remaining error handlingmglocker2019-03-171-58/+48
| | | | | | code in xhci_event_xfer() to the generic handler function. suggested and ok mpi@
* Move the handler code in the xhci_event_xfer() switch case in two separatemglocker2019-03-171-40/+66
| | | | | | | | functions for isoc and !isoc xfers. Suggested by mpi@. ok patrick@, stsp@
* Remove obsolete semicolon at end of case switch.mglocker2019-03-171-2/+2
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* Merge the duplicate code to handle isoc SHORT and SUCCESS xfer eventsmglocker2019-03-161-83/+54
| | | | | | to one single function. ok mpi@
* Improve and enable isochronous transfers in xhci(4). Each isochronouspatrick2019-03-151-58/+193
| | | | | | | | | | | | | | | | frame has to be enqueued as Transfer Descriptor. This means each frame starts with an isoch TRB and may also contain further normal TRBs. The TDs each throw at least one interrupt for a successful completion or possibly more in case of a short xfer. We have to account the amount of data transfered for each frame using the completion of the matching TD and its TRBs. Thanks to stsp@ for initiating this, and many more thanks to mglocker@ for reworking and cleaning up my initial diff. Further improvements can happen in-tree now. Tested by mglocker@, phessler@ and stsp@ ok mglocker@, stsp@
* The max burst size that is encoded in wMaxPacketSize is zero based,patrick2019-03-151-3/+3
| | | | | | | as in: Since there's always one transfer, 0 means 1. Thus we have to add 1 (not OR) to get to the desired number. ok mglocker@ mpi@ stsp@
* Fix typo in debug print: wih -> withpatrick2019-03-121-3/+3
| | | | ok mpi@
* Add missing bus powered bit, from aalm@mpi2019-03-111-2/+2
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* Since ring->index points to the next free slot, once we reach index zeropatrick2019-03-011-14/+17
| | | | | | | | | we know that the last non-link TRB has been written and we can look at the flags to set the chain bit in the link TRB. Since we will now toggle the cycle bit on the first TRB of a ring, set it on the ring reset. Tested by jcs@, jsg@ and visa@ "commit it" jcs@
* Make xhci_ring_produce() check the previous TRB to find out if itpatrick2019-02-271-72/+78
| | | | | | | | | | | | | needs the Chain Bit set or not instead of using the last parameter, which is used to mark the last TRB in a USB transfer, not in a TD. To make that work we need to setup the recently acquired TRB before calling xhci_xfer_get_trb() the next time. Thus setting up the initial TRB has to happen right away. To kick the transfer off we simply flip the toggle bit on the first TRB right at the end. Fixes regression for jcs@, dhill@ and stsp@ Initially discussed with mpi@ ok stsp@
* Transfers that span multiple TRBs which wrap around the ring andpatrick2019-02-211-5/+9
| | | | | | | | | | | | thus have the Link TRB inbetween must have the Chain Bit set in the Link TRB. Otherwise xHCI controllers might think that the transfer ends at that point. Fixes an issue that was most prominently seen as Invalid CSW error when using umass0 on octeon and i.MX8M. Tested by visa@ ok mpi@
* Print xhci version in hex, from sc.dying at gmail.mpi2019-02-011-2/+2
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* If we cannot stop the endpoint when aborting a transfer assume thatmpi2018-09-061-2/+7
| | | | | | | | the device is gone and give back the descriptor to the stack. Without this usbd_abort_pipe() could end up in an infinite loop. Issue reported by Tom Murphy.
* Serialize synchronous commands with a rwlock.mpi2018-09-051-8/+34
| | | | | | | Prevent triggering an assert if two drivers try to submit a command at the same time. Issue reported by Tom Murphy.
* typos, from Michael W. Bombardieri.mpi2018-07-161-5/+5
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* Add bus DMA barriers to ensure the hardware does not see a TRB cycle bitvisa2018-05-131-5/+19
| | | | | | flip before the rest of the TRB is updated. OK dlg@, pirofti@, mpi@
* Print xHCI revision in dmesg.mpi2018-05-081-7/+4
| | | | ok patrick@, kettenis@
* Unsigned values are always >= 0, fix Coverity 1468443.mpi2018-04-291-2/+2
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* Print more debug informations in the event xfer handler.mpi2018-04-281-5/+10
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* Introduce an helper function to extract endpoint's max burst value.mpi2018-04-271-19/+72
| | | | | | | | | Use this helper to calculate the Transfer Burst Count (TBC) and Transfer Last Burst Packet Count (TLBPC) required for isochronous support. Note that SS companion descriptors are still not read. While here print the ETE and IST values in debug mode.
* Print index as unsigned.mpi2018-04-271-5/+5
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* Fix an off-by-one in xhci_xfer_tdsize().mpi2018-04-271-7/+5
| | | | | | While here use UE_GET_SIZE() coherently. ok pirofti@, stsp@, visa@
* Reduce differences between isoch & bulk/intr routines.mpi2018-04-261-21/+20
| | | | ok stsp@
* Follows section 6.2.3.6 to compute endpoint interval.mpi2018-04-261-32/+58
| | | | ok stsp@
* Add support for isochronous transfers to xhci(4).stsp2017-09-081-25/+202
| | | | | | | | | This is just a step forward which allows further progress to happen in-tree. The isochronous code path remains disabled for now. Playing audio over xhci(4) does not work properly yet, and I haven't even tested video input. Based on a work-in-progress diff by mpi@ from 2015. ok mpi@
* Revert previous: "Fix a remaining length miscalculation in xhci(4)."stsp2017-09-041-2/+2
| | | | It made one of my machines get stuck during boot.
* Fix a remaining length miscalculation in xhci(4).stsp2017-09-011-2/+2
| | | | | | | | | | | | | Each TRB contains a remaining TD size, which allows hardware to tell whether additional TRBs follow within the current transfer without reading ahead. The length of the first TRB was subtracted from the total length before calculating the remaining TD sizes. This is wrong because remaining TD sizes are relative to the size of the entire transfer, including the first TRB. Our current USB code does not trigger this bug because there is no code in upper layers yet which triggers use of multiple TRBs per transfer. ok mpi@
* Use memcpy instead of casts to copy 8 bytes of data to avoid unalignedkettenis2017-07-301-2/+2
| | | | | | access. ok visa@, mpi@, deraadt@
* double ;;. xhci one found by geoffhillderaadt2017-06-221-2/+2
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* Fix a use-after-free when sending root hub control transfers.mpi2017-03-101-2/+2
| | | | | | | | | | | *_root_ctrl_start() routines are synchronous and all end up calling usb_transfer_complete() in the non-error case. After calling this function it is unsafe to dereference ``xfer'' since the transfer callback has been called. So returning USBD_IN_PROGRESS is wrong in this case since transfers are always completed at this point. So return USBD_NORMAL_COMPLETION or the corresponding error code if something wrong happen.
* Move per HC polling code to the stack.mpi2017-03-101-30/+3
| | | | | | | | | This code contains a use-after-free which be addressed in an upcoming diff. This fix xhci(4) polling mode. ok kettenis@
* Remove superfluous DMA synchronization now that the stack is doing it formpi2016-11-081-4/+1
| | | | | | all HCs. ok patrick@
* Fix some bus_dmamap_sync(9) calls.mpi2016-10-031-17/+40
| | | | | | | | | Do not fold multiple DMA synchronizations into one when chaining TRBs as the ring might wrap. Add missing "READ" transfer direction from the HC to host when applicable. From Marius Strobl.
* Remove a hack now that the USB stack correctly set the maximum packetmpi2016-09-211-9/+3
| | | | | | size based on the device speed. Tested by and ok jsg@, mlarkin@
* all pools have their ipl set via pool_setipl, so fold it into pool_init.dlg2016-09-151-4/+3
| | | | | | | | | | | | | | | | | | | | | | the ioff argument to pool_init() is unused and has been for many years, so this replaces it with an ipl argument. because the ipl will be set on init we no longer need pool_setipl. most of these changes have been done with coccinelle using the spatch below. cocci sucks at formatting code though, so i fixed that by hand. the manpage and subr_pool.c bits i did myself. ok tedu@ jmatthew@ @ipl@ expression pp; expression ipl; expression s, a, o, f, m, p; @@ -pool_init(pp, s, a, o, f, m, p); -pool_setipl(pp, ipl); +pool_init(pp, s, a, ipl, f, m, p);
* Do not change the status of a transfer before giving it back to thempi2015-12-021-7/+7
| | | | | | | | | | stack. Unbreak polling mode when the host Babbles because a reset of the ring is necessary and xhci_waitintr() stops polling as soon as the xfer status changed. Problem reported by and ok krw@
* Unconnected xhci(4) super speed ports may come up with the XHCI_PS_WRC,kettenis2015-11-291-1/+8
| | | | | | | | | | | | indicating a warm reset has happened. Communicate this as UPS_C_BH_PORT_RESET to the upper layers and make uhub(4) clear this bit such that we receive further connection status change notifications. Make sure we only do this for super speed (USB 3.0) hubs as high speed (USB 2.0) hubs use the same bit for UPS_C_PORT_L1. Make hotplugging USB 3.0 devices work on my MacBookPro12,1. ok mpi@
* Mark xhci_intr() as IPL_MPSAFE since it only schedules a soft-interrupt.mpi2015-11-021-5/+1
| | | | ok visa@
* Do not trust the hardware when it says that the number of remainingmpi2015-07-121-1/+4
| | | | | | bytes to transfer is superior to the length of the transfer. Found by krw@ with an ETRON controller.
* Clear root hub's "port link state".mpi2015-06-291-1/+2
| | | | | | | | Allow to re-plug USB3 devices on the root hub withtout going through a suspend/resume cycle (or rebooting) with Intel ICH7 xHCI as found the hardway by sobrado@. Debugging help from M.A.R. Osorio, tested by sobrado@
* Make xhci(4)'s root hub report the same status bits as physical USB3 hubs.mpi2015-06-221-6/+14
| | | | | | | | | | There's not bit to indicate the speed of a USB3.0 device attached to a hub port so do not abuse the PORT_TEST bit. Instead make the xhci(4) root hub report the PORT_POWER_SS bit when appropriate and use it to determin the speed of a new device. While here make the root hub report the link state and config error, from FreeBSD.
* Improve the controller state check in xhci_resetmikeb2015-05-271-2/+3
| | | | From FreeBSD, OK mpi
* Do not truncate possible remaining transfer length.mpi2015-04-191-2/+3
| | | | Reported by Takahiro HAYASHI on bugs@, thanks!
* Do not try to stop and reset endpoints if USB transfers are abortedmpi2015-01-211-2/+4
| | | | | | | | | | | because the HC has been shut down (during suspend/hibernate) or removed (PCIe card). In both cases the hardware wont complete the commands, resulting in timeouts. Instead just do the software part of the abort process. Unbreak suspend/resume with USB a device connected to xhci(4) as reported by Fabian Raetz on bugs@.
* Do not trust the content of event TRBs coming from the hardware andmpi2015-01-181-10/+18
| | | | maintain a list of possibly submitted commands.
* Complete synchronous abort method modeled after the existing ones.mpi2015-01-181-6/+83
| | | | | | | | | | Because our USB stack wants the aborted xfer to be removed from the pipe during abort(), we have to sleep in the abort function. Regarding the xHCI process, when a TD is being aborted, we simply stop the endpoint and then move the dequeue pointer past its last TRB. This is fairly simple for the moment since only one xfer can be pending on a given pipe.
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