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creating sensors.
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there are machines out there with broken BIOSen with such checksum errors in
thier RSDT tables. Windows runs fine on these machines, so it probably does
not check. Linux ignores checksum errors as well (and prints a warning).
ok deraadt@, krw@
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transfers, so skip the check for such xfers for the moment.
Issue reported by Ingo Feinerer and fix confirmed by Jan Stary.
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seen my mlarkin, ok miod
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and use this idiom everywhere, it is always safest.
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largely stolen from cas(4), but with a few tweaks.
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It seems no 64bit bus space support is forthcoming. Nothing
has happened in DragonflyBSD for several years and FreeBSD
has a different driver for 64bit chips called bwn(4).
ok mpi@ some time ago
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------------------------------------------------------------------------
r192306 | imp | 2009-05-18 17:31:26 +0200 (Mon, 18 May 2009) | 10 lines
Fix a typo from the original driver. We need to write ctrl2 into RF
register 0x52, not ctrl1. This appears to be a mistake in the bcm
reverse engineering page, and has been corrected there. Tracing
through the code, this is more in keeping with the "documented"
register. Sephe thinks it looks interesting and may be worth
fixing. :)
Submitted by: ddkprog at yahoo com
Reviewed by: Sepherosa Ziehau
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r192042 | nwhitehorn | 2009-05-13 16:25:55 +0200 (Wed, 13 May 2009) | 4 lines
Add a short delay after programming PHY registers to give some time for
the engine to catch up. This prevents a machine check exception from
illegal memory requests with a BCM4318.
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No regressions observed by myself, miod@, and Vesa Norrman (vesbula at gmail).
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claims to support both RNDIS and CDC Ethernet. However, RNDIS doesn't seem
to work, at least not with our driver. So blacklist it here such that cdce(4)
takes over.
ok miod@, armani@ (both a while back)
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bus_dmamap_unload(9) on a map that failed to load is a bad idea and causes
panics on some architectures (such as sparc64).
ok mpi@
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with some tweaks.
Nothing use it for the moment, but upcoming upd(4) improvements need
it.
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be enabled by default. Also if the controller doesn't have any RAM,
the cache on the physical disk will be enabled.
discuss with jsg tsubai
ok dlg
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away with being lazy and just passing everything to the vanilla
scsi cdb path.
sending io via the cdb path with chained sgls seems to trigger a
firmware fault on the new invader boards. sending the same io via
the ldio path works fine though.
tested on invader and thunderbolt boards:
mfii0 at pci1 dev 0 function 0 "Symbios Logic MegaRAID SAS3108" rev 0x02: msi
mfii0: "PERC H730 Mini", firmware 25.2.1.0037, 1024MB cache
mfii0 at pci1 dev 0 function 0 "Symbios Logic MegaRAID SAS2208" rev 0x05: msi
mfii0: "PERC H710 Mini", firmware 21.3.0-0009, 512MB cache
ok jmatthew@
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and RTL8168 family, the RTL8139 has different register map for config registers.
From FreeBSD
WoL bits reviewed and tested by stsp@
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by -Wuninitialized reported by jsg@.
ok stsp@
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a single 64bit write on lp64 archs, instead of two sequenced 32bit
writes. cos the 64bit store is atomic, we dont need the mutex
around it either.
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diff from uebayasi jsg
ok uebayasi
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luck finding my bug.
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return EINVAL in this case.
Also change an easily triggerable panic by a printf and return EINVAL.
Reminded by brad@, one typo spotted by sthen@ and ok mpi@
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Ingo Feinerer.
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but not if calling sis_iff() via sis_ioctl().
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controllers. the flags used in sgls on the first gen (thunderbolt)
are different to the ones used on the second and third gens (fury
and invader).
this creates an mfii_iop struct to store differences between these
chips, and uses them to set the flags on the sgls we generate for
the chip.
this solves lockups caused by stuck io on the following chips:
mfii0 at pci1 dev 0 function 0 "Symbios Logic MegaRAID SAS3108" rev 0x02: msi
mfii0: "PERC H730 Mini", firmware 25.2.1.0037, 1024MB cache
and
mfii0 at pci1 dev 0 function 0 "Symbios Logic MegaRAID SAS3008" rev 0x02: msi
mfii0: "PERC H330 Mini", firmware 25.2.1.0037
ive also tested this diff on:
mfii0 at pci10 dev 0 function 0 "Symbios Logic MegaRAID SAS2208" rev 0x05: msi
mfii0: "PERC H810 Adapter", firmware 21.2.0-0007, 1024MB cache
and
mfii0 at pci1 dev 0 function 0 "Symbios Logic MegaRAID SAS2208" rev 0x05: msi
mfii0: "PERC H710 Mini", firmware 21.3.0-0009, 512MB cache
Hrvoje Popovski reported the bug and verified the fix on his hardware.
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This is a workaround needed at least by Renesas controllers. I didn't
find any documentation about this issue and I guess other open source
xHCI implementations do not see this race because they do much more work
upon resume.
Thanks to Remi Locherer for reporting this issue on bugs@.
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the stack. This will allow stricter checks when aborting transfers.
While here update a comment about short transfer and multi-TRB TD since
bulk transfers can also use a chain now.
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