diff options
| author |   Likun Gao <Likun.Gao@amd.com> | 2020-02-24 11:31:13 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-06-03 13:52:08 -0400 |
| commit | 15dbe18fa634b08bd0bb75e3ac730bc1623dd335 (patch) | |
| tree | 8878513dc8e1c7f9439fd7cf181bef17aecf046f | |
| parent | drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid (diff) | |
drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlid
Enable Graphics Clock Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 75310858dc0c..82d38eb7ba58 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -269,7 +269,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, memset(feature_mask, 0, sizeof(uint32_t) * num); *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_FCLK_BIT); + | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) + | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); |