diff options
| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-06-09 13:22:59 +0200 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2022-06-22 17:25:08 +0200 |
| commit | 468deda82faf4d5d28155b0c6c7ea2d2c90624d4 (patch) | |
| tree | 6ae146e69c3d34e8f7b512d13262bc1e2cf90ee0 | |
| parent | arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs (diff) | |
arm64: dts: mediatek: mt6795: Remove incorrect fixed-clocks
Remove the RTC and UART fixed clocks, as these were introduced to
temporarily provide a dummy clock to devices: since the two 26M/32K
fixed oscillators clocks (which do really exist in the SoC) have
been added, there's no reason to keep the aforementioned (and now
redundant) dummies in this devicetree.
In order to remove the uart dummy clock, it was necessary to also
reassign the clock of all UART nodes to clk26m.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220609112303.117928-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt6795.dtsi | 20 |
1 files changed, 4 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 7123c1bf8d9e..b6f7681cc151 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -162,18 +162,6 @@ #clock-cells = <0>; }; - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, @@ -235,7 +223,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -244,7 +232,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -253,7 +241,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -262,7 +250,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; }; |