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| author |   Krzysztof Kozlowski <krzk@kernel.org> | 2020-12-10 22:25:22 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2021-03-07 20:56:17 +0100 |
| commit | 6503c568e97a52f8b7a3109718db438e52e59485 (patch) | |
| tree | 9fef802e48eb03fc32660d9d1e80f336117c2deb | |
| parent | ARM: dts: exynos: correct PMIC interrupt trigger level on Midas family (diff) | |
| download | linux-dev-6503c568e97a52f8b7a3109718db438e52e59485.tar.xz linux-dev-6503c568e97a52f8b7a3109718db438e52e59485.zip | |
ARM: dts: exynos: correct PMIC interrupt trigger level on Odroid X/U3 family
The Maxim PMIC datasheets describe the interrupt line as active low
with a requirement of acknowledge from the CPU. Without specifying the
interrupt type in Devicetree, kernel might apply some fixed
configuration, not necessarily working for this hardware.
Additionally, the interrupt line is shared so using level sensitive
interrupt is here especially important to avoid races.
Fixes: eea6653aae7b ("ARM: dts: Enable PMIC interrupts for exynos4412-odroid-common")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201210212534.216197-6-krzk@kernel.org
| -rw-r--r-- | arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 2b20d9095d9f..eebe6a3952ce 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -278,7 +278,7 @@ max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; reg = <0x09>; |