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author | Arnd Bergmann <arnd@arndb.de> | 2018-10-02 10:11:05 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2018-10-02 10:11:12 +0200 |
commit | 64d20b774f49b31e9d5ebe413d5c3d37195e9a64 (patch) | |
tree | b510d476ed3e4d87c913060274123ca8ca964446 /Documentation/devicetree/bindings/arm | |
parent | Merge tag 'actions-drivers+s900-sps-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/drivers (diff) | |
parent | Merge branch 'drivers-for-4.20' into drivers-for-4.20-final (diff) | |
download | linux-dev-64d20b774f49b31e9d5ebe413d5c3d37195e9a64.tar.xz linux-dev-64d20b774f49b31e9d5ebe413d5c3d37195e9a64.zip |
Merge tag 'qcom-drivers-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers
Qualcomm ARM Based Driver Updates for v4.20
* Refactor of SCM compatibles and clock requirements
* SMEM cleanup
* Add LLCC EDAC driver
* Fixes for GENI clocks and macros
* Fix includes for llcc-slice and smem
* String overflow fixes for APR and wcnss_ctrl
* Fixup for COMPILE_TEST of qcom driver Kconfigs
* Cleanup of Kconfig depends of rpmh, smd_rpm, smsm, and smp2p
* Add SCM dependencies to SPM and rmtfs-mem
* tag 'qcom-drivers-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (38 commits)
soc: qcom: geni: geni_se_clk_freq_match() should always accept multiples
soc: qcom: geni: Don't ignore clk_round_rate() errors in geni_se_clk_tbl_get()
soc: qcom: geni: Make version macros simpler
dt-bindings: firmware: scm: Add MSM8998 and SDM845
firmware: qcom: scm: Refactor clock handling
dt-bindings: firmware: scm: Refactor compatibles and clocks
soc: qcom: smem: a few last cleanups
soc: qcom: smem: verify partition host ids match
soc: qcom: smem: small change in global entry loop
soc: qcom: smem: verify partition offset_free_uncached
soc: qcom: smem: verify partition header size
soc: qcom: smem: introduce qcom_smem_partition_header()
soc: qcom: smem: require order of host ids to match
soc: qcom: smem: verify both host ids in partition header
soc: qcom: smem: small refactor in qcom_smem_enumerate_partitions()
soc: qcom: smem: always ignore partitions with 0 offset or size
soc: qcom: smem: initialize region struct only when successful
soc: qcom: smem: rename variable in qcom_smem_get_global()
drivers: qcom: rpmh-rsc: clear wait_for_compl after use
soc: qcom: rmtfs-mem: Validate that scm is available
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
-rw-r--r-- | Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt index 5e85749262ae..eaee06b2d8f2 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -16,11 +16,26 @@ Properties: - reg: Usage: required Value Type: <prop-encoded-array> - Definition: Start address and the the size of the register region. + Definition: The first element specifies the llcc base start address and + the size of the register region. The second element specifies + the llcc broadcast base address and size of the register region. + +- reg-names: + Usage: required + Value Type: <stringlist> + Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base". + +- interrupts: + Usage: required + Definition: The interrupt is associated with the llcc edac device. + It's used for llcc cache single and double bit error detection + and reporting. Example: cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x250000>; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; |