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authorPratyush Anand <pratyush.anand@gmail.com>2016-07-04 21:44:42 +0530
committerBjorn Helgaas <bhelgaas@google.com>2016-08-22 12:34:43 -0500
commitfe48cb8538421fbd16ecf8bf95829faf8d8c001e (patch)
treee38cfb7e754dc352e03785dab0c33ab793c6c5f3 /Documentation/devicetree/bindings/pci/designware-pcie.txt
parentPCI: designware: Check LTSSM training bit before deciding link is up (diff)
downloadlinux-dev-fe48cb8538421fbd16ecf8bf95829faf8d8c001e.tar.xz
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PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2
Most of the platforms have 3 or more viewports. For such platforms, We do not need to share viewports between IO and CFG. Assign viewport 2 to IO transactions in such cases. Tested-by: Dong Bo <dongbo4@huawei.com> Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/designware-pcie.txt')
-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 6c5322c55411..1392c705ceca 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -17,6 +17,8 @@ Required properties:
- num-lanes: number of lanes to use
Optional properties:
+- num-viewport: number of view ports configured in hardware. If a platform
+ does not specify it, the driver assumes 2.
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
- reset-gpio: gpio pin number of power good signal
@@ -44,4 +46,5 @@ Example configuration:
interrupts = <25>, <24>;
#interrupt-cells = <1>;
num-lanes = <1>;
+ num-viewport = <3>;
};