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| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-10-25 01:14:14 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-10-29 20:29:17 +0100 |
| commit | c19c631a3cb71ccde4a283fea4cb3bf1c56b947f (patch) | |
| tree | 5c4d48b9ec66cfcfdfea5342a2941ec37c69e3ca /arch/arm/boot/dts/tegra20-trimslice.dts | |
| parent | ARM: tegra: paz00: Add CPU Operating Performance Points (diff) | |
| download | linux-dev-c19c631a3cb71ccde4a283fea4cb3bf1c56b947f.tar.xz linux-dev-c19c631a3cb71ccde4a283fea4cb3bf1c56b947f.zip | |
ARM: tegra: trimslice: Add CPU Operating Performance Points
Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available
now on TrimSlice.
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-trimslice.dts')
| -rw-r--r-- | arch/arm/boot/dts/tegra20-trimslice.dts | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 3e5ac096d85e..8debd3d3c20d 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -3,6 +3,7 @@ #include <dt-bindings/input/input.h> #include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" / { model = "Compulab TrimSlice board"; @@ -471,4 +472,14 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; }; |