diff options
| author |   Andre Przywara <andre.przywara@arm.com> | 2014-11-14 15:54:10 +0000 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2014-11-25 15:56:21 +0000 |
| commit | 301bcfac42897dbd1b0b3c1be49f24654a1bc49e (patch) | |
| tree | bd42ce2fcf06bc99fb2b553969cdc2dba3cb1c0b /arch/arm64/include/asm/cputype.h | |
| parent | arm64: detect silicon revisions and set cap bits accordingly (diff) | |
| download | linux-dev-301bcfac42897dbd1b0b3c1be49f24654a1bc49e.tar.xz linux-dev-301bcfac42897dbd1b0b3c1be49f24654a1bc49e.zip | |
arm64: add Cortex-A53 cache errata workaround
The ARM errata 819472, 826319, 827319 and 824069 define the same
workaround for these hardware issues in certain Cortex-A53 parts.
Use the new alternatives framework and the CPU MIDR detection to
patch "cache clean" into "cache clean and invalidate" instructions if
an affected CPU is detected at runtime.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[will: add __maybe_unused to squash gcc warning]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cputype.h')
| -rw-r--r-- | arch/arm64/include/asm/cputype.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 379d0b874328..8adb986a3086 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -57,6 +57,11 @@ #define MIDR_IMPLEMENTOR(midr) \ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_CPU_PART(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_IMP_APM 0x50 |