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| author |   Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-11-22 09:46:45 +0100 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2018-11-27 18:47:33 +0000 |
| commit | 7aaf7b2fd26c3a069472dd9778367b2f941dd866 (patch) | |
| tree | 3e06b76441ce027300e0fa60620964bc5a0d892b /arch/arm64/include/asm/insn.h | |
| parent | arm64: Use a raw spinlock in __install_bp_hardening_cb() (diff) | |
| download | linux-dev-7aaf7b2fd26c3a069472dd9778367b2f941dd866.tar.xz linux-dev-7aaf7b2fd26c3a069472dd9778367b2f941dd866.zip | |
arm64/insn: add support for emitting ADR/ADRP instructions
Add support for emitting ADR and ADRP instructions so we can switch
over our PLT generation code in a subsequent patch.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/insn.h')
| -rw-r--r-- | arch/arm64/include/asm/insn.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index c6802dea6cab..9c01f04db64d 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -261,6 +261,11 @@ enum aarch64_insn_prfm_policy { AARCH64_INSN_PRFM_POLICY_STRM, }; +enum aarch64_insn_adr_type { + AARCH64_INSN_ADR_TYPE_ADRP, + AARCH64_INSN_ADR_TYPE_ADR, +}; + #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ { return (code & (mask)) == (val); } \ @@ -393,6 +398,9 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst, enum aarch64_insn_register src, int imm, enum aarch64_insn_variant variant, enum aarch64_insn_adsb_type type); +u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr, + enum aarch64_insn_register reg, + enum aarch64_insn_adr_type type); u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst, enum aarch64_insn_register src, int immr, int imms, |