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author | Lachlan McIlroy <lachlan@redback.melbourne.sgi.com> | 2009-01-14 16:29:51 +1100 |
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committer | Lachlan McIlroy <lachlan@redback.melbourne.sgi.com> | 2009-01-14 16:29:51 +1100 |
commit | cb7a97d01521797cad9f63e8478403c3e51fea49 (patch) | |
tree | 84cddf20369f82f10c1c3712e6cce20dd1b9d863 /arch/mips/include/asm/mipsregs.h | |
parent | [XFS] Update maintainers (diff) | |
parent | Merge branch 'x86-pat-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip (diff) | |
download | linux-dev-cb7a97d01521797cad9f63e8478403c3e51fea49.tar.xz linux-dev-cb7a97d01521797cad9f63e8478403c3e51fea49.zip |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-linus
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
-rw-r--r-- | arch/mips/include/asm/mipsregs.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9316324d070d..0417516503f6 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1000,6 +1000,26 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) +/* + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. + */ +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) + +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + /* * Macros to access the floating point coprocessor control registers */ @@ -1008,6 +1028,8 @@ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\treorder\n\t" \ + /* gas fails to assemble cfc1 for some archs (octeon).*/ \ + ".set\tmips1\n\t" \ "cfc1\t%0,"STR(source)"\n\t" \ ".set\tpop" \ : "=r" (__res)); \ |