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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-10 18:23:51 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-10 20:49:32 -0700 |
| commit | 3aefb2ee5bdd4a8976298415a5a017bf9844bfd5 (patch) | |
| tree | 3e4c1fdfa09f59b43605efab6102690b9c13bf52 /arch/riscv/Makefile | |
| parent | RISC-V: Canaan devicetree fixes (diff) | |
| parent | riscv: implement cache-management errata for T-Head SoCs (diff) | |
| download | linux-dev-3aefb2ee5bdd4a8976298415a5a017bf9844bfd5.tar.xz linux-dev-3aefb2ee5bdd4a8976298415a5a017bf9844bfd5.zip | |
riscv: implement Zicbom-based CMO instructions + the t-head variant
This series is based on the alternatives changes done in my svpbmt
series and thus also depends on Atish's isa-extension parsing series.
It implements using the cache-management instructions from the Zicbom-
extension to handle cache flush, etc actions on platforms needing them.
SoCs using cpu cores from T-Head like the Allwinne D1 implement a
different set of cache instructions. But while they are different,
instructions they provide the same functionality, so a variant can easly
hook into the existing alternatives mechanism on those.
[Palmer: Some minor fixups, including a RISCV_ISA_ZICBOM dependency on
MMU that's probably not strictly necessary. The Zicbom support will
trip up sparse for users that have new toolchains, I just sent a patch.]
Link: https://lore.kernel.org/all/20220706231536.2041855-1-heiko@sntech.de/
Link: https://lore.kernel.org/linux-sparse/20220811033138.20676-1-palmer@rivosinc.com/T/#u
* palmer/riscv-zicbom:
riscv: implement cache-management errata for T-Head SoCs
riscv: Add support for non-coherent devices using zicbom extension
dt-bindings: riscv: document cbom-block-size
of: also handle dma-noncoherent in of_dma_is_coherent()
Diffstat (limited to 'arch/riscv/Makefile')
| -rw-r--r-- | arch/riscv/Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 81029d40a672..42d7ff8730aa 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei +# Check if the toolchain supports Zicbom extension +toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom) +riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) KBUILD_AFLAGS += -march=$(riscv-march-y) |