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| author |   Anup Patel <Anup.Patel@wdc.com> | 2019-04-25 08:38:41 +0000 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@sifive.com> | 2019-05-16 20:42:11 -0700 |
| commit | a3182c91ef4e7dda90ff080a4132efd3ecb8786a (patch) | |
| tree | 5309b2480f3c6bb9e6df4d7921c7a71ce18dcc4d /arch/riscv/kernel/smp.c | |
| parent | RISC-V: Add interrupt related SCAUSE defines in asm/csr.h (diff) | |
| download | linux-dev-a3182c91ef4e7dda90ff080a4132efd3ecb8786a.tar.xz linux-dev-a3182c91ef4e7dda90ff080a4132efd3ecb8786a.zip | |
RISC-V: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not recognize
newly addes CSRs by name.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/smp.c')
| -rw-r--r-- | arch/riscv/kernel/smp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 0115db1368a4..9253de5d91b6 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -95,7 +95,7 @@ void riscv_software_interrupt(void) unsigned long *stats = ipi_data[smp_processor_id()].stats; /* Clear pending IPI */ - csr_clear(sip, SIE_SSIE); + csr_clear(CSR_SIP, SIE_SSIE); while (true) { unsigned long ops; |