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| author |   Christoph Hellwig <hch@lst.de> | 2019-10-28 13:10:38 +0100 |
|---|---|---|
| committer |   Paul Walmsley <paul.walmsley@sifive.com> | 2019-11-17 15:17:39 -0800 |
| commit | fcdc65375186a5cd69cc2eedfb498b86f4f5a21e (patch) | |
| tree | e5f23c3934dc954ff361e672af761365d37edc49 /arch/riscv/kernel/smp.c | |
| parent | riscv: add support for MMIO access to the timer registers (diff) | |
| download | linux-dev-fcdc65375186a5cd69cc2eedfb498b86f4f5a21e.tar.xz linux-dev-fcdc65375186a5cd69cc2eedfb498b86f4f5a21e.zip | |
riscv: provide native clint access for M-mode
RISC-V has the concept of a cpu level interrupt controller. The
interface for it is split between a standardized part that is exposed
as bits in the mstatus/sstatus register and the mie/mip/sie/sip
CRS. But the bit to actually trigger IPIs is not standardized and
just mentioned as implementable using MMIO.
Add support for IPIs using MMIO using the SiFive clint layout (which
is also shared by Ariane, Kendryte and the Qemu virt platform).
Additionally the MMIO block also supports the time value and timer
compare registers, so they are also set up using the same OF node.
Support for other layouts should also be relatively easy to add in the
future.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
[paul.walmsley@sifive.com: update include guard format; fix checkpatch
issues; minor commit message cleanup]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/smp.c')
| -rw-r--r-- | arch/riscv/kernel/smp.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index c0fbc04e6810..eb878abcaaf8 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -16,6 +16,7 @@ #include <linux/seq_file.h> #include <linux/delay.h> +#include <asm/clint.h> #include <asm/sbi.h> #include <asm/tlbflush.h> #include <asm/cacheflush.h> @@ -92,7 +93,10 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) smp_mb__after_atomic(); riscv_cpuid_to_hartid_mask(mask, &hartid_mask); - sbi_send_ipi(cpumask_bits(&hartid_mask)); + if (IS_ENABLED(CONFIG_RISCV_SBI)) + sbi_send_ipi(cpumask_bits(&hartid_mask)); + else + clint_send_ipi_mask(&hartid_mask); } static void send_ipi_single(int cpu, enum ipi_message_type op) @@ -103,12 +107,18 @@ static void send_ipi_single(int cpu, enum ipi_message_type op) set_bit(op, &ipi_data[cpu].bits); smp_mb__after_atomic(); - sbi_send_ipi(cpumask_bits(cpumask_of(hartid))); + if (IS_ENABLED(CONFIG_RISCV_SBI)) + sbi_send_ipi(cpumask_bits(cpumask_of(hartid))); + else + clint_send_ipi_single(hartid); } static inline void clear_ipi(void) { - csr_clear(CSR_IP, IE_SIE); + if (IS_ENABLED(CONFIG_RISCV_SBI)) + csr_clear(CSR_IP, IE_SIE); + else + clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id())); } void riscv_software_interrupt(void) |