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authorHeiko Stuebner <heiko@sntech.de>2022-07-07 01:15:35 +0200
committerPalmer Dabbelt <palmer@rivosinc.com>2022-07-28 15:30:51 -0700
commit1631ba1259d6d7f49b6028f2a1a0fa02be1c522a (patch)
tree224d5329d0ce1579c48f8f2b68b7a2c989dd9a96 /arch/riscv/mm/Makefile
parentdt-bindings: riscv: document cbom-block-size (diff)
downloadlinux-dev-1631ba1259d6d7f49b6028f2a1a0fa02be1c522a.tar.xz
linux-dev-1631ba1259d6d7f49b6028f2a1a0fa02be1c522a.zip
riscv: Add support for non-coherent devices using zicbom extension
The Zicbom ISA-extension was ratified in november 2021 and introduces instructions for dcache invalidate, clean and flush operations. Implement cache management operations for non-coherent devices based on them. Of course not all cores will support this, so implement an alternative-based mechanism that replaces empty instructions with ones done around Zicbom instructions. As discussed in previous versions, assume the platform being coherent by default so that non-coherent devices need to get marked accordingly by firmware. Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20220706231536.2041855-4-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/mm/Makefile')
-rw-r--r--arch/riscv/mm/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index ac7a25298a04..d76aabf4b94d 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -30,3 +30,4 @@ endif
endif
obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
+obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o