aboutsummaryrefslogtreecommitdiffstats
path: root/arch/riscv/mm/Makefile (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-07-28riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner1-0/+1
2022-03-03riscv: Fix config KASAN && DEBUG_VIRTUALAlexandre Ghiti1-0/+3
2021-01-14riscv: Fixup patch_text panic in ftraceGuo Ren1-0/+1
2021-01-14riscv: Fixup wrong ftrace remove cflagGuo Ren1-1/+1
2020-07-30riscv: Allow building with kcov coverageTobias Klauser1-0/+2
2020-03-26riscv: Add support to dump the kernel page tablesZong Li1-0/+1
2020-03-26riscv: add ARCH_HAS_SET_MEMORY supportZong Li1-1/+1
2020-01-23riscv: mm: add support for CONFIG_DEBUG_VIRTUALZong Li1-0/+2
2020-01-22riscv: Add KASAN supportNick Hu1-0/+6
2019-12-20riscv: move sifive_l2_cache.c to drivers/socChristoph Hellwig1-1/+0
2019-11-28Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremapLinus Torvalds1-1/+1
2019-11-17riscv: add nommu supportChristoph Hellwig1-2/+1
2019-11-11riscv: use the generic ioremap codeChristoph Hellwig1-1/+0
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig1-0/+3
2019-07-03riscv: Introduce huge page support for 32/64bit kernelAlexandre Ghiti1-0/+2
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-16RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah1-0/+1
2019-05-16riscv: move switch_mm to its own fileGary Guo1-0/+1
2019-03-26RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel1-0/+6
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman1-0/+1
2017-09-26RISC-V: Build InfrastructurePalmer Dabbelt1-0/+4