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author | Keerthy <j-keerthy@ti.com> | 2016-12-02 14:35:43 +0530 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-01-26 16:03:04 -0800 |
commit | ced3068344ec9730eb160b462154e5fc53f6c2c5 (patch) | |
tree | b39b588743555c21d5588baa9f4a5b63e7083515 /drivers/clk/mediatek | |
parent | clk: qcom: gdsc: Fix handling of hw control enable/disable (diff) | |
download | linux-dev-ced3068344ec9730eb160b462154e5fc53f6c2c5.tar.xz linux-dev-ced3068344ec9730eb160b462154e5fc53f6c2c5.zip |
clk: ti: divider: Add the table parsing to get the best divider value
Currently the divider selection logic blindly divides the parent_rate
by the clk rate and gives the divider value for the divider clocks
which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider
table parsing to get the closest divider available in the table
provided via Device tree.
The code is pretty much taken from: drivers/clk/clk-divider.c.
and used here to fix up the best divider selection logic.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions