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| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-25 14:48:06 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-25 14:48:06 -0800 |
| commit | b1669432b3555954124ffd987a6ff2308344c88f (patch) | |
| tree | c3a4069092f3cb5501a66d30d43bb15b7ff9f929 /drivers/gpio | |
| parent | Merge tag 'spi-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi (diff) | |
| parent | Merge remote-tracking branch 'regmap/topic/irq' into regmap-next (diff) | |
| download | linux-dev-b1669432b3555954124ffd987a6ff2308344c88f.tar.xz linux-dev-b1669432b3555954124ffd987a6ff2308344c88f.zip | |
Merge tag 'regmap-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap
Pull regmap updates from Mark Brown:
"This has been a busy release for the regmap-irq code, there's several
new features been added, including an API cleanup for how we specify
types that affected one existing driver (gpio-max77620):
- Support for hardware that flags rising and falling edges on
separate status bits from Bartosz Golaszewski.
- Support for explicitly clearing interrupts before unmasking from
Bartosz Golaszewski.
- Support for level triggered IRQs from Matti Vaittinen"
* tag 'regmap-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap:
regmap: irq: add an option to clear status registers on unmask
regmap: regmap-irq/gpio-max77620: add level-irq support
regmap: regmap-irq: Remove default irq type setting from core
regmap: debugfs: convert to DEFINE_SHOW_ATTRIBUTE
regmap: rbtree: convert to DEFINE_SHOW_ATTRIBUTE
regmap: irq: handle HW using separate rising/falling edge interrupts
regmap: add a new macro:REGMAP_IRQ_REG_LINE(_id, _reg_bits)
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/gpio-max77620.c | 96 |
1 files changed, 64 insertions, 32 deletions
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c index 538bce4b5b42..65fa3a198ebd 100644 --- a/drivers/gpio/gpio-max77620.c +++ b/drivers/gpio/gpio-max77620.c @@ -25,60 +25,92 @@ struct max77620_gpio { static const struct regmap_irq max77620_gpio_irqs[] = { [0] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 0, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 0, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [1] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 1, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 1, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [2] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 2, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 2, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [3] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 3, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 3, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [4] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 4, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 4, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [5] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 5, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 5, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [6] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 6, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 6, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [7] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 7, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 7, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, }; |