diff options
| author |   Charlene Liu <charlene.liu@amd.com> | 2019-03-01 11:12:50 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-03-20 23:39:48 -0500 |
| commit | 7fe538a4d64135d8f8e4aca8d0aedf266958025c (patch) | |
| tree | 4acc1d7a90038a20cf4b823e7e5d5b5fe2b8927d /drivers/gpu/drm/amd/display/dc/dce110 | |
| parent | drm/amd/display: Fix setting DP_VID_N_MUL (diff) | |
| download | linux-dev-7fe538a4d64135d8f8e4aca8d0aedf266958025c.tar.xz linux-dev-7fe538a4d64135d8f8e4aca8d0aedf266958025c.zip | |
drm/amd/display: fix DP 422 VID_M half the rate issue.
[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce110')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 7ec9958ddd26..6b24ddd57a4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1052,9 +1052,8 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link *link = stream->link; /* only 3 items below are used by unblank */ - params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; + params.timing = pipe_ctx->stream->timing; params.link_settings.link_rate = link_settings->link_rate; - params.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); |