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| author |   Harry Wentland <harry.wentland@amd.com> | 2019-02-22 15:50:50 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:34 -0500 |
| commit | f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f (patch) | |
| tree | 642f348d5233ecde53fc2422de386c9d2595f311 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | |
| parent | drm/amd/display: Add DCN2 MPC (diff) | |
| download | linux-dev-f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f.tar.xz linux-dev-f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f.zip | |
drm/amd/display: Add DCN2 DPP
Add support to program the DCN2 DPP (Multiple pipe and plane combine)
HW Blocks:
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index ce21a290bf3e..d67e0abeee93 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -218,6 +218,14 @@ static void dpp1_dscl_set_lb( INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ } +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else { + /* DSCL caps: pixel data processed in float format */ + REG_SET_2(LB_DATA_FORMAT, 0, + INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ + LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ + } +#endif REG_SET_2(LB_MEMORY_CTRL, 0, MEMORY_CONFIG, mem_size_config, |