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authorMatt Roper <matthew.d.roper@intel.com>2021-07-29 09:59:55 -0700
committerMatt Roper <matthew.d.roper@intel.com>2021-08-05 08:07:25 -0700
commit927dfdd09d8c03ba100ed0c8c3915f8e1d1f5556 (patch)
treea08c96be3d6ae5e74d8391ce953e489f87be90bc /drivers/gpu/drm/i915/i915_drv.c
parentdrm/i915/dg2: Update steering tables (diff)
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drm/i915/dg2: Add SQIDI steering
Although DG2_G10 platforms will always have all SQIDI's present and don't need steering for registers in a SQIDI MMIO range, this isn't true for DG2_G11 platforms; only SQIDI's 2 and 3 can be used on those. We handle SQIDI ranges a bit differently from other types of explicit steering. The SQIDI ranges belong to either the MCFG unit or the SF unit, both of which have their own dedicated steering registers and do not use the typical 0xFDC steering control that all other types of ranges use. Thus we only need to worry about picking a valid initial value for the MCFG and SF steering registers (0xFD0 and 0xFD8 respectively) at driver init; they won't change after we set them up so we don't need to worry about re-steering them explicitly at runtime. Given that any SQIDI value should work fine for DG2-G10 and XeHP SDV, while only values of 2 and 3 are valid for DG2-G11, we'll just initialize the MCFG and SF steering registers to a constant value of "2" for all XeHP-based platforms for simplicity --- that will work in all cases. Bspec: 66534 Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-6-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
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