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authorManasi Navare <manasi.d.navare@intel.com>2016-09-01 15:08:11 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2016-09-07 13:55:33 -0700
commit81b9fd8fc68e9e0999efc604c4e5477b8d1982aa (patch)
treecfd68e638787b33638d718a3244837acdbafe0ca /drivers/gpu/drm/i915/intel_dpll_mgr.h
parentdrm/i915: Split skl_get_dpll() (diff)
downloadlinux-dev-81b9fd8fc68e9e0999efc604c4e5477b8d1982aa.tar.xz
linux-dev-81b9fd8fc68e9e0999efc604c4e5477b8d1982aa.zip
drm/i915: Split hsw_get_dpll()
Split out the DisplayPort and HDMI pll setup code into separate functions and refactor the DP code that calculates the pll so that it doesn't depend on crtc state. This will be used for acquiring port pll when doing upfront link training. Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpll_mgr.h')
-rw-r--r--drivers/gpu/drm/i915/intel_dpll_mgr.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index cb28f8df8701..aed74084f759 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -164,8 +164,14 @@ void intel_shared_dpll_init(struct drm_device *dev);
bool bxt_ddi_dp_set_dpll_hw_state(int clock,
struct intel_dpll_hw_state *dpll_hw_state);
+
/* SKL dpll related functions */
bool skl_ddi_dp_set_dpll_hw_state(int clock,
struct intel_dpll_hw_state *dpll_hw_state);
+
+/* HSW dpll related functions */
+struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder *encoder,
+ int clock);
+
#endif /* _INTEL_DPLL_MGR_H_ */