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authorRodrigo Vivi <rodrigo.vivi@intel.com>2015-01-12 10:14:30 -0800
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-01-15 01:36:17 +0100
commit6caf36a4f4610b05b32c27b7cc21119fccd54dfa (patch)
tree9ef7df7b4a1d5d47d8569c490b3930732d5d8b22 /drivers/gpu/drm/i915/intel_psr.c
parentdrm/i915: PSR VLV/CHV: Remove condition checks that only applies to Haswell. (diff)
downloadlinux-dev-6caf36a4f4610b05b32c27b7cc21119fccd54dfa.tar.xz
linux-dev-6caf36a4f4610b05b32c27b7cc21119fccd54dfa.zip
drm/i915: PSR HSW/BDW: Fix inverted logic at sink main_link_active bit.
We have only two possible states with so many names and combinations that might be confusing. 1 - Main link active / enabled / stand by / on 2 - Main link disabled / off / full off Let's start organizing it by fixing a inverted logic when setting the sink bit. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 3dd88861f417..0af89dbbe4c8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -163,10 +163,10 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
/* Enable PSR in sink */
if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
- DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
+ DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
else
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
- DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
+ DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
/* Setup AUX registers */
for (i = 0; i < sizeof(aux_msg); i += 4)