diff options
| author |   Ben Skeggs <bskeggs@redhat.com> | 2013-05-13 12:57:10 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-07-01 13:50:39 +1000 |
| commit | d8b02dbbc37de874728181963b1ec9ef874cc81d (patch) | |
| tree | 78777e084103cc35f1c3bcb5d373555a55b75f79 /drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h | |
| parent | drm/nvd9/gr: update initial register/context values (diff) | |
| download | linux-dev-d8b02dbbc37de874728181963b1ec9ef874cc81d.tar.xz linux-dev-d8b02dbbc37de874728181963b1ec9ef874cc81d.zip | |
drm/nvc0/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h | 87 |
1 files changed, 67 insertions, 20 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index b8c9fc3b32bd..427ddf06316c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h @@ -34,32 +34,32 @@ uint32_t nvc0_grgpc_data[] = { 0x00000000, /* 0x0064: chipsets */ 0x000000c0, - 0x013400d4, - 0x01f001a0, + 0x01980138, + 0x02b00264, 0x000000c1, 0x013800d4, - 0x020401a0, + 0x02640200, 0x000000c3, 0x013400d4, - 0x020001a0, + 0x02600200, 0x000000c4, 0x013400d4, - 0x020001a0, + 0x02600200, 0x000000c8, 0x013400d4, - 0x01f001a0, + 0x02500200, 0x000000ce, 0x013400d4, - 0x020001a0, + 0x02600200, 0x000000cf, 0x013400d4, - 0x01fc01a0, + 0x025c0200, 0x000000d9, - 0x01a00138, - 0x02600204, + 0x02000198, + 0x030c02b0, 0x000000d7, - 0x01a00138, - 0x02600204, + 0x02000198, + 0x030c02b0, 0x00000000, /* 0x00d4: nvc0_gpc_mmio_head */ 0x00000380, @@ -89,7 +89,33 @@ uint32_t nvc0_grgpc_data[] = { /* 0x0134: nvc0_gpc_mmio_tail */ 0x00000c6c, /* 0x0138: nvc1_gpc_mmio_tail */ -/* 0x0138: nvd9_gpc_mmio_head */ +/* 0x0138: nnvc0_gpc_mmio_head */ + 0x00000380, + 0x14000400, + 0x20000450, + 0x00000600, + 0x00000684, + 0x10000700, + 0x00000800, + 0x08000808, + 0x00000828, + 0x00000830, + 0x000008d8, + 0x000008e0, + 0x140008e8, + 0x0000091c, + 0x08000924, + 0x00000b00, + 0x14000b08, + 0x00000bb8, + 0x00000c08, + 0x1c000c10, + 0x00000c80, + 0x00000c8c, + 0x08001000, + 0x00001014, +/* 0x0198: nnvc0_gpc_mmio_tail */ +/* 0x0198: nvd9_gpc_mmio_head */ 0x00000380, 0x04000400, 0x0800040c, @@ -116,8 +142,8 @@ uint32_t nvc0_grgpc_data[] = { 0x00000c8c, 0x08001000, 0x00001014, -/* 0x01a0: nvd9_gpc_mmio_tail */ -/* 0x01a0: nvc0_tpc_mmio_head */ +/* 0x0200: nvd9_gpc_mmio_tail */ +/* 0x0200: nvc0_tpc_mmio_head */ 0x00000018, 0x0000003c, 0x00000048, @@ -138,16 +164,37 @@ uint32_t nvc0_grgpc_data[] = { 0x4c000644, 0x00000698, 0x04000750, -/* 0x01f0: nvc0_tpc_mmio_tail */ +/* 0x0250: nvc0_tpc_mmio_tail */ 0x00000758, 0x000002c4, 0x000006e0, -/* 0x01fc: nvcf_tpc_mmio_tail */ +/* 0x025c: nvcf_tpc_mmio_tail */ 0x000004bc, -/* 0x0200: nvc3_tpc_mmio_tail */ +/* 0x0260: nvc3_tpc_mmio_tail */ 0x00000544, -/* 0x0204: nvc1_tpc_mmio_tail */ -/* 0x0204: nvd9_tpc_mmio_head */ +/* 0x0264: nvc1_tpc_mmio_tail */ +/* 0x0264: nnvc0_tpc_mmio_head */ + 0x00000018, + 0x0000003c, + 0x00000048, + 0x00000064, + 0x00000088, + 0x14000200, + 0x14000300, + 0x000003d0, + 0x040003e0, + 0x08000400, + 0x00000420, + 0x000004b0, + 0x000004e8, + 0x000004f4, + 0x04000520, + 0x0c000604, + 0x4c000644, + 0x00000698, + 0x04000750, +/* 0x02b0: nnvc0_tpc_mmio_tail */ +/* 0x02b0: nvd9_tpc_mmio_head */ 0x00000018, 0x0000003c, 0x00000048, |