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| author |   Giulio Benetti <giulio.benetti@micronovasrl.com> | 2021-01-14 09:17:32 +0100 |
|---|---|---|
| committer |   Maxime Ripard <maxime@cerno.tech> | 2021-01-14 12:37:28 +0100 |
| commit | 67f4aeb2b41a0629abde3794d463547f60b0cbdd (patch) | |
| tree | d1853d0d61f8e2a38ece09e9a246f87eda8abadc /drivers/gpu/drm/sun4i/sun4i_tcon.h | |
| parent | drm/hisilicon: Fix build error (diff) | |
| download | linux-dev-67f4aeb2b41a0629abde3794d463547f60b0cbdd.tar.xz linux-dev-67f4aeb2b41a0629abde3794d463547f60b0cbdd.zip | |
drm/sun4i: tcon: fix inverted DCLK polarity
During commit 88bc4178568b ("drm: Use new
DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_*
macros have been changed to avoid ambiguity but just because of this
ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning
_SAMPLE_ not _DRIVE_. This leads to DLCK inversion and need to fix but
instead of swapping phase values, let's adopt an easier approach Maxime
suggested:
It turned out that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to
invert DCLK polarity and this makes things really easier than before. So
let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE
as bit 26 and activating according to bus_flags the same way it is done
for all the other signals polarity.
Fixes: 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags")
Suggested-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20210114081732.9386-1-giulio.benetti@benettiengineering.com
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun4i_tcon.h')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index cfbf4e6c1679..c5ac1b02482c 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -113,6 +113,7 @@ #define SUN4I_TCON0_IO_POL_REG 0x88 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27) +#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26) #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) |