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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2019-07-05 17:56:35 +0800
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2019-07-08 12:22:10 +0100
commit0122af0a08243f344a438f924e5c2486486555b3 (patch)
tree5c12ed2af3b3ed493817584c3c5706e82b8347b4 /drivers/pci
parentPCI: mobiveil: Use the 1st inbound window for MEM inbound transactions (diff)
downloadlinux-dev-0122af0a08243f344a438f924e5c2486486555b3.tar.xz
linux-dev-0122af0a08243f344a438f924e5c2486486555b3.zip
PCI: mobiveil: Fix the Class Code field
Fix up the Class Code field in PCI configuration space and set it to PCI_CLASS_BRIDGE_PCI. Move the Class Code fixup to function mobiveil_host_init() where it belongs. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/controller/pcie-mobiveil.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 827218314ef3..9e080612a97b 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -626,6 +626,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
}
}
+ /* fixup for PCIe class register */
+ value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
+ value &= 0xff;
+ value |= (PCI_CLASS_BRIDGE_PCI << 16);
+ csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
+
/* setup MSI hardware registers */
mobiveil_pcie_enable_msi(pcie);
@@ -866,9 +872,6 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
goto error;
}
- /* fixup for PCIe class register */
- csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
-
/* initialize the IRQ domains */
ret = mobiveil_pcie_init_irq_domain(pcie);
if (ret) {