diff options
| author |   Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2019-11-07 13:58:14 +0900 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-11-21 16:07:45 +0000 |
| commit | 4b1140ade8f5c1ced640286cce79371ade2bd2d1 (patch) | |
| tree | bbcdf12326515f551ed85b4482c6b68b9d5f72f4 /drivers/pci | |
| parent | Linux 5.4-rc1 (diff) | |
| download | linux-dev-4b1140ade8f5c1ced640286cce79371ade2bd2d1.tar.xz linux-dev-4b1140ade8f5c1ced640286cce79371ade2bd2d1.zip | |
PCI: uniphier: Set mode register to host mode
Set the mode register to host(RC) mode so that the host controller
mode is set-up consistently across SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[lorenzo.pieralisi@arm.com: updated log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-uniphier.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 3f30ee4a00b3..8fd7badd59c2 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -33,6 +33,10 @@ #define PCL_PIPEMON 0x0044 #define PCL_PCLK_ALIVE BIT(15) +#define PCL_MODE 0x8000 +#define PCL_MODE_REGEN BIT(8) +#define PCL_MODE_REGVAL BIT(0) + #define PCL_APP_READY_CTRL 0x8008 #define PCL_APP_LTSSM_ENABLE BIT(0) @@ -85,6 +89,12 @@ static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv) { u32 val; + /* set RC MODE */ + val = readl(priv->base + PCL_MODE); + val |= PCL_MODE_REGEN; + val &= ~PCL_MODE_REGVAL; + writel(val, priv->base + PCL_MODE); + /* use auxiliary power detection */ val = readl(priv->base + PCL_APP_PM0); val |= PCL_SYS_AUX_PWR_DET; |