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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2017-11-14 12:11:33 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-11-14 12:11:33 -0600 |
| commit | 89000e89bf4df8b9a0a16e1d3856913907385bd5 (patch) | |
| tree | 25bd1e3b55dc0ff6df1b76d61cf672f4fbbefdc7 /drivers/pci | |
| parent | Merge branch 'pci/host-iproc' into next (diff) | |
| parent | PCI: layerscape: Change default error response behavior (diff) | |
| download | linux-dev-89000e89bf4df8b9a0a16e1d3856913907385bd5.tar.xz linux-dev-89000e89bf4df8b9a0a16e1d3856913907385bd5.zip | |
Merge branch 'pci/host-layerscape' into next
* pci/host-layerscape:
PCI: layerscape: Change default error response behavior
PCI: Disable MSI for Freescale Layerscape PCIe RC mode
arm64: dts: ls1046a: Add PCIe controller DT nodes
arm64: dts: ls1012a: Add PCIe controller DT node
PCI: layerscape: Add support for ls1012a
arm64: dts: ls1012a: Add MSI controller DT node
irqchip/ls-scfg-msi: Add LS1012a MSI support
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/dwc/pci-layerscape.c | 12 | ||||
| -rw-r--r-- | drivers/pci/quirks.c | 8 |
2 files changed, 20 insertions, 0 deletions
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 87fa486bee2c..8f34c2fdc600 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -33,6 +33,8 @@ /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ +#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ +#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */ #define PCIE_IATU_NUM 6 @@ -124,6 +126,14 @@ static int ls_pcie_link_up(struct dw_pcie *pci) return 1; } +/* Forward error response of outbound non-posted requests */ +static void ls_pcie_fix_error_response(struct ls_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + + iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); +} + static int ls_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -135,6 +145,7 @@ static int ls_pcie_host_init(struct pcie_port *pp) * dw_pcie_setup_rc() will reconfigure the outbound windows. */ ls_pcie_disable_outbound_atus(pcie); + ls_pcie_fix_error_response(pcie); dw_pcie_dbi_ro_wr_en(pci); ls_pcie_clear_multifunction(pcie); @@ -253,6 +264,7 @@ static struct ls_pcie_drvdata ls2088_drvdata = { }; static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 0e22cce05742..cbe85e921ede 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4814,3 +4814,11 @@ static void quirk_no_ats(struct pci_dev *pdev) /* AMD Stoney platform GPU */ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); #endif /* CONFIG_PCI_ATS */ + +/* Freescale PCIe doesn't support MSI in RC mode */ +static void quirk_fsl_no_msi(struct pci_dev *pdev) +{ + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) + pdev->no_msi = 1; +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); |