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| author |   Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2022-04-25 15:41:58 +0900 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-29 12:08:36 +0200 |
| commit | 7f906eaa95f38fae24957e0bf61878d5cb3f8847 (patch) | |
| tree | 762cc20c37d4f9e910eb346b9989eba032058a34 /include/uapi/linux/can/git:/ssh: | |
| parent | clk: renesas: r9a07g043: Add WDT clock and reset entries (diff) | |
| download | linux-dev-7f906eaa95f38fae24957e0bf61878d5cb3f8847.tar.xz linux-dev-7f906eaa95f38fae24957e0bf61878d5cb3f8847.zip | |
clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/uapi/linux/can/git:/ssh:')
0 files changed, 0 insertions, 0 deletions