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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2021-12-03 11:51:50 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-12-08 10:05:56 +0100 |
| commit | 7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0 (patch) | |
| tree | a38469ad418a14f0f444d18abb418bf861767b1a /lib/test_overflow.c | |
| parent | clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro (diff) | |
| download | linux-dev-7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0.tar.xz linux-dev-7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0.zip | |
clk: renesas: r9a07g044: Add mux and divider for G clock
G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.
This patch adds a mux and divider for getting different rates from
this clock sources.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'lib/test_overflow.c')
0 files changed, 0 insertions, 0 deletions