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authorDinh Nguyen <dinguyen@kernel.org>2019-05-16 17:30:00 -0500
committerDinh Nguyen <dinguyen@kernel.org>2019-06-06 17:33:36 -0500
commit9aa0cae1d458278a75008885654a0e240020598c (patch)
tree08573b2d434b5d4f7e5531630e13a487ea9e1393 /tools/perf/scripts/python/export-to-postgresql.py
parentARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" binding (diff)
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arm64: dts: stratix10: use the "altr,socfpga-stmmac-a10-s10" binding
Because of register and bits difference for setting PHY modes, PTP reference clock, and FPGA signalling, the Stratix10 SoC needs to use the "altr,socfpga-stmmac-a10-s10" binding to set the correct modes. On Stratix10, each EMAC has its own register for PHY modes, and they all have the same offset, thus we can use the 2nd parameter to specify the offsets for the FPGA signal bits. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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