diff options
| author |   Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-04-30 18:54:05 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@linaro.org> | 2014-05-05 12:26:05 -0700 |
| commit | 9c6344b3fa547ce7ec78da95134d92d9f9309b31 (patch) | |
| tree | 4fc10c4e0474c45a7facd093949e3c822bff94b7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: fsl_spdif: Fix clock source for rxclk rate measurement (diff) | |
| download | linux-dev-9c6344b3fa547ce7ec78da95134d92d9f9309b31.tar.xz linux-dev-9c6344b3fa547ce7ec78da95134d92d9f9309b31.zip | |
ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only
The clock mux for the Freescale S/PDIF controller has eight clock sources
while most of them are from other moudles and even system clocks that do
not allow a rate-changing operation.
So we here only allow the clk_set_rate() and clk_round_rate() happened to
spdif root clock, the private clock for S/PDIF controller.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions