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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-12 17:13:12 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 12:29:08 +0200 |
| commit | c8b088224c25ef4f5270f9de6a3516181b63f38c (patch) | |
| tree | 96b70a069c80c912b7d1db56bd3e199c06f015dd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'renesas-r9a07g043-dt-binding-defs-tag' into renesas-clk-for-v5.19 (diff) | |
| download | linux-dev-c8b088224c25ef4f5270f9de6a3516181b63f38c.tar.xz linux-dev-c8b088224c25ef4f5270f9de6a3516181b63f38c.zip | |
clk: renesas: Add support for RZ/G2UL SoC
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.
This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions