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| author |   Daniel Mack <zonque@gmail.com> | 2012-12-10 10:30:04 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-12-24 15:53:28 +0000 |
| commit | fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 (patch) | |
| tree | a1033cbc88a3ccba164e8d0f6c7469f9efd6713a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'asoc-fix-cs4271' into asoc-cs4271 (diff) | |
| download | linux-dev-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.tar.xz linux-dev-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.zip | |
ALSA: ASoC: cs4271: add optional soft reset workaround
The CS4271 requires its LRCLK and MCLK to be stable before its RESET
line is de-asserted. That also means that clocks cannot be changed
without putting the chip back into hardware reset, which also requires
a complete re-initialization of all registers.
One (undocumented) workaround is to assert and de-assert the PDN bit
in the MODE2 register.
This patch adds a new flag to both the DT bindings as well as to the
platform data to enable that workaround.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Alexander Sverdlin <subaparts@yandex.ru>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions