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| author |   Thierry Reding <treding@nvidia.com> | 2017-06-26 17:38:43 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 13:15:43 +0100 |
| commit | 85593b75ee715490f0207d95de4978fc465fda89 (patch) | |
| tree | e8c520fa7ecb30699f37a7f5bbd66805de76cc78 /tools/perf/scripts/python | |
| parent | arm64: tegra: Add MISC registers on Tegra186 (diff) | |
| download | linux-dev-85593b75ee715490f0207d95de4978fc465fda89.tar.xz linux-dev-85593b75ee715490f0207d95de4978fc465fda89.zip | |
arm64: tegra: Add FUSE block on Tegra186
The FUSE register block found on Tegra186 SoCs encodes various settings,
such as calibration data for other blocks.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions