diff options
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
131 files changed, 4224 insertions, 2112 deletions
diff --git a/Documentation/devicetree/bindings/arm/actions.yaml b/Documentation/devicetree/bindings/arm/actions.yaml index 02dc72c97645..e012f612f039 100644 --- a/Documentation/devicetree/bindings/arm/actions.yaml +++ b/Documentation/devicetree/bindings/arm/actions.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/actions.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Actions Semi platforms device tree bindings +title: Actions Semi platforms maintainers: - Andreas Färber <afaerber@suse.de> diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml new file mode 100644 index 000000000000..3292c669ee11 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha SoC based Platforms + +maintainers: + - Felix Fietkau <nbd@nbd.name> + - John Crispin <john@phrozen.org> + +description: + Boards with an Airoha SoC shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - airoha,en7523-evb + - const: airoha,en7523 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index c15c92fdf2ed..3eee03aa935c 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/altera.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Altera's SoCFPGA platform device tree bindings +title: Altera's SoCFPGA platform maintainers: - Dinh Nguyen <dinguyen@kernel.org> @@ -13,12 +13,54 @@ properties: $nodename: const: "/" compatible: - items: - - enum: - - altr,socfpga-cyclone5 - - altr,socfpga-arria5 - - altr,socfpga-arria10 - - const: altr,socfpga + oneOf: + - description: Arria 5 boards + items: + - enum: + - altr,socfpga-arria5-socdk + - const: altr,socfpga-arria5 + - const: altr,socfpga + + - description: Arria 10 boards + items: + - enum: + - altr,socfpga-arria10-socdk + - const: altr,socfpga-arria10 + - const: altr,socfpga + + - description: Mercury+ AA1 boards + items: + - enum: + - google,chameleon-v3 + - const: enclustra,mercury-aa1 + - const: altr,socfpga-arria10 + - const: altr,socfpga + + - description: Cyclone 5 boards + items: + - enum: + - altr,socfpga-cyclone5-socdk + - denx,mcvevk + - ebv,socrates + - macnica,sodia + - novtech,chameleon96 + - samtec,vining + - terasic,de0-atlas + - terasic,socfpga-cyclone5-sockit + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + + - description: Stratix 10 boards + items: + - enum: + - altr,socfpga-stratix10-socdk + - altr,socfpga-stratix10-swvp + - const: altr,socfpga-stratix10 + + - description: SoCFPGA VT + items: + - const: altr,socfpga-vt + - const: altr,socfpga additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/amazon,al.yaml b/Documentation/devicetree/bindings/arm/amazon,al.yaml index 0f03135d91b6..37dbb4768e5b 100644 --- a/Documentation/devicetree/bindings/arm/amazon,al.yaml +++ b/Documentation/devicetree/bindings/arm/amazon,al.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/amazon,al.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amazon's Annapurna Labs Alpine Platform Device Tree Bindings +title: Amazon's Annapurna Labs Alpine Platform maintainers: - Hanna Hawa <hhhawa@amazon.com> diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 36081734f720..9fda2436c618 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/amlogic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amlogic MesonX device tree bindings +title: Amlogic MesonX maintainers: - Kevin Hilman <khilman@baylibre.com> @@ -108,6 +108,7 @@ properties: - amlogic,p230 - amlogic,p231 - libretech,aml-s905d-pc + - osmc,vero4k-plus - phicomm,n1 - smartlabs,sml5442tw - videostrong,gxl-kii-pro @@ -119,6 +120,7 @@ properties: - enum: - amlogic,q200 - amlogic,q201 + - azw,gt1-ultimate - khadas,vim2 - kingnovel,r-box-pro - libretech,aml-s912-pc @@ -135,6 +137,7 @@ properties: - enum: - amlogic,s400 - jethome,jethub-j100 + - jethome,jethub-j110 - const: amlogic,a113d - const: amlogic,meson-axg @@ -170,9 +173,14 @@ properties: - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC items: - enum: + - amediatech,x96-air + - amediatech,x96-air-gbit - bananapi,bpi-m5 + - cyx,a95xf3-air + - cyx,a95xf3-air-gbit - hardkernel,odroid-c4 - hardkernel,odroid-hc4 + - haochuangyi,h96-max - khadas,vim3l - seirobotics,sei610 - const: amlogic,sm1 @@ -183,6 +191,12 @@ properties: - amlogic,ad401 - const: amlogic,a1 + - description: Boards with the Amlogic Meson S4 S805X2 SoC + items: + - enum: + - amlogic,aq222 + - const: amlogic,s4 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml index 6cc74523ebfd..1748f1605cc7 100644 --- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Amlogic Meson Firmware registers Interface maintainers: - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> description: | The Meson SoCs have a register bank with status and data shared with the diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 8d93e8a6cc18..7262f3c09867 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/apple.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Apple ARM Machine Device Tree Bindings +title: Apple ARM Machine maintainers: - Hector Martin <marcan@marcan.st> diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index b6b5d3a912b3..0dc957a56d35 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -42,7 +42,7 @@ patternProperties: description: The individual power management domains within this controller type: object - $ref: /power/apple,pmgr-pwrstate.yaml# + $ref: /schemas/power/apple,pmgr-pwrstate.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml index 4682f991a5c8..d28303d909e1 100644 --- a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml +++ b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM CCI Cache Coherent Interconnect Device Tree Binding +title: ARM CCI Cache Coherent Interconnect maintainers: - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> @@ -119,6 +119,11 @@ examples: arm,hbi = <0x249>; interrupt-parent = <&gic>; + gic: interrupt-controller { + interrupt-controller; + #interrupt-cells = <3>; + }; + /* * This CCI node corresponds to a CCI component whose control * registers sits at address 0x000000002c090000. @@ -166,16 +171,6 @@ examples: }; }; - dma0: dma@3000000 { - /* compatible = "arm,pl330", "arm,primecell"; */ - cci-control-port = <&cci_control0>; - reg = <0x0 0x3000000 0x0 0x1000>; - interrupts = <10>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - cci@2c090000 { compatible = "arm,cci-400"; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml new file mode 100644 index 000000000000..2bae06eed693 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Address Translation Unit (CATU) + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Address Translation Unit (CATU) translates addresses between an + AXI master and system memory. The CATU is normally used along with the TMC to + implement scattering of virtual trace buffers in physical memory. The CATU + translates contiguous Virtual Addresses (VAs) from an AXI master into + non-contiguous Physical Addresses (PAs) that are intended for system memory. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-catu + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-catu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + interrupts: + maxItems: 1 + description: Address translation error interrupt + + power-domains: + maxItems: 1 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: AXI Slave connected to another Coresight component + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + catu@207e0000 { + compatible = "arm,coresight-catu", "arm,primecell"; + reg = <0x207e0000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + in-ports { + port { + catu_in_port: endpoint { + remote-endpoint = <&etr_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml new file mode 100644 index 000000000000..0a6bc03ebe00 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight CPU Debug Component + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight CPU debug component are compliant with the ARMv8 architecture + reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The + external debug module is mainly used for two modes: self-hosted debug and + external debug, and it can be accessed from mmio region from Coresight and + eventually the debug module connects with CPU for debugging. And the debug + module provides sample-based profiling extension, which can be used to sample + CPU program counter, secure state and exception level, etc; usually every CPU + has one dedicated debug module to be connected. + +select: + properties: + compatible: + contains: + const: arm,coresight-cpu-debug + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-cpu-debug + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + cpu: + description: + A phandle to the cpu this debug component is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + description: + A phandle to the debug power domain if the debug logic has its own + dedicated power domain. CPU idle states may also need to be separately + constrained to keep CPU cores powered. + +required: + - compatible + - reg + - clocks + - clock-names + - cpu + +unevaluatedProperties: false + +examples: + - | + debug@f6590000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0xf6590000 0x1000>; + clocks = <&sys_ctrl 1>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml index 21e3515491f4..0c5b875cb654 100644 --- a/Documentation/devicetree/bindings/arm/coresight-cti.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml @@ -2,7 +2,7 @@ # Copyright 2019 Linaro Ltd. %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/coresight-cti.yaml# +$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Coresight Cross Trigger Interface (CTI) device. @@ -12,8 +12,7 @@ description: | to one or more CoreSight components and/or a CPU, with CTIs interconnected in a star topology via the Cross Trigger Matrix (CTM), which is not programmable. The ECT components are not part of the trace generation data path and are thus - not part of the CoreSight graph described in the general CoreSight bindings - file coresight.txt. + not part of the CoreSight graph. The CTI component properties define the connections between the individual CTI and the components it is directly connected to, consisting of input and @@ -99,6 +98,9 @@ properties: base cti node if compatible string arm,coresight-cti-v8-arch is used, or may appear in a trig-conns child node when appropriate. + power-domains: + maxItems: 1 + arm,cti-ctm-id: $ref: /schemas/types.yaml#/definitions/uint32 description: diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file mode 100644 index 000000000000..44a1041cb0fc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Programmable Trace Bus Funnel + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight funnel merges 2-8 trace sources into a single trace + stream with programmable enable and priority of input ports. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-dynamic-funnel + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-dynamic-funnel + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + power-domains: + maxItems: 1 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-7])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +unevaluatedProperties: false + +examples: + - | + funnel@20040000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x20040000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel_out_port0: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel_in_port2: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml new file mode 100644 index 000000000000..03792e9bd97a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Programmable Trace Bus Replicator + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight replicator splits a single trace stream into two trace streams + for systems that have more than one trace sink component. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-dynamic-replicator + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-dynamic-replicator + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + power-domains: + maxItems: 1 + + qcom,replicator-loses-context: + type: boolean + description: + Indicates that the replicator will lose register context when AMBA clock + is removed which is observed in some replicator designs. + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[01])?$': + description: Output connections to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +unevaluatedProperties: false + +examples: + - | + replicator@20120000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x20120000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&csys2_funnel_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml new file mode 100644 index 000000000000..90679788e0bf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Embedded Trace Buffer + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is + used as a circular buffer. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-etb10 + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-etb10 + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + power-domains: + maxItems: 1 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + etb@20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x20010000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file mode 100644 index 000000000000..01200f67504a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Embedded Trace MacroCell + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Embedded Trace Macrocell (ETM) is a real-time trace module providing + instruction and data tracing of a processor. + +select: + properties: + compatible: + contains: + enum: + - arm,coresight-etm3x + - arm,coresight-etm4x + - arm,coresight-etm4x-sysreg + required: + - compatible + +allOf: + - if: + not: + properties: + compatible: + contains: + const: arm,coresight-etm4x-sysreg + then: + $ref: /schemas/arm/primecell.yaml# + required: + - reg + +properties: + compatible: + oneOf: + - description: + Embedded Trace Macrocell with memory mapped access. + items: + - enum: + - arm,coresight-etm3x + - arm,coresight-etm4x + - const: arm,primecell + - description: + Embedded Trace Macrocell (version 4.x), with system register access only + const: arm,coresight-etm4x-sysreg + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + power-domains: + maxItems: 1 + + arm,coresight-loses-context-with-cpu: + type: boolean + description: + Indicates that the hardware will lose register context on CPU power down + (e.g. CPUIdle). An example of where this may be needed are systems which + contain a coresight component and CPU in the same power domain. When the + CPU powers down the coresight component also powers down and loses its + context. + + arm,cp14: + type: boolean + description: + Must be present if the system accesses ETM/PTM management registers via + co-processor 14. + + qcom,skip-power-up: + type: boolean + description: + Indicates that an implementation can skip powering up the trace unit. + TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems + since ETMs are in the same power domain as their CPU cores. This property + is required to identify such systems with hardware errata where the CPU + watchdog counter is stopped when TRCPDCR.PU is set. + + cpu: + description: + phandle to the cpu this ETM is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection from the ETM to CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - clocks + - clock-names + - cpu + - out-ports + +unevaluatedProperties: false + +examples: + - | + ptm@2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x2201c000 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x2201d000 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml new file mode 100644 index 000000000000..cc8c3baa79b4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Static Trace Bus Funnel + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight static funnel merges 2-8 trace sources into a single trace + stream. + +properties: + compatible: + const: arm,coresight-static-funnel + + power-domains: + maxItems: 1 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port@[0-7]$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + funnel { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + out-ports { + port { + combo_funnel_out: endpoint { + remote-endpoint = <&top_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + combo_funnel_in0: endpoint { + remote-endpoint = <&cluster0_etf_out>; + }; + }; + + port@1 { + reg = <1>; + combo_funnel_in1: endpoint { + remote-endpoint = <&cluster1_etf_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file mode 100644 index 000000000000..1892a091ac35 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Static Trace Bus Replicator + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight replicator splits a single trace stream into two trace streams + for systems that have more than one trace sink component. + +properties: + compatible: + const: arm,coresight-static-replicator + + power-domains: + maxItems: 1 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port@[01]$': + description: Output connections to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file mode 100644 index 000000000000..378380c3f5aa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight System Trace MacroCell + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The STM is a trace source that is integrated into a CoreSight system, designed + primarily for high-bandwidth trace of instrumentation embedded into software. + This instrumentation is made up of memory-mapped writes to the STM Advanced + eXtensible Interface (AXI) slave, which carry information about the behavior + of the software. + +select: + properties: + compatible: + contains: + const: arm,coresight-stm + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-stm + - const: arm,primecell + + reg: + maxItems: 2 + + reg-names: + items: + - const: stm-base + - const: stm-stimulus-base + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + power-domains: + maxItems: 1 + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - out-ports + +unevaluatedProperties: false + +examples: + - | + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x20100000 0x1000>, + <0x28000000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file mode 100644 index 000000000000..cb8dceaca70e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Trace Memory Controller + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace + FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration + mode (ETB, ETF, ETR) is discovered at boot time when the device is probed. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-tmc + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-tmc + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + arm,buffer-size: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: + Size of contiguous buffer space for TMC ETR (embedded trace router). The + buffer size can be configured dynamically via buffer_size property in + sysfs instead. + + arm,scatter-gather: + type: boolean + description: + Indicates that the TMC-ETR can safely use the SG mode on this system. + + arm,max-burst-size: + description: + The maximum burst size initiated by TMC on the AXI master interface. The + burst size can be in the range [0..15], the setting supports one data + transfer per burst up to a maximum of 16 data transfers per burst. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: AXI or ATB Master output connection. Used for ETR + and ETF configurations. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x20070000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator2_out_port0>; + }; + }; + }; + + out-ports { + port { + etr_out_port: endpoint { + remote-endpoint = <&catu_in_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml new file mode 100644 index 000000000000..61a0cdc27745 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Trace Port Interface Unit + +maintainers: + - Mathieu Poirier <mathieu.poirier@linaro.org> + - Mike Leach <mike.leach@linaro.org> + - Leo Yan <leo.yan@linaro.org> + - Suzuki K Poulose <suzuki.poulose@arm.com> + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Trace Port Interface Unit captures trace data from the trace bus + and outputs it to an external trace port. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-tpiu + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-tpiu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + power-domains: + maxItems: 1 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + tpiu@e3c05000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xe3c05000 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&funnel4_out_port0>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml new file mode 100644 index 000000000000..693f3fe7be60 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Corstone1000 + +maintainers: + - Vishnu Banavath <vishnu.banavath@arm.com> + - Rui Miguel Silva <rui.silva@linaro.org> + +description: |+ + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M + processors. + + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion + systems for M-Class (or other) processors for adding sensors, connectivity, + video, audio and machine learning at the edge System and security IPs to build + a secure SoC for a range of rich IoT applications, for example gateways, smart + cameras and embedded systems. + + Integrated Secure Enclave providing hardware Root of Trust and supporting + seamless integration of the optional CryptoCell™-312 cryptographic + accelerator. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA + implementation of the Corstone1000 in the MPS3 prototyping board. See + ARM document DAI0550. + items: + - const: arm,corstone1000-mps3 + - description: Corstone1000 FVP is the Fixed Virtual Platform + implementation of this system. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-fvp + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml index 7f9b2d1e1147..108460627d9a 100644 --- a/Documentation/devicetree/bindings/arm/ete.yaml +++ b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml @@ -2,7 +2,7 @@ # Copyright 2021, Arm Ltd %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/ete.yaml#" +$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: ARM Embedded Trace Extensions @@ -20,7 +20,6 @@ description: | Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to legacy CoreSight components, a node must be listed per instance, along with any optional connection graph as per the coresight bindings. - See bindings/arm/coresight.txt. properties: $nodename: @@ -34,6 +33,9 @@ properties: Handle to the cpu this ETE is bound to. $ref: /schemas/types.yaml#/definitions/phandle + power-domains: + maxItems: 1 + out-ports: description: | Output connections from the ETE to legacy CoreSight trace bus. diff --git a/Documentation/devicetree/bindings/arm/arm,integrator.yaml b/Documentation/devicetree/bindings/arm/arm,integrator.yaml index 528eee64290a..98ff5698ae1f 100644 --- a/Documentation/devicetree/bindings/arm/arm,integrator.yaml +++ b/Documentation/devicetree/bindings/arm/arm,integrator.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,integrator.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM Integrator Boards Device Tree Bindings +title: ARM Integrator Boards maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/Documentation/devicetree/bindings/arm/arm,realview.yaml b/Documentation/devicetree/bindings/arm/arm,realview.yaml index 4f9b21f49e84..8d3ed2e4ed31 100644 --- a/Documentation/devicetree/bindings/arm/arm,realview.yaml +++ b/Documentation/devicetree/bindings/arm/arm,realview.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,realview.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM RealView Boards Device Tree Bindings +title: ARM RealView Boards maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml index 4402d7bfd1fc..b1322658063a 100644 --- a/Documentation/devicetree/bindings/arm/trbe.yaml +++ b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml @@ -2,7 +2,7 @@ # Copyright 2021, Arm Ltd %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/trbe.yaml#" +$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: ARM Trace Buffer Extensions diff --git a/Documentation/devicetree/bindings/arm/arm,versatile-sysreg.yaml b/Documentation/devicetree/bindings/arm/arm,versatile-sysreg.yaml new file mode 100644 index 000000000000..491eef1e1b10 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,versatile-sysreg.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,versatile-sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Versatile system registers + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: + This is a system control registers block, providing multiple low level + platform functions like board detection and identification, software + interrupt generation, MMC and NOR Flash control, etc. + +properties: + compatible: + items: + - const: arm,versatile-sysreg + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + panel: + type: object + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/arm,versatile.yaml b/Documentation/devicetree/bindings/arm/arm,versatile.yaml index 34b437c72751..13e52ba92060 100644 --- a/Documentation/devicetree/bindings/arm/arm,versatile.yaml +++ b/Documentation/devicetree/bindings/arm/arm,versatile.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,versatile.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM Versatile Boards Device Tree Bindings +title: ARM Versatile Boards maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index a4b4452afc1d..eec190a96225 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM Versatile Express and Juno Boards Device Tree Bindings +title: ARM Versatile Express and Juno Boards maintainers: - Sudeep Holla <sudeep.holla@arm.com> diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530f1..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; - cpus = <&cpu_0>, <&cpu_1>; -}; diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml new file mode 100644 index 000000000000..217a1d674863 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed SoC based boards + +maintainers: + - Joel Stanley <joel@jms.id.au> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: AST2400 based boards + items: + - enum: + - facebook,galaxy100-bmc + - facebook,wedge100-bmc + - facebook,wedge40-bmc + - microsoft,olympus-bmc + - quanta,q71l-bmc + - tyan,palmetto-bmc + - yadro,vesnin-bmc + - const: aspeed,ast2400 + + - description: AST2500 based boards + items: + - enum: + - amd,daytonax-bmc + - amd,ethanolx-bmc + - ampere,mtjade-bmc + - aspeed,ast2500-evb + - asrock,e3c246d4i-bmc + - asrock,romed8hm3-bmc + - bytedance,g220a-bmc + - facebook,cmm-bmc + - facebook,minipack-bmc + - facebook,tiogapass-bmc + - facebook,yamp-bmc + - facebook,yosemitev2-bmc + - facebook,wedge400-bmc + - hxt,stardragon4800-rep2-bmc + - ibm,mihawk-bmc + - ibm,mowgli-bmc + - ibm,romulus-bmc + - ibm,swift-bmc + - ibm,witherspoon-bmc + - ingrasys,zaius-bmc + - inspur,fp5280g2-bmc + - inspur,nf5280m6-bmc + - inspur,on5263m5-bmc + - intel,s2600wf-bmc + - inventec,lanyang-bmc + - lenovo,hr630-bmc + - lenovo,hr855xg2-bmc + - portwell,neptune-bmc + - qcom,centriq2400-rep-bmc + - supermicro,x11spi-bmc + - tyan,s7106-bmc + - tyan,s8036-bmc + - yadro,nicole-bmc + - yadro,vegman-n110-bmc + - yadro,vegman-rx20-bmc + - yadro,vegman-sx20-bmc + - const: aspeed,ast2500 + + - description: AST2600 based boards + items: + - enum: + - ampere,mtmitchell-bmc + - aspeed,ast2600-evb + - aspeed,ast2600-evb-a1 + - facebook,bletchley-bmc + - facebook,cloudripper-bmc + - facebook,elbert-bmc + - facebook,fuji-bmc + - ibm,everest-bmc + - ibm,rainier-bmc + - ibm,tacoma-bmc + - inventec,transformer-bmc + - jabil,rbp-bmc + - nuvia,dc-scm-bmc + - quanta,s6q-bmc + - const: aspeed,ast2600 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index c612e1f48dba..2224b18801a1 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -4,11 +4,12 @@ $id: http://devicetree.org/schemas/arm/atmel-at91.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Atmel AT91 device tree bindings. +title: Atmel AT91. maintainers: - Alexandre Belloni <alexandre.belloni@bootlin.com> - - Ludovic Desroches <ludovic.desroches@microchip.com> + - Claudiu Beznea <claudiu.beznea@microchip.com> + - Nicolas Ferre <nicolas.ferre@microchip.com> description: | Boards with a SoC of the Atmel AT91 or SMART family shall have the following @@ -126,6 +127,13 @@ properties: - const: atmel,sama5d3 - const: atmel,sama5 + - description: Microchip SAMA5D3 Ethernet Development System Board + items: + - const: microchip,sama5d3-eds + - const: atmel,sama5d36 + - const: atmel,sama5d3 + - const: atmel,sama5 + - description: CalAmp LMU5000 board items: - const: calamp,lmu5000 @@ -162,9 +170,11 @@ properties: - const: microchip,sama7g5 - const: microchip,sama7 - - description: Microchip LAN9662 PCB8291 Evaluation Board. + - description: Microchip LAN9662 Evaluation Boards. items: - - const: microchip,lan9662-pcb8291 + - enum: + - microchip,lan9662-pcb8291 + - microchip,lan9662-pcb8309 - const: microchip,lan9662 - const: microchip,lan966 @@ -174,6 +184,15 @@ properties: - const: microchip,lan9668 - const: microchip,lan966 + - description: Kontron KSwitch D10 MMT series + items: + - enum: + - kontron,kswitch-d10-mmt-8g + - kontron,kswitch-d10-mmt-6g-2gs + - const: kontron,s1921 + - const: microchip,lan9668 + - const: microchip,lan966 + - items: - enum: - atmel,sams70j19 diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 16eef600d599..ab1b352344ae 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -25,21 +25,6 @@ System Timer (ST) required properties: Its subnodes can be: - watchdog: compatible should be "atmel,at91rm9200-wdt" -RSTC Reset Controller required properties: -- compatible: Should be "atmel,<chip>-rstc". - <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" - it also can be "microchip,sam9x60-rstc" -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -Example: - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - RAMC SDRAM/DDR Controller required properties: - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", diff --git a/Documentation/devicetree/bindings/arm/axxia.yaml b/Documentation/devicetree/bindings/arm/axxia.yaml index e0d2bb71cf50..d60907e43efc 100644 --- a/Documentation/devicetree/bindings/arm/axxia.yaml +++ b/Documentation/devicetree/bindings/arm/axxia.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/axxia.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Axxia AXM55xx device tree bindings +title: Axxia AXM55xx maintainers: - Anders Berg <anders.berg@lsi.com> diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 5dc48241efb3..8051a75c2c79 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -51,6 +51,7 @@ properties: - raspberrypi,3-model-b-plus - raspberrypi,3-compute-module - raspberrypi,3-compute-module-lite + - raspberrypi,model-zero-2-w - const: brcm,bcm2837 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 434d3c6db61e..958df32b4899 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -64,6 +64,7 @@ properties: - description: BCM47094 based boards items: - enum: + - asus,rt-ac88u - dlink,dir-885l - linksys,panamera - luxul,abr-4500-v1 @@ -83,9 +84,21 @@ properties: - brcm,bcm953012er - brcm,bcm953012hr - brcm,bcm953012k + - const: brcm,bcm53012 + - const: brcm,bcm4708 + + - description: BCM53015 based boards + items: + - enum: + - meraki,mr26 + - const: brcm,bcm53015 + - const: brcm,bcm4708 + + - description: BCM53016 based boards + items: + - enum: - meraki,mr32 - - const: brcm,brcm53012 - - const: brcm,brcm53016 + - const: brcm,bcm53016 - const: brcm,bcm4708 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml deleted file mode 100644 index 9b745531ff04..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Broadcom BCM4908 device tree bindings - -description: - Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs. - -maintainers: - - Rafał Miłecki <rafal@milecki.pl> - -properties: - $nodename: - const: '/' - compatible: - oneOf: - - description: BCM4906 based boards - items: - - enum: - - netgear,r8000p - - tplink,archer-c2300-v1 - - const: brcm,bcm4906 - - const: brcm,bcm4908 - - - description: BCM4908 based boards - items: - - enum: - - asus,gt-ac5300 - - netgear,raxe500 - - const: brcm,bcm4908 - - - description: BCM49408 based boards - items: - - const: brcm,bcm49408 - - const: brcm,bcm4908 - -additionalProperties: true - -... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt index 8c7a4908a849..a8866c6e9d46 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt @@ -30,7 +30,7 @@ Example: cpus { cpu@0 { - compatible = "arm,cotex-a9"; + compatible = "arm,cortex-a9"; reg = <0>; ... enable-method = "brcm,bcm63138"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml new file mode 100644 index 000000000000..84866e29cab0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC device tree bindings + +description: + Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless + chips that can be used as home gateway, router and WLAN AP for residential, + enterprise and carrier applications. + +maintainers: + - William Zhang <william.zhang@broadcom.com> + - Anand Gore <anand.gore@broadcom.com> + - Kursad Oney <kursad.oney@broadcom.com> + - Rafał Miłecki <rafal@milecki.pl> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM47622 based boards + items: + - enum: + - brcm,bcm947622 + - const: brcm,bcm47622 + - const: brcm,bcmbca + + - description: BCM4906 based boards + items: + - enum: + - netgear,r8000p + - tplink,archer-c2300-v1 + - const: brcm,bcm4906 + - const: brcm,bcm4908 + - const: brcm,bcmbca + + - description: BCM4908 based boards + items: + - enum: + - asus,gt-ac5300 + - brcm,bcm94908 + - netgear,raxe500 + - const: brcm,bcm4908 + - const: brcm,bcmbca + + - description: BCM49408 based boards + items: + - const: brcm,bcm49408 + - const: brcm,bcm4908 + - const: brcm,bcmbca + + - description: BCM4912 based boards + items: + - enum: + - asus,gt-ax6000 + - brcm,bcm94912 + - const: brcm,bcm4912 + - const: brcm,bcmbca + + - description: BCM63138 based boards + items: + - enum: + - brcm,bcm963138 + - brcm,BCM963138DVT + - const: brcm,bcm63138 + - const: brcm,bcmbca + + - description: BCM63146 based boards + items: + - enum: + - brcm,bcm963146 + - const: brcm,bcm63146 + - const: brcm,bcmbca + + - description: BCM63148 based boards + items: + - enum: + - brcm,bcm963148 + - const: brcm,bcm63148 + - const: brcm,bcmbca + + - description: BCM63158 based boards + items: + - enum: + - brcm,bcm963158 + - const: brcm,bcm63158 + - const: brcm,bcmbca + + - description: BCM63178 based boards + items: + - enum: + - brcm,bcm963178 + - const: brcm,bcm63178 + - const: brcm,bcmbca + + - description: BCM6756 based boards + items: + - enum: + - brcm,bcm96756 + - const: brcm,bcm6756 + - const: brcm,bcmbca + + - description: BCM6813 based boards + items: + - enum: + - brcm,bcm96813 + - const: brcm,bcm6813 + - const: brcm,bcmbca + + - description: BCM6846 based boards + items: + - enum: + - brcm,bcm96846 + - const: brcm,bcm6846 + - const: brcm,bcmbca + + - description: BCM6855 based boards + items: + - enum: + - brcm,bcm96855 + - const: brcm,bcm6855 + - const: brcm,bcmbca + + - description: BCM6856 based boards + items: + - enum: + - brcm,bcm96856 + - const: brcm,bcm6856 + - const: brcm,bcmbca + + - description: BCM6858 based boards + items: + - enum: + - brcm,bcm96858 + - const: brcm,bcm6858 + - const: brcm,bcmbca + + - description: BCM6878 based boards + items: + - enum: + - brcm,bcm96878 + - const: brcm,bcm6878 + - const: brcm,bcmbca + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index 104cc9b41df4..071421dbc4d0 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -187,15 +187,8 @@ Required properties: Sequencer DRAM parameters and control registers. Used for Self-Refresh Power-Down (SRPD), among other things. -Required properties: -- compatible : should contain one of these - "brcm,brcmstb-memc-ddr-rev-b.2.1" - "brcm,brcmstb-memc-ddr-rev-b.2.2" - "brcm,brcmstb-memc-ddr-rev-b.2.3" - "brcm,brcmstb-memc-ddr-rev-b.3.0" - "brcm,brcmstb-memc-ddr-rev-b.3.1" - "brcm,brcmstb-memc-ddr" -- reg : the MEMC DDR register range +See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a +full list of supported compatible strings and properties. Example: diff --git a/Documentation/devicetree/bindings/arm/bitmain.yaml b/Documentation/devicetree/bindings/arm/bitmain.yaml index 90ba02be48ce..55a5a570b5bc 100644 --- a/Documentation/devicetree/bindings/arm/bitmain.yaml +++ b/Documentation/devicetree/bindings/arm/bitmain.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/bitmain.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bitmain platform device tree bindings +title: Bitmain platform maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> diff --git a/Documentation/devicetree/bindings/arm/calxeda.yaml b/Documentation/devicetree/bindings/arm/calxeda.yaml index 46f78addebb0..3e9f5e1d862e 100644 --- a/Documentation/devicetree/bindings/arm/calxeda.yaml +++ b/Documentation/devicetree/bindings/arm/calxeda.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/calxeda.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Calxeda Platforms Device Tree Bindings +title: Calxeda Platforms maintainers: - Rob Herring <robh@kernel.org> diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt deleted file mode 100644 index f1de3247c1b7..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +++ /dev/null @@ -1,49 +0,0 @@ -* CoreSight CPU Debug Component: - -CoreSight CPU debug component are compliant with the ARMv8 architecture -reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The -external debug module is mainly used for two modes: self-hosted debug and -external debug, and it can be accessed from mmio region from Coresight -and eventually the debug module connects with CPU for debugging. And the -debug module provides sample-based profiling extension, which can be used -to sample CPU program counter, secure state and exception level, etc; -usually every CPU has one dedicated debug module to be connected. - -Required properties: - -- compatible : should be "arm,coresight-cpu-debug"; supplemented with - "arm,primecell" since this driver is using the AMBA bus - interface. - -- reg : physical base address and length of the register set. - -- clocks : the clock associated to this component. - -- clock-names : the name of the clock referenced by the code. Since we are - using the AMBA framework, the name of the clock providing - the interconnect should be "apb_pclk" and the clock is - mandatory. The interface between the debug logic and the - processor core is clocked by the internal CPU clock, so it - is enabled with CPU clock by default. - -- cpu : the CPU phandle the debug module is affined to. Do not assume it - to default to CPU0 if omitted. - -Optional properties: - -- power-domains: a phandle to the debug power domain. We use "power-domains" - binding to turn on the debug logic if it has own dedicated - power domain and if necessary to use "cpuidle.off=1" or - "nohlt" in the kernel command line or sysfs node to - constrain idle states to ensure registers in the CPU power - domain are accessible. - -Example: - - debug@f6590000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6590000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - }; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt deleted file mode 100644 index c68d93a35b6c..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ /dev/null @@ -1,402 +0,0 @@ -* CoreSight Components: - -CoreSight components are compliant with the ARM CoreSight architecture -specification and can be connected in various topologies to suit a particular -SoCs tracing needs. These trace components can generally be classified as -sinks, links and sources. Trace data produced by one or more sources flows -through the intermediate links connecting the source to the currently selected -sink. Each CoreSight component device should use these properties to describe -its hardware characteristcs. - -* Required properties for all components *except* non-configurable replicators - and non-configurable funnels: - - * compatible: These have to be supplemented with "arm,primecell" as - drivers are using the AMBA bus interface. Possible values include: - - Embedded Trace Buffer (version 1.0): - "arm,coresight-etb10", "arm,primecell"; - - - Trace Port Interface Unit: - "arm,coresight-tpiu", "arm,primecell"; - - - Trace Memory Controller, used for Embedded Trace Buffer(ETB), - Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) - configuration. The configuration mode (ETB, ETF, ETR) is - discovered at boot time when the device is probed. - "arm,coresight-tmc", "arm,primecell"; - - - Trace Programmable Funnel: - "arm,coresight-dynamic-funnel", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For - backward compatibility and will be removed) - - - Embedded Trace Macrocell (version 3.x) and - Program Flow Trace Macrocell: - "arm,coresight-etm3x", "arm,primecell"; - - - Embedded Trace Macrocell (version 4.x), with memory mapped access. - "arm,coresight-etm4x", "arm,primecell"; - - - Embedded Trace Macrocell (version 4.x), with system register access only. - "arm,coresight-etm4x-sysreg"; - - - Coresight programmable Replicator : - "arm,coresight-dynamic-replicator", "arm,primecell"; - - - System Trace Macrocell: - "arm,coresight-stm", "arm,primecell"; [1] - - Coresight Address Translation Unit (CATU) - "arm,coresight-catu", "arm,primecell"; - - - Coresight Cross Trigger Interface (CTI): - "arm,coresight-cti", "arm,primecell"; - See coresight-cti.yaml for full CTI definitions. - - * reg: physical base address and length of the register - set(s) of the component. - - * clocks: the clocks associated to this component. - - * clock-names: the name of the clocks referenced by the code. - Since we are using the AMBA framework, the name of the clock - providing the interconnect should be "apb_pclk", and some - coresight blocks also have an additional clock "atclk", which - clocks the core of that coresight component. The latter clock - is optional. - - * port or ports: see "Graph bindings for Coresight" below. - -* Additional required property for Embedded Trace Macrocell (version 3.x and - version 4.x): - * cpu: the cpu phandle this ETM/PTM is affined to. Do not - assume it to default to CPU0 if omitted. - -* Additional required properties for System Trace Macrocells (STM): - * reg: along with the physical base address and length of the register - set as described above, another entry is required to describe the - mapping of the extended stimulus port area. - - * reg-names: the only acceptable values are "stm-base" and - "stm-stimulus-base", each corresponding to the areas defined in "reg". - -* Required properties for Coresight Cross Trigger Interface (CTI) - See coresight-cti.yaml for full CTI definitions. - -* Required properties for devices that don't show up on the AMBA bus, such as - non-configurable replicators and non-configurable funnels: - - * compatible: Currently supported value is (note the absence of the - AMBA markee): - - Coresight Non-configurable Replicator: - "arm,coresight-static-replicator"; - "arm,coresight-replicator"; (OBSOLETE. For backward - compatibility and will be removed) - - - Coresight Non-configurable Funnel: - "arm,coresight-static-funnel"; - - * port or ports: see "Graph bindings for Coresight" below. - -* Optional properties for all components: - - * arm,coresight-loses-context-with-cpu : boolean. Indicates that the - hardware will lose register context on CPU power down (e.g. CPUIdle). - An example of where this may be needed are systems which contain a - coresight component and CPU in the same power domain. When the CPU - powers down the coresight component also powers down and loses its - context. This property is currently only used for the ETM 4.x driver. - -* Optional properties for ETM/PTMs: - - * arm,cp14: must be present if the system accesses ETM/PTM management - registers via co-processor 14. - - * qcom,skip-power-up: boolean. Indicates that an implementation can - skip powering up the trace unit. TRCPDCR.PU does not have to be set - on Qualcomm Technologies Inc. systems since ETMs are in the same power - domain as their CPU cores. This property is required to identify such - systems with hardware errata where the CPU watchdog counter is stopped - when TRCPDCR.PU is set. - -* Optional property for TMC: - - * arm,buffer-size: size of contiguous buffer space for TMC ETR - (embedded trace router). This property is obsolete. The buffer size - can be configured dynamically via buffer_size property in sysfs. - - * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely - use the SG mode on this system. - - * arm,max-burst-size: The maximum burst size initiated by TMC on the - AXI master interface. The burst size can be in the range [0..15], - the setting supports one data transfer per burst up to a maximum of - 16 data transfers per burst. - -* Optional property for CATU : - * interrupts : Exactly one SPI may be listed for reporting the address - error - -* Optional property for configurable replicators: - - * qcom,replicator-loses-context: boolean. Indicates that the replicator - will lose register context when AMBA clock is removed which is observed - in some replicator designs. - -Graph bindings for Coresight -------------------------------- - -Coresight components are interconnected to create a data path for the flow of -trace data generated from the "sources" to their collection points "sink". -Each coresight component must describe the "input" and "output" connections. -The connections must be described via generic DT graph bindings as described -by the "bindings/graph.txt", where each "port" along with an "endpoint" -component represents a hardware port and the connection. - - * All output ports must be listed inside a child node named "out-ports" - * All input ports must be listed inside a child node named "in-ports". - * Port address must match the hardware port number. - -Example: - -1. Sinks - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in_port: endpoint@0 { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint@0 { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etr_in_port: endpoint { - remote-endpoint = <&replicator2_out_port0>; - }; - }; - }; - - out-ports { - port { - etr_out_port: endpoint { - remote-endpoint = <&catu_in_port>; - }; - }; - }; - }; - -2. Links - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel { - /* - * non-configurable funnel don't show up on the AMBA - * bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-funnel"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - combo_funnel_out: endpoint { - remote-endpoint = <&top_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - combo_funnel_in0: endpoint { - remote-endpoint = <&cluster0_etf_out>; - }; - }; - - port@1 { - reg = <1>; - combo_funnel_in1: endpoint { - remote-endpoint = <&cluster1_etf_out>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - }; - }; - -3. Sources - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - -4. STM - stm@20100000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x20100000 0 0x1000>, - <0 0x28000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - stm_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port2>; - }; - }; - }; - }; - -5. CATU - - catu@207e0000 { - compatible = "arm,coresight-catu", "arm,primecell"; - reg = <0 0x207e0000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - in-ports { - port { - catu_in_port: endpoint { - remote-endpoint = <&etr_out_port>; - }; - }; - }; - }; - -[1]. There is currently two version of STM: STM32 and STM500. Both -have the same HW interface and as such don't need an explicit binding name. diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/arm/cpu-capacity.txt index 380e21c5fc7e..cc5e190390b7 100644 --- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt +++ b/Documentation/devicetree/bindings/arm/cpu-capacity.txt @@ -62,8 +62,8 @@ Example 1 (ARM 64-bit, 6-cpu system, two clusters): The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024) are 1024 and 578 for cluster0 and cluster1. Further normalization is done by the operating system based on cluster0@max-freq=1100 and -custer1@max-freq=850, final capacities are 1024 for cluster0 and -446 for cluster1 (576*850/1100). +cluster1@max-freq=850, final capacities are 1024 for cluster0 and +446 for cluster1 (578*850/1100). cpus { #address-cells = <2>; diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index dfa28e3525cb..5c13b73e4d57 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -137,6 +137,10 @@ properties: - arm,cortex-a75 - arm,cortex-a76 - arm,cortex-a77 + - arm,cortex-a78 + - arm,cortex-a78ae + - arm,cortex-a510 + - arm,cortex-a710 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -145,8 +149,12 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,cortex-x1 + - arm,cortex-x2 - arm,neoverse-e1 - arm,neoverse-n1 + - arm,neoverse-n2 + - arm,neoverse-v1 - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan @@ -166,6 +174,8 @@ properties: - nvidia,tegra194-carmel - qcom,krait - qcom,kryo + - qcom,kryo240 + - qcom,kryo250 - qcom,kryo260 - qcom,kryo280 - qcom,kryo385 @@ -213,6 +223,7 @@ properties: - qcom,kpss-acc-v1 - qcom,kpss-acc-v2 - qcom,msm8226-smp + - qcom,msm8909-smp # Only valid on ARM 32-bit, see above for ARM v8 64-bit - qcom,msm8916-smp - renesas,apmu @@ -225,17 +236,19 @@ properties: - ti,am4372 cpu-release-addr: - $ref: '/schemas/types.yaml#/definitions/uint64' - + oneOf: + - $ref: '/schemas/types.yaml#/definitions/uint32' + - $ref: '/schemas/types.yaml#/definitions/uint64' description: + The DT specification defines this as 64-bit always, but some 32-bit Arm + systems have used a 32-bit value which must be supported. Required for systems that have an "enable-method" property value of "spin-table". - On ARM v8 64-bit systems must be a two cell - property identifying a 64-bit zero-initialised - memory location. cpu-idle-states: $ref: '/schemas/types.yaml#/definitions/phandle-array' + items: + maxItems: 1 description: | List of phandles to idle state nodes supported by this cpu (see ./idle-states.yaml). diff --git a/Documentation/devicetree/bindings/arm/digicolor.yaml b/Documentation/devicetree/bindings/arm/digicolor.yaml index a35de3c9e284..0cf9ddaa527e 100644 --- a/Documentation/devicetree/bindings/arm/digicolor.yaml +++ b/Documentation/devicetree/bindings/arm/digicolor.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/digicolor.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Conexant Digicolor Platforms Device Tree Bindings +title: Conexant Digicolor Platforms maintainers: - Baruch Siach <baruch@tkos.co.il> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt deleted file mode 100644 index b5cb374dc47d..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt +++ /dev/null @@ -1,19 +0,0 @@ -Freescale DCFG - -DCFG is the device configuration unit, that provides general purpose -configuration and status for the device. Such as setting the secondary -core start address and release the secondary core from holdoff and startup. - -Required properties: - - compatible: Should contain a chip-specific compatible string, - Chip-specific strings are of the form "fsl,<chip>-dcfg", - The following <chip>s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - - - reg : should contain base address and length of DCFG memory-mapped registers - -Example: - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1021a-dcfg"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt deleted file mode 100644 index 0ab67b0b216d..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt +++ /dev/null @@ -1,19 +0,0 @@ -Freescale SCFG - -SCFG is the supplemental configuration unit, that provides SoC specific -configuration and status registers for the chip. Such as getting PEX port -status. - -Required properties: - - compatible: Should contain a chip-specific compatible string, - Chip-specific strings are of the form "fsl,<chip>-scfg", - The following <chip>s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - - - reg: should contain base address and length of SCFG memory-mapped registers - -Example: - scfg: scfg@1570000 { - compatible = "fsl,ls1021a-scfg"; - reg = <0x0 0x1570000 0x0 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt deleted file mode 100644 index fd0061712443..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ /dev/null @@ -1,270 +0,0 @@ -NXP i.MX System Controller Firmware (SCFW) --------------------------------------------------------------------- - -The System Controller Firmware (SCFW) is a low-level system function -which runs on a dedicated Cortex-M core to provide power, clock, and -resource management. It exists on some i.MX8 processors. e.g. i.MX8QM -(QM, QP), and i.MX8QX (QXP, DX). - -The AP communicates with the SC using a multi-ported MU module found -in the LSIO subsystem. The current definition of this MU module provides -5 remote AP connections to the SC to support up to 5 execution environments -(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces -with the LSIO DSC IP bus. The SC firmware will communicate with this MU -using the MSI bus. - -System Controller Device Node: -============================================================ - -The scu node with the following properties shall be under the /firmware/ node. - -Required properties: -------------------- -- compatible: should be "fsl,imx-scu". -- mbox-names: should include "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3"; - include "gip3" if want to support general MU interrupt. -- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for - rx, and 1 optional MU channel for general interrupt. - All MU channels must be in the same MU instance. - Cross instances are not allowed. The MU instance can only - be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need - to make sure use the one which is not conflict with other - execution environments. e.g. ATF. - Note: - Channel 0 must be "tx0" or "rx0". - Channel 1 must be "tx1" or "rx1". - Channel 2 must be "tx2" or "rx2". - Channel 3 must be "tx3" or "rx3". - General interrupt rx channel must be "gip3". - e.g. - mboxes = <&lsio_mu1 0 0 - &lsio_mu1 0 1 - &lsio_mu1 0 2 - &lsio_mu1 0 3 - &lsio_mu1 1 0 - &lsio_mu1 1 1 - &lsio_mu1 1 2 - &lsio_mu1 1 3 - &lsio_mu1 3 3>; - See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml - for detailed mailbox binding. - -Note: Each mu which supports general interrupt should have an alias correctly -numbered in "aliases" node. -e.g. -aliases { - mu1 = &lsio_mu1; -}; - -i.MX SCU Client Device Node: -============================================================ - -Client nodes are maintained as children of the relevant IMX-SCU device node. - -Power domain bindings based on SCU Message Protocol ------------------------------------------------------------- - -This binding for the SCU power domain providers uses the generic power -domain binding[2]. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-scu-pd", - "fsl,imx8qxp-scu-pd" - followed by "fsl,scu-pd" - -- #power-domain-cells: Must be 1. Contains the Resource ID used by - SCU commands. - See detailed Resource ID list from: - include/dt-bindings/firmware/imx/rsrc.h - -Clock bindings based on SCU Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-clk" - "fsl,imx8qxp-clk" - followed by "fsl,scu-clk" -- #clock-cells: Should be 2. - Contains the Resource and Clock ID value. -- clocks: List of clock specifiers, must contain an entry for - each required entry in clock-names -- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. - -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h - -Pinctrl bindings based on SCU Message Protocol ------------------------------------------------------------- - -This binding uses the i.MX common pinctrl binding[3]. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-iomuxc", - "fsl,imx8qxp-iomuxc", - "fsl,imx8dxl-iomuxc". - -Required properties for Pinctrl sub nodes: -- fsl,pins: Each entry consists of 3 integers which represents - the mux and config setting for one pin. The first 2 - integers <pin_id mux_mode> are specified using a - PIN_FUNC_ID macro, which can be found in - <dt-bindings/pinctrl/pads-imx8qm.h>, - <dt-bindings/pinctrl/pads-imx8qxp.h>, - <dt-bindings/pinctrl/pads-imx8dxl.h>. - The last integer CONFIG is the pad setting value like - pull-up on this pin. - - Please refer to i.MX8QXP Reference Manual for detailed - CONFIG settings. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/power/power-domain.yaml -[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt - -RTC bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: should be "fsl,imx8qxp-sc-rtc"; - -OCOTP bindings based on SCU Message Protocol ------------------------------------------------------------- -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-scu-ocotp", - "fsl,imx8qxp-scu-ocotp". -- #address-cells: Must be 1. Contains byte index -- #size-cells: Must be 1. Contains byte length - -Optional Child nodes: - -- Data cells of ocotp: - Detailed bindings are described in bindings/nvmem/nvmem.txt - -Watchdog bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: should be: - "fsl,imx8qxp-sc-wdt" - followed by "fsl,imx-sc-wdt"; -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -SCU key bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: should be: - "fsl,imx8qxp-sc-key" - followed by "fsl,imx-sc-key"; -- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml - -Thermal bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: Should be : - "fsl,imx8qxp-sc-thermal" - followed by "fsl,imx-sc-thermal"; - -- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml - for a description. - -Example (imx8qxp): -------------- -aliases { - mu1 = &lsio_mu1; -}; - -lsio_mu1: mailbox@5d1c0000 { - ... - #mbox-cells = <2>; -}; - -firmware { - scu { - compatible = "fsl,imx-scu"; - mbox-names = "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3", - "gip3"; - mboxes = <&lsio_mu1 0 0 - &lsio_mu1 0 1 - &lsio_mu1 0 2 - &lsio_mu1 0 3 - &lsio_mu1 1 0 - &lsio_mu1 1 1 - &lsio_mu1 1 2 - &lsio_mu1 1 3 - &lsio_mu1 3 3>; - - clk: clk { - compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <2>; - }; - - iomuxc { - compatible = "fsl,imx8qxp-iomuxc"; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 - SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - ... - }; - - ocotp: imx8qx-ocotp { - compatible = "fsl,imx8qxp-scu-ocotp"; - #address-cells = <1>; - #size-cells = <1>; - - fec_mac0: mac@2c4 { - reg = <0x2c4 8>; - }; - }; - - pd: imx8qx-pd { - compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; - #power-domain-cells = <1>; - }; - - rtc: rtc { - compatible = "fsl,imx8qxp-sc-rtc"; - }; - - scu_key: scu-key { - compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; - linux,keycodes = <KEY_POWER>; - }; - - watchdog { - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; - timeout-sec = <60>; - }; - - tsens: thermal-sensor { - compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; - #thermal-sensor-cells = <1>; - }; - }; -}; - -serial@5a060000 { - ... - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_UART_0>; -}; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 97f6eebad76a..fbfc4f99c01e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/fsl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale i.MX Platforms Device Tree Bindings +title: Freescale i.MX Platforms maintainers: - Shawn Guo <shawnguo@kernel.org> @@ -172,7 +172,7 @@ properties: - karo,tx53 # Ka-Ro electronics TX53 module - kiebackpeter,imx53-ddc # K+P imx53 DDC - kiebackpeter,imx53-hsc # K+P imx53 HSC - - menlo,m53menlo + - menlo,m53menlo # i.MX53 Menlo board - voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668 - const: fsl,imx53 @@ -192,6 +192,7 @@ properties: items: - enum: - auvidea,h100 # Auvidea H100 + - bosch,imx6q-acc # Bosch ACC i.MX6 Dual - boundary,imx6q-nitrogen6_max - boundary,imx6q-nitrogen6_som2 - boundary,imx6q-nitrogen6x @@ -320,6 +321,7 @@ properties: - enum: - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board + - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board - const: toradex,apalis_imx6q - const: fsl,imx6q @@ -411,7 +413,6 @@ properties: - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - toradex,colibri_imx6dl # Colibri iMX6 Modules - - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board @@ -488,17 +489,13 @@ properties: - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules items: - enum: + - toradex,colibri_imx6dl-aster # Colibri iMX6DL/S Module on Aster Board - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3 + - toradex,colibri_imx6dl-iris # Colibri iMX6DL/S Module on Iris Board + - toradex,colibri_imx6dl-iris-v2 # Colibri iMX6DL/S Module on Iris Board V2 - const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module - const: fsl,imx6dl - - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules - items: - - enum: - - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3 - - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module - - const: fsl,imx6dl - - description: i.MX6S DHCOM DRC02 Board items: - const: dh,imx6s-dhcom-drc02 @@ -557,8 +554,7 @@ properties: - engicam,imx6ul-isiot # Engicam Is.IoT MX6UL eMMC/NAND Starter kit - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board - karo,imx6ul-tx6ul # Ka-Ro electronics TXUL-0010 Module - - kontron,imx6ul-n6310-som # Kontron N6310 SOM - - kontron,imx6ul-n6311-som # Kontron N6311 SOM + - kontron,sl-imx6ul # Kontron SL i.MX6UL SoM - prt,prti6g # Protonic PRTI6G Board - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit @@ -594,23 +590,39 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul - - description: Kontron N6310 S Board + - description: Kontron BL i.MX6UL (N631X S) Board + items: + - const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board + - const: kontron,sl-imx6ul # Kontron SL i.MX6UL SoM + - const: fsl,imx6ul + + - description: Kontron BL i.MX6UL 43 (N631X S 43) Board + items: + - const: kontron,bl-imx6ul-43 # Kontron BL i.MX6UL Carrier Board with 4.3" Display + - const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board + - const: kontron,sl-imx6ul # Kontron SL i.MX6UL SoM + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board items: - - const: kontron,imx6ul-n6310-s - - const: kontron,imx6ul-n6310-som + - enum: + - tq,imx6ul-tqma6ul1-mba6ulx + - const: tq,imx6ul-tqma6ul1 # MCIMX6G1 - const: fsl,imx6ul - - description: Kontron N6311 S Board + - description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board items: - - const: kontron,imx6ul-n6311-s - - const: kontron,imx6ul-n6311-som + - enum: + - tq,imx6ul-tqma6ul2-mba6ulx + - const: tq,imx6ul-tqma6ul2 # MCIMX6G2 - const: fsl,imx6ul - - description: Kontron N6310 S 43 Board + - description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board items: - - const: kontron,imx6ul-n6310-s-43 - - const: kontron,imx6ul-n6310-s - - const: kontron,imx6ul-n6310-som + - enum: + - tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter + - tq,imx6ul-tqma6ul2l-mba6ulxl + - const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant - const: fsl,imx6ul - description: i.MX6ULL based Boards @@ -618,7 +630,7 @@ properties: - enum: - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board - joz,jozacp # JOZ Access Point - - kontron,imx6ull-n6411-som # Kontron N6411 SOM + - kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - toradex,colibri-imx6ull # Colibri iMX6ULL Modules - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module @@ -640,31 +652,64 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyGATE-Tauri + items: + - enum: + - phytec,imx6ull-phygate-tauri-emmc + - phytec,imx6ull-phygate-tauri-nand + - const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL + - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: - - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board + - toradex,colibri-imx6ull-aster # Aster Carrier Board + - toradex,colibri-imx6ull-eval # Colibri Evaluation Board V3 + - toradex,colibri-imx6ull-iris # Iris Carrier Board + - toradex,colibri-imx6ull-iris-v2 # Iris V2 Carrier Board - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module - - const: fsl,imx6dl + - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module items: - enum: - - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board - - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - - const: fsl,imx6dl + - toradex,colibri-imx6ull-emmc-aster # Aster Carrier Board + - toradex,colibri-imx6ull-emmc-eval # Colibri Evaluation B. V3 + - toradex,colibri-imx6ull-emmc-iris # Iris Carrier Board + - toradex,colibri-imx6ull-emmc-iris-v2 # Iris V2 Carrier Board + - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module + - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules items: - enum: - - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board - - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module - - const: fsl,imx6dl + - toradex,colibri-imx6ull-wifi-eval # Colibri Eval. B. V3 + - toradex,colibri-imx6ull-wifi-aster # Aster Carrier Board + - toradex,colibri-imx6ull-wifi-iris # Iris Carrier Board + - toradex,colibri-imx6ull-wifi-iris-v2 # Iris V2 Carrier Board + - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module + - const: fsl,imx6ull + + - description: Kontron BL i.MX6ULL (N6411 S) Board + items: + - const: kontron,bl-imx6ull # Kontron BL i.MX6ULL Carrier Board + - const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM + - const: fsl,imx6ull + + - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board + items: + - enum: + - tq,imx6ull-tqma6ull2-mba6ulx + - const: tq,imx6ull-tqma6ull2 # MCIMX6Y2 + - const: fsl,imx6ull - - description: Kontron N6411 S Board + - description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board items: - - const: kontron,imx6ull-n6411-s - - const: kontron,imx6ull-n6411-som + - enum: + - tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter + - tq,imx6ull-tqma6ull2l-mba6ulxl + - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant - const: fsl,imx6ull - description: i.MX6ULZ based Boards @@ -687,6 +732,8 @@ properties: - enum: - toradex,colibri-imx7s-aster # Module on Aster Carrier Board - toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7s-iris # Module on Iris Carrier Board + - toradex,colibri-imx7s-iris-v2 # Module on Iris Carrier Board V2 - const: toradex,colibri-imx7s - const: fsl,imx7s @@ -707,6 +754,7 @@ properties: - kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board - remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet + - storopack,imx7d-smegw01 # Storopack i.MX7D SMEGW01 - technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph @@ -737,8 +785,10 @@ properties: - description: i.MX7D Boards with Toradex Colibri i.MX7D Module items: - enum: - - toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board - - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7d-aster # Aster Carrier Board + - toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3 + - toradex,colibri-imx7d-iris # Iris Carrier Board + - toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2 - const: toradex,colibri-imx7d - const: fsl,imx7d @@ -747,6 +797,8 @@ properties: - enum: - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board - toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7d-emmc-iris # Module on Iris Carrier Board + - toradex,colibri-imx7d-emmc-iris-v2 # Module on Iris Carrier Board V2 - const: toradex,colibri-imx7d-emmc - const: fsl,imx7d @@ -762,15 +814,25 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board + - dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC + - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board + - gateworks,imx8mm-gw7904 - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM + - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board + - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM + - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM + - menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM + - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules + - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT + - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module + - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm - description: Engicam i.Core MX8M Mini SoM based boards @@ -783,8 +845,38 @@ properties: - description: Kontron BL i.MX8MM (N801X S) Board items: - - const: kontron,imx8mm-n801x-s - - const: kontron,imx8mm-n801x-som + - const: kontron,imx8mm-bl + - const: kontron,imx8mm-sl + - const: fsl,imx8mm + + - description: Kontron BL i.MX8MM OSM-S (N802X S) Board + items: + - const: kontron,imx8mm-bl-osm-s + - const: kontron,imx8mm-osm-s + - const: fsl,imx8mm + + - description: Toradex Boards with Verdin iMX8M Mini Modules + items: + - enum: + - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia + - toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board + - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT + - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module + - const: fsl,imx8mm + + - description: Toradex Boards with Verdin iMX8M Mini Wi-Fi / BT Modules + items: + - enum: + - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia + - toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B. + - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module + - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module + - const: fsl,imx8mm + + - description: PHYTEC phyCORE-i.MX8MM SoM based boards + items: + - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK + - const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM - const: fsl,imx8mm - description: Variscite VAR-SOM-MX8MM based boards @@ -810,6 +902,7 @@ properties: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO + - fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board @@ -835,7 +928,27 @@ properties: - description: i.MX8MP based Boards items: - enum: + - dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM + - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board - fsl,imx8mp-evk # i.MX8MP EVK Board + - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board + - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules + - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT + - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules + - const: fsl,imx8mp + + - description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules + items: + - const: avnet,sm2s-imx8mp-14N0600E-ep1 # SM2S-IMX8PLUS-14N0600E on SM2-MB-EP1 Carrier Board + - const: avnet,sm2s-imx8mp-14N0600E # 14N0600E variant of SM2S-IMX8PLUS SoM + - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM + - const: fsl,imx8mp + + - description: Engicam i.Core MX8M Plus SoM based boards + items: + - enum: + - engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit + - const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM - const: fsl,imx8mp - description: PHYTEC phyCORE-i.MX8MP SoM based boards @@ -844,6 +957,36 @@ properties: - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM - const: fsl,imx8mp + - description: Toradex Boards with Verdin iMX8M Plus Modules + items: + - enum: + - toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia + - toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board + - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT + - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module + - const: fsl,imx8mp + + - description: Toradex Boards with Verdin iMX8M Plus Wi-Fi / BT Modules + items: + - enum: + - toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia + - toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B. + - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module + - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module + - const: fsl,imx8mp + + - description: + TQMa8MPxL is a series of LGA SOM featuring NXP i.MX8MP system-on-chip + variants. It is designed to be soldered on different carrier boards. + All CPU variants use the same device tree hence only one compatible + is needed. MBa8MPxL mainboard can be used as starterkit or in a boxed + version as an industrial computing device. + items: + - enum: + - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL + - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM + - const: fsl,imx8mp + - description: i.MX8MQ based Boards items: - enum: @@ -899,6 +1042,12 @@ properties: - toradex,colibri-imx8x # Colibri iMX8X Modules - const: fsl,imx8qxp + - description: i.MX8DXL based Boards + items: + - enum: + - fsl,imx8dxl-evk # i.MX8DXL EVK Board + - const: fsl,imx8dxl + - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules items: - enum: @@ -912,6 +1061,12 @@ properties: - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp + - description: i.MX93 based Boards + items: + - enum: + - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings @@ -975,6 +1130,7 @@ properties: - description: LS1021A based Boards items: - enum: + - fsl,ls1021a-iot - fsl,ls1021a-moxa-uc-8410a - fsl,ls1021a-qds - fsl,ls1021a-tsn diff --git a/Documentation/devicetree/bindings/arm/fw-cfg.txt b/Documentation/devicetree/bindings/arm/fw-cfg.txt deleted file mode 100644 index fd54e1db2156..000000000000 --- a/Documentation/devicetree/bindings/arm/fw-cfg.txt +++ /dev/null @@ -1,38 +0,0 @@ -* QEMU Firmware Configuration bindings for ARM - -QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets -provide the following Firmware Configuration interface on the "virt" machine -type: - -- A write-only, 16-bit wide selector (or control) register, -- a read-write, 64-bit wide data register. - -QEMU exposes the control and data register to ARM guests as memory mapped -registers; their location is communicated to the guest's UEFI firmware in the -DTB that QEMU places at the bottom of the guest's DRAM. - -The authoritative guest-side hardware interface documentation to the fw_cfg -device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. - - -Required properties: - -- compatible: "qemu,fw-cfg-mmio". - -- reg: the MMIO region used by the device. - * Bytes 0x0 to 0x7 cover the data register. - * Bytes 0x8 to 0x9 cover the selector register. - * Further registers may be appended to the region in case of future interface - revisions / feature bits. - -Example: - -/ { - #size-cells = <0x2>; - #address-cells = <0x2>; - - fw-cfg@9020000 { - compatible = "qemu,fw-cfg-mmio"; - reg = <0x0 0x9020000 0x0 0xa>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml index 7378159e61df..483caf0ce25b 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml @@ -17,14 +17,15 @@ properties: - const: hisilicon,hip04-bootwrapper boot-method: + $ref: /schemas/types.yaml#/definitions/uint32-array description: | Address and size of boot method. [0]: bootwrapper physical address [1]: bootwrapper size [2]: relocation physical address [3]: relocation size - minItems: 1 - maxItems: 2 + minItems: 2 + maxItems: 4 required: - compatible diff --git a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml new file mode 100644 index 000000000000..224bbcb93f95 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hpe,gxp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE BMC GXP platforms + +maintainers: + - Nick Hawkins <nick.hawkins@hpe.com> + - Jean-Marie Verdun <verdun@hpe.com> + +properties: + compatible: + oneOf: + - description: GXP Based Boards + items: + - enum: + - hpe,gxp-dl360gen10 + - const: hpe,gxp + +required: + - compatible + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/idle-states.yaml b/Documentation/devicetree/bindings/arm/idle-states.yaml deleted file mode 100644 index 52bce5dbb11f..000000000000 --- a/Documentation/devicetree/bindings/arm/idle-states.yaml +++ /dev/null @@ -1,661 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/idle-states.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: ARM idle states binding description - -maintainers: - - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> - -description: |+ - ========================================== - 1 - Introduction - ========================================== - - ARM systems contain HW capable of managing power consumption dynamically, - where cores can be put in different low-power states (ranging from simple wfi - to power gating) according to OS PM policies. The CPU states representing the - range of dynamic idle states that a processor can enter at run-time, can be - specified through device tree bindings representing the parameters required to - enter/exit specific idle states on a given processor. - - According to the Server Base System Architecture document (SBSA, [3]), the - power states an ARM CPU can be put into are identified by the following list: - - - Running - - Idle_standby - - Idle_retention - - Sleep - - Off - - The power states described in the SBSA document define the basic CPU states on - top of which ARM platforms implement power management schemes that allow an OS - PM implementation to put the processor in different idle states (which include - states listed above; "off" state is not an idle state since it does not have - wake-up capabilities, hence it is not considered in this document). - - Idle state parameters (e.g. entry latency) are platform specific and need to - be characterized with bindings that provide the required information to OS PM - code so that it can build the required tables and use them at runtime. - - The device tree binding definition for ARM idle states is the subject of this - document. - - =========================================== - 2 - idle-states definitions - =========================================== - - Idle states are characterized for a specific system through a set of - timing and energy related properties, that underline the HW behaviour - triggered upon idle states entry and exit. - - The following diagram depicts the CPU execution phases and related timing - properties required to enter and exit an idle state: - - ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. - | | | | | - - |<------ entry ------->| - | latency | - |<- exit ->| - | latency | - |<-------- min-residency -------->| - |<------- wakeup-latency ------->| - - Diagram 1: CPU idle state execution phases - - EXEC: Normal CPU execution. - - PREP: Preparation phase before committing the hardware to idle mode - like cache flushing. This is abortable on pending wake-up - event conditions. The abort latency is assumed to be negligible - (i.e. less than the ENTRY + EXIT duration). If aborted, CPU - goes back to EXEC. This phase is optional. If not abortable, - this should be included in the ENTRY phase instead. - - ENTRY: The hardware is committed to idle mode. This period must run - to completion up to IDLE before anything else can happen. - - IDLE: This is the actual energy-saving idle period. This may last - between 0 and infinite time, until a wake-up event occurs. - - EXIT: Period during which the CPU is brought back to operational - mode (EXEC). - - entry-latency: Worst case latency required to enter the idle state. The - exit-latency may be guaranteed only after entry-latency has passed. - - min-residency: Minimum period, including preparation and entry, for a given - idle state to be worthwhile energywise. - - wakeup-latency: Maximum delay between the signaling of a wake-up event and the - CPU being able to execute normal code again. If not specified, this is assumed - to be entry-latency + exit-latency. - - These timing parameters can be used by an OS in different circumstances. - - An idle CPU requires the expected min-residency time to select the most - appropriate idle state based on the expected expiry time of the next IRQ - (i.e. wake-up) that causes the CPU to return to the EXEC phase. - - An operating system scheduler may need to compute the shortest wake-up delay - for CPUs in the system by detecting how long will it take to get a CPU out - of an idle state, e.g.: - - wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) - - In other words, the scheduler can make its scheduling decision by selecting - (e.g. waking-up) the CPU with the shortest wake-up delay. - The wake-up delay must take into account the entry latency if that period - has not expired. The abortable nature of the PREP period can be ignored - if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than - the worst case since it depends on the CPU operating conditions, i.e. caches - state). - - An OS has to reliably probe the wakeup-latency since some devices can enforce - latency constraint guarantees to work properly, so the OS has to detect the - worst case wake-up latency it can incur if a CPU is allowed to enter an - idle state, and possibly to prevent that to guarantee reliable device - functioning. - - The min-residency time parameter deserves further explanation since it is - expressed in time units but must factor in energy consumption coefficients. - - The energy consumption of a cpu when it enters a power state can be roughly - characterised by the following graph: - - | - | - | - e | - n | /--- - e | /------ - r | /------ - g | /----- - y | /------ - | ---- - | /| - | / | - | / | - | / | - | / | - | / | - |/ | - -----|-------+---------------------------------- - 0| 1 time(ms) - - Graph 1: Energy vs time example - - The graph is split in two parts delimited by time 1ms on the X-axis. - The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope - and denotes the energy costs incurred while entering and leaving the idle - state. - The graph curve in the area delimited by X-axis values = {x | x > 1ms } has - shallower slope and essentially represents the energy consumption of the idle - state. - - min-residency is defined for a given idle state as the minimum expected - residency time for a state (inclusive of preparation and entry) after - which choosing that state become the most energy efficient option. A good - way to visualise this, is by taking the same graph above and comparing some - states energy consumptions plots. - - For sake of simplicity, let's consider a system with two idle states IDLE1, - and IDLE2: - - | - | - | - | /-- IDLE1 - e | /--- - n | /---- - e | /--- - r | /-----/--------- IDLE2 - g | /-------/--------- - y | ------------ /---| - | / /---- | - | / /--- | - | / /---- | - | / /--- | - | --- | - | / | - | / | - |/ | time - ---/----------------------------+------------------------ - |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy - | - IDLE2-min-residency - - Graph 2: idle states min-residency example - - In graph 2 above, that takes into account idle states entry/exit energy - costs, it is clear that if the idle state residency time (i.e. time till next - wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state - choice energywise. - - This is mainly down to the fact that IDLE1 entry/exit energy costs are lower - than IDLE2. - - However, the lower power consumption (i.e. shallower energy curve slope) of - idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy - efficient. - - The time at which IDLE2 becomes more energy efficient than IDLE1 (and other - shallower states in a system with multiple idle states) is defined - IDLE2-min-residency and corresponds to the time when energy consumption of - IDLE1 and IDLE2 states breaks even. - - The definitions provided in this section underpin the idle states - properties specification that is the subject of the following sections. - - =========================================== - 3 - idle-states node - =========================================== - - ARM processor idle states are defined within the idle-states node, which is - a direct child of the cpus node [1] and provides a container where the - processor idle states, defined as device tree nodes, are listed. - - On ARM systems, it is a container of processor idle states nodes. If the - system does not provide CPU power management capabilities, or the processor - just supports idle_standby, an idle-states node is not required. - - =========================================== - 4 - References - =========================================== - - [1] ARM Linux Kernel documentation - CPUs bindings - Documentation/devicetree/bindings/arm/cpus.yaml - - [2] ARM Linux Kernel documentation - PSCI bindings - Documentation/devicetree/bindings/arm/psci.yaml - - [3] ARM Server Base System Architecture (SBSA) - http://infocenter.arm.com/help/index.jsp - - [4] ARM Architecture Reference Manuals - http://infocenter.arm.com/help/index.jsp - - [6] ARM Linux Kernel documentation - Booting AArch64 Linux - Documentation/arm64/booting.rst - -properties: - $nodename: - const: idle-states - - entry-method: - description: | - Usage and definition depend on ARM architecture version. - - On ARM v8 64-bit this property is required. - On ARM 32-bit systems this property is optional - - This assumes that the "enable-method" property is set to "psci" in the cpu - node[6] that is responsible for setting up CPU idle management in the OS - implementation. - const: psci - -patternProperties: - "^(cpu|cluster)-": - type: object - description: | - Each state node represents an idle state description and must be defined - as follows. - - The idle state entered by executing the wfi instruction (idle_standby - SBSA,[3][4]) is considered standard on all ARM platforms and therefore - must not be listed. - - In addition to the properties listed above, a state node may require - additional properties specific to the entry-method defined in the - idle-states node. Please refer to the entry-method bindings - documentation for properties definitions. - - properties: - compatible: - const: arm,idle-state - - local-timer-stop: - description: - If present the CPU local timer control logic is - lost on state entry, otherwise it is retained. - type: boolean - - entry-latency-us: - description: - Worst case latency in microseconds required to enter the idle state. - - exit-latency-us: - description: - Worst case latency in microseconds required to exit the idle state. - The exit-latency-us duration may be guaranteed only after - entry-latency-us has passed. - - min-residency-us: - description: - Minimum residency duration in microseconds, inclusive of preparation - and entry, for this idle state to be considered worthwhile energy wise - (refer to section 2 of this document for a complete description). - - wakeup-latency-us: - description: | - Maximum delay between the signaling of a wake-up event and the CPU - being able to execute normal code again. If omitted, this is assumed - to be equal to: - - entry-latency-us + exit-latency-us - - It is important to supply this value on systems where the duration of - PREP phase (see diagram 1, section 2) is non-neglibigle. In such - systems entry-latency-us + exit-latency-us will exceed - wakeup-latency-us by this duration. - - idle-state-name: - $ref: /schemas/types.yaml#/definitions/string - description: - A string used as a descriptive name for the idle state. - - required: - - compatible - - entry-latency-us - - exit-latency-us - - min-residency-us - -additionalProperties: false - -examples: - - | - - cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - idle-states { - entry-method = "psci"; - - CPU_RETENTION_0_0: cpu-retention-0-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <80>; - }; - - CLUSTER_RETENTION_0: cluster-retention-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <250>; - wakeup-latency-us = <130>; - }; - - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <250>; - exit-latency-us = <500>; - min-residency-us = <950>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <600>; - exit-latency-us = <1100>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - - CPU_RETENTION_1_0: cpu-retention-1-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <90>; - }; - - CLUSTER_RETENTION_1: cluster-retention-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <270>; - wakeup-latency-us = <100>; - }; - - CPU_SLEEP_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <70>; - exit-latency-us = <100>; - min-residency-us = <300>; - wakeup-latency-us = <150>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1200>; - min-residency-us = <3500>; - wakeup-latency-us = <1300>; - }; - }; - }; - - - | - // Example 2 (ARM 32-bit, 8-cpu system, two clusters): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; - }; - - cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; - }; - - cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; - }; - - idle-states { - cpu_sleep_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <200>; - exit-latency-us = <100>; - min-residency-us = <400>; - wakeup-latency-us = <250>; - }; - - cluster_sleep_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <500>; - exit-latency-us = <1500>; - min-residency-us = <2500>; - wakeup-latency-us = <1700>; - }; - - cpu_sleep_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <500>; - min-residency-us = <900>; - wakeup-latency-us = <600>; - }; - - cluster_sleep_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <800>; - exit-latency-us = <2000>; - min-residency-us = <6500>; - wakeup-latency-us = <2300>; - }; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/arm/intel,keembay.yaml b/Documentation/devicetree/bindings/arm/intel,keembay.yaml index 107e686ab207..53d2ce02b207 100644 --- a/Documentation/devicetree/bindings/arm/intel,keembay.yaml +++ b/Documentation/devicetree/bindings/arm/intel,keembay.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/intel,keembay.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Keem Bay platform device tree bindings +title: Keem Bay platform maintainers: - Paul J. Murphy <paul.j.murphy@intel.com> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml new file mode 100644 index 000000000000..4b4dcf551eb6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA platform + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-n6000 + - intel,socfpga-agilex-socdk + - const: intel,socfpga-agilex + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml index 230bffeec0e5..553dcbc70e35 100644 --- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel IXP4xx Device Tree Bindings +title: Intel IXP4xx maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/Documentation/devicetree/bindings/arm/linux,dummy-virt.yaml b/Documentation/devicetree/bindings/arm/linux,dummy-virt.yaml new file mode 100644 index 000000000000..c7c5eb48fc7e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/linux,dummy-virt.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/linux,dummy-virt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QEMU virt machine + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + $nodename: + const: "/" + compatible: + const: linux,dummy-virt + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt index 052a967c1f28..c83245065d44 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt @@ -72,7 +72,7 @@ mpp19 19 gpio, uart0(rxd), sdio(pw_off) GPIO: ----- For common binding part and usage, refer to -Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. +Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml. Required properties: diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt index f6d6642d81c0..29fa93dad52b 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt @@ -1,21 +1,3 @@ -Marvell Armada 37xx Platforms Device Tree Bindings --------------------------------------------------- - -Boards using a SoC of the Marvell Armada 37xx family must carry the -following root node property: - - - compatible: must contain "marvell,armada3710" - -In addition, boards using the Marvell Armada 3720 SoC shall have the -following property before the previous one: - - - compatible: must contain "marvell,armada3720" - -Example: - -compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; - - Power management ---------------- @@ -48,11 +30,3 @@ avs: avs@11500 { compatible = "marvell,armada-3700-avs", "syscon"; reg = <0x11500 0x40>; } - - -CZ.NIC's Turris Mox SOHO router Device Tree Bindings ----------------------------------------------------- - -Required root node property: - - - compatible: must contain "cznic,turris-mox" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml new file mode 100644 index 000000000000..6905d29f3108 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-37xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 37xx Platforms + +maintainers: + - Robert Marko <robert.marko@sartura.hr> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Armada 3720 SoC boards + items: + - enum: + - cznic,turris-mox + - globalscale,espressobin + - marvell,armada-3720-db + - methode,edpu + - methode,udpu + - const: marvell,armada3720 + - const: marvell,armada3710 + + - description: Globalscale Espressobin boards + items: + - enum: + - globalscale,espressobin-emmc + - globalscale,espressobin-ultra + - globalscale,espressobin-v7 + - const: globalscale,espressobin + - const: marvell,armada3720 + - const: marvell,armada3710 + + - description: Globalscale Espressobin V7 boards + items: + - enum: + - globalscale,espressobin-v7-emmc + - const: globalscale,espressobin-v7 + - const: globalscale,espressobin + - const: marvell,armada3720 + - const: marvell,armada3710 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index 0705e765f432..d84105c7c935 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -156,7 +156,7 @@ GPIO: ----- For common binding part and usage, refer to -Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. +Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml. Required properties: diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml new file mode 100644 index 000000000000..8960fb8b2b2f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Alleycat5/5X Platforms + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Alleycat5 (98DX25xx) Reference Design + items: + - enum: + - marvell,rd-ac5 + - const: marvell,ac5 + + - description: Alleycat5X (98DX35xx) Reference Design + items: + - enum: + - marvell,rd-ac5x + - const: marvell,ac5x + - const: marvell,ac5 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 0ffe1acf1344..d76ce4c3819d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/mediatek.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek SoC based Platforms Device Tree Bindings +title: MediaTek SoC based Platforms maintainers: - Sean Wang <sean.wang@mediatek.com> @@ -32,6 +32,10 @@ properties: - const: mediatek,mt6580 - items: - enum: + - prestigio,pmt5008-3g + - const: mediatek,mt6582 + - items: + - enum: - fairphone,fp1 - mundoreader,bq-aquaris5 - const: mediatek,mt6589 @@ -127,8 +131,43 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - description: Google Hayato + items: + - const: google,hayato-rev1 + - const: google,hayato + - const: mediatek,mt8192 + - description: Google Spherion (Acer Chromebook 514) + items: + - const: google,spherion-rev3 + - const: google,spherion-rev2 + - const: google,spherion-rev1 + - const: google,spherion-rev0 + - const: google,spherion + - const: mediatek,mt8192 + - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) + items: + - enum: + - google,tomato-rev2 + - google,tomato-rev1 + - const: google,tomato + - const: mediatek,mt8195 + - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) + items: + - const: google,tomato-rev4 + - const: google,tomato-rev3 + - const: google,tomato + - const: mediatek,mt8195 + - items: + - enum: + - mediatek,mt8186-evb + - const: mediatek,mt8186 + - items: + - enum: + - mediatek,mt8192-evb + - const: mediatek,mt8192 - items: - enum: + - mediatek,mt8195-demo - mediatek,mt8195-evb - const: mediatek,mt8195 - description: Google Burnet (HP Chromebook x360 11MK G3 EE) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt deleted file mode 100644 index ea827e8763de..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ /dev/null @@ -1,34 +0,0 @@ -Mediatek apmixedsys controller -============================== - -The Mediatek apmixedsys controller provides the PLLs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-apmixedsys" - - "mediatek,mt2712-apmixedsys", "syscon" - - "mediatek,mt6765-apmixedsys", "syscon" - - "mediatek,mt6779-apmixedsys", "syscon" - - "mediatek,mt6797-apmixedsys" - - "mediatek,mt7622-apmixedsys" - - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - - "mediatek,mt7629-apmixedsys" - - "mediatek,mt8135-apmixedsys" - - "mediatek,mt8167-apmixedsys", "syscon" - - "mediatek,mt8173-apmixedsys" - - "mediatek,mt8183-apmixedsys", "syscon" - - "mediatek,mt8516-apmixedsys" -- #clock-cells: Must be 1 - -The apmixedsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -apmixedsys: clock-controller@10209000 { - compatible = "mediatek,mt8173-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index 6b7e8067e7aa..0502db73686b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7629-ethsys", "syscon" + - "mediatek,mt7986-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt deleted file mode 100644 index eb3523c7a7be..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ /dev/null @@ -1,41 +0,0 @@ -Mediatek infracfg controller -============================ - -The Mediatek infracfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt2712-infracfg", "syscon" - - "mediatek,mt6765-infracfg", "syscon" - - "mediatek,mt6779-infracfg_ao", "syscon" - - "mediatek,mt6797-infracfg", "syscon" - - "mediatek,mt7622-infracfg", "syscon" - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt7629-infracfg", "syscon" - - "mediatek,mt8135-infracfg", "syscon" - - "mediatek,mt8167-infracfg", "syscon" - - "mediatek,mt8173-infracfg", "syscon" - - "mediatek,mt8183-infracfg", "syscon" - - "mediatek,mt8516-infracfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The infracfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -infracfg: power-controller@10001000 { - compatible = "mediatek,mt8173-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml new file mode 100644 index 000000000000..1d7c837d9378 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Infrastructure System Configuration Controller + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +description: + The Mediatek infracfg controller provides various clocks and reset outputs + to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>, + and reset values in <dt-bindings/reset/mt*-reset.h> and + <dt-bindings/reset/mt*-resets.h>. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt6765-infracfg + - mediatek,mt6795-infracfg + - mediatek,mt6779-infracfg_ao + - mediatek,mt6797-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7629-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8167-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg + - mediatek,mt8516-infracfg + - const: syscon + - items: + - const: mediatek,mt7623-infracfg + - const: mediatek,mt2701-infracfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt6795-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg +then: + required: + - '#reset-cells' + +additionalProperties: false + +examples: + - | + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 763c62323a74..eb451bec23d3 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -25,11 +25,14 @@ properties: - mediatek,mt2712-mmsys - mediatek,mt6765-mmsys - mediatek,mt6779-mmsys + - mediatek,mt6795-mmsys - mediatek,mt6797-mmsys - mediatek,mt8167-mmsys - mediatek,mt8173-mmsys - mediatek,mt8183-mmsys + - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys + - mediatek,mt8195-mmsys - mediatek,mt8365-mmsys - const: syscon - items: @@ -40,6 +43,31 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier as defined by bindings + of the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mboxes: + description: + Using mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. See + Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml + for details. + $ref: /schemas/types.yaml#/definitions/phandle-array + + mediatek,gce-client-reg: + description: + The register of client driver can be configured by gce with 4 arguments + defined in this property, such as phandle of gce, subsys id, + register offset and size. + Each subsys id is mapping to a base address of display function blocks + register which is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + "#clock-cells": const: 1 @@ -55,9 +83,16 @@ additionalProperties: false examples: - | + #include <dt-bindings/power/mt8173-power.h> + #include <dt-bindings/gce/mt8173-gce.h> + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml new file mode 100644 index 000000000000..9fbeb626ab23 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek PCIE Mirror Controller for MT7622 + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + - Felix Fietkau <nbd@nbd.name> + +description: + The mediatek PCIE mirror provides a configuration interface for PCIE + controller on MT7622 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7622-pcie-mirror + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_mirror: pcie-mirror@10000400 { + compatible = "mediatek,mt7622-pcie-mirror", "syscon"; + reg = <0 0x10000400 0 0x10>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml new file mode 100644 index 000000000000..84fb0a146b6e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Wireless Ethernet Dispatch Controller for MT7622 + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + - Felix Fietkau <nbd@nbd.name> + +description: + The mediatek wireless ethernet dispatch controller can be configured to + intercept and handle access to the WLAN DMA queues and PCIe interrupts + and implement hardware flow offloading from ethernet to WLAN. + +properties: + compatible: + items: + - enum: + - mediatek,mt7622-wed + - mediatek,mt7986-wed + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + wed0: wed@1020a000 { + compatible = "mediatek,mt7622-wed","syscon"; + reg = <0 0x1020a000 0 0x1000>; + interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml new file mode 100644 index 000000000000..96221f51c1c3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek PCIE WED Controller for MT7986 + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + - Felix Fietkau <nbd@nbd.name> + +description: + The mediatek WED PCIE provides a configuration interface for PCIE + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wed-pcie + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml new file mode 100644 index 000000000000..cf1002c3efa6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Functional Clock Controller for MT8186 + +maintainers: + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8186-imp_iic_wrap + - mediatek,mt8186-mfgsys + - mediatek,mt8186-wpesys + - mediatek,mt8186-imgsys1 + - mediatek,mt8186-imgsys2 + - mediatek,mt8186-vdecsys + - mediatek,mt8186-vencsys + - mediatek,mt8186-camsys + - mediatek,mt8186-camsys_rawa + - mediatek,mt8186-camsys_rawb + - mediatek,mt8186-mdpsys + - mediatek,mt8186-ipesys + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + imp_iic_wrap: clock-controller@11017000 { + compatible = "mediatek,mt8186-imp_iic_wrap"; + reg = <0x11017000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml new file mode 100644 index 000000000000..661047d26e11 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek System Clock Controller for MT8186 + +maintainers: + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. + The mcusys provides mux control to select the clock source in AP MCU. + The device nodes also provide the system control capacity for configuration. + +properties: + compatible: + items: + - enum: + - mediatek,mt8186-mcusys + - mediatek,mt8186-topckgen + - mediatek,mt8186-infracfg_ao + - mediatek,mt8186-apmixedsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + topckgen: syscon@10000000 { + compatible = "mediatek,mt8186-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml index c8c67c033f8c..b57cc2e69efb 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml @@ -24,7 +24,6 @@ properties: - mediatek,mt8192-imp_iic_wrap_w - mediatek,mt8192-imp_iic_wrap_n - mediatek,mt8192-msdc_top - - mediatek,mt8192-msdc - mediatek,mt8192-mfgcfg - mediatek,mt8192-imgsys - mediatek,mt8192-imgsys2 @@ -108,13 +107,6 @@ examples: }; - | - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0x11f60000 0x1000>; - #clock-cells = <1>; - }; - - - | mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8192-mfgcfg"; reg = <0x13fbf000 0x1000>; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml index 5705bcf1fe47..27f79175c678 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml @@ -29,6 +29,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml index 57a1503d95fe..95b6bdf99936 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -37,6 +37,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 8723dfe34bab..ef62cbb13590 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -21,11 +21,14 @@ properties: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg - mediatek,mt6765-pericfg + - mediatek,mt6795-pericfg - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8186-pericfg + - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon - items: diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index 30cb645c0e54..29ca7a10b315 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -8,6 +8,8 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" - "mediatek,mt7629-sgmiisys", "syscon" + - "mediatek,mt7986-sgmiisys_0", "syscon" + - "mediatek,mt7986-sgmiisys_1", "syscon" - #clock-cells: Must be 1 The SGMIISYS controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt deleted file mode 100644 index 5ce7578cf274..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ /dev/null @@ -1,34 +0,0 @@ -Mediatek topckgen controller -============================ - -The Mediatek topckgen controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-topckgen" - - "mediatek,mt2712-topckgen", "syscon" - - "mediatek,mt6765-topckgen", "syscon" - - "mediatek,mt6779-topckgen", "syscon" - - "mediatek,mt6797-topckgen" - - "mediatek,mt7622-topckgen" - - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - - "mediatek,mt7629-topckgen" - - "mediatek,mt8135-topckgen" - - "mediatek,mt8167-topckgen", "syscon" - - "mediatek,mt8173-topckgen" - - "mediatek,mt8183-topckgen", "syscon" - - "mediatek,mt8516-topckgen" -- #clock-cells: Must be 1 - -The topckgen controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -topckgen: power-controller@10000000 { - compatible = "mediatek,mt8173-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml index 6193388c6318..9a0d54e9799c 100644 --- a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip Sparx5 Boards Device Tree Bindings +title: Microchip Sparx5 Boards maintainers: - Lars Povlsen <lars.povlsen@microchip.com> diff --git a/Documentation/devicetree/bindings/arm/moxart.yaml b/Documentation/devicetree/bindings/arm/moxart.yaml index 670d24ce8ec5..42565280914c 100644 --- a/Documentation/devicetree/bindings/arm/moxart.yaml +++ b/Documentation/devicetree/bindings/arm/moxart.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/moxart.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MOXA ART device tree bindings +title: MOXA ART maintainers: - Jonas Jensen <jonas.jensen@gmail.com> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt index 6ce0b212ec6d..606b4b1b709d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt @@ -81,4 +81,4 @@ Example: }; }; -[1]. Documentation/devicetree/bindings/arm/idle-states.yaml +[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 03882aac8d2d..5ea506412b4e 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -23,10 +23,14 @@ properties: enum: - qcom,sc7180-llcc - qcom,sc7280-llcc + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc - qcom,sdm845-llcc - qcom,sm6350-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc reg: items: diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt index 94d50a949be1..c0e3c3a42bea 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt @@ -10,7 +10,7 @@ system, notifying them when a low power state is entered or exited. Multiple revisions of the SAW hardware are supported using these Device Nodes. SAW2 revisions differ in the register offset and configuration data. Also, the same revision of the SAW in different SoCs may have different configuration -data due the the differences in hardware capabilities. Hence the SoC name, the +data due the differences in hardware capabilities. Hence the SoC name, the version of the SAW hardware in that SoC and the distinction between cpu (big or Little) or cache, may be needed to uniquely identify the SAW register configuration and initialization data. The compatible string is used to diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index a316eef1b728..8892eb6bd3ef 100644 --- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -23,8 +23,12 @@ properties: - description: infinity2m boards items: - enum: + - 100ask,dongshanpione # 100ask DongShanPiOne - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit - m5stack,unitv2 # M5Stack UnitV2 + - miyoo,miyoo-mini # Miyoo Mini + - wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01 + - wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W - const: mstar,infinity2m - description: infinity3 boards diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml index 95e51378089c..43409e5721d5 100644 --- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml @@ -8,6 +8,7 @@ title: NPCM Platforms Device Tree Bindings maintainers: - Jonathan Neuschäfer <j.neuschaefer@gmx.net> + - Tomer Maimon <tmaimon77@gmail.com> properties: $nodename: @@ -26,4 +27,10 @@ properties: - nuvoton,npcm750-evb # NPCM750 evaluation board - const: nuvoton,npcm750 + - description: NPCM845 based boards + items: + - enum: + - nuvoton,npcm845-evb # NPCM845 evaluation board + - const: nuvoton,npcm845 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 000000000000..94e72f25b331 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer <j.neuschaefer@gmx.net> + - Tomer Maimon <tmaimon77@gmail.com> + +description: + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - nuvoton,npcm845-gcr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + gcr: syscon@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml index c9675c4cdc1b..b6f57d79a753 100644 --- a/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml +++ b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: NVIDIA Tegra194 CPU Complex device tree bindings +title: NVIDIA Tegra194 CPU Complex maintainers: - Thierry Reding <thierry.reding@gmail.com> diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index e77635c5422c..fa8b31660cad 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -119,6 +119,9 @@ Boards (incomplete list of examples): - OMAP3 BeagleBoard : Low cost community board compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3" +- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3" + - OMAP3 Tobi with Overo : Commercial expansion board with daughter board compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3" diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 3eb6d7afff14..431ef8c56a13 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -31,12 +31,17 @@ Required properties: (base address and length) - clocks: clocks for this module - clockdomains: clockdomains for this module +- #clock-cells: From common clock binding +- clock-output-names: From common clock binding + Example: -cm: cm@48004000 { +cm: clock@48004000 { compatible = "ti,omap3-cm"; reg = <0x48004000 0x4000>; + #clock-cells = <0>; + clock-output-names = "cm"; cm_clocks: clocks { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index e17ac049e890..dbb6f3dc5ae5 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,firestorm-pmu + - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu @@ -44,10 +46,18 @@ properties: - arm,cortex-a76-pmu - arm,cortex-a77-pmu - arm,cortex-a78-pmu + - arm,cortex-a510-pmu + - arm,cortex-a710-pmu + - arm,cortex-x1-pmu + - arm,cortex-x2-pmu - arm,neoverse-e1-pmu - arm,neoverse-n1-pmu + - arm,neoverse-n2-pmu + - arm,neoverse-v1-pmu - brcm,vulcan-pmu - cavium,thunder-pmu + - nvidia,denver-pmu + - nvidia,carmel-pmu - qcom,krait-pmu - qcom,scorpion-pmu - qcom,scorpion-mp-pmu @@ -58,6 +68,8 @@ properties: interrupt-affinity: $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 description: When using SPIs, specifies a list of phandles to CPU nodes corresponding directly to the affinity of diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 8b77cf83a095..3a2c908ff282 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -43,29 +43,24 @@ properties: - description: For implementations complying to PSCI 0.2. - const: arm,psci-0.2 - - - description: - For implementations complying to PSCI 0.2. Function IDs are not required and should be ignored by an OS with PSCI 0.2 support, but are permitted to be present for compatibility with existing software when "arm,psci" is later in the compatible list. + minItems: 1 items: - const: arm,psci-0.2 - const: arm,psci - description: For implementations complying to PSCI 1.0. - const: arm,psci-1.0 - - - description: - For implementations complying to PSCI 1.0. PSCI 1.0 is backward compatible with PSCI 0.2 with minor specification updates, as defined in the PSCI specification[2]. + minItems: 1 items: - const: arm,psci-1.0 - const: arm,psci-0.2 + - const: arm,psci method: description: The method of calling the PSCI firmware. @@ -101,7 +96,7 @@ properties: bindings in [1]) must specify this property. [1] Kernel documentation - ARM idle states bindings - Documentation/devicetree/bindings/arm/idle-states.yaml + Documentation/devicetree/bindings/cpu/idle-states.yaml patternProperties: "^power-domain-": diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 370aab274cd1..1b5ac6b02bc5 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -4,10 +4,10 @@ $id: http://devicetree.org/schemas/arm/qcom.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: QCOM device tree bindings +title: QCOM maintainers: - - Stephen Boyd <sboyd@codeaurora.org> + - Bjorn Andersson <bjorn.andersson@linaro.org> description: | Some qcom based bootloaders identify the dtb blob based on a set of @@ -38,17 +38,26 @@ description: | msm8992 msm8994 msm8996 + msm8998 + qcs404 sa8155p + sa8540p sc7180 sc7280 + sc8180x + sc8280xp + sda660 sdm630 + sdm632 + sdm636 sdm660 sdm845 sdx55 sdx65 + sm6125 + sm6350 sm7225 sm8150 - sdx65 sm8250 sm8350 sm8450 @@ -87,6 +96,11 @@ description: | A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in foundry 2. + There are many devices in the list below that run the standard ChromeOS + bootloader setup and use the open source depthcharge bootloader to boot the + OS. These devices do not use the scheme described above. For details, see: + https://docs.kernel.org/arm/google/chromebook-boot-flow.html + properties: $nodename: const: "/" @@ -99,6 +113,7 @@ properties: - items: - enum: + - asus,sparrow - lg,lenok - const: qcom,apq8026 @@ -149,31 +164,85 @@ properties: - const: qcom,msm8974 - items: - - enum: - - alcatel,idol347 - - const: qcom,msm8916-mtp/1 - const: qcom,msm8916-mtp + - const: qcom,msm8916-mtp/1 - const: qcom,msm8916 - items: - enum: - - longcheer,l8150 + - alcatel,idol347 + - asus,z00l + - huawei,g7 + - longcheer,l8910 - samsung,a3u-eur - samsung,a5u-eur + - samsung,e5 + - samsung,e7 + - samsung,grandmax + - samsung,j5 + - samsung,serranove + - wingtech,wt88047 - const: qcom,msm8916 - items: + - const: longcheer,l8150 + - const: qcom,msm8916-v1-qrd/9-v1 + - const: qcom,msm8916 + + - items: + - enum: + - lg,bullhead + - microsoft,talkman + - xiaomi,libra + - const: qcom,msm8992 + + - items: - enum: - sony,karin_windy + - const: qcom,apq8094 + + - items: + - enum: + - huawei,angler + - microsoft,cityman + - sony,ivy-row - sony,karin-row - sony,satsuki-row - sony,sumire-row - sony,suzuran-row - - qcom,msm8994 - - const: qcom,apq8094 + - const: qcom,msm8994 + + - items: + - enum: + - arrow,apq8096-db820c + - inforce,ifc6640 + - const: qcom,apq8096-sbc + - const: qcom,apq8096 + + - items: + - enum: + - qcom,msm8996-mtp + - sony,dora-row + - sony,kagura-row + - sony,keyaki-row + - xiaomi,gemini + - xiaomi,natrium + - xiaomi,scorpio + - const: qcom,msm8996 - items: - - const: qcom,msm8996-mtp + - enum: + - asus,novago-tp370ql + - fxtec,pro1 + - hp,envy-x2 + - lenovo,miix-630 + - oneplus,cheeseburger + - oneplus,dumpling + - qcom,msm8998-mtp + - sony,xperia-lilac + - sony,xperia-maple + - sony,xperia-poplar + - const: qcom,msm8998 - items: - enum: @@ -196,20 +265,372 @@ properties: - qcom,ipq8074-hk10-c2 - const: qcom,ipq8074 - - items: + - description: Qualcomm Technologies, Inc. SC7180 IDP + items: - enum: - qcom,sc7180-idp - const: qcom,sc7180 + - description: HP Chromebook x2 11c (rev1 - 2) + items: + - const: google,coachz-rev1 + - const: google,coachz-rev2 + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c (newest rev) + items: + - const: google,coachz + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c with LTE (rev1 - 2) + items: + - const: google,coachz-rev1-sku0 + - const: google,coachz-rev2-sku0 + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c with LTE (newest rev) + items: + - const: google,coachz-sku0 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (rev2) + items: + - const: google,homestar-rev2 + - const: google,homestar-rev23 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (rev3) + items: + - const: google,homestar-rev3 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (newest rev) + items: + - const: google,homestar + - const: qcom,sc7180 + + - description: Google Kingoftown (rev0) + items: + - const: google,kingoftown-rev0 + - const: qcom,sc7180 + + - description: Google Kingoftown (newest rev) + items: + - const: google,kingoftown + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev0) + items: + - const: google,lazor-rev0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev1 - 2) + items: + - const: google,lazor-rev1 + - const: google,lazor-rev2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev3 - 8) + items: + - const: google,lazor-rev3 + - const: google,lazor-rev4 + - const: google,lazor-rev5 + - const: google,lazor-rev6 + - const: google,lazor-rev7 + - const: google,lazor-rev8 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (newest rev) + items: + - const: google,lazor + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (rev1 - 2) + items: + - const: google,lazor-rev1-sku2 + - const: google,lazor-rev2-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (rev3 - 8) + items: + - const: google,lazor-rev3-sku2 + - const: google,lazor-rev4-sku2 + - const: google,lazor-rev5-sku2 + - const: google,lazor-rev6-sku2 + - const: google,lazor-rev7-sku2 + - const: google,lazor-rev8-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (newest rev) + items: + - const: google,lazor-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (rev1 - 2) + items: + - const: google,lazor-rev1-sku0 + - const: google,lazor-rev2-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (rev3 - 8) + items: + - const: google,lazor-rev3-sku0 + - const: google,lazor-rev4-sku0 + - const: google,lazor-rev5-sku0 + - const: google,lazor-rev6-sku0 + - const: google,lazor-rev7-sku0 + - const: google,lazor-rev8-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (newest rev) + items: + - const: google,lazor-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 (rev4 - rev8) + items: + - const: google,lazor-rev4-sku4 + - const: google,lazor-rev5-sku4 + - const: google,lazor-rev6-sku4 + - const: google,lazor-rev7-sku4 + - const: google,lazor-rev8-sku4 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 (newest rev) + items: + - const: google,lazor-sku4 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (rev4) + items: + - const: google,lazor-rev4-sku5 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (rev5 - rev8) + items: + - const: google,lazor-rev5-sku5 + - const: google,lazor-rev5-sku6 + - const: google,lazor-rev6-sku6 + - const: google,lazor-rev7-sku6 + - const: google,lazor-rev8-sku6 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (newest rev) + items: + - const: google,lazor-sku6 + - const: qcom,sc7180 + + - description: Google Mrbland with AUO panel (rev0) + items: + - const: google,mrbland-rev0-sku0 + - const: qcom,sc7180 + + - description: Google Mrbland with AUO panel (newest rev) + items: + - const: google,mrbland-sku1536 + - const: qcom,sc7180 + + - description: Google Mrbland with BOE panel (rev0) + items: + - const: google,mrbland-rev0-sku16 + - const: qcom,sc7180 + + - description: Google Mrbland with BOE panel (newest rev) + items: + - const: google,mrbland-sku1024 + - const: google,mrbland-sku768 + - const: qcom,sc7180 + + - description: Google Pazquel with Parade (newest rev) + items: + - const: google,pazquel-sku5 + - const: qcom,sc7180 + + - description: Google Pazquel with TI (newest rev) + items: + - const: google,pazquel-sku1 + - const: qcom,sc7180 + + - description: Google Pazquel with LTE and Parade (newest rev) + items: + - const: google,pazquel-sku6 + - const: google,pazquel-sku4 + - const: qcom,sc7180 + + - description: Google Pazquel with LTE and TI (newest rev) + items: + - const: google,pazquel-sku0 + - const: google,pazquel-sku2 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (rev1) + items: + - const: google,pompom-rev1 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (rev2) + items: + - const: google,pompom-rev2 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (newest rev) + items: + - const: google,pompom + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (rev1) + items: + - const: google,pompom-rev1-sku0 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (rev2) + items: + - const: google,pompom-rev2-sku0 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (newest rev) + items: + - const: google,pompom-sku0 + - const: qcom,sc7180 + + - description: Google Quackingstick (newest rev) + items: + - const: google,quackingstick-sku1537 + - const: qcom,sc7180 + + - description: Google Quackingstick with LTE (newest rev) + items: + - const: google,quackingstick-sku1536 + - const: qcom,sc7180 + + - description: Google Trogdor (newest rev) + items: + - const: google,trogdor + - const: qcom,sc7180 + + - description: Google Trogdor with LTE (newest rev) + items: + - const: google,trogdor-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (rev0) + items: + - const: google,wormdingler-rev0-sku16 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (newest rev) + items: + - const: google,wormdingler-sku1024 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel and rt5682s (newest rev) + items: + - const: google,wormdingler-sku1025 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (rev0) + items: + - const: google,wormdingler-rev0-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (newest rev) + items: + - const: google,wormdingler-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel and rt5682s (newest rev) + items: + - const: google,wormdingler-sku1 + - const: qcom,sc7180 + + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4) + items: + - const: qcom,sc7280-crd + - const: google,hoglin-rev3 + - const: google,hoglin-rev4 + - const: google,piglin-rev3 + - const: google,piglin-rev4 + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev) + items: + - const: google,zoglin + - const: google,hoglin + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform + items: + - const: qcom,sc7280-idp + - const: google,senor + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform + items: + - const: qcom,sc7280-idp2 + - const: google,piglin + - const: qcom,sc7280 + + - description: Google Evoker (newest rev) + items: + - const: google,evoker + - const: qcom,sc7280 + + - description: Google Herobrine (newest rev) + items: + - const: google,herobrine + - const: qcom,sc7280 + + - description: Google Villager (rev0) + items: + - const: google,villager-rev0 + - const: qcom,sc7280 + + - description: Google Villager (newest rev) + items: + - const: google,villager + - const: qcom,sc7280 + + - description: Google Villager with LTE (newest rev) + items: + - const: google,villager-sku512 + - const: qcom,sc7280 + - items: - enum: - - qcom,sc7280-crd - - qcom,sc7280-idp - - qcom,sc7280-idp2 - - google,hoglin - - google,piglin - - google,senor - - const: qcom,sc7280 + - lenovo,flex-5g + - microsoft,surface-prox + - qcom,sc8180x-primus + - const: qcom,sc8180x + + - items: + - enum: + - lenovo,thinkpad-x13s + - qcom,sc8280xp-crd + - qcom,sc8280xp-qrd + - const: qcom,sc8280xp + + - items: + - enum: + - sony,discovery-row + - sony,kirin-row + - sony,pioneer-row + - sony,voyager-row + - const: qcom,sdm630 + + - items: + - enum: + - inforce,ifc6560 + - const: qcom,sda660 + + - items: + - enum: + - fairphone,fp3 + - const: qcom,sdm632 + + - items: + - enum: + - sony,mermaid-row + - const: qcom,sdm636 - items: - enum: @@ -230,45 +651,92 @@ properties: - items: - enum: - - qcom,sdx65-mtp - - const: qcom,sdx65 - - - items: - - enum: - qcom,ipq6018-cp01 - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 - items: - enum: + - qcom,qcs404-evb-1000 + - qcom,qcs404-evb-4000 + - const: qcom,qcs404-evb + - const: qcom,qcs404 + + - items: + - enum: - qcom,sa8155p-adp - const: qcom,sa8155p - items: - enum: + - qcom,sa8295p-adp + - const: qcom,sa8540p + + - items: + - enum: + - lenovo,yoga-c630 + - lg,judyln + - lg,judyp + - oneplus,enchilada + - oneplus,fajita + - qcom,sdm845-mtp + - shift,axolotl + - samsung,w737 + - sony,akari-row + - sony,akatsuki-row + - sony,apollo-row + - thundercomm,db845c + - xiaomi,beryllium + - xiaomi,polaris + - const: qcom,sdm845 + + - items: + - enum: + - sony,pdx201 + - const: qcom,sm6125 + + - items: + - enum: + - sony,pdx213 + - const: qcom,sm6350 + + - items: + - enum: - fairphone,fp4 - const: qcom,sm7225 - items: - enum: + - microsoft,surface-duo + - qcom,sm8150-hdk - qcom,sm8150-mtp + - sony,bahamut-generic + - sony,griffin-generic - const: qcom,sm8150 - items: - enum: - qcom,qrb5165-rb5 + - qcom,sm8250-hdk - qcom,sm8250-mtp + - sony,pdx203-generic + - sony,pdx206-generic - const: qcom,sm8250 - items: - enum: + - microsoft,surface-duo2 - qcom,sm8350-hdk - qcom,sm8350-mtp + - sony,pdx214-generic + - sony,pdx215-generic - const: qcom,sm8350 - items: - enum: + - qcom,sm8450-hdk - qcom,sm8450-qrd + - sony,pdx223 - const: qcom,sm8450 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/rda.yaml b/Documentation/devicetree/bindings/arm/rda.yaml index a5c0444aa2b4..09241ea1d228 100644 --- a/Documentation/devicetree/bindings/arm/rda.yaml +++ b/Documentation/devicetree/bindings/arm/rda.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/rda.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: RDA Micro platforms device tree bindings +title: RDA Micro platforms maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index 9fb0297fe1ce..ddd9a85099e9 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/realtek.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Realtek platforms device tree bindings +title: Realtek platforms maintainers: - Andreas Färber <afaerber@suse.de> diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml deleted file mode 100644 index 1f80767da38b..000000000000 --- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml +++ /dev/null @@ -1,37 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/renesas,prr.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Renesas Product Register - -maintainers: - - Geert Uytterhoeven <geert+renesas@glider.be> - - Magnus Damm <magnus.damm@gmail.com> - -description: | - Most Renesas ARM SoCs have a Product Register or Boundary Scan ID - Register that allows to retrieve SoC product and revision information. - If present, a device node for this register should be added. - -properties: - compatible: - enum: - - renesas,prr - - renesas,bsid - reg: - maxItems: 1 - -required: - - compatible - - reg - -additionalProperties: false - -examples: - - | - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0xff000044 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 6a9350ee690b..f51464a08aff 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/renesas.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings +title: Renesas SH-Mobile, R-Mobile, and R-Car Platform maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> @@ -264,6 +264,7 @@ properties: - renesas,r8a779m4 - renesas,r8a779m5 - renesas,r8a779m8 + - renesas,r8a779mb - enum: - renesas,r8a7795 - renesas,r8a77961 @@ -291,6 +292,13 @@ properties: - renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10) - const: renesas,r8a77980 + - description: R-Car V3H2 (R8A77980A) + items: + - enum: + - renesas,condor-i # Condor-I (RTP0RC77980SEBS012SA01) + - const: renesas,r8a77980a + - const: renesas,r8a77980 + - description: R-Car E3 (R8A77990) items: - enum: @@ -327,6 +335,18 @@ properties: - const: renesas,spider-cpu - const: renesas,r8a779f0 + - description: R-Car V4H (R8A779G0) + items: + - enum: + - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000) + - const: renesas,r8a779g0 + + - items: + - enum: + - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) + - const: renesas,white-hawk-cpu + - const: renesas,r8a779g0 + - description: R-Car H3e (R8A779M0) items: - enum: @@ -397,6 +417,14 @@ properties: - const: renesas,r8a779m8 - const: renesas,r8a7795 + - description: R-Car H3Ne-1.7G (R8A779MB) + items: + - enum: + - renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version) + - const: renesas,r8a779mb + - const: renesas,r8a7795 + - description: RZ/N1D (R9A06G032) items: - enum: @@ -406,6 +434,8 @@ properties: - description: RZ/G2UL (R9A07G043) items: - enum: + - renesas,smarc-evk # SMARC EVK + - enum: - renesas,r9a07g043u11 # RZ/G2UL Type-1 - renesas,r9a07g043u12 # RZ/G2UL Type-2 - const: renesas,r9a07g043 @@ -421,6 +451,21 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) + items: + - enum: + - renesas,smarc-evk # SMARC EVK + - enum: + - renesas,r9a07g054l1 # Single Cortex-A55 RZ/V2L + - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L + - const: renesas,r9a07g054 + + - description: RZ/V2M (R9A09G011) + items: + - enum: + - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 + - const: renesas,r9a09g011 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 4aed16176434..c6c69a4e3777 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/rockchip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip platforms device tree bindings +title: Rockchip platforms maintainers: - Heiko Stuebner <heiko@sntech.de> @@ -30,6 +30,16 @@ properties: - const: amarula,vyasa-rk3288 - const: rockchip,rk3288 + - description: Anbernic RG353P + items: + - const: anbernic,rg353p + - const: rockchip,rk3566 + + - description: Anbernic RG503 + items: + - const: anbernic,rg503 + - const: rockchip,rk3566 + - description: Asus Tinker board items: - const: asus,rk3288-tinker @@ -133,6 +143,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 + - description: Firefly Station M2 + items: + - const: firefly,rk3566-roc-pc + - const: rockchip,rk3566 + - description: FriendlyElec NanoPi R2S items: - const: friendlyarm,nanopi-r2s @@ -146,6 +161,7 @@ properties: - friendlyarm,nanopi-m4b - friendlyarm,nanopi-neo4 - friendlyarm,nanopi-r4s + - friendlyarm,nanopi-r4s-enterprise - const: rockchip,rk3399 - description: GeekBuying GeekBox @@ -358,30 +374,55 @@ properties: - const: google,gru - const: rockchip,rk3399 - - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) + - description: | + Google Scarlet - Innolux display (Acer Chromebook Tab 10 and more) items: + - const: google,scarlet-rev15-sku2 + - const: google,scarlet-rev15-sku4 - const: google,scarlet-rev15-sku6 - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku2 + - const: google,scarlet-rev14-sku4 - const: google,scarlet-rev14-sku6 - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku2 + - const: google,scarlet-rev13-sku4 - const: google,scarlet-rev13-sku6 - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku2 + - const: google,scarlet-rev12-sku4 - const: google,scarlet-rev12-sku6 - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku2 + - const: google,scarlet-rev11-sku4 - const: google,scarlet-rev11-sku6 - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku2 + - const: google,scarlet-rev10-sku4 - const: google,scarlet-rev10-sku6 - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku2 + - const: google,scarlet-rev9-sku4 - const: google,scarlet-rev9-sku6 - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku2 + - const: google,scarlet-rev8-sku4 - const: google,scarlet-rev8-sku6 - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku2 + - const: google,scarlet-rev7-sku4 - const: google,scarlet-rev7-sku6 - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku2 + - const: google,scarlet-rev6-sku4 - const: google,scarlet-rev6-sku6 - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku2 + - const: google,scarlet-rev5-sku4 - const: google,scarlet-rev5-sku6 - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku2 + - const: google,scarlet-rev4-sku4 - const: google,scarlet-rev4-sku6 - const: google,scarlet-rev4 - const: google,scarlet @@ -465,6 +506,11 @@ properties: - const: netxeon,r89 - const: rockchip,rk3288 + - description: OPEN AI LAB EAIDK-610 + items: + - const: openailab,eaidk-610 + - const: rockchip,rk3399 + - description: Orange Pi RK3399 board items: - const: rockchip,rk3399-orangepi @@ -481,6 +527,19 @@ properties: - const: pine64,pinebook-pro - const: rockchip,rk3399 + - description: Pine64 PineNote + items: + - enum: + - pine64,pinenote-v1.1 + - pine64,pinenote-v1.2 + - const: pine64,pinenote + - const: rockchip,rk3566 + + - description: Pine64 PinePhonePro + items: + - const: pine64,pinephone-pro + - const: rockchip,rk3399 + - description: Pine64 Rock64 items: - const: pine64,rock64 @@ -494,9 +553,18 @@ properties: - const: pine64,rockpro64 - const: rockchip,rk3399 - - description: Pine64 Quartz64 Model A + - description: Pine64 Quartz64 Model A/B items: - - const: pine64,quartz64-a + - enum: + - pine64,quartz64-a + - pine64,quartz64-b + - const: rockchip,rk3566 + + - description: Pine64 SoQuartz SoM + items: + - enum: + - pine64,soquartz-cm4io + - const: pine64,soquartz - const: rockchip,rk3566 - description: Radxa Rock @@ -515,6 +583,11 @@ properties: - const: radxa,rockpi4 - const: rockchip,rk3399 + - description: Radxa ROCK 4C+ + items: + - const: radxa,rock-4c-plus + - const: rockchip,rk3399 + - description: Radxa ROCK Pi E items: - const: radxa,rockpi-e @@ -532,11 +605,21 @@ properties: - const: vamrs,rk3399pro-vmarc-som - const: rockchip,rk3399pro + - description: Radxa ROCK Pi S + items: + - const: radxa,rockpis + - const: rockchip,rk3308 + - description: Radxa Rock2 Square items: - const: radxa,rock2-square - const: rockchip,rk3288 + - description: Radxa ROCK3 Model A + items: + - const: radxa,rock3a + - const: rockchip,rk3568 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 @@ -651,6 +734,11 @@ properties: - const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568 + - description: Rockchip RK3568 Banana Pi R2 Pro + items: + - const: rockchip,rk3568-bpi-r2pro + - const: rockchip,rk3568 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml index 5ece38065e54..8c73bc7f4009 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -21,10 +21,12 @@ select: enum: - rockchip,px30-pmu - rockchip,rk3066-pmu + - rockchip,rk3128-pmu - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu - rockchip,rk3568-pmu + - rockchip,rk3588-pmu required: - compatible @@ -35,10 +37,12 @@ properties: - enum: - rockchip,px30-pmu - rockchip,rk3066-pmu + - rockchip,rk3128-pmu - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu - rockchip,rk3568-pmu + - rockchip,rk3588-pmu - const: syscon - const: simple-mfd diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 052cd94113d4..faea33e4f731 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -140,6 +140,8 @@ properties: items: - enum: - insignal,arndale-octa # Insignal Arndale Octa + - samsung,chagall-wifi # Samsung SM-T800 + - samsung,klimt-wifi # Samsung SM-T700 - samsung,smdk5420 # Samsung SMDK5420 eval - const: samsung,exynos5420 - const: samsung,exynos5 diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml new file mode 100644 index 000000000000..653f85997643 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C, S5P and Exynos SoC compatibles naming convention + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Guidelines for new compatibles for SoC blocks/components. + When adding new compatibles in new bindings, use the format:: + samsung,SoC-IP + + For example:: + samsung,exynos5433-cmu-isp + +select: + properties: + compatible: + pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$" + required: + - compatible + +properties: + compatible: + oneOf: + - description: Preferred naming style for compatibles of SoC components + pattern: "^samsung,(s3c|s5pv|exynos|exynosautov)[0-9]+-.*$" + + # Legacy compatibles with wild-cards - list cannot grow with new bindings: + - enum: + - samsung,exynos4x12-pinctrl + - samsung,exynos4x12-usb2-phy + - samsung,s3c64xx-pinctrl + - samsung,s3c64xx-wakeup-eint + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml index 7ca5375f278f..6096c082d56d 100644 --- a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml +++ b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml @@ -22,7 +22,6 @@ properties: description: | should contain 3 regions: control register, revision register, operation register, in this order. - minItems: 3 maxItems: 3 interrupts: diff --git a/Documentation/devicetree/bindings/arm/sp810.txt b/Documentation/devicetree/bindings/arm/sp810.txt deleted file mode 100644 index 46652bf65147..000000000000 --- a/Documentation/devicetree/bindings/arm/sp810.txt +++ /dev/null @@ -1,46 +0,0 @@ -SP810 System Controller ------------------------ - -Required properties: - -- compatible: standard compatible string for a Primecell peripheral, - see Documentation/devicetree/bindings/arm/primecell.yaml - for more details - should be: "arm,sp810", "arm,primecell" - -- reg: standard registers property, physical address and size - of the control registers - -- clock-names: from the common clock bindings, for more details see - Documentation/devicetree/bindings/clock/clock-bindings.txt; - should be: "refclk", "timclk", "apb_pclk" - -- clocks: from the common clock bindings, phandle and clock - specifier pairs for the entries of clock-names property - -- #clock-cells: from the common clock bindings; - should be: <1> - -- clock-output-names: from the common clock bindings; - should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" - -- assigned-clocks: from the common clock binding; - should be: clock specifier for each output clock of this - provider node - -- assigned-clock-parents: from the common clock binding; - should be: phandle of input clock listed in clocks - property with the highest frequency - -Example: - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - - }; diff --git a/Documentation/devicetree/bindings/arm/sp810.yaml b/Documentation/devicetree/bindings/arm/sp810.yaml new file mode 100644 index 000000000000..bc8e524aa90a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sp810.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sp810.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Express SP810 System Controller bindings + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +description: + The Arm SP810 system controller provides clocks, timers and a watchdog. + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,sp810 + required: + - compatible + +properties: + compatible: + items: + - const: arm,sp810 + - const: arm,primecell + + reg: + maxItems: 1 + + clock-names: + items: + - const: refclk + - const: timclk + - const: apb_pclk + + clocks: + items: + - description: reference clock + - description: timer clock + - description: APB register access clock + + "#clock-cells": + const: 1 + + clock-output-names: + maxItems: 4 + + assigned-clocks: + maxItems: 4 + + assigned-clock-parents: + maxItems: 4 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +examples: + - | + sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", + "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, + <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, + <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt deleted file mode 100644 index 93372f2a7df9..000000000000 --- a/Documentation/devicetree/bindings/arm/spe-pmu.txt +++ /dev/null @@ -1,20 +0,0 @@ -* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU) - -ARMv8.2 introduces the optional Statistical Profiling Extension for collecting -performance sample data using an in-memory trace buffer. - -** SPE Required properties: - -- compatible : should be one of: - "arm,statistical-profiling-extension-v1" - -- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where - SPE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. - -** Example: - -spe-pmu { - compatible = "arm,statistical-profiling-extension-v1"; - interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>; -}; diff --git a/Documentation/devicetree/bindings/arm/spear.yaml b/Documentation/devicetree/bindings/arm/spear.yaml index 605ad3f882ef..a465c9eca76e 100644 --- a/Documentation/devicetree/bindings/arm/spear.yaml +++ b/Documentation/devicetree/bindings/arm/spear.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/spear.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ST SPEAr Platforms Device Tree Bindings +title: ST SPEAr Platforms maintainers: - Viresh Kumar <vireshk@kernel.org> diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml index a41cd8764885..3ca054c64377 100644 --- a/Documentation/devicetree/bindings/arm/sti.yaml +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/sti.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ST STi Platforms Device Tree Bindings +title: ST STi Platforms maintainers: - Patrice Chotard <patrice.chotard@foss.st.com> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index b07720ea9611..4c605bccc474 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -14,20 +14,11 @@ properties: const: "/" compatible: oneOf: - - description: DH STM32MP1 SoM based Boards + - description: emtrion STM32MP1 Argon based Boards items: - - enum: - - arrow,stm32mp157a-avenger96 # Avenger96 - - dh,stm32mp153c-dhcom-drc02 - - dh,stm32mp157c-dhcom-pdk2 - - dh,stm32mp157c-dhcom-picoitx - - enum: - - dh,stm32mp153c-dhcom-som - - dh,stm32mp157a-dhcor-som - - dh,stm32mp157c-dhcom-som - - enum: - - st,stm32mp153 - - st,stm32mp157 + - const: emtrion,stm32mp157c-emsbc-argon + - const: emtrion,stm32mp157c-emstamp-argon + - const: st,stm32mp157 - items: - enum: - st,stm32f429i-disco @@ -59,6 +50,27 @@ properties: - enum: - st,stm32mp135f-dk - const: st,stm32mp135 + + - description: ST STM32MP151 based Boards + items: + - enum: + - prt,prtt1a # Protonic PRTT1A + - prt,prtt1c # Protonic PRTT1C + - prt,prtt1s # Protonic PRTT1S + - const: st,stm32mp151 + + - description: DH STM32MP153 DHCOM SoM based Boards + items: + - const: dh,stm32mp153c-dhcom-drc02 + - const: dh,stm32mp153c-dhcom-som + - const: st,stm32mp153 + + - description: DH STM32MP153 DHCOR SoM based Boards + items: + - const: dh,stm32mp153c-dhcor-drc-compact + - const: dh,stm32mp153c-dhcor-som + - const: st,stm32mp153 + - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box @@ -66,12 +78,44 @@ properties: - st,stm32mp157c-ed1 - st,stm32mp157a-dk1 - st,stm32mp157c-dk2 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157a-dk1-scmi + - const: st,stm32mp157a-dk1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-dk2-scmi + - const: st,stm32mp157c-dk2 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ed1-scmi + - const: st,stm32mp157c-ed1 - const: st,stm32mp157 - items: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1-scmi + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - const: dh,stm32mp157a-dhcor-som + - const: st,stm32mp157 + + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - dh,stm32mp157c-dhcom-pdk2 + - dh,stm32mp157c-dhcom-picoitx + - const: dh,stm32mp157c-dhcom-som + - const: st,stm32mp157 - description: Engicam i.Core STM32MP1 SoM based Boards items: @@ -97,6 +141,7 @@ properties: - const: oct,stm32mp15xx-osd32 - enum: - st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file mode 100644 index 000000000000..def7d0cfeb31 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Boards + +maintainers: + - qinjian <qinjian@cqplus1.com> + +description: | + ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. + Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - sunplus,sp7021-achip + - sunplus,sp7021-demo-v3 + - const: sunplus,sp7021 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c8a3102c0fde..3ad1cd50e3fe 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/sunxi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner platforms device tree bindings +title: Allwinner platforms maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -391,6 +391,11 @@ properties: - const: libretech,all-h5-cc-h5 - const: allwinner,sun50i-h5 + - description: Lichee Pi Nano + items: + - const: licheepi,licheepi-nano + - const: allwinner,suniv-f1c100s + - description: Lichee Pi One items: - const: licheepi,licheepi-one @@ -444,6 +449,11 @@ properties: - const: haoyu,a10-marsboard - const: allwinner,sun4i-a10 + - description: HAOYU Electronics Marsboard A20 + items: + - const: haoyu,a20-marsboard + - const: allwinner,sun7i-a20 + - description: MapleBoard MP130 items: - const: mapleboard,mp130 @@ -853,6 +863,11 @@ properties: - const: yones-toptech,bs1078-v2 - const: allwinner,sun6i-a31s + - description: X96 Mate TV box + items: + - const: hechuang,x96-mate + - const: allwinner,sun50i-h616 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -953,4 +968,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi Zero 2 + items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 8eee312c2e6f..99566688d033 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -29,10 +29,20 @@ properties: compatible: enum: - allwinner,sun5i-a13-mbus + - allwinner,sun8i-a33-mbus + - allwinner,sun8i-a50-mbus + - allwinner,sun8i-a83t-mbus - allwinner,sun8i-h3-mbus - allwinner,sun8i-r40-mbus + - allwinner,sun8i-v3s-mbus + - allwinner,sun8i-v536-mbus + - allwinner,sun20i-d1-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-a100-mbus - allwinner,sun50i-h5-mbus + - allwinner,sun50i-h6-mbus + - allwinner,sun50i-h616-mbus + - allwinner,sun50i-r329-mbus reg: minItems: 1 @@ -81,13 +91,13 @@ required: - dma-ranges if: - properties: - compatible: - contains: - enum: - - allwinner,sun8i-h3-mbus - - allwinner,sun50i-a64-mbus - - allwinner,sun50i-h5-mbus + not: + properties: + compatible: + contains: + enum: + - allwinner,sun5i-a13-mbus + - allwinner,sun8i-r40-mbus then: properties: diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt index d8b48f2edf1b..851f48ead927 100644 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ b/Documentation/devicetree/bindings/arm/syna.txt @@ -18,10 +18,6 @@ stable binding/ABI. --------------------------------------------------------------- -Boards with the Synaptics AS370 SoC shall have the following properties: - Required root node property: - compatible: "syna,as370" - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 49841ca272ee..1f62253f9410 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/tegra.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NVIDIA Tegra device tree bindings +title: NVIDIA Tegra maintainers: - Thierry Reding <thierry.reding@gmail.com> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml new file mode 100644 index 000000000000..711bb4d08c60 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings + +maintainers: + - Sumit Gupta <sumitg@nvidia.com> + - Mikko Perttunen <mperttunen@nvidia.com> + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: |+ + The Tegra CPU COMPLEX CLUSTER area contains memory-mapped + registers that initiate CPU frequency/voltage transitions. + +properties: + $nodename: + pattern: "ccplex@([0-9a-f]+)$" + + compatible: + enum: + - nvidia,tegra186-ccplex-cluster + - nvidia,tegra234-ccplex-cluster + + reg: + maxItems: 1 + + nvidia,bpmp: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the BPMP node that needs to be queried to get + operating point data for all CPUs. + +additionalProperties: false + +required: + - compatible + - reg + - nvidia,bpmp + +examples: + - | + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0e000000 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml new file mode 100644 index 000000000000..788a13f8aa93 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra194 AXI2APB bridge + +maintainers: + - Sumit Gupta <sumitg@nvidia.com> + +properties: + $nodename: + pattern: "^axi2apb@([0-9a-f]+)$" + + compatible: + enum: + - nvidia,tegra194-axi2apb + + reg: + maxItems: 6 + description: Physical base address and length of registers for all bridges + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + axi2apb: axi2apb@2390000 { + compatible = "nvidia,tegra194-axi2apb"; + reg = <0x02390000 0x1000>, + <0x023a0000 0x1000>, + <0x023b0000 0x1000>, + <0x023c0000 0x1000>, + <0x023d0000 0x1000>, + <0x023e0000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml new file mode 100644 index 000000000000..debb2b0c8013 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra194 CBB 1.0 bindings + +maintainers: + - Sumit Gupta <sumitg@nvidia.com> + +description: |+ + The Control Backbone (CBB) is comprised of the physical path from an + initiator to a target's register configuration space. CBB 1.0 has + multiple hierarchical sub-NOCs (Network-on-Chip) and connects various + initiators and targets using different bridges like AXIP2P, AXI2APB. + + This driver handles errors due to illegal register accesses reported + by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs + "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" + which is the main NOC. + + By default, the access issuing initiator is informed about the error + using SError or Data Abort exception unless the ERD (Error Response + Disable) is enabled/set for that initiator. If the ERD is enabled, then + SError or Data Abort is masked and the error is reported with interrupt. + + - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the + errors due to illegal accesses from CCPLEX are reported by interrupts. + If ERD is not set, then error is reported by SError. + - For other initiators, the ERD is disabled. So, the access issuing + initiator is informed about the illegal access by Data Abort exception. + In addition, an interrupt is also generated to CCPLEX. These initiators + include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and + engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder + engine) etc which can initiate transactions. + + The driver prints relevant debug information like Error Code, Error + Description, Master, Address, AXI ID, Cache, Protection, Security Group + etc on receiving error notification. + +properties: + $nodename: + pattern: "^[a-z]+-noc@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra194-cbb-noc + - nvidia,tegra194-aon-noc + - nvidia,tegra194-bpmp-noc + - nvidia,tegra194-rce-noc + - nvidia,tegra194-sce-noc + + reg: + maxItems: 1 + + interrupts: + description: + CCPLEX receives secure or nonsecure interrupt depending on error type. + A secure interrupt is received for SEC(firewall) & SLV errors and a + non-secure interrupt is received for TMO & DEC errors. + items: + - description: non-secure interrupt + - description: secure interrupt + + nvidia,axi2apb: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + Specifies the node having all axi2apb bridges which need to be checked + for any error logged in their status register. + + nvidia,apbmisc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + Specifies the apbmisc node which need to be used for reading the ERD + register. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - nvidia,apbmisc + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + cbb-noc@2300000 { + compatible = "nvidia,tegra194-cbb-noc"; + reg = <0x02300000 0x1000>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 0afec83cc723..7fd8d47b1be4 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -14,7 +14,6 @@ properties: compatible: enum: - nvidia,tegra20-pmc - - nvidia,tegra20-pmc - nvidia,tegra30-pmc - nvidia,tegra114-pmc - nvidia,tegra124-pmc @@ -209,7 +208,7 @@ properties: "^[a-z0-9]+$": type: object - patternProperties: + properties: clocks: minItems: 1 maxItems: 8 diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml new file mode 100644 index 000000000000..7b1fe50ffbe0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra CBB 2.0 bindings + +maintainers: + - Sumit Gupta <sumitg@nvidia.com> + +description: |+ + The Control Backbone (CBB) is comprised of the physical path from an + initiator to a target's register configuration space. CBB 2.0 consists + of multiple sub-blocks connected to each other to create a topology. + The Tegra234 SoC has different fabrics based on CBB 2.0 architecture + which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and + "CBB central fabric". + + In CBB 2.0, each initiator which can issue transactions connects to a + Root Master Node (MN) before it connects to any other element of the + fabric. Each Root MN contains a Error Monitor (EM) which detects and + logs error. Interrupts from various EM blocks are collated by Error + Notifier (EN) which is per fabric and presents a single interrupt from + fabric to the SoC interrupt controller. + + The driver handles errors from CBB due to illegal register accesses + and prints debug information about failed transaction on receiving + the interrupt from EN. Debug information includes Error Code, Error + Description, MasterID, Fabric, SlaveID, Address, Cache, Protection, + Security Group etc on receiving error notification. + + If the Error Response Disable (ERD) is set/enabled for an initiator, + then SError or Data abort exception error response is masked and an + interrupt is used for reporting errors due to illegal accesses from + that initiator. The value returned on read failures is '0xFFFFFFFF' + for compatibility with PCIE. + +properties: + $nodename: + pattern: "^[a-z]+-fabric@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra234-aon-fabric + - nvidia,tegra234-bpmp-fabric + - nvidia,tegra234-cbb-fabric + - nvidia,tegra234-dce-fabric + - nvidia,tegra234-rce-fabric + - nvidia,tegra234-sce-fabric + + reg: + maxItems: 1 + + interrupts: + items: + - description: secure interrupt from error notifier + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + cbb-fabric@1300000 { + compatible = "nvidia,tegra234-cbb-fabric"; + reg = <0x13a00000 0x400000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml b/Documentation/devicetree/bindings/arm/tesla.yaml new file mode 100644 index 000000000000..d670a0d56222 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tesla.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tesla.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla Full Self Driving(FSD) platforms + +maintainers: + - Alim Akhtar <alim.akhtar@samsung.com> + - linux-fsd@tesla.com + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: FSD SoC board + items: + - enum: + - tesla,fsd-evb # Tesla FSD Evaluation + - const: tesla,fsd + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index b03c10fa2e7a..28b8232e1c5b 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -19,25 +19,35 @@ properties: compatible: oneOf: + - description: K3 AM62A7 SoC + items: + - enum: + - ti,am62a7-sk + - const: ti,am62a7 + + - description: K3 AM625 SoC + items: + - enum: + - ti,am625-sk + - const: ti,am625 + + - description: K3 AM642 SoC + items: + - enum: + - ti,am642-evm + - ti,am642-sk + - const: ti,am642 + - description: K3 AM654 SoC items: - enum: - - ti,am654-evm - - siemens,iot2050-basic - - siemens,iot2050-basic-pg2 - siemens,iot2050-advanced - siemens,iot2050-advanced-pg2 + - siemens,iot2050-basic + - siemens,iot2050-basic-pg2 + - ti,am654-evm - const: ti,am654 - - description: K3 J721E SoC - oneOf: - - const: ti,j721e - - items: - - enum: - - ti,j721e-evm - - ti,j721e-sk - - const: ti,j721e - - description: K3 J7200 SoC oneOf: - const: ti,j7200 @@ -46,12 +56,14 @@ properties: - ti,j7200-evm - const: ti,j7200 - - description: K3 AM642 SoC - items: - - enum: - - ti,am642-evm - - ti,am642-sk - - const: ti,am642 + - description: K3 J721E SoC + oneOf: + - const: ti,j721e + - items: + - enum: + - ti,j721e-evm + - ti,j721e-sk + - const: ti,j721e - description: K3 J721s2 SoC items: diff --git a/Documentation/devicetree/bindings/arm/toshiba.yaml b/Documentation/devicetree/bindings/arm/toshiba.yaml index 9c1cacbdc916..716ba4a3cab4 100644 --- a/Documentation/devicetree/bindings/arm/toshiba.yaml +++ b/Documentation/devicetree/bindings/arm/toshiba.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/toshiba.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Toshiba Visconti Platform Device Tree Bindings +title: Toshiba Visconti Platform maintainers: - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> diff --git a/Documentation/devicetree/bindings/arm/ux500.yaml b/Documentation/devicetree/bindings/arm/ux500.yaml index 5db7cfba81a4..b42d20fa4359 100644 --- a/Documentation/devicetree/bindings/arm/ux500.yaml +++ b/Documentation/devicetree/bindings/arm/ux500.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/ux500.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ux500 platforms device tree bindings +title: Ux500 platforms maintainers: - Linus Walleij <linus.walleij@linaro.org> @@ -20,6 +20,11 @@ properties: - const: st-ericsson,mop500 - const: st-ericsson,u8500 + - description: ST-Ericsson HREF520 + items: + - const: st-ericsson,href520 + - const: st-ericsson,u8500 + - description: ST-Ericsson HREF (v60+) items: - const: st-ericsson,hrefv60+ @@ -30,9 +35,39 @@ properties: - const: calaosystems,snowball-a9500 - const: st-ericsson,u9500 + - description: Samsung Galaxy Ace 2 (GT-I8160) + items: + - const: samsung,codina + - const: st-ericsson,u8500 + + - description: Samsung Galaxy Exhibit (SGH-T599) + items: + - const: samsung,codina-tmo + - const: st-ericsson,u8500 + + - description: Samsung Galaxy Beam (GT-I8530) + items: + - const: samsung,gavini + - const: st-ericsson,u8500 + - description: Samsung Galaxy S III mini (GT-I8190) items: - const: samsung,golden - const: st-ericsson,u8500 + - description: Samsung Galaxy S Advance (GT-I9070) + items: + - const: samsung,janice + - const: st-ericsson,u8500 + + - description: Samsung Galaxy Amp (SGH-I407) + items: + - const: samsung,kyle + - const: st-ericsson,u8500 + + - description: Samsung Galaxy XCover 2 (GT-S7710) + items: + - const: samsung,skomer + - const: st-ericsson,u8500 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/versatile-sysreg.txt b/Documentation/devicetree/bindings/arm/versatile-sysreg.txt deleted file mode 100644 index a4f15262d717..000000000000 --- a/Documentation/devicetree/bindings/arm/versatile-sysreg.txt +++ /dev/null @@ -1,10 +0,0 @@ -ARM Versatile system registers --------------------------------------- - -This is a system control registers block, providing multiple low level -platform functions like board detection and identification, software -interrupt generation, MMC and NOR Flash control etc. - -Required node properties: -- compatible value : = "arm,versatile-sysreg", "syscon" -- reg : physical base address and the size of the registers window diff --git a/Documentation/devicetree/bindings/arm/vexpress-config.yaml b/Documentation/devicetree/bindings/arm/vexpress-config.yaml new file mode 100644 index 000000000000..09e1adf5ca7a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vexpress-config.yaml @@ -0,0 +1,285 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/vexpress-config.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Express configuration bus bindings + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +description: + This is a system control register block, acting as a bridge to the + platform's configuration bus via "system control" interface, addressing + devices with site number, position in the board stack, config controller, + function and device numbers - see motherboard's TRM for more details. + +properties: + compatible: + const: arm,vexpress,config-bus + + arm,vexpress,config-bridge: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the sysreg node. + + muxfpga: + type: object + properties: + compatible: + const: arm,vexpress-muxfpga + + arm,vexpress-sysreg,func: + description: FPGA specifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 7 + - description: device number + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + shutdown: + type: object + properties: + compatible: + const: arm,vexpress-shutdown + + arm,vexpress-sysreg,func: + description: shutdown identifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 8 + - description: device number + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + reboot: + type: object + properties: + compatible: + const: arm,vexpress-reboot + + arm,vexpress-sysreg,func: + description: reboot identifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 9 + - description: device number + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + dvimode: + type: object + properties: + compatible: + const: arm,vexpress-dvimode + + arm,vexpress-sysreg,func: + description: DVI mode identifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 11 + - description: device number + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + +additionalProperties: false + +required: + - compatible + - arm,vexpress,config-bridge + +patternProperties: + 'clk[0-9]*$': + type: object + description: + clocks + + properties: + compatible: + const: arm,vexpress-osc + + arm,vexpress-sysreg,func: + description: clock specifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 1 + - description: clock number + + freq-range: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: minimal clock frequency + - description: maximum clock frequency + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + - "#clock-cells" + + "^volt-.+$": + $ref: /schemas/regulator/regulator.yaml# + properties: + compatible: + const: arm,vexpress-volt + + arm,vexpress-sysreg,func: + description: regulator specifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 2 + - description: device number + + label: + maxItems: 1 + + unevaluatedProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + "^amp-.+$": + type: object + properties: + compatible: + const: arm,vexpress-amp + + arm,vexpress-sysreg,func: + description: current sensor identifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 3 + - description: device number + + label: + maxItems: 1 + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + "^temp-.+$": + type: object + properties: + compatible: + const: arm,vexpress-temp + + arm,vexpress-sysreg,func: + description: temperature sensor identifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 4 + - description: device number + + label: + maxItems: 1 + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + "^reset[0-9]*$": + type: object + properties: + compatible: + const: arm,vexpress-reset + + arm,vexpress-sysreg,func: + description: reset specifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 5 + - description: reset device number + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + "^power-.+$": + type: object + properties: + compatible: + const: arm,vexpress-power + + arm,vexpress-sysreg,func: + description: power sensor identifier + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 12 + - description: device number + + label: + maxItems: 1 + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + + "^energy(-.+)?$": + type: object + properties: + compatible: + const: arm,vexpress-energy + + arm,vexpress-sysreg,func: + description: energy sensor identifier + $ref: /schemas/types.yaml#/definitions/uint32-array + oneOf: + - items: + - const: 13 + - description: device number + - items: + - const: 13 + - description: device number + - const: 13 + - description: second device number + + label: + maxItems: 1 + + additionalProperties: false + required: + - compatible + - arm,vexpress-sysreg,func + +examples: + - | + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + clk0 { + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + #clock-cells = <0>; + }; + + energy { + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 0>, <13 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt deleted file mode 100644 index 50095802fb4a..000000000000 --- a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt +++ /dev/null @@ -1,103 +0,0 @@ -ARM Versatile Express system registers --------------------------------------- - -This is a system control registers block, providing multiple low level -platform functions like board detection and identification, software -interrupt generation, MMC and NOR Flash control etc. - -Required node properties: -- compatible value : = "arm,vexpress,sysreg"; -- reg : physical base address and the size of the registers window - -Deprecated properties, replaced by GPIO subnodes (see below): -- gpio-controller : specifies that the node is a GPIO controller -- #gpio-cells : size of the GPIO specifier, should be 2: - - first cell is the pseudo-GPIO line number: - 0 - MMC CARDIN - 1 - MMC WPROT - 2 - NOR FLASH WPn - - second cell can take standard GPIO flags (currently ignored). - -Control registers providing pseudo-GPIO lines must be represented -by subnodes, each of them requiring the following properties: -- compatible value : one of - "arm,vexpress-sysreg,sys_led" - "arm,vexpress-sysreg,sys_mci" - "arm,vexpress-sysreg,sys_flash" -- gpio-controller : makes the node a GPIO controller -- #gpio-cells : size of the GPIO specifier, must be 2: - - first cell is the function number: - - for sys_led : 0..7 = LED 0..7 - - for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT - - for sys_flash : 0 = NOR FLASH WPn - - second cell can take standard GPIO flags (currently ignored). - -Example: - v2m_sysreg: sysreg@10000000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x10000000 0x1000>; - - v2m_led_gpios: sys_led@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: sys_mci@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: sys_flash@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - -This block also can also act a bridge to the platform's configuration -bus via "system control" interface, addressing devices with site number, -position in the board stack, config controller, function and device -numbers - see motherboard's TRM for more details. All configuration -controller accessible via this interface must reference the sysreg -node via "arm,vexpress,config-bridge" phandle and define appropriate -topology properties - see main vexpress node documentation for more -details. Each child of such node describes one function and must -define the following properties: -- compatible value : must be one of (corresponding to the TRM): - "arm,vexpress-amp" - "arm,vexpress-dvimode" - "arm,vexpress-energy" - "arm,vexpress-muxfpga" - "arm,vexpress-osc" - "arm,vexpress-power" - "arm,vexpress-reboot" - "arm,vexpress-reset" - "arm,vexpress-scc" - "arm,vexpress-shutdown" - "arm,vexpress-temp" - "arm,vexpress-volt" -- arm,vexpress-sysreg,func : must contain a set of two cells long groups: - - first cell of each group defines the function number - (eg. 1 for clock generator, 2 for voltage regulators etc.) - - second cell of each group defines device number (eg. osc 0, - osc 1 etc.) - - some functions (eg. energy meter, with its 64 bit long counter) - are using more than one function/device number pair - -Example: - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - osc@0 { - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - }; - - energy@0 { - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>, <13 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml b/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml new file mode 100644 index 000000000000..f04db802a732 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Express system registers bindings + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +description: + This is a system control registers block, providing multiple low level + platform functions like board detection and identification, software + interrupt generation, MMC and NOR Flash control, etc. + +properties: + compatible: + const: arm,vexpress-sysreg + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + gpio-controller: + deprecated: true + + "#gpio-cells": + deprecated: true + const: 2 + +additionalProperties: false + +patternProperties: + '^gpio@[0-9a-f]+$': + type: object + additionalProperties: false + description: + GPIO children + + properties: + compatible: + enum: + - arm,vexpress-sysreg,sys_led + - arm,vexpress-sysreg,sys_mci + - arm,vexpress-sysreg,sys_flash + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is the function number: + for sys_led : 0..7 = LED 0..7 + for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT + for sys_flash : 0 = NOR FLASH WPn + The second cell can take standard GPIO flags. + + reg: + maxItems: 1 + + required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +required: + - compatible + - reg + +examples: + - | + sysreg@0 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + v2m_led_gpios: gpio@8 { + compatible = "arm,vexpress-sysreg,sys_led"; + reg = <0x008 4>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/vt8500.yaml b/Documentation/devicetree/bindings/arm/vt8500.yaml index 7b762bfc11e7..5d5ad5a60451 100644 --- a/Documentation/devicetree/bindings/arm/vt8500.yaml +++ b/Documentation/devicetree/bindings/arm/vt8500.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/vt8500.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: VIA/Wondermedia VT8500 Platforms Device Tree Bindings +title: VIA/Wondermedia VT8500 Platforms maintainers: - Tony Prisk <linux@prisktech.co.nz> diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt index db5c56db30ec..61d77acbeb5e 100644 --- a/Documentation/devicetree/bindings/arm/xen.txt +++ b/Documentation/devicetree/bindings/arm/xen.txt @@ -7,15 +7,17 @@ the following properties: compatible = "xen,xen-<version>", "xen,xen"; where <version> is the version of the Xen ABI of the platform. -- reg: specifies the base physical address and size of a region in - memory where the grant table should be mapped to, using an - HYPERVISOR_memory_op hypercall. The memory region is large enough to map - the whole grant table (it is larger or equal to gnttab_max_grant_frames()). - This property is unnecessary when booting Dom0 using ACPI. +- reg: specifies the base physical address and size of the regions in memory + where the special resources should be mapped to, using an HYPERVISOR_memory_op + hypercall. + Region 0 is reserved for mapping grant table, it must be always present. + The memory region is large enough to map the whole grant table (it is larger + or equal to gnttab_max_grant_frames()). + Regions 1...N are extended regions (unused address space) for mapping foreign + GFNs and grants, they might be absent if there is nothing to expose. - interrupts: the interrupt used by Xen to inject event notifications. A GIC node is also required. - This property is unnecessary when booting Dom0 using ACPI. To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node under /hypervisor with following parameters: diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index 4dc0e0195974..969cfe6dc434 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/xilinx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx Zynq Platforms Device Tree Bindings +title: Xilinx Zynq Platforms maintainers: - Michal Simek <michal.simek@xilinx.com> |