aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/exynos5420-cpus.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/exynos5420-cpus.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5420-cpus.dtsi23
1 files changed, 19 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 5c052d7ff554..123f0cef658d 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5420 SoC cpu device tree source
*
@@ -14,10 +15,6 @@
* booting cluster (big or LITTLE) is chosen by IROM code by reading
* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
* from the LITTLE: Cortex-A7.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/ {
@@ -36,6 +33,7 @@
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <1024>;
};
cpu1: cpu@1 {
@@ -48,6 +46,7 @@
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <1024>;
};
cpu2: cpu@2 {
@@ -60,6 +59,7 @@
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <1024>;
};
cpu3: cpu@3 {
@@ -72,6 +72,7 @@
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <1024>;
};
cpu4: cpu@100 {
@@ -85,6 +86,7 @@
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <539>;
};
cpu5: cpu@101 {
@@ -97,6 +99,7 @@
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <539>;
};
cpu6: cpu@102 {
@@ -109,6 +112,7 @@
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <539>;
};
cpu7: cpu@103 {
@@ -121,6 +125,17 @@
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <539>;
};
};
};
+
+&arm_a7_pmu {
+ interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ status = "okay";
+};
+
+&arm_a15_pmu {
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ status = "okay";
+};