diff options
Diffstat (limited to 'arch/arm/boot/dts')
714 files changed, 38150 insertions, 16485 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index eff87a344566..ade7a38543dc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,6 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -ifeq ($(CONFIG_OF),y) - dtb-$(CONFIG_ARCH_ALPINE) += \ alpine-db.dtb dtb-$(CONFIG_MACH_ARTPEC6) += \ @@ -47,7 +45,9 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91sam9x35ek.dtb dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2.dtb \ + at91-nattis-2-natte-2.dtb \ at91-sama5d27_som1_ek.dtb \ + at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ at91-tse850-3.dtb \ @@ -101,6 +101,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-tplink-archer-c9-v1.dtb \ bcm47094-dlink-dir-885l.dtb \ bcm47094-linksys-panamera.dtb \ + bcm47094-luxul-abr-4500.dtb \ + bcm47094-luxul-xbr-4500.dtb \ bcm47094-luxul-xwr-3100.dtb \ bcm47094-netgear-r8500.dtb \ bcm94708.dtb \ @@ -109,6 +111,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm953012hr.dtb \ bcm953012k.dtb dtb-$(CONFIG_ARCH_BCM_53573) += \ + bcm47189-luxul-xap-1440.dtb \ + bcm47189-luxul-xap-810.dtb \ bcm47189-tenda-ac9.dtb \ bcm947189acdbmr.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ @@ -118,6 +122,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ bcm911360k.dtb \ bcm958300k.dtb \ bcm958305k.dtb +dtb-$(CONFIG_ARCH_BCM_HR2) += \ + bcm53340-ubnt-unifi-switch8.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm28155-ap.dtb \ bcm21664-garnet.dtb \ @@ -177,6 +183,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5420-arndale-octa.dtb \ exynos5420-peach-pit.dtb \ exynos5420-smdk5420.dtb \ + exynos5422-odroidhc1.dtb \ exynos5422-odroidxu3.dtb \ exynos5422-odroidxu3-lite.dtb \ exynos5422-odroidxu4.dtb \ @@ -185,6 +192,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-dlink-dir-685.dtb \ + gemini-dlink-dns-313.dtb \ gemini-nas4220b.dtb \ gemini-rut1xx.dtb \ gemini-sq201.dtb \ @@ -342,12 +350,14 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-babbage.dtb \ imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ - imx51-ts4800.dtb + imx51-ts4800.dtb \ + imx51-zii-rdu1.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ + imx53-ppd.dtb \ imx53-qsb.dtb \ imx53-qsrb.dtb \ imx53-smd.dtb \ @@ -363,6 +373,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ imx6dl-cubox-i.dtb \ + imx6dl-cubox-i-emmc-som-v15.dtb \ + imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ @@ -375,6 +387,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw5903.dtb \ imx6dl-gw5904.dtb \ imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ + imx6dl-hummingboard2.dtb \ + imx6dl-hummingboard2-emmc-som-v15.dtb \ + imx6dl-hummingboard2-som-v15.dtb \ imx6dl-icore.dtb \ imx6dl-icore-rqs.dtb \ imx6dl-nit6xlite.dtb \ @@ -387,16 +404,22 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-sabresd.dtb \ imx6dl-savageboard.dtb \ imx6dl-ts4900.dtb \ + imx6dl-ts7970.dtb \ imx6dl-tx6dl-comtft.dtb \ imx6dl-tx6s-8034.dtb \ + imx6dl-tx6s-8034-mb7.dtb \ imx6dl-tx6s-8035.dtb \ + imx6dl-tx6s-8035-mb7.dtb \ imx6dl-tx6u-801x.dtb \ + imx6dl-tx6u-80xx-mb7.dtb \ imx6dl-tx6u-8033.dtb \ + imx6dl-tx6u-8033-mb7.dtb \ imx6dl-tx6u-811x.dtb \ imx6dl-tx6u-81xx-mb7.dtb \ imx6dl-udoo.dtb \ imx6dl-wandboard.dtb \ imx6dl-wandboard-revb1.dtb \ + imx6dl-wandboard-revd1.dtb \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ @@ -407,7 +430,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-b850v3.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ + imx6q-cubox-i-emmc-som-v15.dtb \ + imx6q-cubox-i-som-v15.dtb \ imx6q-dfi-fs700-m60.dtb \ + imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ @@ -424,6 +450,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw5904.dtb \ imx6q-h100.dtb \ imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ + imx6q-hummingboard-som-v15.dtb \ + imx6q-hummingboard2.dtb \ + imx6q-hummingboard2-emmc-som-v15.dtb \ + imx6q-hummingboard2-som-v15.dtb \ imx6q-icore.dtb \ imx6q-icore-ofcap10.dtb \ imx6q-icore-ofcap12.dtb \ @@ -435,6 +466,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-nitrogen6_som2.dtb \ imx6q-novena.dtb \ imx6q-phytec-pbab01.dtb \ + imx6q-pistachio.dtb \ imx6q-rex-pro.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ @@ -443,22 +475,32 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-sbc6x.dtb \ imx6q-tbs2910.dtb \ imx6q-ts4900.dtb \ + imx6q-ts7970.dtb \ imx6q-tx6q-1010.dtb \ imx6q-tx6q-1010-comtft.dtb \ imx6q-tx6q-1020.dtb \ imx6q-tx6q-1020-comtft.dtb \ imx6q-tx6q-1036.dtb \ + imx6q-tx6q-1036-mb7.dtb \ + imx6q-tx6q-10x0-mb7.dtb \ imx6q-tx6q-1110.dtb \ imx6q-tx6q-11x0-mb7.dtb \ imx6q-udoo.dtb \ imx6q-utilite-pro.dtb \ + imx6q-var-dt6customboard.dtb \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ + imx6q-wandboard-revd1.dtb \ imx6q-zii-rdu2.dtb \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ + imx6qp-tx6qp-8037.dtb \ + imx6qp-tx6qp-8037-mb7.dtb \ + imx6qp-tx6qp-8137.dtb \ + imx6qp-tx6qp-8137-mb7.dtb \ + imx6qp-wandboard-revd1.dtb \ imx6qp-zii-rdu2.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ @@ -469,6 +511,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sdb-reva.dtb \ imx6sx-sdb-sai.dtb \ imx6sx-sdb.dtb \ + imx6sx-softing-vining-2000.dtb \ imx6sx-udoo-neo-basic.dtb \ imx6sx-udoo-neo-extended.dtb \ imx6sx-udoo-neo-full.dtb @@ -486,15 +529,17 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-14x14-evk.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ + imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ imx7d-nitrogen7.dtb \ - imx7d-pico.dtb \ + imx7d-pico-pi.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-warp.dtb dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ ls1021a-twr.dtb dtb-$(CONFIG_SOC_VF610) += \ @@ -533,6 +578,7 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-m28cu3.dtb \ imx28-m28evk.dtb \ imx28-sps1.dtb \ + imx28-ts4600.dtb \ imx28-tx28.dtb dtb-$(CONFIG_ARCH_NOMADIK) += \ ste-nomadik-s8815.dtb \ @@ -664,6 +710,7 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-sbc-am57x.dtb \ am572x-idk.dtb \ am571x-idk.dtb \ + am574x-idk.dtb \ dra7-evm.dtb \ dra72-evm.dtb \ dra72-evm-revc.dtb \ @@ -681,12 +728,14 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-netgear-wnr854t.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_ACTIONS) += \ - owl-s500-guitar-bb-rev-b.dtb + owl-s500-cubieboard6.dtb \ + owl-s500-guitar-bb-rev-b.dtb \ + owl-s500-sparky.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_OXNAS) += \ - wd-mbwe.dtb \ - cloudengines-pogoplug-series-3.dtb + ox810se-wd-mbwe.dtb \ + ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-arrow-sd-600eval.dtb \ @@ -701,7 +750,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ + qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ + qcom-msm8974-sony-xperia-castor.dtb \ qcom-msm8974-sony-xperia-honami.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ @@ -725,7 +776,10 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-iwg20d-q7.dtb \ + r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ + r8a7745-iwg22d-sodimm.dtb \ + r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ @@ -768,7 +822,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3288-veyron-pinky.dtb \ - rk3288-veyron-speedy.dtb + rk3288-veyron-speedy.dtb \ + rk3288-vyasa.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ @@ -891,6 +946,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-lime2-emmc.dtb \ sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ sun7i-a20-orangepi.dtb \ sun7i-a20-orangepi-mini.dtb \ sun7i-a20-pcduino3.dtb \ @@ -916,9 +972,12 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ sun8i-h3-nanopi-m1.dtb \ sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ @@ -932,8 +991,10 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb @@ -1066,13 +1127,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8127-moose.dtb \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb -dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \ +dtb-$(CONFIG_ARCH_ASPEED) += \ + aspeed-ast2500-evb.dtb \ + aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ - aspeed-ast2500-evb.dtb -endif - -dtstree := $(srctree)/$(src) -dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) - -always := $(dtb-y) -clean-files := *.dtb + aspeed-bmc-opp-witherspoon.dtb \ + aspeed-bmc-opp-zaius.dtb \ + aspeed-bmc-quanta-q71l.dtb diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 48a15fc641f2..e67b4d65c8d0 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -409,6 +409,6 @@ }; &rtc { - clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index cdc1b2be792f..3f2480d05a3b 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -159,6 +159,7 @@ >; }; + /* UT0 */ uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ @@ -166,6 +167,37 @@ >; }; + /* UT1 */ + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */ + >; + }; + + /* GPS */ + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ + AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ + >; + }; + + /* DSM2 */ + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + >; + }; + + /* UT5 */ + uart5_pins: pinmux_uart5_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8C4, PIN_INPUT_PULLUP | MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ + AM33XX_IOPAD(0x8C0, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ + >; + }; + mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ @@ -216,10 +248,19 @@ wl18xx_pins: pinmux_wl18xx_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] - WL_IRQ */ + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ >; }; + + /* DCAN */ + dcan1_pins: pinmux_dcan1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ + AM33XX_IOPAD(0x940, PIN_OUTPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + >; + }; }; &uart0 { @@ -229,6 +270,34 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + + status = "okay"; +}; + &usb { status = "okay"; }; @@ -414,7 +483,7 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio0>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; }; }; @@ -446,10 +515,16 @@ &rtc { system-power-controller; - clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + &gpio3 { ls_buf_en { gpio-hog; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index ddd897556e03..fee6b3ee1741 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -790,6 +790,6 @@ }; &rtc { - clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 9ba4b18c0cb2..fa608cd5dc14 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -722,6 +722,6 @@ }; &rtc { - clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 03c7d77023c6..9fb7426070ce 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -139,7 +139,7 @@ &audio_codec { status = "okay"; - gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; AVDD-supply = <&ldo3_reg>; IOVDD-supply = <&ldo3_reg>; DRVDD-supply = <&ldo3_reg>; diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 8d8319590cde..95d5c9d136c5 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -292,14 +292,6 @@ clock-div = <4>; }; - cefuse_fck: cefuse_fck@a20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <1>; - reg = <0x0a20>; - }; - clk_24mhz: clk_24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -316,14 +308,6 @@ clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick@14c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ck>; - ti,bit-shift = <1>; - reg = <0x014c>; - }; - l3_gclk: l3_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -350,49 +334,49 @@ timer1_fck: timer1_fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; + clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; timer2_fck: timer2_fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0508>; }; timer3_fck: timer3_fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x050c>; }; timer4_fck: timer4_fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0510>; }; timer5_fck: timer5_fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0518>; }; timer6_fck: timer6_fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x051c>; }; timer7_fck: timer7_fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0504>; }; @@ -423,7 +407,7 @@ wdt1_fck: wdt1_fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; + clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0538>; }; @@ -493,42 +477,10 @@ gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x053c>; }; - gpio0_dbclk: gpio0_dbclk@408 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&gpio0_dbclk_mux_ck>; - ti,bit-shift = <18>; - reg = <0x0408>; - }; - - gpio1_dbclk: gpio1_dbclk@ac { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00ac>; - }; - - gpio2_dbclk: gpio2_dbclk@b0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00b0>; - }; - - gpio3_dbclk: gpio3_dbclk@b4 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00b4>; - }; - lcd_gclk: lcd_gclk@534 { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -577,58 +529,6 @@ reg = <0x0700>; }; - dbg_sysclk_ck: dbg_sysclk_ck@414 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <19>; - reg = <0x0414>; - }; - - dbg_clka_ck: dbg_clka_ck@414 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_core_m4_ck>; - ti,bit-shift = <30>; - reg = <0x0414>; - }; - - stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; - ti,bit-shift = <22>; - reg = <0x0414>; - }; - - trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; - ti,bit-shift = <20>; - reg = <0x0414>; - }; - - stm_clk_div_ck: stm_clk_div_ck@414 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&stm_pmd_clock_mux_ck>; - ti,bit-shift = <27>; - ti,max-div = <64>; - reg = <0x0414>; - ti,index-power-of-two; - }; - - trace_clk_div_ck: trace_clk_div_ck@414 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&trace_pmd_clk_mux_ck>; - ti,bit-shift = <24>; - ti,max-div = <64>; - reg = <0x0414>; - ti,index-power-of-two; - }; - clkout2_ck: clkout2_ck@700 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -638,9 +538,88 @@ }; }; -&prcm_clockdomains { - clk_24mhz_clkdm: clk_24mhz_clkdm { - compatible = "ti,clockdomain"; - clocks = <&clkdiv32k_ick>; +&prcm { + l4_per_cm: l4_per_cm@0 { + compatible = "ti,omap4-cm"; + reg = <0x0 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x200>; + + l4_per_clkctrl: clk@14 { + compatible = "ti,clkctrl"; + reg = <0x14 0x13c>; + #clock-cells = <2>; + }; + }; + + l4_wkup_cm: l4_wkup_cm@400 { + compatible = "ti,omap4-cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + l4_wkup_clkctrl: clk@4 { + compatible = "ti,clkctrl"; + reg = <0x4 0xd4>; + #clock-cells = <2>; + }; + }; + + mpu_cm: mpu_cm@600 { + compatible = "ti,omap4-cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + mpu_clkctrl: clk@4 { + compatible = "ti,clkctrl"; + reg = <0x4 0x4>; + #clock-cells = <2>; + }; + }; + + l4_rtc_cm: l4_rtc_cm@800 { + compatible = "ti,omap4-cm"; + reg = <0x800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x100>; + + l4_rtc_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x4>; + #clock-cells = <2>; + }; + }; + + gfx_l3_cm: gfx_l3_cm@900 { + compatible = "ti,omap4-cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + gfx_l3_clkctrl: clk@4 { + compatible = "ti,clkctrl"; + reg = <0x4 0x4>; + #clock-cells = <2>; + }; + }; + + l4_cefuse_cm: l4_cefuse_cm@a00 { + compatible = "ti,omap4-cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + l4_cefuse_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index e58fab8aec5d..628c77b0b386 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/am33xx.h> +#include <dt-bindings/clock/am3.h> / { compatible = "ti,am33xx"; @@ -130,9 +131,11 @@ }; }; - pmu { + pmu@4b000000 { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; + reg = <0x4b000000 0x1000000>; + ti,hwmods = "debugss"; }; /* @@ -177,8 +180,11 @@ }; prcm: prcm@200000 { - compatible = "ti,am3-prcm"; + compatible = "ti,am3-prcm", "simple-bus"; reg = <0x200000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x4000>; prcm_clocks: clocks { #address-cells = <1>; @@ -494,7 +500,7 @@ status = "disabled"; }; - mailbox: mailbox@480C8000 { + mailbox: mailbox@480c8000 { compatible = "ti,omap4-mailbox"; reg = <0x480C8000 0x200>; interrupts = <77>; @@ -515,6 +521,8 @@ interrupts = <67>; ti,hwmods = "timer1"; ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; }; timer2: timer@48040000 { @@ -522,6 +530,8 @@ reg = <0x48040000 0x400>; interrupts = <68>; ti,hwmods = "timer2"; + clocks = <&timer2_fck>; + clock-names = "fck"; }; timer3: timer@48042000 { @@ -569,7 +579,7 @@ interrupts = <75 76>; ti,hwmods = "rtc"; - clocks = <&clkdiv32k_ick>; + clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "int-clk"; }; @@ -628,6 +638,7 @@ reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb0: usb@47401000 { @@ -676,6 +687,7 @@ reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb1: usb@47401800 { @@ -929,6 +941,12 @@ }; }; + emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; @@ -981,7 +999,7 @@ dma-names = "tx", "rx"; }; - mcasp1: mcasp@4803C000 { + mcasp1: mcasp@4803c000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp1"; reg = <0x4803C000 0x2000>, @@ -1004,4 +1022,4 @@ }; }; -/include/ "am33xx-clocks.dtsi" +#include "am33xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 00da3f2c4072..ca294914bbb1 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -26,7 +26,7 @@ interrupt-names = "mc"; }; - davinci_emac: ethernet@0x5c000000 { + davinci_emac: ethernet@5c000000 { compatible = "ti,am3517-emac"; ti,hwmods = "davinci_emac"; status = "disabled"; @@ -41,7 +41,7 @@ local-mac-address = [ 00 00 00 00 00 00 ]; }; - davinci_mdio: ethernet@0x5c030000 { + davinci_mdio: ethernet@5c030000 { compatible = "ti,davinci_mdio"; ti,hwmods = "davinci_mdio"; status = "disabled"; @@ -99,9 +99,5 @@ status = "disabled"; }; -&smartreflex_mpu_iva { - status = "disabled"; -}; - /include/ "am35xx-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index e5b061469bf8..964f3ef79728 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/am4.h> / { compatible = "ti,am4372", "ti,am43"; @@ -163,9 +164,12 @@ }; prcm: prcm@1f0000 { - compatible = "ti,am4-prcm"; + compatible = "ti,am4-prcm", "simple-bus"; reg = <0x1f0000 0x11000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1f0000 0x11000>; prcm_clocks: clocks { #address-cells = <1>; @@ -325,7 +329,7 @@ status = "disabled"; }; - mailbox: mailbox@480C8000 { + mailbox: mailbox@480c8000 { compatible = "ti,omap4-mailbox"; reg = <0x480C8000 0x200>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -346,6 +350,8 @@ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,timer-alwon; ti,hwmods = "timer1"; + clocks = <&timer1_fck>; + clock-names = "fck"; }; timer2: timer@48040000 { @@ -353,6 +359,8 @@ reg = <0x48040000 0x400>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer2"; + clocks = <&timer2_fck>; + clock-names = "fck"; }; timer3: timer@48042000 { @@ -927,7 +935,8 @@ reg = <0x48038000 0x2000>, <0x46000000 0x400000>; reg-names = "mpu", "dat"; - interrupts = <80>, <81>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 8 2>, @@ -935,13 +944,14 @@ dma-names = "tx", "rx"; }; - mcasp1: mcasp@4803C000 { + mcasp1: mcasp@4803c000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp1"; reg = <0x4803C000 0x2000>, <0x46400000 0x400000>; reg-names = "mpu", "dat"; - interrupts = <82>, <83>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 10 2>, @@ -991,7 +1001,7 @@ reg = <0x483a8000 0x8000>; syscon-phy-power = <&scm_conf 0x620>; clocks = <&usb_phy0_always_on_clk32k>, - <&usb_otg_ss0_refclk960m>; + <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; @@ -1010,7 +1020,7 @@ reg = <0x483e8000 0x8000>; syscon-phy-power = <&scm_conf 0x628>; clocks = <&usb_phy1_always_on_clk32k>, - <&usb_otg_ss1_refclk960m>; + <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; @@ -1173,4 +1183,4 @@ }; }; -/include/ "am43xx-clocks.dtsi" +#include "am43xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 9e92d480576b..3b9a94c274a7 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -301,8 +301,8 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - dmas = <&edma 16 - &edma 17>; + dmas = <&edma 16 0 + &edma 17 0>; dma-names = "tx0", "rx0"; flash: w25q64cvzpig@0 { diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index afb8eb0a0a16..c3b1a3fb5a2e 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -55,7 +55,7 @@ enable-active-high; }; - backlight { + lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; @@ -86,6 +86,8 @@ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; label = "lcd"; + backlight = <&lcd_bl>; + panel-timing { clock-frequency = <33000000>; hactive = <800>; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 5e364473067f..20132477a871 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -519,3 +519,17 @@ &cpu { cpu0-supply = <&tps>; }; + +&cpu0_opp_table { + /* + * Supply voltage supervisor on board will not allow opp50 so + * disable it and set opp100 as suspend OPP. + */ + opp50@300000000 { + status = "disabled"; + }; + + opp100@600000000 { + opp-suspend; + }; +}; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 2c6bf0684f50..3fa3b226995d 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -35,7 +35,7 @@ clock-frequency = <32768>; }; - backlight { + lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; @@ -132,6 +132,8 @@ pinctrl-names = "default"; pinctrl-0 = <&lcd_pins>; + backlight = <&lcd_bl>; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; panel-timing { diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 081fa68b6f98..00c3d1de384f 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -48,6 +48,8 @@ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; label = "lcd"; + backlight = <&lcd_bl>; + panel-timing { clock-frequency = <33000000>; hactive = <800>; @@ -75,6 +77,9 @@ compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&matrix_keypad_default>; + pinctrl-1 = <&matrix_keypad_sleep>; row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ @@ -104,7 +109,7 @@ 0x03030069>; /* LEFT */ }; - backlight { + lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; @@ -145,6 +150,43 @@ }; &am43xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&unused_pins>; + + unused_pins: unused_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ @@ -198,7 +240,7 @@ >; }; - nand_flash_x8: nand_flash_x8 { + nand_flash_x8_default: nand_flash_x8_default { pinctrl-single,pins = < AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ @@ -219,12 +261,39 @@ >; }; - ecap0_pins: backlight_pins { + nand_flash_x8_sleep: nand_flash_x8_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + ecap0_pins_default: backlight_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; + ecap0_pins_sleep: backlight_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ @@ -232,7 +301,7 @@ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins_default: pinmux_spi0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ @@ -241,7 +310,16 @@ >; }; - spi1_pins: pinmux_spi1_pins { + spi0_pins_sleep: pinmux_spi0_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + spi1_pins_default: pinmux_spi1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ @@ -250,13 +328,54 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + spi1_pins_sleep: pinmux_spi1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins_default: pinmux_mmc1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - qspi1_default: qspi1_default { + mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) + >; + }; + + matrix_keypad_default: matrix_keypad_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ + AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ + AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ + AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ + AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ + AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ + AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ + AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ + >; + }; + + matrix_keypad_sleep: matrix_keypad_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + qspi1_pins_default: qspi1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) @@ -267,12 +386,29 @@ >; }; - pixcir_ts_pins: pixcir_ts_pins { + qspi1_pins_sleep: qspi1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + pixcir_ts_pins_default: pixcir_ts_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; + pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; + hdq_pins: pinmux_hdq_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ @@ -355,6 +491,48 @@ >; }; + uart0_pins_default: uart0_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart0_pins_sleep: uart0_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) + AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) + >; + }; + + usb2_phy1_default: usb2_phy1_default { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + usb2_phy1_sleep: usb2_phy1_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb2_phy2_default: usb2_phy2_default { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + usb2_phy2_sleep: usb2_phy2_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ @@ -378,8 +556,9 @@ status = "okay"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; @@ -478,8 +657,10 @@ pixcir_ts@5c { compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default"; - pinctrl-0 = <&pixcir_ts_pins>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pixcir_ts_pins_default>; + pinctrl-1 = <&pixcir_ts_pins_sleep>; + reg = <0x5c>; interrupt-parent = <&gpio1>; interrupts = <17 IRQ_TYPE_EDGE_FALLING>; @@ -550,8 +731,9 @@ &gpmc { status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&nand_flash_x8_default>; + pinctrl-1 = <&nand_flash_x8_sleep>; ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ nand@0,0 { compatible = "ti,omap2-nand"; @@ -647,24 +829,30 @@ &ecap0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ecap0_pins_default>; + pinctrl-1 = <&ecap0_pins_sleep>; }; &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi0_pins_default>; + pinctrl-1 = <&spi0_pins_sleep>; }; &spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_default>; + pinctrl-1 = <&spi1_pins_sleep>; }; &usb2_phy1 { status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb2_phy1_default>; + pinctrl-1 = <&usb2_phy1_sleep>; }; &usb1 { @@ -674,6 +862,9 @@ &usb2_phy2 { status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb2_phy2_default>; + pinctrl-1 = <&usb2_phy2_sleep>; }; &usb2 { @@ -683,8 +874,9 @@ &qspi { status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_default>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi1_pins_default>; + pinctrl-1 = <&qspi1_pins_sleep>; spi-max-frequency = <48000000>; m25p80@0 { @@ -770,6 +962,13 @@ }; }; +&uart0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_pins_default>; + pinctrl-1 = <&uart0_pins_sleep>; +}; + &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; @@ -788,7 +987,11 @@ rx-num-evt = <32>; }; -&synctimer_32kclk { +&mux_synctimer32k_ck { assigned-clocks = <&mux_synctimer32k_ck>; assigned-clock-parents = <&clkdiv32k_ick>; }; + +&cpu { + cpu0-supply = <&dcdc2>; +}; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 430be5829f8f..a7037a4b4fd4 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -524,54 +524,6 @@ reg = <0x4240>; }; - gpio0_dbclk: gpio0_dbclk@2b68 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&gpio0_dbclk_mux_ck>; - ti,bit-shift = <8>; - reg = <0x2b68>; - }; - - gpio1_dbclk: gpio1_dbclk@8c78 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c78>; - }; - - gpio2_dbclk: gpio2_dbclk@8c80 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c80>; - }; - - gpio3_dbclk: gpio3_dbclk@8c88 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c88>; - }; - - gpio4_dbclk: gpio4_dbclk@8c90 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c90>; - }; - - gpio5_dbclk: gpio5_dbclk@8c98 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c98>; - }; - mmc_clk: mmc_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -629,14 +581,6 @@ reg = <0x4230>; }; - synctimer_32kclk: synctimer_32kclk@2a30 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&mux_synctimer32k_ck>; - ti,bit-shift = <8>; - reg = <0x2a30>; - }; - timer8_fck: timer8_fck@421c { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -763,110 +707,76 @@ ti,bit-shift = <8>; reg = <0x2a48>; }; +}; - usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x8a60>; - }; - - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x8a68>; - }; - - clkout1_osc_div_ck: clkout1_osc_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <20>; - ti,max-div = <4>; - reg = <0x4100>; - }; - - clkout1_src2_mux_ck: clkout1_src2_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, - <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, - <&dpll_mpu_m2_ck>; - reg = <0x4100>; - }; - - clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_mux_ck>; - ti,bit-shift = <4>; - ti,max-div = <8>; - reg = <0x4100>; - }; - - clkout1_src2_post_div_ck: clkout1_src2_post_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_pre_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - ti,index-power-of-two; - reg = <0x4100>; - }; - - clkout1_mux_ck: clkout1_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, - <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; - ti,bit-shift = <16>; - reg = <0x4100>; - }; - - clkout1_ck: clkout1_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout1_mux_ck>; - ti,bit-shift = <23>; - reg = <0x4100>; - }; - - clkout2_src_mux_ck: clkout2_src_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, - <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, - <&dpll_mpu_m2_ck>, <&dpll_extdev_ck>; - reg = <0x4108>; - }; - - clkout2_pre_div_ck: clkout2_pre_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_src_mux_ck>; - ti,bit-shift = <4>; - ti,max-div = <8>; - reg = <0x4108>; - }; - - clkout2_post_div_ck: clkout2_post_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_pre_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - ti,index-power-of-two; - reg = <0x4108>; - }; - - clkout2_ck: clkout2_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout2_post_div_ck>; - ti,bit-shift = <16>; - reg = <0x4108>; +&prcm { + l4_wkup_cm: l4_wkup_cm@2800 { + compatible = "ti,omap4-cm"; + reg = <0x2800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2800 0x400>; + + l4_wkup_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x34c>; + #clock-cells = <2>; + }; + }; + + mpu_cm: mpu_cm@8300 { + compatible = "ti,omap4-cm"; + reg = <0x8300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8300 0x100>; + + mpu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + gfx_l3_cm: gfx_l3_cm@8400 { + compatible = "ti,omap4-cm"; + reg = <0x8400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8400 0x100>; + + gfx_l3_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l4_rtc_cm: l4_rtc_cm@8500 { + compatible = "ti,omap4-cm"; + reg = <0x8500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8500 0x100>; + + l4_rtc_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l4_per_cm: l4_per_cm@8800 { + compatible = "ti,omap4-cm"; + reg = <0x8800 0xc00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8800 0xc00>; + + l4_per_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xb04>; + #clock-cells = <2>; + }; }; }; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index debf9464403e..6d3c83743156 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -117,3 +117,7 @@ pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; }; + +&cpu0 { + vdd-supply = <&smps12_reg>; +}; diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi new file mode 100644 index 000000000000..c6d858b31011 --- /dev/null +++ b/arch/arm/boot/dts/am572x-idk-common.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "am57xx-idk-common.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + status-leds { + compatible = "gpio-leds"; + cpu0-led { + label = "status0:red:cpu0"; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + usr0-led { + label = "status0:green:usr"; + gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat-led { + label = "status0:blue:heartbeat"; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + cpu1-led { + label = "status1:red:cpu1"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu1"; + }; + + usr1-led { + label = "status1:green:usr"; + gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + mmc0-led { + label = "status1:blue:mmc0"; + gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&extcon_usb2 { + id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; +}; + +&sn65hvs882 { + load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +&pcie1_rc { + status = "okay"; + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index a578fe97ba3b..9ab0af5017df 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -9,8 +9,7 @@ /dts-v1/; #include "dra74x.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> +#include "am572x-idk-common.dtsi" #include "am57xx-idk-common.dtsi" #include "dra74x-mmc-iodelay.dtsi" @@ -18,54 +17,6 @@ model = "TI AM5728 IDK"; compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - status-leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - cpu1-led { - label = "status1:red:cpu1"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu1"; - }; - - usr1-led { - label = "status1:green:usr"; - gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; }; &mmc1 { @@ -86,44 +37,6 @@ pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&extcon_usb2 { - id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; -}; - -&sn65hvs882 { - load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&pcie1_ep { - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; +&cpu0 { + vdd-supply = <&smps12_reg>; }; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts new file mode 100644 index 000000000000..41e12a382d2f --- /dev/null +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + + +/dts-v1/; + +#include "dra76x.dtsi" +#include "am572x-idk-common.dtsi" + +/ { + model = "TI AM5748 IDK"; + compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7"; +}; + +&qspi { + spi-max-frequency = <96000000>; + m25p80@0 { + spi-max-frequency = <96000000>; + }; +}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 49aeecd312b4..ab60035bc50c 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -388,7 +388,7 @@ }; &cpu0 { - cpu0-supply = <&smps12_reg>; + vdd-supply = <&smps12_reg>; voltage-tolerance = <1>; }; @@ -554,7 +554,7 @@ &mcasp3 { #sound-dai-cells = <0>; - assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&sys_clkin2>; status = "okay"; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 26ade8c0a960..b67a75179784 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -43,6 +43,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usart0: serial@fffb0000 { pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>; linux,rs485-enabled-at-boot-time; diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi index 7b8d90b7aeea..29b636fce23f 100644 --- a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi @@ -150,11 +150,6 @@ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; }; -&charlcd { - interrupt-parent = <&intc>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; -}; - &serial0 { interrupt-parent = <&intc>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index 4978011df5bd..95040810c094 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -316,32 +316,32 @@ * change the default environment, unless you know * what you are doing. */ - partition@00000000 { /* u-boot */ + partition@0 { /* u-boot */ label = "RedBoot"; reg = <0x00000000 0x000c0000>; /* 768KB */ }; - partition@000c0000 { /* uImage */ + partition@c0000 { /* uImage */ label = "zImage"; reg = <0x000c0000 0x002d0000>; /* 2880KB */ }; - partition@00390000 { /* uInitramfs */ + partition@390000 { /* uInitramfs */ label = "rd.gz"; reg = <0x00390000 0x00440000>; /* 4250KB */ }; - partition@007d0000 { /* MAC address and serial number */ + partition@7d0000 { /* MAC address and serial number */ label = "vendor"; reg = <0x007d0000 0x00010000>; /* 64KB */ }; - partition@007e0000 { + partition@7e0000 { label = "RedBoot config"; reg = <0x007e0000 0x00010000>; /* 64KB */ }; - partition@007f0000 { + partition@7f0000 { label = "FIS directory"; reg = <0x007f0000 0x00010000>; /* 64KB */ }; diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 25d2d720dc0e..678aa023335d 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -236,6 +236,7 @@ usb3_phy: usb3_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_xhci0_vbus>; + #phy-cells = <0>; }; reg_xhci0_vbus: xhci0-vbus { diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index e1f355ffc8f7..434dc9aaa5e4 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -66,6 +66,7 @@ usb3_1_phy: usb3_1-phy { compatible = "usb-nop-xceiv"; vcc-supply = <&usb3_1_vbus>; + #phy-cells = <0>; }; usb3_1_vbus: usb3_1-vbus { diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts index 31510eb56f10..0a3552ebda3b 100644 --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts +++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts @@ -191,11 +191,13 @@ usb3_0_phy: usb3_0_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb3_0_vbus>; + #phy-cells = <0>; }; usb3_1_phy: usb3_1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb3_1_vbus>; + #phy-cells = <0>; }; reg_usb3_0_vbus: usb3-vbus0 { @@ -267,35 +269,35 @@ * enumerated. The MAC address and the serial number are listed * in the "vendor" partition. */ - partition@00000000 { + partition@0 { label = "RedBoot"; reg = <0x00000000 0x000f0000>; read-only; }; - partition@000c0000 { + partition@c0000 { label = "zImage"; reg = <0x000f0000 0x002d0000>; }; - partition@00390000 { + partition@390000 { label = "rd.gz"; reg = <0x003c0000 0x00410000>; }; - partition@007d0000 { + partition@7d0000 { label = "vendor"; reg = <0x007d0000 0x00010000>; read-only; }; - partition@007e0000 { + partition@7e0000 { label = "RedBoot config"; reg = <0x007e0000 0x00010000>; read-only; }; - partition@007f0000 { + partition@7f0000 { label = "FIS directory"; reg = <0x007f0000 0x00010000>; read-only; diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index f503955dbd3b..51b4ee6df130 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -276,11 +276,13 @@ usb2_1_phy: usb2_1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb2_1_vbus>; + #phy-cells = <0>; }; usb3_phy: usb3_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_usb3_vbus>; + #phy-cells = <0>; }; reg_usb3_vbus: usb3-vbus { diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 00ff549d4e39..a6cc568f74f7 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -279,6 +279,11 @@ marvell,function = "dev"; }; + nand_rb: nand-rb { + marvell,pins = "mpp41"; + marvell,function = "nand"; + }; + uart0_pins: uart-pins-0 { marvell,pins = "mpp0", "mpp1"; marvell,function = "ua0"; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index d8e05bab0cee..d7228a5461c8 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -332,32 +332,32 @@ * change the default environment, unless you know * what you are doing. */ - partition@00000000 { /* u-boot */ + partition@0 { /* u-boot */ label = "RedBoot"; reg = <0x00000000 0x000d0000>; /* 832KB */ }; - partition@000c0000 { /* uImage */ + partition@c0000 { /* uImage */ label = "zImage"; reg = <0x000d0000 0x002d0000>; /* 2880KB */ }; - partition@003a0000 { /* uInitramfs */ + partition@3a0000 { /* uInitramfs */ label = "rd.gz"; reg = <0x003a0000 0x00430000>; /* 4250KB */ }; - partition@007d0000 { /* MAC address and serial number */ + partition@7d0000 { /* MAC address and serial number */ label = "vendor"; reg = <0x007d0000 0x00010000>; /* 64KB */ }; - partition@007e0000 { + partition@7e0000 { label = "RedBoot config"; reg = <0x007e0000 0x00010000>; /* 64KB */ }; - partition@007f0000 { + partition@7f0000 { label = "FIS directory"; reg = <0x007f0000 0x00010000>; /* 64KB */ }; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 767cbe8d8557..2ed11773048d 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -151,7 +151,6 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; - interrupt-parent = <&intc>; }; pcie: pcie@f8050000 { @@ -185,7 +184,6 @@ compatible = "simple-bus"; #address-cells = <0x1>; #size-cells = <0x1>; - interrupt-parent = <&intc>; ranges; dma-ranges = <0x80000000 0x00000000 0x40000000>; dma-coherent; @@ -195,7 +193,6 @@ clocks = <ð_phy_ref_clk>, <&clkctrl ARTPEC6_CLK_ETH_ACLK>; compatible = "snps,dwc-qos-ethernet-4.10"; - interrupt-parent = <&intc>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf8010000 0x4000>; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index f53e89d63477..91a36c1f029b 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /dts-v1/; #include "aspeed-g5.dtsi" @@ -16,7 +16,7 @@ bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; }; @@ -60,3 +60,22 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; }; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c7 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index e1b523bd5b8b..4379d09a261f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /dts-v1/; #include "aspeed-g4.dtsi" @@ -7,16 +7,12 @@ model = "Palmetto BMC"; compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; - aliases { - serial4 = &uart5; - }; - chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { + memory@40000000 { reg = <0x40000000 0x20000000>; }; @@ -38,6 +34,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; +#include "openbmc-flash-layout.dtsi" }; }; @@ -62,3 +59,55 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; }; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; + + rtc@68 { + compatible = "dallas,ds3231"; + reg = <0x68>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + tmp423@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 6dd77cba191c..623b6ab42021 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -1,23 +1,19 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /dts-v1/; - #include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> / { model = "Romulus BMC"; compatible = "ibm,romulus-bmc", "aspeed,ast2500"; - aliases { - serial4 = &uart5; - }; - chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { - reg = <0x80000000 0x40000000>; + memory@80000000 { + reg = <0x80000000 0x20000000>; }; reserved-memory { @@ -29,6 +25,49 @@ no-map; reg = <0xbf000000 0x01000000>; /* 16M */ }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + fault { + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + }; + + power { + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(J, 2)>; + }; }; }; @@ -38,6 +77,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; +#include "openbmc-flash-layout.dtsi" }; }; @@ -53,6 +93,12 @@ }; }; +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + &uart1 { /* Rear RS-232 connector */ status = "okay"; @@ -80,3 +126,134 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; }; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + /* PCIe slot 1 (x8) */ + status = "okay"; +}; + +&i2c7 { + /* PCIe slot 2 (x16) */ + status = "okay"; +}; + +&i2c8 { + /* PCIe slot 3 (x16) */ + status = "okay"; +}; + +&i2c9 { + /* PCIe slot 4 (x16) */ + status = "okay"; +}; + +&i2c10 { + /* PCIe slot 5 (x8) */ + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&i2c12 { + status = "okay"; + + max31785@52 { + compatible = "maxim,max31785"; + reg = <0x52>; + }; +}; + +&gpio { + nic_func_mode0 { + gpio-hog; + gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "nic_func_mode0"; + }; + nic_func_mode1 { + gpio-hog; + gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "nic_func_mode1"; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@5 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@6 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts new file mode 100644 index 000000000000..5f9049d2c4c3 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> + +/ { + model = "Witherspoon BMC"; + compatible = "ibm,witherspoon-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 3 GPIO_ACTIVE_LOW>; + }; + + front-fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + }; + + front-power { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 14 GPIO_ACTIVE_LOW>; + }; + + front-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 15 GPIO_ACTIVE_LOW>; + }; + + rear-fault { + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; + }; + + rear-id { + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; + }; + + rear-power { + gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; + }; + + power-button { + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + + iio-hwmon-bmp280 { + compatible = "iio-hwmon"; + io-channels = <&bmp 1>; + }; + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; + + flash@1 { + status = "okay"; + label = "alt"; + m25p,fast-read; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&i2c2 { + status = "okay"; + + /* MUX -> + * Samtec 1 + * Samtec 2 + */ +}; + +&i2c3 { + status = "okay"; + + bmp: bmp280@77 { + compatible = "bosch,bmp280"; + reg = <0x77>; + #io-channel-cells = <1>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + + +&i2c5 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c9 { + status = "okay"; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c10 { + /* MUX + * -> PCIe Slot 3 + * -> PCIe Slot 4 + */ + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts new file mode 100644 index 000000000000..c881484a85cf --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Zaius BMC"; + compatible = "ingrasys,zaius-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + }; + + onewire0 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + }; + + onewire1 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + }; + + onewire2 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + }; + + onewire3 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(F, 7)>; + }; + }; + + leds { + compatible = "gpio-leds"; + + sys_boot_status { + label = "System boot status"; + gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>; + }; + + attention { + label = "Attention"; + gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>; + }; + + plt_fault { + label = "Platform fault"; + gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>; + }; + + hdd_fault { + label = "Onboard drive fault"; + gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + + trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 13>, <&adc 14>, <&adc 15>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2cs0_default + &pinctrl_spi2cs1_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default>; + + flash@0 { + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; + + /* Power sequencer UCD90160 PMBUS @64h + * FRU AT24C64D @50h + * RTC PCF8523 @68h + * Clock buffer 9DBL04 @6dh + */ +}; + +&i2c1 { + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* MUX1 PCA9546A @71h + * PCIe 0 + * PCIe 1 + * PCIe 2 + * TPM header + */ +}; + +&i2c2 { + status = "disabled"; + + /* OCP Mezz Connector A (OOB SMBUS) */ +}; + +&i2c3 { + status = "disabled"; + + /* OCP Mezz Connector A (PCIe slot SMBUS) */ +}; + +&i2c4 { + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* MUX1 PCA9546A @71h + * PCIe 3 + * PCIe 4 + */ +}; + + +&i2c5 { + status = "disabled"; + + /* CPU0 PRM 0.7V */ + /* CPU0 PRM 1.2V CH03 */ + /* CPU0 PRM 0.8V */ + /* CPU0 PRM 1.2V CH47 */ +}; + +&i2c6 { + status = "disabled"; + + /* CPU1 PRM 0.7V */ + /* CPU1 PRM 1.2V CH03 */ + /* CPU1 PRM 0.8V */ + /* CPU1 PRM 1.2V CH47 */ +}; + +&i2c7 { + status = "okay"; + + pca9541a@70 { + compatible = "nxp,pca9541"; + reg = <0x70>; + + i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + hotswap@54 { + compatible = "ti,lm5066i"; + reg = <0x54>; + }; + }; + }; + + /* Master selector PCA9541A @70h (other master: CPU0) + * LM5066I PMBUS @10h + */ + + /* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */ + power-brick@61 { + compatible = "delta,dps800"; + reg = <0x61>; + }; + + /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ + /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ + /* CPU0 VR ISL68137 0.8V PMBUS @60h */ + /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */ + /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ +}; + +&i2c8 { + status = "okay"; + + /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */ + /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */ + /* CPU1 VR ISL68137 0.8V PMBUS @61h */ + /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ + /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */ +}; + + +&i2c9 { + status = "disabled"; + + /* Fan board */ +}; + +&i2c10 { + status = "disabled"; +}; + +&i2c11 { + status = "disabled"; + + /* GPU sideband */ +}; + +&i2c12 { + status = "disabled"; +}; + +&i2c13 { + status = "disabled"; + + /* MUX PI3USB102 + * CPU0 debug + * CPU1 debug + */ +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; + + pinctrl_gpioh_unbiased: gpioi_unbiased { + pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7"; + bias-disable; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioh_unbiased>; + + line_iso_u146_en { + gpio-hog; + gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "iso_u164_en"; + }; + + ncsi_mux_en_n { + gpio-hog; + gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "ncsi_mux_en_n"; + }; + + line_bmc_i2c2_sw_rst_n { + gpio-hog; + gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc_i2c2_sw_rst_n"; + }; + + line_bmc_i2c5_sw_rst_n { + gpio-hog; + gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc_i2c5_sw_rst_n"; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts new file mode 100644 index 000000000000..76aa6ea1f988 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "aspeed-g4.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Quanta Q71L BMC"; + compatible = "quanta,q71l-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@40000000 { + reg = <0x40000000 0x8000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@47800000 { + no-map; + reg = <0x47800000 0x00800000>; /* 8MB */ + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + }; + + power { + gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 11>; + }; + + i2c1mux: i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */ + i2c-parent = <&i2c1>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default + &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + /* temp2 inlet */ + tmp75@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + + /* temp3 */ + tmp75@4e { + compatible = "ti,tmp75"; + reg = <0x4e>; + }; + + /* temp1 */ + tmp75@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; + + /* Baseboard FRU */ + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; + + /* FP FRU */ + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; +}; + +&i2c2 { + status = "okay"; + + /* 0: PCIe Slot 2, + * Slot 3, + * Slot 6, + * Slot 7 + */ + i2c-switch@74 { + compatible = "nxp,pca9546"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; /* may use mux@77 next. */ + + i2c_pcie2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_pcie3: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_pcie6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_pcie7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + /* 0: PCIe Slot 1, + * Slot 4, + * Slot 5, + * Slot 8, + * Slot 9, + * Slot 10, + * SSD 1, + * SSD 2 + */ + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; /* may use mux@74 next. */ + + i2c_pcie1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_pcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_pcie5: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_pcie8: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_pcie9: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_pcie10: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_ssd1: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c_ssd2: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; + + /* BIOS FRU */ + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + /* 0: PSU4 + * PSU1 + * PSU3 + * PSU2 + */ + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_psu4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_psu1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_psu3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_psu2: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + /* PDB FRU */ + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; +}; + +&i2c8 { + status = "okay"; + + /* BMC FRU */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&vuart { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&i2c1mux { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Memory Riser 1 FRU */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* Memory Riser 2 FRU */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* Memory Riser 3 FRU */ + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Memory Riser 4 FRU */ + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Memory Riser 5 FRU */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* Memory Riser 6 FRU */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* Memory Riser 7 FRU */ + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Memory Riser 8 FRU */ + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index fcc5efbd0879..b0d8431a3700 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -1,5 +1,5 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "skeleton.dtsi" +// SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/clock/aspeed-clock.h> / { model = "Aspeed BMC"; @@ -8,6 +8,29 @@ #size-cells = <1>; interrupt-parent = <&vic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -31,6 +54,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2400-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; interrupts = <19>; flash@0 { @@ -46,6 +70,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2400-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; flash@0 { reg = < 0 >; @@ -66,6 +91,7 @@ compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; interrupts = <2>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; status = "disabled"; }; @@ -73,6 +99,7 @@ compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; reg = <0x1e680000 0x180>; interrupts = <3>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; status = "disabled"; }; @@ -83,900 +110,1170 @@ ranges; syscon: syscon@1e6e2000 { - compatible = "aspeed,g4-scu", "syscon", "simple-mfd"; + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; #address-cells = <1>; #size-cells = <0>; - - clk_clkin: clk_clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; - - clk_hpll: clk_hpll@70 { - #clock-cells = <0>; - compatible = "aspeed,g4-hpll-clock", "fixed-clock"; - reg = <0x70>; - clocks = <&clk_clkin>; - clock-frequency = <384000000>; - }; - - clk_ahb: clk_ahb@70 { - #clock-cells = <0>; - compatible = "aspeed,g4-ahb-clock", "fixed-clock"; - reg = <0x70>; - clocks = <&clk_hpll>; - clock-frequency = <192000000>; - }; - - clk_apb: clk_apb@08 { - #clock-cells = <0>; - compatible = "aspeed,g4-apb-clock", "fixed-clock"; - reg = <0x08>; - clocks = <&clk_hpll>; - clock-frequency = <48000000>; - }; - - clk_uart: clk_uart@2c{ - #clock-cells = <0>; - compatible = "aspeed,g4-uart-clock", "fixed-clock"; - reg = <0x2c>; - clock-frequency = <24000000>; - }; + #clock-cells = <1>; + #reset-cells = <1>; pinctrl: pinctrl { compatible = "aspeed,g4-pinctrl"; + }; + }; - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; + adc: adc@1e6e9000 { + compatible = "aspeed,ast2400-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; + #io-channel-cells = <1>; + status = "disabled"; + }; - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x8000>; // 32K + }; - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2400-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + clocks = <&syscon ASPEED_CLK_APB>; + interrupt-controller; + }; - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; + timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + interrupts = <16 17 18 35 36 37 38 39>; + clocks = <&syscon ASPEED_CLK_APB>; + clock-names = "PCLK"; + }; - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2400-wdt"; + reg = <0x1e785000 0x1c>; + clocks = <&syscon ASPEED_CLK_APB>; + }; - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; + wdt2: watchdog@1e785020 { + compatible = "aspeed,ast2400-wdt"; + reg = <0x1e785020 0x1c>; + clocks = <&syscon ASPEED_CLK_APB>; + }; - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2400-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_PWM>; + status = "disabled"; + }; - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; + vuart: serial@1e787000 { + compatible = "aspeed,ast2400-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; + lpc: lpc@1e789000 { + compatible = "aspeed,ast2400-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2400-lpc-bmc"; + reg = <0x0 0x80>; + }; - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>; - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>; - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2400-lpc-ctrl"; + reg = <0x0 0x80>; + status = "disabled"; }; - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2400-lpc-snoop"; + reg = <0x0 0x80>; + interrupts = <8>; + status = "disabled"; }; - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; + lhc: lhc@20 { + compatible = "aspeed,ast2400-lhc"; + reg = <0x20 0x24 0x48 0x8>; }; + }; + }; - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_extrst_default: extrst_default { - function = "EXTRST"; - groups = "EXTRST"; - }; + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_flack_default: flack_default { - function = "FLACK"; - groups = "FLACK"; - }; + i2c: i2c@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; + }; +}; - pinctrl_flbusy_default: flbusy_default { - function = "FLBUSY"; - groups = "FLBUSY"; - }; +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2400-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; - pinctrl_flwp_default: flwp_default { - function = "FLWP"; - groups = "FLWP"; - }; + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_gpid_default: gpid_default { - function = "GPID"; - groups = "GPID"; - }; + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; + pinctrl_extrst_default: extrst_default { + function = "EXTRST"; + groups = "EXTRST"; + }; - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; + pinctrl_flack_default: flack_default { + function = "FLACK"; + groups = "FLACK"; + }; - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; + pinctrl_flbusy_default: flbusy_default { + function = "FLBUSY"; + groups = "FLBUSY"; + }; - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; + pinctrl_flwp_default: flwp_default { + function = "FLWP"; + groups = "FLWP"; + }; - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; + pinctrl_gpid_default: gpid_default { + function = "GPID"; + groups = "GPID"; + }; - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; - pinctrl_ndts4_default: ndts4_default { - function = "NDTS4"; - groups = "NDTS4"; - }; + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; - pinctrl_rom16_default: rom16_default { - function = "ROM16"; - groups = "ROM16"; - }; + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; - pinctrl_rom8_default: rom8_default { - function = "ROM8"; - groups = "ROM8"; - }; + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; - pinctrl_romcs1_default: romcs1_default { - function = "ROMCS1"; - groups = "ROMCS1"; - }; + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; - pinctrl_romcs2_default: romcs2_default { - function = "ROMCS2"; - groups = "ROMCS2"; - }; + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; - pinctrl_romcs3_default: romcs3_default { - function = "ROMCS3"; - groups = "ROMCS3"; - }; + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; - pinctrl_romcs4_default: romcs4_default { - function = "ROMCS4"; - groups = "ROMCS4"; - }; + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; - pinctrl_sgpmck_default: sgpmck_default { - function = "SGPMCK"; - groups = "SGPMCK"; - }; + pinctrl_ndts4_default: ndts4_default { + function = "NDTS4"; + groups = "NDTS4"; + }; - pinctrl_sgpmi_default: sgpmi_default { - function = "SGPMI"; - groups = "SGPMI"; - }; + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; - pinctrl_sgpmld_default: sgpmld_default { - function = "SGPMLD"; - groups = "SGPMLD"; - }; + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; - pinctrl_sgpmo_default: sgpmo_default { - function = "SGPMO"; - groups = "SGPMO"; - }; + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; - pinctrl_sgpsck_default: sgpsck_default { - function = "SGPSCK"; - groups = "SGPSCK"; - }; + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; - pinctrl_sgpsi0_default: sgpsi0_default { - function = "SGPSI0"; - groups = "SGPSI0"; - }; + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; - pinctrl_sgpsi1_default: sgpsi1_default { - function = "SGPSI1"; - groups = "SGPSI1"; - }; + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; - pinctrl_sgpsld_default: sgpsld_default { - function = "SGPSLD"; - groups = "SGPSLD"; - }; + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; - pinctrl_spics1_default: spics1_default { - function = "SPICS1"; - groups = "SPICS1"; - }; + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; + pinctrl_rom16_default: rom16_default { + function = "ROM16"; + groups = "ROM16"; + }; - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; + pinctrl_rom8_default: rom8_default { + function = "ROM8"; + groups = "ROM8"; + }; - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; + pinctrl_romcs1_default: romcs1_default { + function = "ROMCS1"; + groups = "ROMCS1"; + }; - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; + pinctrl_romcs2_default: romcs2_default { + function = "ROMCS2"; + groups = "ROMCS2"; + }; - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; + pinctrl_romcs3_default: romcs3_default { + function = "ROMCS3"; + groups = "ROMCS3"; + }; - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; + pinctrl_romcs4_default: romcs4_default { + function = "ROMCS4"; + groups = "ROMCS4"; + }; - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; - pinctrl_vgabios_rom_default: vgabios_rom_default { - function = "VGABIOS_ROM"; - groups = "VGABIOS_ROM"; - }; + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; - pinctrl_vpi18_default: vpi18_default { - function = "VPI18"; - groups = "VPI18"; - }; + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; - pinctrl_vpi30_default: vpi30_default { - function = "VPI30"; - groups = "VPI30"; - }; + pinctrl_sgpmck_default: sgpmck_default { + function = "SGPMCK"; + groups = "SGPMCK"; + }; - pinctrl_vpo12_default: vpo12_default { - function = "VPO12"; - groups = "VPO12"; - }; + pinctrl_sgpmi_default: sgpmi_default { + function = "SGPMI"; + groups = "SGPMI"; + }; - pinctrl_vpo24_default: vpo24_default { - function = "VPO24"; - groups = "VPO24"; - }; + pinctrl_sgpmld_default: sgpmld_default { + function = "SGPMLD"; + groups = "SGPMLD"; + }; - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; + pinctrl_sgpmo_default: sgpmo_default { + function = "SGPMO"; + groups = "SGPMO"; + }; - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; + pinctrl_sgpsck_default: sgpsck_default { + function = "SGPSCK"; + groups = "SGPSCK"; + }; - }; - }; + pinctrl_sgpsi0_default: sgpsi0_default { + function = "SGPSI0"; + groups = "SGPSI0"; + }; - sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x8000>; // 32K - }; + pinctrl_sgpsi1_default: sgpsi1_default { + function = "SGPSI1"; + groups = "SGPSI1"; + }; - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2400-gpio"; - reg = <0x1e780000 0x1000>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; - interrupt-controller; - }; + pinctrl_sgpsld_default: sgpsld_default { + function = "SGPSLD"; + groups = "SGPSLD"; + }; - timer: timer@1e782000 { - /* This timer is a Faraday FTTMR010 derivative */ - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&clk_apb>; - clock-names = "PCLK"; - }; + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; - wdt1: wdt@1e785000 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785000 0x1c>; - interrupts = <27>; - }; + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; - wdt2: wdt@1e785020 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785020 0x1c>; - interrupts = <27>; - clocks = <&clk_apb>; - status = "disabled"; - }; + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; - adc: adc@1e6e9000 { - compatible = "aspeed,ast2400-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; + + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; + + pinctrl_spics1_default: spics1_default { + function = "SPICS1"; + groups = "SPICS1"; + }; + + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; + + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_vgabios_rom_default: vgabios_rom_default { + function = "VGABIOS_ROM"; + groups = "VGABIOS_ROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi18_default: vpi18_default { + function = "VPI18"; + groups = "VPI18"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpi30_default: vpi30_default { + function = "VPI30"; + groups = "VPI30"; + }; + + pinctrl_vpo12_default: vpo12_default { + function = "VPO12"; + groups = "VPO12"; + }; + + pinctrl_vpo24_default: vpo24_default { + function = "VPO24"; + groups = "VPO24"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index eab8f549a6fe..40de3b66c33f 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -1,5 +1,5 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "skeleton.dtsi" +// SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/clock/aspeed-clock.h> / { model = "Aspeed BMC"; @@ -8,6 +8,29 @@ #size-cells = <1>; interrupt-parent = <&vic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -31,6 +54,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; interrupts = <19>; flash@0 { @@ -56,6 +80,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; flash@0 { reg = < 0 >; @@ -75,6 +100,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; flash@0 { reg = < 0 >; @@ -100,6 +126,7 @@ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; interrupts = <2>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; status = "disabled"; }; @@ -107,6 +134,7 @@ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e680000 0x180>; interrupts = <3>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; status = "disabled"; }; @@ -117,1009 +145,1251 @@ ranges; syscon: syscon@1e6e2000 { - compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; + compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; + #reset-cells = <1>; - clk_clkin: clk_clkin@70 { - #clock-cells = <0>; - compatible = "aspeed,g5-clkin-clock", "fixed-clock"; - reg = <0x70>; - clock-frequency = <24000000>; - }; + pinctrl: pinctrl { + compatible = "aspeed,g5-pinctrl"; + aspeed,external-nodes = <&gfx &lhc>; - clk_hpll: clk_hpll@24 { - #clock-cells = <0>; - compatible = "aspeed,g5-hpll-clock", "fixed-clock"; - reg = <0x24>; - clocks = <&clk_clkin>; - clock-frequency = <792000000>; }; + }; - clk_ahb: clk_ahb@70 { - #clock-cells = <0>; - compatible = "aspeed,g5-ahb-clock", "fixed-clock"; - reg = <0x70>; - clocks = <&clk_hpll>; - clock-frequency = <198000000>; - }; + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + }; - clk_apb: clk_apb@08 { - #clock-cells = <0>; - compatible = "aspeed,g5-apb-clock", "fixed-clock"; - reg = <0x08>; - clocks = <&clk_hpll>; - clock-frequency = <24750000>; - }; + adc: adc@1e6e9000 { + compatible = "aspeed,ast2500-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + clocks = <&syscon ASPEED_CLK_APB>; + interrupt-controller; + }; + + timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + interrupts = <16 17 18 35 36 37 38 39>; + clocks = <&syscon ASPEED_CLK_APB>; + clock-names = "PCLK"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; + no-loopback-test; + status = "disabled"; + }; + + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x20>; + clocks = <&syscon ASPEED_CLK_APB>; + }; + + wdt2: watchdog@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x20>; + clocks = <&syscon ASPEED_CLK_APB>; + }; + + wdt3: watchdog@1e785040 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785040 0x20>; + clocks = <&syscon ASPEED_CLK_APB>; + status = "disabled"; + }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2500-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_PWM>; + status = "disabled"; + }; + + vuart: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; + no-loopback-test; + status = "disabled"; + }; + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; - clk_uart: clk_uart@2c { - #clock-cells = <0>; - compatible = "aspeed,uart-clock", "fixed-clock"; - reg = <0x2c>; - clock-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e789000 0x1000>; + + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2500-lpc-bmc"; + reg = <0x0 0x80>; }; - pinctrl: pinctrl { - compatible = "aspeed,g5-pinctrl"; - aspeed,external-nodes = <&gfx &lhc>; + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80 0x1e0>; - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; + reg-io-width = <4>; - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + status = "disabled"; }; - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2500-lpc-snoop"; + reg = <0x0 0x80>; + interrupts = <8>; + status = "disabled"; }; - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; + lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; }; + }; + }; - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; + i2c: i2c@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; + }; +}; - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; - pinctrl_fwspics1_default: fwspics1_default { - function = "FWSPICS1"; - groups = "FWSPICS1"; - }; + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; - pinctrl_fwspics2_default: fwspics2_default { - function = "FWSPICS2"; - groups = "FWSPICS2"; - }; + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; - pinctrl_lad0_default: lad0_default { - function = "LAD0"; - groups = "LAD0"; - }; - pinctrl_lad1_default: lad1_default { - function = "LAD1"; - groups = "LAD1"; - }; + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; - pinctrl_lad2_default: lad2_default { - function = "LAD2"; - groups = "LAD2"; - }; + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; - pinctrl_lad3_default: lad3_default { - function = "LAD3"; - groups = "LAD3"; - }; + pinctrl_fwspics1_default: fwspics1_default { + function = "FWSPICS1"; + groups = "FWSPICS1"; + }; - pinctrl_lclk_default: lclk_default { - function = "LCLK"; - groups = "LCLK"; - }; + pinctrl_fwspics2_default: fwspics2_default { + function = "FWSPICS2"; + groups = "FWSPICS2"; + }; - pinctrl_lframe_default: lframe_default { - function = "LFRAME"; - groups = "LFRAME"; - }; + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; - pinctrl_lpcplus_default: lpcplus_default { - function = "LPCPLUS"; - groups = "LPCPLUS"; - }; + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; + pinctrl_lad0_default: lad0_default { + function = "LAD0"; + groups = "LAD0"; + }; - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; + pinctrl_lad1_default: lad1_default { + function = "LAD1"; + groups = "LAD1"; + }; - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; + pinctrl_lad2_default: lad2_default { + function = "LAD2"; + groups = "LAD2"; + }; - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; + pinctrl_lad3_default: lad3_default { + function = "LAD3"; + groups = "LAD3"; + }; - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; + pinctrl_lclk_default: lclk_default { + function = "LCLK"; + groups = "LCLK"; + }; - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; + pinctrl_lframe_default: lframe_default { + function = "LFRAME"; + groups = "LFRAME"; + }; - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; + pinctrl_lpcplus_default: lpcplus_default { + function = "LPCPLUS"; + groups = "LPCPLUS"; + }; - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; - pinctrl_pnor_default: pnor_default { - function = "PNOR"; - groups = "PNOR"; - }; + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; - pinctrl_salt10_default: salt10_default { - function = "SALT10"; - groups = "SALT10"; - }; + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; - pinctrl_salt11_default: salt11_default { - function = "SALT11"; - groups = "SALT11"; - }; + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; - pinctrl_salt12_default: salt12_default { - function = "SALT12"; - groups = "SALT12"; - }; + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; - pinctrl_salt13_default: salt13_default { - function = "SALT13"; - groups = "SALT13"; - }; + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; - pinctrl_salt14_default: salt14_default { - function = "SALT14"; - groups = "SALT14"; - }; + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; + pinctrl_pnor_default: pnor_default { + function = "PNOR"; + groups = "PNOR"; + }; - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; - pinctrl_salt9_default: salt9_default { - function = "SALT9"; - groups = "SALT9"; - }; + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; - pinctrl_scl1_default: scl1_default { - function = "SCL1"; - groups = "SCL1"; - }; + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; - pinctrl_scl2_default: scl2_default { - function = "SCL2"; - groups = "SCL2"; - }; + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; - pinctrl_sda1_default: sda1_default { - function = "SDA1"; - groups = "SDA1"; - }; + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; - pinctrl_sda2_default: sda2_default { - function = "SDA2"; - groups = "SDA2"; - }; + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; - pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; + pinctrl_salt10_default: salt10_default { + function = "SALT10"; + groups = "SALT10"; + }; - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; + pinctrl_salt11_default: salt11_default { + function = "SALT11"; + groups = "SALT11"; + }; - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; + pinctrl_salt12_default: salt12_default { + function = "SALT12"; + groups = "SALT12"; + }; - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; + pinctrl_salt13_default: salt13_default { + function = "SALT13"; + groups = "SALT13"; + }; - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; + pinctrl_salt14_default: salt14_default { + function = "SALT14"; + groups = "SALT14"; + }; - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; - pinctrl_spi2ck_default: spi2ck_default { - function = "SPI2CK"; - groups = "SPI2CK"; - }; + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; - pinctrl_spi2cs0_default: spi2cs0_default { - function = "SPI2CS0"; - groups = "SPI2CS0"; - }; + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; - pinctrl_spi2miso_default: spi2miso_default { - function = "SPI2MISO"; - groups = "SPI2MISO"; - }; + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; - pinctrl_spi2mosi_default: spi2mosi_default { - function = "SPI2MOSI"; - groups = "SPI2MOSI"; - }; + pinctrl_salt9_default: salt9_default { + function = "SALT9"; + groups = "SALT9"; + }; - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; + pinctrl_scl1_default: scl1_default { + function = "SCL1"; + groups = "SCL1"; + }; - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; + pinctrl_scl2_default: scl2_default { + function = "SCL2"; + groups = "SCL2"; + }; - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; + pinctrl_sda1_default: sda1_default { + function = "SDA1"; + groups = "SDA1"; + }; - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; + pinctrl_sda2_default: sda2_default { + function = "SDA2"; + groups = "SDA2"; + }; - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; - pinctrl_vgabiosrom_default: vgabiosrom_default { - function = "VGABIOSROM"; - groups = "VGABIOSROM"; - }; + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; - pinctrl_vpo_default: vpo_default { - function = "VPO"; - groups = "VPO"; - }; + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; - }; + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; - }; + pinctrl_spi2ck_default: spi2ck_default { + function = "SPI2CK"; + groups = "SPI2CK"; + }; - gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - }; + pinctrl_spi2cs0_default: spi2cs0_default { + function = "SPI2CS0"; + groups = "SPI2CS0"; + }; - sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x9000>; // 36K - }; + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2500-gpio"; - reg = <0x1e780000 0x1000>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; - interrupt-controller; - }; + pinctrl_spi2miso_default: spi2miso_default { + function = "SPI2MISO"; + groups = "SPI2MISO"; + }; - timer: timer@1e782000 { - /* This timer is a Faraday FTTMR010 derivative */ - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&clk_apb>; - clock-names = "PCLK"; - }; + pinctrl_spi2mosi_default: spi2mosi_default { + function = "SPI2MOSI"; + groups = "SPI2MOSI"; + }; + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; - wdt1: wdt@1e785000 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785000 0x20>; - interrupts = <27>; - }; + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; - wdt2: wdt@1e785020 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785020 0x20>; - interrupts = <27>; - status = "disabled"; - }; + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; - wdt3: wdt@1e785040 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785040 0x20>; - status = "disabled"; - }; + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; - lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e789000 0x1000>; + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; - reg = <0x0 0x80>; - }; + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80 0x1e0>; + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; - reg-io-width = <4>; + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; - lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - }; - }; + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_vgabiosrom_default: vgabiosrom_default { + function = "VGABIOSROM"; + groups = "VGABIOSROM"; + }; - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_vpo_default: vpo_default { + function = "VPO"; + groups = "VPO"; + }; - adc: adc@1e6e9000 { - compatible = "aspeed,ast2500-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; }; }; diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index 4da011a7a698..e3e14b7e25aa 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -58,6 +58,18 @@ }; }; + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + i2c0: i2c@f8010000 { status = "okay"; }; @@ -147,12 +159,12 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts index 21c5b56c92e0..7a34c4dc05d2 100644 --- a/arch/arm/boot/dts/at91-ariettag25.dts +++ b/arch/arm/boot/dts/at91-ariettag25.dts @@ -46,6 +46,18 @@ }; }; + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + usb2: gadget@f803c000 { status = "okay"; }; @@ -59,12 +71,12 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index 89cde175154e..295a5a43fe01 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -37,6 +37,18 @@ ahb { apb { + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + mmc0: mmc@f0008000 { pinctrl-0 = < &pinctrl_board_mmc0 diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts index 27ebb0f722fd..c452654b843a 100644 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -62,7 +62,7 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ @@ -71,7 +71,7 @@ >; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 50d5e719b451..d413e2d9abdf 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -34,6 +34,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usb1: gadget@fffa4000 { atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 1f31df846d61..1003846679c1 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -31,6 +31,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + macb0: ethernet@fffc4000 { phy-mode = "mii"; pinctrl-0 = <&pinctrl_macb_rmii diff --git a/arch/arm/boot/dts/at91-kizbox2.dts b/arch/arm/boot/dts/at91-kizbox2.dts index 4372c0287c1c..30041e8f12d5 100644 --- a/arch/arm/boot/dts/at91-kizbox2.dts +++ b/arch/arm/boot/dts/at91-kizbox2.dts @@ -94,6 +94,18 @@ }; }; + tcb0: timer@f0010000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + usart0: serial@f001c000 { status = "okay"; }; @@ -133,11 +145,11 @@ }; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { status = "okay"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-kizboxmini.dts b/arch/arm/boot/dts/at91-kizboxmini.dts index 33238fcb6d0b..15b0746e44e2 100644 --- a/arch/arm/boot/dts/at91-kizboxmini.dts +++ b/arch/arm/boot/dts/at91-kizboxmini.dts @@ -34,6 +34,18 @@ ahb { apb { + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + usart0: serial@f801c000 { status = "okay"; }; @@ -59,12 +71,12 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { num-ports = <1>; status = "okay"; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi index 87e5090fb4c4..c7b964e25321 100644 --- a/arch/arm/boot/dts/at91-linea.dtsi +++ b/arch/arm/boot/dts/at91-linea.dtsi @@ -27,6 +27,18 @@ clock-frequency = <12000000>; }; +&tcb0 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm/boot/dts/at91-natte.dtsi b/arch/arm/boot/dts/at91-natte.dtsi new file mode 100644 index 000000000000..49f0a0c46cde --- /dev/null +++ b/arch/arm/boot/dts/at91-natte.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * at91-natte.dts - Device Tree include file for the Natte board + * + * Copyright (C) 2017 Axentia Technologies AB + * + * Author: Peter Rosin <peda@axentia.se> + */ + +/ { + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, + <&ioexp 1 GPIO_ACTIVE_HIGH>, + <&ioexp 2 GPIO_ACTIVE_HIGH>; + }; + + batntc-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 5>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "batntc0", "batntc1", "batntc2", "batntc3", + "batntc4", "batntc5", "batntc6", "batntc7"; + }; + + batv-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 6>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "batv0", "batv1", "batv2", "batv3", + "batv4", "batv5", "batv6", "batv7"; + }; + + iout-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 7>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "iout0", "iout1", "iout2", "iout3", + "iout4", "iout5", "iout6", "iout7"; + }; + + i2c-mux { + compatible = "i2c-mux"; + mux-locked; + i2c-parent = <&i2c0>; + mux-controls = <&mux>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + ioexp: ioexp@20 { + #gpio-cells = <2>; + compatible = "semtech,sx1502q"; + reg = <0x20>; + + gpio-controller; + ngpios = <8>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio3_cfg_pins>; + + gpio3_cfg_pins: gpio3_cfg { + pins = "gpio3"; + bias-pull-up; + }; + }; + + adc: adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@5 { + reg = <5>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <4>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts new file mode 100644 index 000000000000..3ea1d26e1c68 --- /dev/null +++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board + * + * Copyright (C) 2017 Axentia Technologies AB + * + * Author: Peter Rosin <peda@axentia.se> + */ +/dts-v1/; +#include "at91-linea.dtsi" +#include "sama5d3_lcd.dtsi" +#include "at91-natte.dtsi" + +/ { + model = "Axentia Linea-Nattis v2 Natte v2"; + compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + pinctrl@fffff200 { + nattis { + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOD 28 + AT91_PERIPH_GPIO + AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + <AT91_PIOD 5 + AT91_PERIPH_GPIO + AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + pinctrl_lcd_prlud0: lcd_prlud0 { + atmel,pins = + <AT91_PIOA 21 + AT91_PERIPH_GPIO + AT91_PINCTRL_OUTPUT_VAL(0)>; + }; + + pinctrl_lcd_hipow0: lcd_hipow0 { + atmel,pins = + <AT91_PIOA 23 + AT91_PERIPH_GPIO + AT91_PINCTRL_OUTPUT_VAL(0)>; + }; + }; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + wakeup { + label = "Wakeup"; + linux,code = <10>; + gpio-key,wakeup; + gpios = <&pioB 27 GPIO_ACTIVE_LOW>; + }; + }; + + panel_reg: panel-regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-VCC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + bl_reg: backlight-regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-VDD"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + panel_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <40>; + + power-supply = <&bl_reg>; + enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; + }; + + panel: panel { + compatible = "sharp,lq150x1lg11"; + backlight = <&panel_bl>; + power-supply = <&panel_reg>; + + port { + panel_input: endpoint { + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "nattis-tfa9879"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,widgets = "Line", "Line Out Jack"; + simple-audio-card,routing = "Line Out Jack", "LINEOUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssc0>; + }; + + simple-audio-card,codec { + sound-dai = <&>; + }; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <100000>; + + temp@18 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x18>; + smbus-timeout-disable; + }; + + eeprom@50 { + compatible = "nxp,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + amp: amplifier@6c { + compatible = "nxp,tfa9879"; + reg = <0x6c>; + #sound-dai-cells = <0>; + }; +}; + +&ssc0 { + status = "okay"; + + atmel,clk-from-rk-pin; + #sound-dai-cells = <0>; +}; + +&hlcdc { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base + &pinctrl_lcd_rgb565 + &pinctrl_lcd_prlud0 + &pinctrl_lcd_hipow0>; + + port@0 { + hlcdc_panel_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 + &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_cd>; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&usart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + atmel,use-dma-rx; +}; + +&nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; +}; + +&dbgu { + status = "okay"; + + atmel,use-dma-rx; +}; + +&usb0 { + status = "okay"; + + atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; +}; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index f46352790a41..72e9148ca096 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -31,6 +31,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usb1: gadget@fffa4000 { atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index 171243ca4f2f..70cb36f7a9d7 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -32,6 +32,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + mmc0: mmc@fffa8000 { pinctrl-0 = < &pinctrl_board_mmc0 diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 60cb084a8d92..e86e0c00eb6b 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -53,19 +53,27 @@ model = "Atmel SAMA5D27 SOM1 EK"; compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + serial0 = &uart1; /* DBGU */ + serial1 = &uart4; /* mikro BUS 1 */ + serial2 = &uart2; /* mikro BUS 2 */ + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + chosen { stdout-path = "serial0:115200n8"; }; ahb { - usb0: gadget@00300000 { + usb0: gadget@300000 { atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00400000 { + usb1: ohci@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ &pioA PIN_PA27 GPIO_ACTIVE_HIGH @@ -76,7 +84,7 @@ status = "okay"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { status = "okay"; }; @@ -111,6 +119,18 @@ status = "okay"; }; + tcb0: timer@f800c000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + uart1: serial@f8020000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; @@ -128,12 +148,14 @@ }; pwm0: pwm@f802c000 { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; + status = "disabled"; /* Conflict with leds. */ }; flx1: flexcom@f8038000 { atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; - status = "disabled"; + status = "okay"; i2c2: i2c@600 { compatible = "atmel,sama5d2-i2c"; @@ -147,7 +169,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_i2c>; atmel,fifo-size = <16>; - status = "disabled"; + status = "okay"; }; }; @@ -165,17 +187,12 @@ status = "okay"; }; - can0: can@f8054000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; - }; - uart3: serial@fc008000 { atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_default>; - status = "disabled"; + status = "disabled"; /* Conflict with isc. */ }; uart4: serial@fc00c000 { @@ -199,7 +216,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; atmel,fifo-size = <32>; - status = "disabled"; + status = "disabled"; /* Conflict with isc. */ }; spi2: spi@400 { @@ -211,7 +228,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; atmel,fifo-size = <16>; - status = "disabled"; + status = "disabled"; /* Conflict with isc. */ }; }; @@ -228,7 +245,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <32>; - status = "disabled"; + status = "disabled"; /* Conflict with spi3 and i2c3. */ }; spi3: spi@400 { @@ -240,7 +257,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; atmel,fifo-size = <16>; - status = "okay"; + status = "okay"; /* Conflict with uart6 and i2c3. */ }; i2c3: i2c@600 { @@ -255,7 +272,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <16>; - status = "disabled"; + status = "disabled"; /* Conflict with uart6 and spi3. */ }; }; @@ -268,12 +285,6 @@ pinctrl@fc038000 { - pinctrl_can0_default: can0_default { - pinmux = <PIN_PC10__CANTX0>, - <PIN_PC11__CANRX0>; - bias-disable; - }; - pinctrl_can1_default: can1_default { pinmux = <PIN_PC26__CANTX1>, <PIN_PC27__CANRX1>; @@ -350,7 +361,7 @@ <PIN_PA7__SDMMC0_DAT5>, <PIN_PA8__SDMMC0_DAT6>, <PIN_PA9__SDMMC0_DAT7>; - bias-pull-up; + bias-disable; }; ck_cd_vddsel { @@ -368,7 +379,7 @@ <PIN_PA19__SDMMC1_DAT1>, <PIN_PA20__SDMMC1_DAT2>, <PIN_PA21__SDMMC1_DAT3>; - bias-pull-up; + bias-disable; }; conf-ck_cd { @@ -512,6 +523,7 @@ label = "USER"; gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; linux,code = <0x104>; + wakeup-source; }; }; @@ -519,7 +531,7 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; + status = "okay"; /* Conflict with pwm0. */ red { label = "red"; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts new file mode 100644 index 000000000000..e603a267bdf1 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board + * + * Copyright (C) 2017 Microchip/Atmel, + * 2017 Wenyou Yang <wenyou.yang@microchip.com> + * 2017 Ludovic Desroches <ludovic.desroches@microchip.com> + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Atmel SAMA5D2 PTC EK"; + compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + ahb { + usb0: gadget@300000 { + atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@400000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PB12 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@500000 { + status = "okay"; + }; + + ebi: ebi@10000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_default>; + status = "okay"; /* conflicts with sdmmc1 and qspi0 */ + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenv@0x100000 { + label = "bootloader env"; + reg = <0x100000 0x40000>; + }; + + bootloaderenvred@0x140000 { + label = "bootloader env redundant"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + non-removable; + mmc-ddr-1_8v; + status = "okay"; + }; + + apb { + spi0: spi@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + status = "okay"; + }; + + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioA>; + interrupts = <56 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + tcb0: timer@f800c000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + uart0: serial@f801c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + uart2: serial@f8024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + status = "okay"; + }; + + flx0: flexcom@f8034000 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c2: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <0>, <0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&flx0_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + atmel,fifo-size = <16>; + status = "okay"; + }; + }; + + shdwc@f8048010 { + atmel,shdwc-debouncer = <976>; + + input@0 { + reg = <0>; + atmel,wakeup-type = "low"; + }; + }; + + watchdog@f8048040 { + status = "okay"; + }; + + spi1: spi@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + status = "okay"; + }; + + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + at24@50 { + compatible = "24c02"; + reg = <0x50>; + pagesize = <8>; + }; + }; + + pinctrl@fc038000 { + pinctrl_flx0_default: flx0_default { + pinmux = <PIN_PB28__FLEXCOM0_IO0>, + <PIN_PB29__FLEXCOM0_IO1>; + bias-disable; + }; + + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PC6__TWD1>, + <PIN_PC7__TWCK1>; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = <PIN_PA10__GPIO>; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = <PIN_PB6__GPIO>, + <PIN_PB8__GPIO>, + <PIN_PB10__GPIO>; + bias-pull-up; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + }; + + pinctrl_nand_default: nand_default { + re_we_data { + pinmux = <PIN_PA22__D0>, + <PIN_PA23__D1>, + <PIN_PA24__D2>, + <PIN_PA25__D3>, + <PIN_PA26__D4>, + <PIN_PA27__D5>, + <PIN_PA28__D6>, + <PIN_PA29__D7>, + <PIN_PA30__NWE_NANDWE>, + <PIN_PB2__NRD_NANDOE>; + bias-pull-up; + }; + + ale_cle_rdy_cs { + pinmux = <PIN_PB0__A21_NANDALE>, + <PIN_PB1__A22_NANDCLE>, + <PIN_PC8__NANDRDY>, + <PIN_PA31__NCS3>; + bias-pull-up; + }; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA6__SDMMC0_DAT4>, + <PIN_PA7__SDMMC0_DAT5>, + <PIN_PA8__SDMMC0_DAT6>, + <PIN_PA9__SDMMC0_DAT7>; + bias-pull-up; + }; + + ck_cd_vddsel { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA11__SDMMC0_VDDSEL>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + }; + }; + + pinctrl_spi0_default: spi0_default { + pinmux = <PIN_PA14__SPI0_SPCK>, + <PIN_PA15__SPI0_MOSI>, + <PIN_PA16__SPI0_MISO>, + <PIN_PA17__SPI0_NPCS0>; + bias-disable; + }; + + pinctrl_spi1_default: spi1_default { + pinmux = <PIN_PC1__SPI1_SPCK>, + <PIN_PC2__SPI1_MOSI>, + <PIN_PC3__SPI1_MISO>, + <PIN_PC4__SPI1_NPCS0>; + bias-disable; + }; + + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + + pinctrl_uart2_default: uart2_default { + pinmux = <PIN_PD23__URXD2>, + <PIN_PD24__UTXD2>; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB12__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PB11__GPIO>; + bias-disable; + }; + + }; + + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + bp1 { + label = "PB_USER"; + gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; + + red { + label = "red"; + gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "green"; + gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; + }; + + blue { + label = "blue"; + gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index cbc26001247b..e4bbb7e0f793 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -67,14 +67,14 @@ }; ahb { - usb0: gadget@00300000 { + usb0: gadget@300000 { atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00400000 { + usb1: ohci@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ &pioA PIN_PB10 GPIO_ACTIVE_HIGH @@ -85,7 +85,7 @@ status = "okay"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { status = "okay"; }; @@ -103,6 +103,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; /* conflict with qspi0 */ + vqmmc-supply = <&vdd_3v3_reg>; + vmmc-supply = <&vdd_3v3_reg>; }; apb { @@ -131,6 +133,18 @@ }; }; + tcb0: timer@f800c000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + pdmic@f8018000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pdmic_default>; @@ -160,14 +174,6 @@ compatible = "active-semi,act8945a"; reg = <0x5b>; active-semi,vsel-high; - active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; - active-semi,irq_gpios = <&pioA PIN_PB13 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; status = "okay"; regulators { @@ -220,11 +226,28 @@ regulator-always-on; }; }; + + charger { + compatible = "active-semi,act8945a-charger"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; + interrupt-parent = <&pioA>; + interrupts = <PIN_PB13 GPIO_ACTIVE_LOW>; + + active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; + active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; + active-semi,input-voltage-threshold-microvolt = <6600>; + active-semi,precondition-timeout = <40>; + active-semi,total-timeout = <3>; + status = "okay"; + }; }; }; pwm0: pwm@f802c000 { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; + status = "disabled"; /* conflict with leds */ }; flx0: flexcom@f8034000 { @@ -449,7 +472,7 @@ <PIN_PA7__SDMMC0_DAT5>, <PIN_PA8__SDMMC0_DAT6>, <PIN_PA9__SDMMC0_DAT7>; - bias-pull-up; + bias-disable; }; ck_cd_rstn_vddsel { @@ -468,7 +491,7 @@ <PIN_PA19__SDMMC1_DAT1>, <PIN_PA20__SDMMC1_DAT2>, <PIN_PA21__SDMMC1_DAT3>; - bias-pull-up; + bias-disable; }; conf-ck_cd { @@ -508,6 +531,11 @@ bias-disable; }; + pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { + pinmux = <PIN_PB5__PWMH2>, + <PIN_PB6__PWML2>; + bias-pull-up; + }; }; classd: classd@fc048000 { @@ -536,6 +564,7 @@ label = "PB_USER"; gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; linux,code = <0x104>; + wakeup-source; }; }; @@ -543,7 +572,7 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; + status = "okay"; /* conflict with pwm0 */ red { label = "red"; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 3af088d2cba7..02c1d2958d78 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -65,6 +65,18 @@ status = "okay"; }; + tcb0: timer@f0010000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + i2c0: i2c@f0014000 { pinctrl-0 = <&pinctrl_i2c0_pu>; status = "okay"; @@ -235,14 +247,14 @@ }; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 3 GPIO_ACTIVE_LOW @@ -251,7 +263,7 @@ status = "okay"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index b813fdfa2842..d3e79fbf1944 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -89,6 +89,18 @@ }; }; + tcb2: timer@fc024000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + adc0: adc@fc034000 { pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index 84be29f38dae..fe05aaa7ac87 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -21,14 +21,14 @@ }; ahb { - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -37,7 +37,7 @@ status = "okay"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index cf712444b2c2..4b7c762d5f22 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -130,6 +130,18 @@ status = "okay"; }; + tcb2: timer@fc024000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + adc0: adc@fc034000 { pinctrl-names = "default"; pinctrl-0 = < @@ -170,14 +182,14 @@ }; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_HIGH @@ -186,7 +198,7 @@ status = "okay"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index bae5248f126e..7887a7160a54 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -174,6 +174,18 @@ status = "okay"; }; + tcb2: timer@fc024000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + watchdog@fc068640 { status = "okay"; }; @@ -216,14 +228,14 @@ }; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ &pioE 11 GPIO_ACTIVE_LOW @@ -232,7 +244,7 @@ status = "okay"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts index 5f29010cdbd8..9b82cc8843e1 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/at91-tse850-3.dts @@ -221,6 +221,7 @@ jc42@18 { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x18>; + smbus-timeout-disable; }; dpot: mcp4651-104@28 { diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index e0c0b2897a49..1be9889a2b3a 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -151,6 +151,18 @@ status = "okay"; }; + tcb2: timer@fc024000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + macb1: ethernet@fc028000 { phy-mode = "rmii"; status = "okay"; @@ -180,14 +192,14 @@ }; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "disable"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -196,7 +208,7 @@ status = "disable"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { /* 4G Modem */ status = "okay"; }; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index f057e0b15a6f..ba61893a02a0 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -66,7 +66,7 @@ }; }; - sram: sram@00200000 { + sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x4000>; }; @@ -375,7 +375,9 @@ }; tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfffa0000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 @@ -385,7 +387,9 @@ }; tcb1: timer@fffa4000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfffa4000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0 @@ -938,7 +942,7 @@ status = "disabled"; }; - usb0: ohci@00300000 { + usb0: ohci@300000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index f90e1c2d3caa..81aaf8151c76 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -32,6 +32,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usb1: gadget@fffb0000 { atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; @@ -78,7 +90,7 @@ }; }; - usb0: ohci@00300000 { + usb0: ohci@300000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 6582f3cca929..655f06cd716a 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -69,7 +69,7 @@ }; }; - sram0: sram@002ff000 { + sram0: sram@2ff000 { compatible = "mmio-sram"; reg = <0x002ff000 0x2000>; }; @@ -386,7 +386,9 @@ }; tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfffa0000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 @@ -396,7 +398,9 @@ }; tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfffdc000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH 0 diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index b2578feceb08..e16c706d91ef 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -69,6 +69,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usb1: gadget@fffa4000 { atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index a05353f96151..ddfc63b8fd4e 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -60,7 +60,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x28000>; }; @@ -71,7 +71,7 @@ #size-cells = <1>; ranges; - usb0: ohci@00500000 { + usb0: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; @@ -80,7 +80,7 @@ status = "disabled"; }; - fb0: fb@0x00600000 { + fb0: fb@600000 { compatible = "atmel,at91sam9261-lcdc"; reg = <0x00600000 0x1000>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; @@ -125,7 +125,9 @@ ranges; tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfffa0000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>, diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 157e1493e6eb..a29fc0494076 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -15,6 +15,14 @@ chosen { bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; stdout-path = "serial0:115200n8"; + + clocksource { + timer = <&timer0>; + }; + + clockevent { + timer = <&timer1>; + }; }; memory { @@ -32,11 +40,11 @@ }; ahb { - usb0: ohci@00500000 { + usb0: ohci@500000 { status = "okay"; }; - fb0: fb@0x00600000 { + fb0: fb@600000 { display = <&display0>; atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; status = "okay"; @@ -125,6 +133,18 @@ }; apb { + tcb0: timer@fffa0000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer1: timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usb1: gadget@fffa4000 { atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index ed4b564f8de5..f2405671e3bd 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -62,12 +62,12 @@ }; }; - sram0: sram@00300000 { + sram0: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x14000>; }; - sram1: sram@00500000 { + sram1: sram@500000 { compatible = "mmio-sram"; reg = <0x00500000 0x4000>; }; @@ -389,7 +389,9 @@ }; tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfff7c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb_clk>, <&slow_xtal>; @@ -999,7 +1001,7 @@ }; }; - fb0: fb@0x00700000 { + fb0: fb@700000 { compatible = "atmel,at91sam9263-lcdc"; reg = <0x00700000 0x1000>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; @@ -1010,7 +1012,7 @@ status = "disabled"; }; - usb0: ohci@00a00000 { + usb0: ohci@a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 10a0925da10e..e9a7c70830a8 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -37,6 +37,18 @@ status = "okay"; }; + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usart0: serial@fff8c000 { pinctrl-0 = < &pinctrl_usart0 @@ -95,7 +107,7 @@ }; }; - fb0: fb@0x00700000 { + fb0: fb@700000 { display = <&display0>; status = "okay"; @@ -191,7 +203,7 @@ }; }; - usb0: ohci@00a00000 { + usb0: ohci@a00000 { num-ports = <2>; status = "okay"; atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index f59301618163..90705ee6008b 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -16,11 +16,11 @@ reg = <0x20000000 0x08000000>; }; - sram0: sram@002ff000 { + sram0: sram@2ff000 { status = "disabled"; }; - sram1: sram@002fc000 { + sram1: sram@2fc000 { compatible = "mmio-sram"; reg = <0x002fc000 0x8000>; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index ac9a1511e239..50561b7b7939 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -51,6 +51,18 @@ status = "okay"; }; + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usart0: serial@fffb0000 { pinctrl-0 = <&pinctrl_usart0 diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 91a71774472e..31fecc2cdaf9 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -25,7 +25,7 @@ }; i2c0: i2c@f8010000 { - ov2640: camera@0x30 { + ov2640: camera@30 { compatible = "ovti,ov2640"; reg = <0x30>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 64fa3f9a39d3..3a30eec7f508 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -74,7 +74,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; }; @@ -415,7 +415,9 @@ }; tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfff7c000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; @@ -423,7 +425,9 @@ }; tcb1: timer@fffd4000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfffd4000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; @@ -1302,7 +1306,7 @@ }; }; - fb0: fb@0x00500000 { + fb0: fb@500000 { compatible = "atmel,at91sam9g45-lcdc"; reg = <0x00500000 0x1000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; @@ -1313,7 +1317,7 @@ status = "disabled"; }; - usb0: ohci@00700000 { + usb0: ohci@700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1322,7 +1326,7 @@ status = "disabled"; }; - usb1: ehci@00800000 { + usb1: ehci@800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 94c52c555f83..25888339d8de 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -39,6 +39,18 @@ status = "okay"; }; + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usart1: serial@fff90000 { pinctrl-0 = <&pinctrl_usart1 @@ -220,7 +232,7 @@ }; }; - fb0: fb@0x00500000 { + fb0: fb@500000 { display = <&display0>; status = "okay"; @@ -290,14 +302,14 @@ }; }; - usb0: ohci@00700000 { + usb0: ohci@700000 { status = "okay"; num-ports = <2>; atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW &pioD 3 GPIO_ACTIVE_LOW>; }; - usb1: ehci@00800000 { + usb1: ehci@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 06516d02d351..4b62f4f963f6 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -64,7 +64,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; }; @@ -446,7 +446,9 @@ }; tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb_clk>, <&clk32k>; @@ -454,7 +456,9 @@ }; tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb_clk>, <&clk32k>; @@ -1018,7 +1022,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 5bea8c59b115..c43095c5cb5c 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -42,6 +42,18 @@ status = "okay"; }; + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + i2c0: i2c@f8010000 { status = "okay"; @@ -169,7 +181,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <1>; atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 7768342a6638..3cae687dccbd 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -70,7 +70,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; }; @@ -81,7 +81,7 @@ #size-cells = <1>; ranges; - fb0: fb@00500000 { + fb0: fb@500000 { compatible = "atmel,at91sam9rl-lcdc"; reg = <0x00500000 0x1000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; @@ -124,7 +124,9 @@ ranges; tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfffa0000 0x100>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, <17 IRQ_TYPE_LEVEL_HIGH 0>, diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 9047c168298a..4bde9f245e61 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -32,7 +32,7 @@ }; ahb { - fb0: fb@00500000 { + fb0: fb@500000 { display = <&display0>; status = "okay"; @@ -124,6 +124,18 @@ }; apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + mmc0: mmc@fffa4000 { pinctrl-0 = < &pinctrl_board_mmc0 diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index 494864836e83..f705a3165656 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts @@ -16,6 +16,10 @@ ahb { apb { + can1: can@f8004000 { + status = "okay"; + }; + macb0: ethernet@f802c000 { phy-mode = "rmii"; status = "okay"; @@ -25,6 +29,12 @@ phy-mode = "rmii"; status = "okay"; }; + + pwm0: pwm@f8034000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm0_1>; + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 57f307541d2e..fee4fe51a97e 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -72,7 +72,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; }; @@ -433,7 +433,9 @@ }; tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>, <&clk32k>; @@ -441,7 +443,9 @@ }; tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>, <&clk32k>; @@ -1231,7 +1235,7 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1240,7 +1244,7 @@ status = "disabled"; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index bdeaa0b64a5b..4908ee07e628 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -24,6 +24,18 @@ ahb { apb { + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + pinctrl@fffff400 { 1wire_cm { pinctrl_1wire_cm: 1wire_cm-0 { diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 9d2bbc41a7b0..4a2e13c8bf00 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -50,6 +50,8 @@ }; usart0: serial@f801c000 { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; }; @@ -134,7 +136,7 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ @@ -143,7 +145,7 @@ >; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi index 0278f63b2daf..1304452f0fae 100644 --- a/arch/arm/boot/dts/at91sam9xe.dtsi +++ b/arch/arm/boot/dts/at91sam9xe.dtsi @@ -49,11 +49,11 @@ model = "Atmel AT91SAM9XE family SoC"; compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; - sram0: sram@002ff000 { + sram0: sram@2ff000 { status = "disabled"; }; - sram1: sram@00300000 { + sram1: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x4000>; }; diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index 3c8fa26e87b7..897103e0a79b 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -107,7 +107,7 @@ }; }; - usb_power_supply: usb_power_supply { + usb_power_supply: usb-power-supply { compatible = "x-powers,axp202-usb-power-supply"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi new file mode 100644 index 000000000000..fd55b896afa1 --- /dev/null +++ b/arch/arm/boot/dts/axp81x.dtsi @@ -0,0 +1,159 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* AXP813/818 Integrated Power Management Chip */ + +&axp81x { + interrupt-controller; + #interrupt-cells = <1>; + + axp_gpio: axp-gpio { + compatible = "x-powers,axp813-gpio"; + gpio-controller; + #gpio-cells = <2>; + + gpio0_ldo: gpio0-ldo { + pins = "GPIO0"; + function = "ldo"; + }; + + gpio1_ldo: gpio1-ldo { + pins = "GPIO1"; + function = "ldo"; + }; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; + + reg_dcdc1: dcdc1 { + }; + + reg_dcdc2: dcdc2 { + }; + + reg_dcdc3: dcdc3 { + }; + + reg_dcdc4: dcdc4 { + }; + + reg_dcdc5: dcdc5 { + }; + + reg_dcdc6: dcdc6 { + }; + + reg_dcdc7: dcdc7 { + }; + + reg_aldo1: aldo1 { + }; + + reg_aldo2: aldo2 { + }; + + reg_aldo3: aldo3 { + }; + + reg_dldo1: dldo1 { + }; + + reg_dldo2: dldo2 { + }; + + reg_dldo3: dldo3 { + }; + + reg_dldo4: dldo4 { + }; + + reg_eldo1: eldo1 { + }; + + reg_eldo2: eldo2 { + }; + + reg_eldo3: eldo3 { + }; + + reg_fldo1: fldo1 { + }; + + reg_fldo2: fldo2 { + }; + + reg_fldo3: fldo3 { + }; + + reg_ldo_io0: ldo-io0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_ldo>; + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_ldo_io1: ldo-io1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_ldo>; + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_rtc_ldo: rtc-ldo { + /* RTC_LDO is a fixed, always-on regulator */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sw: sw { + }; + + reg_drivevbus: drivevbus { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 7c957ea06c66..699fdf94d139 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -96,14 +96,14 @@ #address-cells = <1>; #size-cells = <1>; - otp: otp@0301c800 { + otp: otp@301c800 { compatible = "brcm,ocotp"; reg = <0x0301c800 0x2c>; brcm,ocotp-size = <2048>; status = "disabled"; }; - pcie_phy: phy@0301d0a0 { + pcie_phy: phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; @@ -120,7 +120,7 @@ }; }; - pinctrl: pinctrl@0301d0c8 { + pinctrl: pinctrl@301d0c8 { compatible = "brcm,cygnus-pinmux"; reg = <0x0301d0c8 0x30>, <0x0301d24c 0x2c>; @@ -141,7 +141,7 @@ }; }; - mailbox: mailbox@03024024 { + mailbox: mailbox@3024024 { compatible = "brcm,iproc-mailbox"; reg = <0x03024024 0x40>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -150,7 +150,7 @@ #mbox-cells = <1>; }; - gpio_crmu: gpio@03024800 { + gpio_crmu: gpio@3024800 { compatible = "brcm,cygnus-crmu-gpio"; reg = <0x03024800 0x50>, <0x03024008 0x18>; @@ -473,6 +473,16 @@ status = "disabled"; }; + clcd: clcd@180a0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x180a0000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; + clocks = <&axi41_clk>, <&apb_clk>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + v3d: v3d@180a2000 { compatible = "brcm,cygnus-v3d"; reg = <0x180a2000 0x1000>; @@ -575,6 +585,14 @@ status = "disabled"; }; + pwm: pwm@180aa500 { + compatible = "brcm,kona-pwm"; + reg = <0x180aa500 0xc4>; + #pwm-cells = <3>; + clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>; + status = "disabled"; + }; + keypad: keypad@180ac000 { compatible = "brcm,bcm-keypad"; reg = <0x180ac000 0x14c>; diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi new file mode 100644 index 000000000000..3f9cedd8011f --- /dev/null +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -0,0 +1,368 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,hr2"; + model = "Broadcom Hurricane 2 SoC"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + mpcore@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,hr2-armpll"; + clocks = <&osc>; + reg = <0x0 0x1000>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + }; + + twd-timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&periph_clk>; + }; + + twd-watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: l2-cache@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x0011c40c>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550a"; + reg = <0x0400 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + status = "disabled"; + }; + + dma@20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + status = "disabled"; + }; + + amac0: ethernet@22000 { + compatible = "brcm,nsp-amac"; + reg = <0x22000 0x1000>, + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + nand: nand@26000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x26000 0x600>, + <0x11b408 0x600>, + <0x026f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + gpiob: gpio@30000 { + compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; + reg = <0x30000 0x50>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <4>; + interrupt-controller; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + }; + + pwm: pwm@31000 { + compatible = "brcm,iproc-pwm"; + reg = <0x31000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + rng: rng@33000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x33000 0x14>; + }; + + qspi: qspi@27200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* partitions defined in board DTS */ + }; + + ccbtimer0: timer@34000 { + compatible = "arm,sp804"; + reg = <0x34000 0x1000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + ccbtimer1: timer@35000 { + compatible = "arm,sp804"; + reg = <0x35000 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c0: i2c@38000 { + compatible = "brcm,iproc-i2c"; + reg = <0x38000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_NONE>; + clock-frequency = <100000>; + }; + + watchdog@39000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x39000 0x1000>; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c1: i2c@3b000 { + compatible = "brcm,iproc-i2c"; + reg = <0x3b000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>; + clock-frequency = <100000>; + }; + }; + + pflash: nor@20000000 { + compatible = "cfi-flash", "jedec-flash"; + reg = <0x20000000 0x04000000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + + /* partitions defined in board DTS */ + }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + + status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi-controller { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 182 IRQ_TYPE_NONE>, + <GIC_SPI 183 IRQ_TYPE_NONE>, + <GIC_SPI 184 IRQ_TYPE_NONE>, + <GIC_SPI 185 IRQ_TYPE_NONE>; + brcm,pcie-msi-inten; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + + status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi-controller { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>, + <GIC_SPI 189 IRQ_TYPE_NONE>, + <GIC_SPI 190 IRQ_TYPE_NONE>, + <GIC_SPI 191 IRQ_TYPE_NONE>; + brcm,pcie-msi-inten; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index dff66974feed..dcc55aa84583 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -75,7 +75,7 @@ #address-cells = <1>; #size-cells = <1>; - a9pll: arm_clk@00000 { + a9pll: arm_clk@0 { #clock-cells = <0>; compatible = "brcm,nsp-armpll"; clocks = <&osc>; @@ -85,7 +85,7 @@ timer@20200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x20200 0x100>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; clocks = <&periph_clk>; }; @@ -93,7 +93,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x20600 0x20>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_HIGH)>; + IRQ_TYPE_EDGE_RISING)>; clocks = <&periph_clk>; }; @@ -164,7 +164,7 @@ #address-cells = <1>; #size-cells = <1>; - gpioa: gpio@0020 { + gpioa: gpio@20 { compatible = "brcm,nsp-gpio-a"; reg = <0x0020 0x70>, <0x3f1c4 0x1c>; @@ -176,7 +176,7 @@ gpio-ranges = <&pinctrl 0 0 32>; }; - uart0: serial@0300 { + uart0: serial@300 { compatible = "ns16550a"; reg = <0x0300 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -184,7 +184,7 @@ status = "disabled"; }; - uart1: serial@0400 { + uart1: serial@400 { compatible = "ns16550a"; reg = <0x0400 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 18045c38bcf1..db7cded1b7ad 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -55,7 +55,7 @@ <0x3ff00100 0x100>; }; - smc@0x3404c000 { + smc@3404c000 { compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ }; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 6dde95f21cef..266f2611dc22 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -55,7 +55,7 @@ <0x3ff00100 0x100>; }; - smc@0x3404e000 { + smc@3404e000 { compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index f81ae0a10310..aa1fc7babfea 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -10,12 +10,12 @@ leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; pwr { label = "PWR"; - gpios = <&gpio 35 0>; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; linux,default-trigger = "default-on"; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 7a960a048204..425f6b0a5ef8 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -10,7 +10,7 @@ leds { act { - gpios = <&gpio 16 1>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 0161a8483e39..effa195e7895 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -11,12 +11,12 @@ leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; pwr { label = "PWR"; - gpios = <&gpio 35 0>; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; linux,default-trigger = "default-on"; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 4bc70efe43d6..772ec3b48231 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -11,7 +11,7 @@ leds { act { - gpios = <&gpio 16 1>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index cca4a75a5651..434483d6fc14 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -11,7 +11,7 @@ leds { act { - gpios = <&gpio 16 1>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 0e3d2a5ff208..a5c3824c8056 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -18,10 +18,10 @@ soc { ranges = <0x7e000000 0x20000000 0x02000000>; dma-ranges = <0x40000000 0x00000000 0x20000000>; + }; - arm-pmu { - compatible = "arm,arm1176-pmu"; - }; + arm-pmu { + compatible = "arm,arm1176-pmu"; }; }; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 6669355fd655..5c339adabdf0 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -15,12 +15,12 @@ leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; pwr { label = "PWR"; - gpios = <&gpio 35 0>; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; linux,default-trigger = "default-on"; }; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 61e158003509..c933e8413884 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -9,28 +9,28 @@ <0x40000000 0x40000000 0x00001000>; dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - local_intc: local_intc { + local_intc: local_intc@40000000 { compatible = "brcm,bcm2836-l1-intc"; reg = <0x40000000 0x100>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-parent = <&local_intc>; }; + }; - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&local_intc>; - interrupts = <9>; - }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&local_intc>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; }; timer { compatible = "arm,armv7-timer"; interrupt-parent = <&local_intc>; - interrupts = <0>, // PHYS_SECURE_PPI - <1>, // PHYS_NONSECURE_PPI - <3>, // VIRT_PPI - <2>; // HYP_PPI + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI + <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI + <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI + <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI always-on; }; @@ -76,7 +76,7 @@ compatible = "brcm,bcm2836-armctrl-ic"; reg = <0x7e00b200 0x200>; interrupt-parent = <&local_intc>; - interrupts = <8>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; }; &cpu_thermal { diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index eb1a28da57e3..3e4ed7c5b0b3 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -20,7 +20,7 @@ leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; }; }; @@ -30,6 +30,11 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + }; }; /* uart1 is mapped to the pin header */ diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index bc1cca5cf43c..7704bb029605 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -8,11 +8,11 @@ <0x40000000 0x40000000 0x00001000>; dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - local_intc: local_intc { + local_intc: local_intc@40000000 { compatible = "brcm,bcm2836-l1-intc"; reg = <0x40000000 0x100>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-parent = <&local_intc>; }; }; @@ -20,10 +20,10 @@ timer { compatible = "arm,armv7-timer"; interrupt-parent = <&local_intc>; - interrupts = <0>, // PHYS_SECURE_PPI - <1>, // PHYS_NONSECURE_PPI - <3>, // VIRT_PPI - <2>; // HYP_PPI + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI + <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI + <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI + <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI always-on; }; @@ -73,7 +73,7 @@ compatible = "brcm,bcm2836-armctrl-ic"; reg = <0x7e00b200 0x200>; interrupt-parent = <&local_intc>; - interrupts = <8>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; }; &cpu_thermal { diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 013431e3d7c3..9d293decf8d3 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/clock/bcm2835.h> #include <dt-bindings/clock/bcm2835-aux.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> /* firmware-provided startup stubs live here, where the secondary CPUs are * spinning. @@ -464,7 +465,7 @@ status = "disabled"; }; - aux: aux@0x7e215000 { + aux: aux@7e215000 { compatible = "brcm,bcm2835-aux"; #clock-cells = <1>; reg = <0x7e215000 0x8>; @@ -639,5 +640,6 @@ usbphy: phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index c544ab302012..ba1c19b1b3eb 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -57,7 +57,8 @@ usb { label = "bcm53xx:green:usb"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; }; status { diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts new file mode 100644 index 000000000000..ecd22a246746 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,abr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul ABR-4500 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000 + 0x88000000 0x18000000>; + }; + + leds { + compatible = "gpio-leds"; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts new file mode 100644 index 000000000000..15ffb1abc440 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,xbr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XBR-4500 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000 + 0x88000000 0x18000000>; + }; + + leds { + compatible = "gpio-leds"; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts new file mode 100644 index 000000000000..74c83b0ca54e --- /dev/null +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "luxul,xap-1440-v1", "brcm,bcm47189", "brcm,bcm53573"; + model = "Luxul XAP-1440 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + label = "bcm53xx:blue:wlan"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts new file mode 100644 index 000000000000..214df18f3a75 --- /dev/null +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -0,0 +1,87 @@ +/* + * Copyright 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573"; + model = "Luxul XAP-810 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + pcie0_leds { + compatible = "gpio-leds"; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pcie0 { + ranges = <0x00000000 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + pcie0_chipcommon: chipcommon@0 { + reg = <0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 045b9bb857f9..9a076c409f4e 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -24,7 +24,7 @@ #address-cells = <1>; #size-cells = <1>; - uart0: serial@0300 { + uart0: serial@300 { compatible = "ns16550"; reg = <0x0300 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -32,7 +32,7 @@ status = "disabled"; }; - uart1: serial@0400 { + uart1: serial@400 { compatible = "ns16550"; reg = <0x0400 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <1>; - a9pll: arm_clk@00000 { + a9pll: arm_clk@0 { #clock-cells = <0>; compatible = "brcm,nsp-armpll"; clocks = <&osc>; diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts new file mode 100644 index 000000000000..431cda514230 --- /dev/null +++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts @@ -0,0 +1,85 @@ +/* + * DTS for Unifi Switch 8 port + * + * Copyright (C) 2017 Florian Fainelli <f.fainelli@gmail.com> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm-hr2.dtsi" + +/ { + compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2"; + model = "Ubiquiti UniFi Switch 8 (BCM53342)"; + + /* Hurricane 2 designs use the second UART */ + chosen { + bootargs = "console=ttyS1,115200 earlyprintk"; + }; + + memory@0 { + reg = <0x00000000 0x08000000>, + <0x68000000 0x08000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + + flash: m25p80@0 { + compatible = "m25p80"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12500000>; + spi-cpol; + spi-cpha; + + partition@0 { + label = "u-boot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + partition@d0000 { + label = "shmoo"; + reg = <0xd0000 0x10000>; + }; + + partition@e0000 { + label = "kernel0"; + reg = <0xe0000 0xf00000>; + }; + + partition@fe0000 { + label = "kernel1"; + reg = <0xfe0000 0xf10000>; + }; + + partition@1ef0000 { + label = "cfg"; + reg = <0x1ef0000 0x100000>; + }; + + partition@1ff0000 { + label = "EEPROM"; + reg = <0x1ff0000 0x10000>; + }; + }; +}; + +&pcie0 { + /* Attaches to the internal switch */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index c698a565b8ae..16007d72c346 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -107,7 +107,7 @@ gpio-controller; #gpio-cells = <2>; - uart0: serial@0300 { + uart0: serial@300 { compatible = "ns16550a"; reg = <0x0300 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index 3bc50849d013..b8bde13de90a 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -141,10 +141,6 @@ status = "okay"; }; -&sata { - status = "okay"; -}; - &qspi { bspi-sel = <0>; flash: m25p80@0 { diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index d94d14b3c745..f0e2008f7490 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -49,7 +49,7 @@ memory { device_type = "memory"; - reg = <0x60000000 0x80000000>; + reg = <0x60000000 0x20000000>; }; gpio-restart { @@ -177,10 +177,6 @@ status = "okay"; }; -&sata { - status = "okay"; -}; - &srab { compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; status = "okay"; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 425c48971abe..d575823c5750 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -202,7 +202,7 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; - gpio0: gpio@0400 { + gpio0: gpio@400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; @@ -220,7 +220,7 @@ }; }; - gpio1: gpio@0800 { + gpio1: gpio@800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; @@ -238,7 +238,7 @@ }; }; - gpio2: gpio@0c00 { + gpio2: gpio@c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 4fe1574d08c3..501c59d97eae 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -182,7 +182,7 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; - gpio0: gpio@0400 { + gpio0: gpio@400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; @@ -200,7 +200,7 @@ }; }; - gpio1: gpio@0800 { + gpio1: gpio@800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; @@ -218,7 +218,7 @@ }; }; - gpio2: gpio@0c00 { + gpio2: gpio@c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index e548229697fc..bf3a6c9a1d34 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -234,7 +234,7 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; - gpio0: gpio@0400 { + gpio0: gpio@400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; @@ -252,7 +252,7 @@ }; }; - gpio1: gpio@0800 { + gpio1: gpio@800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; @@ -270,7 +270,7 @@ }; }; - gpio2: gpio@0c00 { + gpio2: gpio@c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index a0f0916156e6..a1f4d6d5a569 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -26,6 +26,19 @@ reg = <0xc0000000 0x08000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@c3000000 { + compatible = "shared-dma-pool"; + reg = <0xc3000000 0x1000000>; + reusable; + status = "okay"; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "DA850/OMAP-L138 LCDK"; @@ -280,12 +293,12 @@ label = "u-boot env"; reg = <0 0x020000>; }; - partition@0x020000 { + partition@20000 { /* The LCDK defaults to booting from this partition */ label = "u-boot"; reg = <0x020000 0x080000>; }; - partition@0x0a0000 { + partition@a0000 { label = "free space"; reg = <0x0a0000 0>; }; @@ -319,3 +332,8 @@ pinctrl-0 = <&vpif_capture_pins>; status = "okay"; }; + +&dsp { + memory-region = <&dsp_memory_region>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts index 413dbd5d9f64..81942ae83e1f 100644 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/da850-lego-ev3.dts @@ -178,7 +178,7 @@ */ battery { pinctrl-names = "default"; - pintctrl-0 = <&battery_pins>; + pinctrl-0 = <&battery_pins>; compatible = "lego,ev3-battery"; io-channels = <&adc 4>, <&adc 3>; io-channel-names = "voltage", "current"; @@ -392,7 +392,7 @@ batt_volt_en { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; + output-high; }; }; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index af68ef7b0caa..c66cf7895363 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -23,6 +23,18 @@ reg = <0xfffee000 0x2000>; }; }; + dsp: dsp@11800000 { + compatible = "ti,da850-dsp"; + reg = <0x11800000 0x40000>, + <0x11e00000 0x8000>, + <0x11f00000 0x8000>, + <0x01c14044 0x4>, + <0x01c14174 0x8>; + reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; + interrupt-parent = <&intc>; + interrupts = <28>; + status = "disabled"; + }; soc@1c00000 { compatible = "simple-bus"; model = "da850"; diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi index c4671af0a28d..f80525a290bb 100644 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -337,3 +337,33 @@ clock-frequency = <20000000>; }; }; + +&prcm { + default_cm: default_cm@500 { + compatible = "ti,omap4-cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + default_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x5c>; + #clock-cells = <2>; + }; + }; + + alwon_cm: alwon_cm@1400 { + compatible = "ti,omap4-cm"; + reg = <0x1400 0x300>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x300>; + + alwon_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x228>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 9708157f5daf..601c57afd4fe 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -75,6 +75,7 @@ reg = <0x47401300 0x100>; reg-names = "phy"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb0: usb@47401000 { @@ -249,6 +250,8 @@ interrupts = <67>; ti,hwmods = "timer1"; ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; }; uart1: uart@20000 { @@ -286,6 +289,8 @@ reg = <0x40000 0x2000>; interrupts = <68>; ti,hwmods = "timer2"; + clocks = <&timer2_fck>; + clock-names = "fck"; }; timer3: timer@42000 { @@ -385,6 +390,7 @@ reg = <0x1b00 0x100>; reg-names = "phy"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/dm816x-clocks.dtsi index 51865eb84a80..1efd4e23e50d 100644 --- a/arch/arm/boot/dts/dm816x-clocks.dtsi +++ b/arch/arm/boot/dts/dm816x-clocks.dtsi @@ -248,3 +248,33 @@ reg = <0x03a8>; }; }; + +&prcm { + default_cm: default_cm@500 { + compatible = "ti,omap4-cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + default_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x5c>; + #clock-cells = <2>; + }; + }; + + alwon_cm: alwon_cm@1400 { + compatible = "ti,omap4-cm"; + reg = <0x1400 0x300>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x300>; + + alwon_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x208>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 566b2a8c8b96..1edc2b48b254 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -67,8 +67,11 @@ ranges; prcm: prcm@48180000 { - compatible = "ti,dm816-prcm"; + compatible = "ti,dm816-prcm", "simple-bus"; reg = <0x48180000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48180000 0x4000>; prcm_clocks: clocks { #address-cells = <1>; @@ -331,6 +334,8 @@ interrupts = <67>; ti,hwmods = "timer1"; ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; }; timer2: timer@48040000 { @@ -338,6 +343,8 @@ reg = <0x48040000 0x2000>; interrupts = <68>; ti,hwmods = "timer2"; + clocks = <&timer2_fck>; + clock-names = "fck"; }; timer3: timer@48042000 { diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index f4a07bb7c3a2..4a0a5115b298 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -457,25 +457,25 @@ }; }; - thermal: thermal-diode@001c { + thermal: thermal-diode@1c { compatible = "marvell,dove-thermal"; reg = <0x001c 0x0c>, <0x005c 0x08>; }; - gate_clk: clock-gating-ctrl@0038 { + gate_clk: clock-gating-ctrl@38 { compatible = "marvell,dove-gating-clock"; reg = <0x0038 0x4>; clocks = <&core_clk 0>; #clock-cells = <1>; }; - divider_clk: core-clock@0064 { + divider_clk: core-clock@64 { compatible = "marvell,dove-divider-clock"; reg = <0x0064 0x8>; #clock-cells = <1>; }; - pinctrl: pin-ctrl@0200 { + pinctrl: pin-ctrl@200 { compatible = "marvell,dove-pinctrl"; reg = <0x0200 0x14>, <0x0440 0x04>; @@ -719,13 +719,13 @@ }; }; - core_clk: core-clocks@0214 { + core_clk: core-clocks@214 { compatible = "marvell,dove-core-clock"; reg = <0x0214 0x4>; #clock-cells = <1>; }; - gpio0: gpio-ctrl@0400 { + gpio0: gpio-ctrl@400 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; gpio-controller; @@ -737,7 +737,7 @@ interrupts = <12>, <13>, <14>, <60>; }; - gpio1: gpio-ctrl@0420 { + gpio1: gpio-ctrl@420 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index 155eb32ee213..fee0547f7302 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -74,19 +74,19 @@ label = "X-Loader"; reg = <0 0x80000>; }; - partition@0x80000 { + partition@80000 { label = "U-Boot"; reg = <0x80000 0x1c0000>; }; - partition@0x1c0000 { + partition@1c0000 { label = "Environment"; reg = <0x240000 0x40000>; }; - partition@0x280000 { + partition@280000 { label = "Kernel"; reg = <0x280000 0x500000>; }; - partition@0x780000 { + partition@780000 { label = "Filesystem"; reg = <0x780000 0xf880000>; }; diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 343e95f9a001..05a7b1a01bc3 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -204,7 +204,7 @@ &atl { assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_gfclk_mux>, + <&atl_clkctrl DRA7_ATL_CLKCTRL 26>, <&dpll_abe_ck>, <&dpll_abe_m2x2_ck>, <&atl_clkin2_ck>; @@ -222,7 +222,7 @@ &mcasp3 { #sound-dai-cells = <0>; - assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&atl_clkin2_ck>; status = "okay"; @@ -256,3 +256,7 @@ status = "okay"; }; }; + +&pcie1_rc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index aa426dabb6c3..a7385c338ee9 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -361,7 +361,7 @@ }; &cpu0 { - cpu0-supply = <&smps123_reg>; + vdd-supply = <&smps123_reg>; }; &omap_dwc3_2 { @@ -497,7 +497,3 @@ pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; - -&pcie1_rc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 02a136a4661a..e4a420f16800 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -7,8 +7,11 @@ * Based on "omap4.dtsi" */ +#include <dt-bindings/bus/ti-sysc.h> +#include <dt-bindings/clock/dra7.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/dra.h> +#include <dt-bindings/clock/dra7.h> #define MAX_SOURCES 400 @@ -92,6 +95,8 @@ cooling-min-level = <0>; cooling-max-level = <2>; #cooling-cells = <2>; /* min followed by max */ + + vbb-supply = <&abb_mpu>; }; }; @@ -101,16 +106,26 @@ opp_nom-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1060000 850000 1150000>; + opp-microvolt = <1060000 850000 1150000>, + <1060000 850000 1150000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; opp_od-1176000000 { opp-hz = /bits/ 64 <1176000000>; - opp-microvolt = <1160000 885000 1160000>; + opp-microvolt = <1160000 885000 1160000>, + <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; }; + + opp_high@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1210000 950000 1250000>, + <1210000 950000 1250000>; + opp-supported-hw = <0xFF 0x04>; + }; }; /* @@ -170,7 +185,7 @@ pbias_mmc_reg: pbias_mmc_omap5 { regulator-name = "pbias_mmc_omap5"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; }; }; @@ -224,8 +239,12 @@ }; cm_core_aon: cm_core_aon@5000 { - compatible = "ti,dra7-cm-core-aon"; + compatible = "ti,dra7-cm-core-aon", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x5000 0x2000>; + ranges = <0 0x5000 0x2000>; cm_core_aon_clocks: clocks { #address-cells = <1>; @@ -237,8 +256,11 @@ }; cm_core: cm_core@8000 { - compatible = "ti,dra7-cm-core"; + compatible = "ti,dra7-cm-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x8000 0x3000>; + ranges = <0 0x8000 0x3000>; cm_core_clocks: clocks { #address-cells = <1>; @@ -263,9 +285,12 @@ }; prm: prm@6000 { - compatible = "ti,dra7-prm"; + compatible = "ti,dra7-prm", "simple-bus"; reg = <0x6000 0x3000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x6000 0x3000>; prm_clocks: clocks { #address-cells = <1>; @@ -293,7 +318,6 @@ * node and enable pcie1_ep mode. */ pcie1_rc: pcie@51000000 { - compatible = "ti,dra7-pcie"; reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 232 0x4>, <0 233 0x4>; @@ -323,7 +347,6 @@ }; pcie1_ep: pcie_ep@51000000 { - compatible = "ti,dra7-pcie-ep"; reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; interrupts = <0 232 0x4>; @@ -345,8 +368,7 @@ ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>; status = "disabled"; - pcie@51800000 { - compatible = "ti,dra7-pcie"; + pcie2_rc: pcie@51800000 { reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 355 0x4>, <0 356 0x4>; @@ -457,6 +479,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; edma: edma@43300000 { @@ -875,6 +898,8 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer1"; ti,timer-alwon; + clock-names = "fck"; + clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; }; timer2: timer@48032000 { @@ -1069,6 +1094,13 @@ max-frequency = <192000000>; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "hdq1w"; + }; + mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; @@ -1350,7 +1382,7 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; - clocks = <&qspi_gfclk_div>; + clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>; clock-names = "fck"; num-cs = <4>; interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; @@ -1365,14 +1397,15 @@ ranges; reg = <0x4a090000 0x20>; ti,hwmods = "ocp2scp3"; - sata_phy: phy@4A096000 { + sata_phy: phy@4a096000 { compatible = "ti,phy-pipe3-sata"; reg = <0x4A096000 0x80>, /* phy_rx */ <0x4A096400 0x64>, /* phy_tx */ <0x4A096800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin1>, <&sata_ref_clk>; + clocks = <&sys_clkin1>, + <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; clock-names = "sysclk", "refclk"; syscon-pllreset = <&scm_conf 0x3fc>; #phy-cells = <0>; @@ -1387,9 +1420,9 @@ syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, - <&optfclk_pciephy1_32khz>, - <&optfclk_pciephy1_clk>, - <&optfclk_pciephy1_div_clk>, + <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>, + <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>, + <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>, <&optfclk_pciephy_div>, <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", @@ -1407,9 +1440,9 @@ syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, - <&optfclk_pciephy2_32khz>, - <&optfclk_pciephy2_clk>, - <&optfclk_pciephy2_div_clk>, + <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>, + <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>, + <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>, <&optfclk_pciephy_div>, <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", @@ -1426,7 +1459,7 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; phys = <&sata_phy>; phy-names = "sata-phy"; - clocks = <&sata_ref_clk>; + clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; ti,hwmods = "sata"; ports-implemented = <0x1>; }; @@ -1454,7 +1487,7 @@ reg = <0x4a084000 0x400>; syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, - <&usb_otg_ss1_refclk960m>; + <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; @@ -1466,7 +1499,7 @@ reg = <0x4a085000 0x400>; syscon-phy-power = <&scm_conf 0xe74>; clocks = <&usb_phy2_always_on_clk32k>, - <&usb_otg_ss2_refclk960m>; + <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; @@ -1481,7 +1514,7 @@ syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy3_always_on_clk32k>, <&sys_clkin1>, - <&usb_otg_ss1_refclk960m>; + <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "sysclk", "refclk"; @@ -1489,6 +1522,44 @@ }; }; + target-module@4a0dd000 { + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x4a0dd038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0dd000 0x001000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + + target-module@4a0d9000 { + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu"; + reg = <0x4a0d9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0d9000 0x001000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + omap_dwc3_1: omap_dwc3_1@48880000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1"; @@ -1513,6 +1584,7 @@ dr_mode = "otg"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; + snps,dis_metastability_quirk; }; }; @@ -1602,7 +1674,7 @@ ti,hwmods = "atl"; ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, <&atl_clkin2_ck>, <&atl_clkin3_ck>; - clocks = <&atl_gfclk_mux>; + clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; clock-names = "fck"; status = "disabled"; }; @@ -1618,8 +1690,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dma-names = "tx", "rx"; - clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, - <&mcasp1_ahclkr_mux>; + clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>, + <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; }; @@ -1635,8 +1707,9 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dma-names = "tx", "rx"; - clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, - <&mcasp2_ahclkr_mux>; + clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>, + <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>, + <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; }; @@ -1652,7 +1725,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dma-names = "tx", "rx"; - clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; + clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>, + <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1668,7 +1742,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dma-names = "tx", "rx"; - clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; + clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>, + <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1684,7 +1759,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dma-names = "tx", "rx"; - clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; + clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>, + <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1700,7 +1776,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dma-names = "tx", "rx"; - clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; + clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>, + <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1716,7 +1793,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dma-names = "tx", "rx"; - clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; + clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>, + <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1732,7 +1810,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dma-names = "tx", "rx"; - clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; + clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>, + <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1754,7 +1833,7 @@ mac: ethernet@48484000 { compatible = "ti,dra7-cpsw","ti,cpsw"; ti,hwmods = "gmac"; - clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; + clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; @@ -1824,7 +1903,7 @@ reg = <0x4ae3c000 0x2000>; syscon-raminit = <&scm_conf 0x558 0>; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dcan1_sys_clk_mux>; + clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>; status = "disabled"; }; @@ -1855,7 +1934,7 @@ reg = <0x58001000 0x1000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "dss_dispc"; - clocks = <&dss_dss_clk>; + clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; /* CTRL_CORE_SMA_SW_1 */ syscon-pol = <&scm_conf 0x534>; @@ -1871,8 +1950,11 @@ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ti,hwmods = "dss_hdmi"; - clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; + clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + dmas = <&sdma_xbar 76>; + dma-names = "audio_tx"; }; }; @@ -2018,6 +2100,19 @@ clocks = <&l3_iclk_div>; clock-names = "fck"; }; + + opp_supply_mpu: opp-supply@4a003b20 { + compatible = "ti,omap5-opp-supply"; + reg = <0x4a003b20 0xc>; + ti,efuse-settings = < + /* uV offset */ + 1060000 0x0 + 1160000 0x4 + 1210000 0x8 + >; + ti,absolute-max-voltage-uv = <1500000>; + }; + }; thermal_zones: thermal-zones { @@ -2055,4 +2150,20 @@ temperature = <120000>; /* milli Celsius */ }; -/include/ "dra7xx-clocks.dtsi" +#include "dra7xx-clocks.dtsi" + +&core_crit { + temperature = <120000>; /* milli Celsius */ +}; + +&gpu_crit { + temperature = <120000>; /* milli Celsius */ +}; + +&dspeve_crit { + temperature = <120000>; /* milli Celsius */ +}; + +&iva_crit { + temperature = <120000>; /* milli Celsius */ +}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 2e485a13dfd7..e85f560a2f78 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -514,7 +514,7 @@ &atl { assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_gfclk_mux>, + <&atl_clkctrl DRA7_ATL_CLKCTRL 26>, <&dpll_abe_ck>, <&dpll_abe_m2x2_ck>, <&atl_clkin2_ck>; @@ -532,7 +532,7 @@ &mcasp3 { #sound-dai-cells = <0>; - assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&atl_clkin2_ck>; status = "okay"; diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi index 57bfe5caf5e4..47bb90f41f3f 100644 --- a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi +++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi @@ -148,3 +148,7 @@ &mmc1 { vqmmc-supply = <&ldo1_reg>; }; + +&cpu0 { + vdd-supply = <&smps1_reg>; +}; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index 67107605fb4c..c011d2e64fef 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -25,8 +25,8 @@ <0x58004300 0x20>; reg-names = "dss", "pll1_clkctrl", "pll1"; - clocks = <&dss_dss_clk>, - <&dss_video1_clk>; + clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>; clock-names = "fck", "video1_clk"; }; @@ -50,3 +50,15 @@ status = "disabled"; }; }; + +&pcie1_rc { + compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +}; + +&pcie1_ep { + compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; +}; + +&pcie2_rc { + compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +}; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 24e6746c5b26..91e93ab588ca 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -93,9 +93,9 @@ reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2"; - clocks = <&dss_dss_clk>, - <&dss_video1_clk>, - <&dss_video2_clk>; + clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>; clock-names = "fck", "video1_clk", "video2_clk"; }; @@ -124,3 +124,15 @@ status = "disabled"; }; }; + +&pcie1_rc { + compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +}; + +&pcie1_ep { + compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep"; +}; + +&pcie2_rc { + compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +}; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index b024a65c6e27..c4fe7f8ef72a 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -148,6 +148,7 @@ compatible = "ti,tps65917"; reg = <0x58>; ti,system-power-controller; + ti,palmas-override-powerhold; interrupt-controller; #interrupt-cells = <2>; @@ -421,3 +422,19 @@ spi-max-frequency = <96000000>; }; }; + +&pcie2_phy { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; + +&pcie1_ep { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index e62b62875cba..69562cdbeada 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -11,25 +11,25 @@ atl_clkin0_ck: atl_clkin0_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; + clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; }; atl_clkin1_ck: atl_clkin1_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; + clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; }; atl_clkin2_ck: atl_clkin2_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; + clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; }; atl_clkin3_ck: atl_clkin3_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; + clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; }; hdmi_clkin_ck: hdmi_clkin_ck { @@ -809,70 +809,6 @@ assigned-clock-parents = <&dpll_core_h22x2_ck>; }; - mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <28>; - reg = <0x0550>; - }; - - mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x0550>; - }; - - mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x0550>; - }; - - timer5_gfclk_mux: timer5_gfclk_mux@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0558>; - }; - - timer6_gfclk_mux: timer6_gfclk_mux@560 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0560>; - }; - - timer7_gfclk_mux: timer7_gfclk_mux@568 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0568>; - }; - - timer8_gfclk_mux: timer8_gfclk_mux@570 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0570>; - }; - - uart6_gfclk_mux: uart6_gfclk_mux@580 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x0580>; - }; - dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; @@ -1188,39 +1124,8 @@ clocks = <&sys_clkin1>, <&abe_lp_clk_div>; reg = <0x0108>; }; - - gpio1_dbclk: gpio1_dbclk@1838 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1838>; - }; - - dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - ti,bit-shift = <24>; - reg = <0x1888>; - }; - - timer1_gfclk_mux: timer1_gfclk_mux@1840 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1840>; - }; - - uart10_gfclk_mux: uart10_gfclk_mux@1880 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1880>; - }; }; + &cm_core_clocks { dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { #clock-cells = <0>; @@ -1255,22 +1160,6 @@ reg = <0x021c>, <0x0220>; }; - optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - #clock-cells = <0>; - reg = <0x13b0>; - ti,bit-shift = <8>; - }; - - optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - #clock-cells = <0>; - reg = <0x13b8>; - ti,bit-shift = <8>; - }; - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; @@ -1281,38 +1170,6 @@ ti,max-div = <2>; }; - optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { - compatible = "ti,gate-clock"; - clocks = <&apll_pcie_ck>; - #clock-cells = <0>; - reg = <0x13b0>; - ti,bit-shift = <9>; - }; - - optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { - compatible = "ti,gate-clock"; - clocks = <&apll_pcie_ck>; - #clock-cells = <0>; - reg = <0x13b8>; - ti,bit-shift = <9>; - }; - - optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { - compatible = "ti,gate-clock"; - clocks = <&optfclk_pciephy_div>; - #clock-cells = <0>; - reg = <0x13b0>; - ti,bit-shift = <10>; - }; - - optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { - compatible = "ti,gate-clock"; - clocks = <&optfclk_pciephy_div>; - #clock-cells = <0>; - reg = <0x13b8>; - ti,bit-shift = <10>; - }; - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1541,167 +1398,6 @@ reg = <0x06c0>; }; - dss_32khz_clk: dss_32khz_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <11>; - reg = <0x1120>; - }; - - dss_48mhz_clk: dss_48mhz_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48m_fclk>; - ti,bit-shift = <9>; - reg = <0x1120>; - }; - - dss_dss_clk: dss_dss_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_h12x2_ck>; - ti,bit-shift = <8>; - reg = <0x1120>; - ti,set-rate-parent; - }; - - dss_hdmi_clk: dss_hdmi_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&hdmi_dpll_clk_mux>; - ti,bit-shift = <10>; - reg = <0x1120>; - }; - - dss_video1_clk: dss_video1_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&video1_dpll_clk_mux>; - ti,bit-shift = <12>; - reg = <0x1120>; - }; - - dss_video2_clk: dss_video2_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&video2_dpll_clk_mux>; - ti,bit-shift = <13>; - reg = <0x1120>; - }; - - gpio2_dbclk: gpio2_dbclk@1760 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1760>; - }; - - gpio3_dbclk: gpio3_dbclk@1768 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1768>; - }; - - gpio4_dbclk: gpio4_dbclk@1770 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1770>; - }; - - gpio5_dbclk: gpio5_dbclk@1778 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1778>; - }; - - gpio6_dbclk: gpio6_dbclk@1780 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1780>; - }; - - gpio7_dbclk: gpio7_dbclk@1810 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1810>; - }; - - gpio8_dbclk: gpio8_dbclk@1818 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1818>; - }; - - mmc1_clk32k: mmc1_clk32k@1328 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1328>; - }; - - mmc2_clk32k: mmc2_clk32k@1330 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1330>; - }; - - mmc3_clk32k: mmc3_clk32k@1820 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1820>; - }; - - mmc4_clk32k: mmc4_clk32k@1828 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1828>; - }; - - sata_ref_clk: sata_ref_clk@1388 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin1>; - ti,bit-shift = <8>; - reg = <0x1388>; - }; - - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_960m_gfclk>; - ti,bit-shift = <8>; - reg = <0x13f0>; - }; - - usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_960m_gfclk>; - ti,bit-shift = <8>; - reg = <0x1340>; - }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -1726,38 +1422,6 @@ reg = <0x0698>; }; - atl_dpll_clk_mux: atl_dpll_clk_mux@c00 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>; - ti,bit-shift = <24>; - reg = <0x0c00>; - }; - - atl_gfclk_mux: atl_gfclk_mux@c00 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>; - ti,bit-shift = <26>; - reg = <0x0c00>; - }; - - rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; - ti,bit-shift = <24>; - reg = <0x13d0>; - }; - - gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>; - ti,bit-shift = <25>; - reg = <0x13d0>; - }; - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -1787,362 +1451,6 @@ ti,dividers = <8>, <16>, <32>; }; - mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <28>; - reg = <0x1860>; - }; - - mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1860>; - }; - - mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1860>; - }; - - mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1868>; - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&abe_24m_fclk>; - }; - - mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1868>; - }; - - mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1898>; - }; - - mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1898>; - }; - - mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1878>; - }; - - mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1878>; - }; - - mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1904>; - }; - - mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1904>; - }; - - mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1908>; - }; - - mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1908>; - }; - - mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <22>; - reg = <0x1890>; - }; - - mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <24>; - reg = <0x1890>; - }; - - mmc1_fclk_mux: mmc1_fclk_mux@1328 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1328>; - }; - - mmc1_fclk_div: mmc1_fclk_div@1328 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc1_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1328>; - ti,index-power-of-two; - }; - - mmc2_fclk_mux: mmc2_fclk_mux@1330 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1330>; - }; - - mmc2_fclk_div: mmc2_fclk_div@1330 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc2_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1330>; - ti,index-power-of-two; - }; - - mmc3_gfclk_mux: mmc3_gfclk_mux@1820 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1820>; - }; - - mmc3_gfclk_div: mmc3_gfclk_div@1820 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc3_gfclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1820>; - ti,index-power-of-two; - }; - - mmc4_gfclk_mux: mmc4_gfclk_mux@1828 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1828>; - }; - - mmc4_gfclk_div: mmc4_gfclk_div@1828 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc4_gfclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1828>; - ti,index-power-of-two; - }; - - qspi_gfclk_mux: qspi_gfclk_mux@1838 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; - ti,bit-shift = <24>; - reg = <0x1838>; - }; - - qspi_gfclk_div: qspi_gfclk_div@1838 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&qspi_gfclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1838>; - ti,index-power-of-two; - }; - - timer10_gfclk_mux: timer10_gfclk_mux@1728 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1728>; - }; - - timer11_gfclk_mux: timer11_gfclk_mux@1730 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1730>; - }; - - timer13_gfclk_mux: timer13_gfclk_mux@17c8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x17c8>; - }; - - timer14_gfclk_mux: timer14_gfclk_mux@17d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x17d0>; - }; - - timer15_gfclk_mux: timer15_gfclk_mux@17d8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x17d8>; - }; - - timer16_gfclk_mux: timer16_gfclk_mux@1830 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1830>; - }; - - timer2_gfclk_mux: timer2_gfclk_mux@1738 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1738>; - }; - - timer3_gfclk_mux: timer3_gfclk_mux@1740 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1740>; - }; - - timer4_gfclk_mux: timer4_gfclk_mux@1748 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1748>; - }; - - timer9_gfclk_mux: timer9_gfclk_mux@1750 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1750>; - }; - - uart1_gfclk_mux: uart1_gfclk_mux@1840 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1840>; - }; - - uart2_gfclk_mux: uart2_gfclk_mux@1848 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1848>; - }; - - uart3_gfclk_mux: uart3_gfclk_mux@1850 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1850>; - }; - - uart4_gfclk_mux: uart4_gfclk_mux@1858 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1858>; - }; - - uart5_gfclk_mux: uart5_gfclk_mux@1870 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1870>; - }; - - uart7_gfclk_mux: uart7_gfclk_mux@18d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x18d0>; - }; - - uart8_gfclk_mux: uart8_gfclk_mux@18e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x18e0>; - }; - - uart9_gfclk_mux: uart9_gfclk_mux@18e8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x18e8>; - }; - vip1_gclk_mux: vip1_gclk_mux@1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -2216,3 +1524,210 @@ reg = <0x6c4>; }; }; + +&cm_core_aon { + mpu_cm: mpu_cm@300 { + compatible = "ti,omap4-cm"; + reg = <0x300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300 0x100>; + + mpu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + ipu_cm: ipu_cm@500 { + compatible = "ti,omap4-cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + ipu_clkctrl: clk@40 { + compatible = "ti,clkctrl"; + reg = <0x40 0x44>; + #clock-cells = <2>; + }; + }; + + rtc_cm: rtc_cm@700 { + compatible = "ti,omap4-cm"; + reg = <0x700 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x100>; + + rtc_clkctrl: clk@40 { + compatible = "ti,clkctrl"; + reg = <0x40 0x8>; + #clock-cells = <2>; + }; + }; + +}; + +&cm_core { + coreaon_cm: coreaon_cm@600 { + compatible = "ti,omap4-cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + coreaon_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + l3main1_cm: l3main1_cm@700 { + compatible = "ti,omap4-cm"; + reg = <0x700 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x100>; + + l3main1_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x74>; + #clock-cells = <2>; + }; + }; + + dma_cm: dma_cm@a00 { + compatible = "ti,omap4-cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + dma_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + emif_cm: emif_cm@b00 { + compatible = "ti,omap4-cm"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb00 0x100>; + + emif_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + atl_cm: atl_cm@c00 { + compatible = "ti,omap4-cm"; + reg = <0xc00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xc00 0x100>; + + atl_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x4>; + #clock-cells = <2>; + }; + }; + + l4cfg_cm: l4cfg_cm@d00 { + compatible = "ti,omap4-cm"; + reg = <0xd00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd00 0x100>; + + l4cfg_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x84>; + #clock-cells = <2>; + }; + }; + + l3instr_cm: l3instr_cm@e00 { + compatible = "ti,omap4-cm"; + reg = <0xe00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe00 0x100>; + + l3instr_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + dss_cm: dss_cm@1100 { + compatible = "ti,omap4-cm"; + reg = <0x1100 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1100 0x100>; + + dss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + l3init_cm: l3init_cm@1300 { + compatible = "ti,omap4-cm"; + reg = <0x1300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1300 0x100>; + + l3init_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xd4>; + #clock-cells = <2>; + }; + }; + + l4per_cm: l4per_cm@1700 { + compatible = "ti,omap4-cm"; + reg = <0x1700 0x300>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1700 0x300>; + + l4per_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x20c>; + #clock-cells = <2>; + + assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; + assigned-clock-parents = <&abe_24m_fclk>; + }; + }; + +}; + +&prm { + wkupaon_cm: wkupaon_cm@1800 { + compatible = "ti,omap4-cm"; + reg = <0x1800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1800 0x100>; + + wkupaon_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x6c>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts index c9f3ea29cf9e..adfa559a488b 100644 --- a/arch/arm/boot/dts/efm32gg-dk3750.dts +++ b/arch/arm/boot/dts/efm32gg-dk3750.dts @@ -37,7 +37,7 @@ }; eeprom@50 { - compatible = "microchip,24c02"; + compatible = "microchip,24c02", "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts index 9a134ed271eb..bc9d5b697452 100644 --- a/arch/arm/boot/dts/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/ep7211-edb7211.dts @@ -75,7 +75,7 @@ }; &bus { - flash: nor@00000000 { + flash: nor@0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <2>; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 123b203be06c..b554f85add41 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -36,6 +36,18 @@ status = "okay"; }; + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usart0: serial@fffb0000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index 4cbfa09c6c4e..20446a846a98 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source * @@ -6,10 +7,6 @@ * * Device tree source file for Samsung's ARTIK5 evaluation board * which is based on Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 639c2e605f3c..0aa577fe9f95 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos3250 based ARTIK5 module device tree source * @@ -6,10 +7,6 @@ * * Device tree source file for Samsung's ARTIK5 module which is based on * Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "exynos3250.dtsi" @@ -29,7 +26,7 @@ reg = <0x40000000 0x1ff00000>; }; - firmware@0205f000 { + firmware@205f000 { compatible = "samsung,secure-firmware"; reg = <0x0205f000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index bbdfcbc6e7d2..6ffedf4ed9f2 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos3250 based Monk board device tree source * @@ -6,10 +7,6 @@ * * Device tree source file for Samsung's Monk board which is based on * Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -32,7 +29,7 @@ reg = <0x40000000 0x1ff00000>; }; - firmware@0205F000 { + firmware@205f000 { compatible = "samsung,secure-firmware"; reg = <0x0205F000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index a149f148e659..dff3c6e3aa1f 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source * @@ -6,11 +7,7 @@ * * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 0b45467d77a8..2c3460781cc6 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos3250 based Rinato board device tree source * @@ -6,10 +7,6 @@ * * Device tree source file for Samsung's Rinato board which is based on * Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -32,7 +29,7 @@ reg = <0x40000000 0x1ff00000>; }; - firmware@0205F000 { + firmware@205f000 { compatible = "samsung,secure-firmware"; reg = <0x0205F000 0x1000>; }; @@ -227,28 +224,6 @@ vci-supply = <&ldo20_reg>; reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - power-on-delay= <30>; - power-off-delay= <120>; - reset-delay = <5>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <29>; - panel-height-mm = <29>; - - display-timings { - timing-0 { - clock-frequency = <4600000>; - hactive = <320>; - vactive = <320>; - hfront-porch = <1>; - hback-porch = <1>; - hsync-len = <1>; - vfront-porch = <150>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; }; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 590ee442d0ae..b8fb94f5daa8 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos3250 SoC device tree source * @@ -11,10 +12,6 @@ * Note: This file does not include device nodes for all the controllers in * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "exynos4-cpu-thermal.dtsi" @@ -122,7 +119,7 @@ }; }; - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x40000>; #address-cells = <1>; @@ -164,31 +161,31 @@ syscon = <&pmu_system_controller>; }; - pd_cam: cam-power-domain@10023C00 { + pd_cam: cam-power-domain@10023c00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x20>; #power-domain-cells = <0>; }; - pd_mfc: mfc-power-domain@10023C40 { + pd_mfc: mfc-power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C40 0x20>; #power-domain-cells = <0>; }; - pd_g3d: g3d-power-domain@10023C60 { + pd_g3d: g3d-power-domain@10023c60 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C60 0x20>; #power-domain-cells = <0>; }; - pd_lcd0: lcd0-power-domain@10023C80 { + pd_lcd0: lcd0-power-domain@10023c80 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C80 0x20>; #power-domain-cells = <0>; }; - pd_isp: isp-power-domain@10023CA0 { + pd_isp: isp-power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; #power-domain-cells = <0>; @@ -204,7 +201,7 @@ <&cmu CLK_FIN_PLL>; }; - cmu_dmc: clock-controller@105C0000 { + cmu_dmc: clock-controller@105c0000 { compatible = "samsung,exynos3250-cmu-dmc"; reg = <0x105C0000 0x2000>; #clock-cells = <1>; @@ -219,7 +216,7 @@ status = "disabled"; }; - tmu: tmu@100C0000 { + tmu: tmu@100c0000 { compatible = "samsung,exynos3250-tmu"; reg = <0x100C0000 0x100>; interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; @@ -287,7 +284,7 @@ status = "disabled"; }; - sysmmu_jpeg: sysmmu@11A60000 { + sysmmu_jpeg: sysmmu@11a60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11a60000 0x1000>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, @@ -313,7 +310,7 @@ status = "disabled"; }; - dsi_0: dsi@11C80000 { + dsi_0: dsi@11c80000 { compatible = "samsung,exynos3250-mipi-dsi"; reg = <0x11C80000 0x10000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -328,7 +325,7 @@ status = "disabled"; }; - sysmmu_fimd0: sysmmu@11E20000 { + sysmmu_fimd0: sysmmu@11e20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11e20000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, @@ -386,7 +383,7 @@ status = "disabled"; }; - exynos_usbphy: exynos-usbphy@125B0000 { + exynos_usbphy: exynos-usbphy@125b0000 { compatible = "samsung,exynos3250-usb2-phy"; reg = <0x125B0000 0x100>; samsung,pmureg-phandle = <&pmu_system_controller>; @@ -425,7 +422,7 @@ }; }; - adc: adc@126C0000 { + adc: adc@126c0000 { compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2"; reg = <0x126C0000 0x100>; @@ -544,7 +541,7 @@ status = "disabled"; }; - i2c_4: i2c@138A0000 { + i2c_4: i2c@138a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -557,7 +554,7 @@ status = "disabled"; }; - i2c_5: i2c@138B0000 { + i2c_5: i2c@138b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -570,7 +567,7 @@ status = "disabled"; }; - i2c_6: i2c@138C0000 { + i2c_6: i2c@138c0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -583,7 +580,7 @@ status = "disabled"; }; - i2c_7: i2c@138D0000 { + i2c_7: i2c@138d0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -641,7 +638,7 @@ status = "disabled"; }; - pwm: pwm@139D0000 { + pwm: pwm@139d0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi index 735cb2f10817..021d9fc1b492 100644 --- a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device tree sources for Exynos4 thermal zone * * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 5739389f5bb8..6d59cc827649 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4 SoC series common device tree source * @@ -13,10 +14,6 @@ * Note: This file does not include device nodes for all the controllers in * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/clock/exynos4.h> @@ -55,7 +52,7 @@ serial3 = &serial_3; }; - clock_audss: clock-controller@03810000 { + clock_audss: clock-controller@3810000 { compatible = "samsung,exynos4210-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; @@ -64,7 +61,7 @@ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; - i2s0: i2s@03830000 { + i2s0: i2s@3830000 { compatible = "samsung,s5pv210-i2s"; reg = <0x03830000 0x100>; clocks = <&clock_audss EXYNOS_I2S_BUS>, @@ -101,28 +98,28 @@ syscon = <&pmu_system_controller>; }; - pd_mfc: mfc-power-domain@10023C40 { + pd_mfc: mfc-power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C40 0x20>; #power-domain-cells = <0>; label = "MFC"; }; - pd_g3d: g3d-power-domain@10023C60 { + pd_g3d: g3d-power-domain@10023c60 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C60 0x20>; #power-domain-cells = <0>; label = "G3D"; }; - pd_lcd0: lcd0-power-domain@10023C80 { + pd_lcd0: lcd0-power-domain@10023c80 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C80 0x20>; #power-domain-cells = <0>; label = "LCD0"; }; - pd_tv: tv-power-domain@10023C20 { + pd_tv: tv-power-domain@10023c20 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C20 0x20>; #power-domain-cells = <0>; @@ -130,21 +127,21 @@ label = "TV"; }; - pd_cam: cam-power-domain@10023C00 { + pd_cam: cam-power-domain@10023c00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x20>; #power-domain-cells = <0>; label = "CAM"; }; - pd_gps: gps-power-domain@10023CE0 { + pd_gps: gps-power-domain@10023ce0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CE0 0x20>; #power-domain-cells = <0>; label = "GPS"; }; - pd_gps_alive: gps-alive-power-domain@10023D00 { + pd_gps_alive: gps-alive-power-domain@10023d00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023D00 0x20>; #power-domain-cells = <0>; @@ -184,7 +181,7 @@ interrupt-parent = <&gic>; }; - dsi_0: dsi@11C80000 { + dsi_0: dsi@11c80000 { compatible = "samsung,exynos4210-mipi-dsi"; reg = <0x11C80000 0x10000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; @@ -297,7 +294,7 @@ status = "disabled"; }; - keypad: keypad@100A0000 { + keypad: keypad@100a0000 { compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; @@ -342,7 +339,7 @@ status = "disabled"; }; - exynos_usbphy: exynos-usbphy@125B0000 { + exynos_usbphy: exynos-usbphy@125b0000 { compatible = "samsung,exynos4210-usb2-phy"; reg = <0x125B0000 0x100>; samsung,pmureg-phandle = <&pmu_system_controller>; @@ -538,7 +535,7 @@ status = "disabled"; }; - i2c_4: i2c@138A0000 { + i2c_4: i2c@138a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -551,7 +548,7 @@ status = "disabled"; }; - i2c_5: i2c@138B0000 { + i2c_5: i2c@138b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -564,7 +561,7 @@ status = "disabled"; }; - i2c_6: i2c@138C0000 { + i2c_6: i2c@138c0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -577,7 +574,7 @@ status = "disabled"; }; - i2c_7: i2c@138D0000 { + i2c_7: i2c@138d0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -590,7 +587,7 @@ status = "disabled"; }; - i2c_8: i2c@138E0000 { + i2c_8: i2c@138e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-hdmiphy-i2c"; @@ -651,7 +648,7 @@ status = "disabled"; }; - pwm: pwm@139D0000 { + pwm: pwm@139d0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, @@ -720,7 +717,7 @@ status = "disabled"; }; - tmu: tmu@100C0000 { + tmu: tmu@100c0000 { #include "exynos4412-tmu-sensor-conf.dtsi" }; @@ -743,7 +740,7 @@ iommus = <&sysmmu_rotator>; }; - hdmi: hdmi@12D00000 { + hdmi: hdmi@12d00000 { compatible = "samsung,exynos4210-hdmi"; reg = <0x12D00000 0x70000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; @@ -755,10 +752,11 @@ phy = <&hdmi_i2c_phy>; power-domains = <&pd_tv>; samsung,syscon-phandle = <&pmu_system_controller>; + #sound-dai-cells = <0>; status = "disabled"; }; - hdmicec: cec@100B0000 { + hdmicec: cec@100b0000 { compatible = "samsung,s5p-cec"; reg = <0x100B0000 0x200>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -771,7 +769,7 @@ status = "disabled"; }; - mixer: mixer@12C10000 { + mixer: mixer@12c10000 { compatible = "samsung,exynos4210-mixer"; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; @@ -910,7 +908,7 @@ #iommu-cells = <0>; }; - sysmmu_tv: sysmmu@12E20000 { + sysmmu_tv: sysmmu@12e20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12E20000 0x1000>; interrupt-parent = <&combiner>; @@ -921,7 +919,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc0: sysmmu@11A20000 { + sysmmu_fimc0: sysmmu@11a20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11A20000 0x1000>; interrupt-parent = <&combiner>; @@ -932,7 +930,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc1: sysmmu@11A30000 { + sysmmu_fimc1: sysmmu@11a30000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11A30000 0x1000>; interrupt-parent = <&combiner>; @@ -943,7 +941,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc2: sysmmu@11A40000 { + sysmmu_fimc2: sysmmu@11a40000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11A40000 0x1000>; interrupt-parent = <&combiner>; @@ -954,7 +952,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc3: sysmmu@11A50000 { + sysmmu_fimc3: sysmmu@11a50000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11A50000 0x1000>; interrupt-parent = <&combiner>; @@ -965,7 +963,7 @@ #iommu-cells = <0>; }; - sysmmu_jpeg: sysmmu@11A60000 { + sysmmu_jpeg: sysmmu@11a60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11A60000 0x1000>; interrupt-parent = <&combiner>; @@ -976,7 +974,7 @@ #iommu-cells = <0>; }; - sysmmu_rotator: sysmmu@12A30000 { + sysmmu_rotator: sysmmu@12a30000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12A30000 0x1000>; interrupt-parent = <&combiner>; @@ -986,7 +984,7 @@ #iommu-cells = <0>; }; - sysmmu_fimd0: sysmmu@11E20000 { + sysmmu_fimd0: sysmmu@11e20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11E20000 0x1000>; interrupt-parent = <&combiner>; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 084fcc5574ef..9a310e841d5d 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4210 based Origen board device tree source * @@ -8,11 +9,7 @@ * * Device tree source file for Insignal's Origen board which is based on * Samsung's Exynos4210 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4210.dtsi" diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index f280954b260a..dbe6c052d8c1 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source * @@ -8,11 +9,7 @@ * * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/pinctrl/samsung.h> @@ -843,7 +840,7 @@ }; }; - pinctrl@03860000 { + pinctrl@3860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 9c98a3724396..7a3e621edede 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4210 based SMDKV310 board device tree source * @@ -8,11 +9,7 @@ * * Device tree source file for Samsung's SMDKV310 board which is based on * Samsung's Exynos4210 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4210.dtsi" diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 7b6ab7265110..aaade17b140e 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4210 based Trats board device tree source * @@ -6,11 +7,7 @@ * * Device tree source file for Samsung's Trats board which is based on * Samsung's Exynos4210 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4210.dtsi" diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 0c89ea99de54..21fff7cd3aa4 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4210 based Universal C210 board device tree source * @@ -6,11 +7,7 @@ * * Device tree source file for Samsung's Universal C210 board which is based on * Samsung's Exynos4210 rev0 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4210.dtsi" @@ -31,7 +28,7 @@ stdout-path = &serial_2; }; - sysram@02020000 { + sysram@2020000 { smp-sysram@0 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 768fb075b1fd..cc978cf28267 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4210 SoC device tree source * @@ -13,11 +14,7 @@ * Note: This file does not include device nodes for all the controllers in * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include "exynos4.dtsi" #include "exynos4210-pinctrl.dtsi" @@ -64,7 +61,7 @@ }; }; - sysram: sysram@02020000 { + sysram: sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x20000>; #address-cells = <1>; @@ -82,7 +79,7 @@ }; }; - pd_lcd1: lcd1-power-domain@10023CA0 { + pd_lcd1: lcd1-power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; #power-domain-cells = <0>; @@ -151,12 +148,12 @@ }; }; - pinctrl_2: pinctrl@03860000 { + pinctrl_2: pinctrl@3860000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x03860000 0x1000>; }; - tmu: tmu@100C0000 { + tmu: tmu@100c0000 { compatible = "samsung,exynos4210-tmu"; interrupt-parent = <&combiner>; reg = <0x100C0000 0x100>; @@ -229,7 +226,7 @@ }; }; - mixer: mixer@12C10000 { + mixer: mixer@12c10000 { clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", "sclk_mixer"; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, @@ -245,7 +242,7 @@ status = "disabled"; }; - sysmmu_g2d: sysmmu@12A20000 { + sysmmu_g2d: sysmmu@12a20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12A20000 0x1000>; interrupt-parent = <&combiner>; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index d66093084dbb..a4cd4939fe9a 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * TOPEET's Exynos4412 based itop board device tree source * @@ -7,10 +8,6 @@ * * Device tree source file for TOPEET iTop Exynos 4412 core board * which is based on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index 14ce2c69bc0b..ab7affab7f1c 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * TOPEET's Exynos4412 based itop board device tree source * @@ -7,10 +8,6 @@ * * Device tree source file for TOPEET iTop Exynos 4412 SCP package core * board which is based on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/clock/samsung,s2mps11.h> @@ -26,7 +23,7 @@ reg = <0x40000000 0x40000000>; }; - firmware@0203F000 { + firmware@203f000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 102acd78be15..556ea78b8e32 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards * device tree source - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/sound/samsung-i2s.h> @@ -20,7 +17,7 @@ stdout-path = &serial_1; }; - firmware@0204F000 { + firmware@204f000 { compatible = "samsung,secure-firmware"; reg = <0x0204F000 0x1000>; }; @@ -31,8 +28,6 @@ pinctrl-0 = <&gpio_power_key>; power_key { - interrupt-parent = <&gpx1>; - interrupts = <3 IRQ_TYPE_NONE>; gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "power key"; @@ -253,7 +248,7 @@ samsung,i2c-max-bus-freq = <400000>; status = "okay"; - usb3503: usb3503@08 { + usb3503: usb3503@8 { compatible = "smsc,usb3503"; reg = <0x08>; @@ -263,7 +258,7 @@ initial-mode = <1>; }; - max77686: pmic@09 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 44a4de08466b..bdcd4523cc1c 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel's Exynos4412 based ODROID-U3 board device tree source * @@ -5,11 +6,7 @@ * * Device tree source file for Hardkernel's ODROID-U3 board which is based * on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4412-odroid-common.dtsi" diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 97882267ef09..2dff129bc2ad 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel's Exynos4412 based ODROID-X board device tree source * @@ -5,11 +6,7 @@ * * Device tree source file for Hardkernel's ODROID-X board which is based * on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4412-odroid-common.dtsi" @@ -43,8 +40,6 @@ pinctrl-0 = <&gpio_power_key &gpio_home_key>; home_key { - interrupt-parent = <&gpx2>; - interrupts = <2 IRQ_TYPE_NONE>; gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; linux,code = <KEY_HOME>; label = "home key"; diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts index d867b2ee95ca..f4b68c75c962 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel's Exynos4412 based ODROID-X2 board device tree source * @@ -5,11 +6,7 @@ * * Device tree source file for Hardkernel's ODROID-X2 board which is based * on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include "exynos4412-odroidx.dts" #include "exynos4412-prime.dtsi" diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 8a89eb893d64..1514f0dbaff8 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Insignal's Exynos4412 based Origen board device tree source * @@ -6,11 +7,7 @@ * * Device tree source file for Insignal's Origen board which is based on * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4412.dtsi" @@ -32,7 +29,7 @@ stdout-path = &serial_2; }; - firmware@0203F000 { + firmware@203f000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi index 1d27c28564e4..e8dd5f2d976f 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source * @@ -6,11 +7,7 @@ * * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/pinctrl/samsung.h> @@ -899,7 +896,7 @@ }; }; - pinctrl_2: pinctrl@03860000 { + pinctrl_2: pinctrl@3860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; @@ -925,7 +922,7 @@ }; }; - pinctrl_3: pinctrl@106E0000 { + pinctrl_3: pinctrl@106e0000 { gpv0: gpv0 { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi index 16e4b77d8cb1..3a3b2fafefdd 100644 --- a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device tree sources for Exynos4412 PPMU common device tree * * Copyright (C) 2015 Samsung Electronics * Author: Chanwoo Choi <cw00.choi@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &ppmu_dmc0 { diff --git a/arch/arm/boot/dts/exynos4412-prime.dtsi b/arch/arm/boot/dts/exynos4412-prime.dtsi index a67bd953d754..8e7a7fb98124 100644 --- a/arch/arm/boot/dts/exynos4412-prime.dtsi +++ b/arch/arm/boot/dts/exynos4412-prime.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4412 Prime SoC device tree source * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /* diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 7fcb43431b59..5c5c2887c14f 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4412 based SMDK board device tree source * @@ -6,11 +7,7 @@ * * Device tree source file for Samsung's SMDK4412 board which is based on * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4412.dtsi" diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index bceb919ac637..f285790e8e04 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -18,6 +18,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/maxim,max77686.h> +#include <dt-bindings/pinctrl/samsung.h> / { model = "Samsung Trats 2 based on Exynos4412"; @@ -40,7 +41,7 @@ stdout-path = &serial_2; }; - firmware@0204F000 { + firmware@204f000 { compatible = "samsung,secure-firmware"; reg = <0x0204F000 0x1000>; }; @@ -97,6 +98,34 @@ gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vsil12: voltage-regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "VSIL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&buck7_reg>; + }; + + vcc33mhl: voltage-regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3.3_MHL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc18mhl: voltage-regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8_MHL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; gpio-keys { @@ -206,7 +235,7 @@ #size-cells = <0>; status = "okay"; - ak8975@0c { + ak8975@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; @@ -229,6 +258,36 @@ }; }; + i2c-mhl { + compatible = "i2c-gpio"; + gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <100>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&i2c_mhl_bus>; + pinctrl-names = "default"; + status = "okay"; + + sii9234: hdmi-bridge@39 { + compatible = "sil,sii9234"; + avcc33-supply = <&vcc33mhl>; + iovcc18-supply = <&vcc18mhl>; + avcc12-supply = <&vsil12>; + cvcc12-supply = <&vsil12>; + reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpf3>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x39>; + + port { + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; + }; + }; + }; + camera: camera { pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; pinctrl-names = "default"; @@ -241,6 +300,13 @@ }; + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + }; + sound { compatible = "samsung,trats2-audio"; samsung,i2s-controller = <&i2s0>; @@ -395,7 +461,7 @@ reg = <0>; vdd3-supply = <&lcd_vdd3_reg>; vci-supply = <&ldo25_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; power-on-delay= <50>; reset-delay = <100>; init-delay = <100>; @@ -501,6 +567,29 @@ status = "okay"; }; +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + vdd-supply = <&ldo3_reg>; + vdd_osc-supply = <&ldo4_reg>; + vdd_pll-supply = <&ldo3_reg>; + ddc = <&i2c_5>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + hdmi_to_mhl: endpoint { + remote-endpoint = <&mhl_to_hdmi>; + }; + }; + }; +}; + &hsotg { vusb_d-supply = <&ldo15_reg>; vusb_a-supply = <&ldo12_reg>; @@ -579,6 +668,10 @@ }; }; +&i2c_5 { + status = "okay"; +}; + &i2c_7 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -587,7 +680,7 @@ pinctrl-names = "default"; status = "okay"; - max77686: max77686_pmic@09 { + max77686: max77686_pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; @@ -873,12 +966,20 @@ }; }; +&i2c_8 { + status = "okay"; +}; + &i2s0 { pinctrl-0 = <&i2s0_bus>; pinctrl-names = "default"; status = "okay"; }; +&mixer { + status = "okay"; +}; + &mshc_0 { broken-cd; non-removable; @@ -904,6 +1005,18 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; + mhl_int: mhl-int { + samsung,pins = "gpf3-5"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + i2c_mhl_bus: i2c-mhl-bus { + samsung,pins = "gpf0-4", "gpf0-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + sleep0: sleep-states { PIN_SLP(gpa0-0, INPUT, NONE); PIN_SLP(gpa0-1, OUT0, NONE); @@ -1007,6 +1120,11 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; + hdmi_hpd: hdmi-hpd { + samsung,pins = "gpx3-7"; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + sleep1: sleep-states { PIN_SLP(gpk0-0, PREV, NONE); PIN_SLP(gpk0-1, PREV, NONE); @@ -1239,6 +1357,26 @@ status = "okay"; }; +&sdhci_3 { + #address-cells = <1>; + #size-cells = <0>; + non-removable; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_NONE>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7ff03a7e8fb9..e4ad2fc0329e 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4412 SoC device tree source * @@ -11,11 +12,7 @@ * Note: This file does not include device nodes for all the controllers in * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include "exynos4.dtsi" #include "exynos4412-pinctrl.dtsi" @@ -38,7 +35,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@A00 { + cpu0: cpu@a00 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA00>; @@ -50,21 +47,21 @@ #cooling-cells = <2>; /* min followed by max */ }; - cpu@A01 { + cpu@a01 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA01>; operating-points-v2 = <&cpu0_opp_table>; }; - cpu@A02 { + cpu@a02 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA02>; operating-points-v2 = <&cpu0_opp_table>; }; - cpu@A03 { + cpu@a03 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA03>; @@ -150,7 +147,7 @@ }; }; - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x40000>; #address-cells = <1>; @@ -168,7 +165,7 @@ }; }; - pd_isp: isp-power-domain@10023CA0 { + pd_isp: isp-power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; #power-domain-cells = <0>; @@ -191,10 +188,19 @@ clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x20000>; + reg = <0x10030000 0x18000>; #clock-cells = <1>; }; + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; @@ -224,7 +230,7 @@ samsung,syscon-phandle = <&pmu_system_controller>; }; - adc: adc@126C0000 { + adc: adc@126c0000 { compatible = "samsung,exynos-adc-v1"; reg = <0x126C0000 0x100>; interrupt-parent = <&combiner>; @@ -257,18 +263,18 @@ reg = <0x12390000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite0>; status = "disabled"; }; - fimc_lite_1: fimc-lite@123A0000 { + fimc_lite_1: fimc-lite@123a0000 { compatible = "samsung,exynos4212-fimc-lite"; reg = <0x123A0000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite1>; status = "disabled"; @@ -280,29 +286,35 @@ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>, - <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, - <&clock CLK_PPMUISPMX>, + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, - <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, - <&clock CLK_PWM_ISP>, - <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, - <&clock CLK_DIV_MCUISP0>, - <&clock CLK_DIV_MCUISP1>, - <&clock CLK_UART_ISP_SCLK>, - <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, + <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK400_MCUISP>; + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "mpll", "isp", + "ppmuispmx", "isp", "drc", "fd", "mcuisp", "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "uart", "aclk200", - "div_aclk200", "aclk400mcuisp", - "div_aclk400mcuisp"; + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; iommu-names = "isp", "drc", "fd", "mcuctl"; @@ -318,7 +330,7 @@ i2c1_isp: i2c-isp@12140000 { compatible = "samsung,exynos4212-i2c-isp"; reg = <0x12140000 0x100>; - clocks = <&clock CLK_I2C1_ISP>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; clock-names = "i2c_isp"; #address-cells = <1>; #size-cells = <0>; @@ -355,7 +367,7 @@ interrupts = <16 2>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISP>; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; #iommu-cells = <0>; }; @@ -366,51 +378,53 @@ interrupts = <16 3>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_DRC>; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; #iommu-cells = <0>; }; - sysmmu_fimc_fd: sysmmu@122A0000 { + sysmmu_fimc_fd: sysmmu@122a0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x122A0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 4>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FD>; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; #iommu-cells = <0>; }; - sysmmu_fimc_mcuctl: sysmmu@122B0000 { + sysmmu_fimc_mcuctl: sysmmu@122b0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x122B0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 5>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISPCX>; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; #iommu-cells = <0>; }; - sysmmu_fimc_lite0: sysmmu@123B0000 { + sysmmu_fimc_lite0: sysmmu@123b0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x123B0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 0>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; #iommu-cells = <0>; }; - sysmmu_fimc_lite1: sysmmu@123C0000 { + sysmmu_fimc_lite1: sysmmu@123c0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x123C0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 1>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; #iommu-cells = <0>; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 66d22521c976..f8d7de1144f1 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos5 SoC series common device tree source * @@ -7,10 +8,6 @@ * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular * SoCs from Exynos5 series can include this file and provide values for SoCs * specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -106,31 +103,31 @@ reg = <0x10050000 0x5000>; }; - serial_0: serial@12C00000 { + serial_0: serial@12c00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; }; - serial_1: serial@12C10000 { + serial_1: serial@12c10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; }; - serial_2: serial@12C20000 { + serial_2: serial@12c20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; }; - serial_3: serial@12C30000 { + serial_3: serial@12c30000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C30000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; }; - i2c_0: i2c@12C60000 { + i2c_0: i2c@12c60000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -140,7 +137,7 @@ status = "disabled"; }; - i2c_1: i2c@12C70000 { + i2c_1: i2c@12c70000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C70000 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -150,7 +147,7 @@ status = "disabled"; }; - i2c_2: i2c@12C80000 { + i2c_2: i2c@12c80000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C80000 0x100>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; @@ -160,7 +157,7 @@ status = "disabled"; }; - i2c_3: i2c@12C90000 { + i2c_3: i2c@12c90000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C90000 0x100>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; @@ -170,14 +167,14 @@ status = "disabled"; }; - pwm: pwm@12DD0000 { + pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x12DD0000 0x100>; samsung,pwm-outputs = <0>, <1>, <2>, <3>; #pwm-cells = <3>; }; - rtc: rtc@101E0000 { + rtc: rtc@101e0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, @@ -195,7 +192,7 @@ status = "disabled"; }; - dp: dp-controller@145B0000 { + dp: dp-controller@145b0000 { compatible = "samsung,exynos5-dp"; reg = <0x145B0000 0x1000>; interrupts = <10 3>; @@ -204,5 +201,28 @@ #size-cells = <0>; status = "disabled"; }; + + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + prng: rng@10830400 { + compatible = "samsung,exynos5250-prng"; + reg = <0x10830400 0x200>; + }; + + trng: rng@10830600 { + compatible = "samsung,exynos5250-trng"; + reg = <0x10830600 0x100>; + }; + + g2d: g2d@10850000 { + compatible = "samsung,exynos5250-g2d"; + reg = <0x10850000 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 18a7f396ac5f..7a8a5c55701a 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos5250 based Arndale board device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -152,6 +149,8 @@ }; &hdmi { + status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_LOW>; vdd_osc-supply = <&ldo10_reg>; vdd_pll-supply = <&ldo8_reg>; @@ -455,15 +454,9 @@ &i2c_2 { status = "okay"; - + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_3 { @@ -489,15 +482,9 @@ &i2c_8 { status = "okay"; - + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x38>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2c_9 { @@ -516,6 +503,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 1fd122db18e6..6ff6dea29d44 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source * @@ -6,11 +7,7 @@ * * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 062cba4c2c31..d5e66189ed2a 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG SMDK5250 board device tree source * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -116,6 +113,8 @@ }; &hdmi { + status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; }; @@ -129,7 +128,7 @@ reg = <0x50>; }; - max77686@09 { + max77686@9 { compatible = "maxim,max77686"; reg = <0x09>; interrupt-parent = <&gpx3>; @@ -308,24 +307,16 @@ &i2c_2 { status = "okay"; + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_8 { status = "okay"; + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2c_9 { @@ -344,6 +335,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 8788880e459d..59cf1b202849 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Snow board device tree source * * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/gpio/gpio.h> @@ -261,10 +258,10 @@ }; &hdmi { + status = "okay"; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; ddc = <&i2c_2>; hdmi-en-supply = <&tps65090_fet7>; vdd-supply = <&ldo8_reg>; @@ -281,7 +278,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - max77686: max77686@09 { + max77686: max77686@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; @@ -450,13 +447,9 @@ &i2c_2 { status = "okay"; + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_3 { @@ -514,19 +507,19 @@ &i2c_8 { status = "okay"; + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2s0 { status = "okay"; }; +&mixer { + status = "okay"; +}; + /* eMMC flash */ &mmc_0 { status = "okay"; diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts index 90560c316f64..0348b1c49a69 100644 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Snow Rev 5+ board device tree source * * Copyright (c) 2012 Google, Inc * Copyright (c) 2015 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index df48f2cc96f7..4827cb506fa3 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Snow board device tree source * * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index d53bfcbeb39c..3d501926c227 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Spring board device tree source * * Copyright (c) 2013 Google, Inc * Copyright (c) 2014 SUSE LINUX Products GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -91,10 +88,10 @@ }; &hdmi { + status = "okay"; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; ddc = <&i2c_2>; hdmi-en-supply = <&ldo8_reg>; vdd-supply = <&ldo8_reg>; @@ -362,13 +359,9 @@ &i2c_2 { status = "okay"; + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_3 { @@ -412,19 +405,19 @@ &i2c_8 { status = "okay"; + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2s0 { status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 8dbeb873e99c..56626d1a4235 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5250 SoC device tree source * @@ -11,11 +12,7 @@ * Note: This file does not include device nodes for all the controllers in * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, * additional nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/clock/exynos5250.h> #include "exynos5.dtsi" @@ -93,7 +90,7 @@ }; soc: soc { - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x30000>; #address-cells = <1>; @@ -111,21 +108,28 @@ }; }; - pd_gsc: gsc-power-domain@10044000 { + pd_gsc: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; label = "GSC"; }; - pd_mfc: mfc-power-domain@10044040 { + pd_mfc: power-domain@10044040 { compatible = "samsung,exynos4210-pd"; reg = <0x10044040 0x20>; #power-domain-cells = <0>; label = "MFC"; }; - pd_disp1: disp1-power-domain@100440A0 { + pd_g3d: power-domain@10044060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044060 0x20>; + #power-domain-cells = <0>; + label = "G3D"; + }; + + pd_disp1: power-domain@100440a0 { compatible = "samsung,exynos4210-pd"; reg = <0x100440A0 0x20>; #power-domain-cells = <0>; @@ -136,6 +140,13 @@ clock-names = "oscclk", "clk0", "clk1"; }; + pd_mau: power-domain@100440c0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + #power-domain-cells = <0>; + label = "MAU"; + }; + clock: clock-controller@10010000 { compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; @@ -149,6 +160,7 @@ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + power-domains = <&pd_mau>; }; timer { @@ -165,7 +177,7 @@ clock-frequency = <24000000>; }; - mct@101C0000 { + mct@101c0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; @@ -219,10 +231,11 @@ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; - pinctrl_3: pinctrl@03860000 { + pinctrl_3: pinctrl@3860000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_mau>; }; pmu_system_controller: system-controller@10040000 { @@ -236,7 +249,7 @@ interrupt-parent = <&gic>; }; - watchdog@101D0000 { + watchdog@101d0000 { compatible = "samsung,exynos5250-wdt"; reg = <0x101D0000 0x100>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; @@ -245,15 +258,6 @@ samsung,syscon-phandle = <&pmu_system_controller>; }; - g2d@10850000 { - compatible = "samsung,exynos5250-g2d"; - reg = <0x10850000 0x1000>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_G2D>; - clock-names = "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - mfc: codec@11000000 { compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; @@ -265,7 +269,7 @@ iommu-names = "left", "right"; }; - rotator: rotator@11C00000 { + rotator: rotator@11c00000 { compatible = "samsung,exynos5250-rotator"; reg = <0x11C00000 0x64>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -283,7 +287,7 @@ #include "exynos4412-tmu-sensor-conf.dtsi" }; - sata: sata@122F0000 { + sata: sata@122f0000 { compatible = "snps,dwc-ahci"; samsung,sata-freq = <66>; reg = <0x122F0000 0x1ff>; @@ -306,7 +310,7 @@ }; /* i2c_0-3 are defined in exynos5.dtsi */ - i2c_4: i2c@12CA0000 { + i2c_4: i2c@12ca0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CA0000 0x100>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -319,7 +323,7 @@ status = "disabled"; }; - i2c_5: i2c@12CB0000 { + i2c_5: i2c@12cb0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CB0000 0x100>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; @@ -332,7 +336,7 @@ status = "disabled"; }; - i2c_6: i2c@12CC0000 { + i2c_6: i2c@12cc0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CC0000 0x100>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; @@ -345,7 +349,7 @@ status = "disabled"; }; - i2c_7: i2c@12CD0000 { + i2c_7: i2c@12cd0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CD0000 0x100>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; @@ -358,7 +362,7 @@ status = "disabled"; }; - i2c_8: i2c@12CE0000 { + i2c_8: i2c@12ce0000 { compatible = "samsung,s3c2440-hdmiphy-i2c"; reg = <0x12CE0000 0x1000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; @@ -367,9 +371,14 @@ clocks = <&clock CLK_I2C_HDMI>; clock-names = "i2c"; status = "disabled"; + + hdmiphy: hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; }; - i2c_9: i2c@121D0000 { + i2c_9: i2c@121d0000 { compatible = "samsung,exynos5-sata-phy-i2c"; reg = <0x121D0000 0x100>; #address-cells = <1>; @@ -475,7 +484,7 @@ status = "disabled"; }; - i2s0: i2s@03830000 { + i2s0: i2s@3830000 { compatible = "samsung,s5pv210-i2s"; status = "disabled"; reg = <0x03830000 0x100>; @@ -490,9 +499,10 @@ samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + power-domains = <&pd_mau>; }; - i2s1: i2s@12D60000 { + i2s1: i2s@12d60000 { compatible = "samsung,s3c6410-i2s"; status = "disabled"; reg = <0x12D60000 0x100>; @@ -503,9 +513,10 @@ clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; + power-domains = <&pd_mau>; }; - i2s2: i2s@12D70000 { + i2s2: i2s@12d70000 { compatible = "samsung,s3c6410-i2s"; status = "disabled"; reg = <0x12D70000 0x100>; @@ -516,6 +527,7 @@ clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; + power-domains = <&pd_mau>; }; usb_dwc3 { @@ -591,7 +603,7 @@ interrupt-parent = <&gic>; ranges; - pdma0: pdma@121A0000 { + pdma0: pdma@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; @@ -602,7 +614,7 @@ #dma-requests = <32>; }; - pdma1: pdma@121B0000 { + pdma1: pdma@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -624,7 +636,7 @@ #dma-requests = <1>; }; - mdma1: mdma@11C10000 { + mdma1: mdma@11c10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; @@ -637,7 +649,7 @@ }; gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -647,7 +659,7 @@ }; gsc_1: gsc@13e10000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -657,7 +669,7 @@ }; gsc_2: gsc@13e20000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -667,7 +679,7 @@ }; gsc_3: gsc@13e30000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -687,9 +699,11 @@ clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; samsung,syscon-phandle = <&pmu_system_controller>; + phy = <&hdmiphy>; + status = "disabled"; }; - hdmicec: cec@101B0000 { + hdmicec: cec@101b0000 { compatible = "samsung,s5p-cec"; reg = <0x101B0000 0x200>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -702,7 +716,7 @@ status = "disabled"; }; - mixer@14450000 { + mixer: mixer@14450000 { compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; power-domains = <&pd_disp1>; @@ -711,6 +725,7 @@ <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; iommus = <&sysmmu_tv>; + status = "disabled"; }; dp_phy: video-phy { @@ -719,7 +734,7 @@ #phy-cells = <0>; }; - adc: adc@12D10000 { + adc: adc@12d10000 { compatible = "samsung,exynos-adc-v1"; reg = <0x12D10000 0x100>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -731,15 +746,7 @@ status = "disabled"; }; - sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - - sysmmu_g2d: sysmmu@10A60000 { + sysmmu_g2d: sysmmu@10a60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A60000 0x1000>; interrupt-parent = <&combiner>; @@ -771,7 +778,7 @@ #iommu-cells = <0>; }; - sysmmu_rotator: sysmmu@11D40000 { + sysmmu_rotator: sysmmu@11d40000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11D40000 0x1000>; interrupt-parent = <&combiner>; @@ -781,7 +788,7 @@ #iommu-cells = <0>; }; - sysmmu_jpeg: sysmmu@11F20000 { + sysmmu_jpeg: sysmmu@11f20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11F20000 0x1000>; interrupt-parent = <&combiner>; @@ -812,7 +819,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_fd: sysmmu@132A0000 { + sysmmu_fimc_fd: sysmmu@132a0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x132A0000 0x1000>; interrupt-parent = <&combiner>; @@ -842,7 +849,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_mcuctl: sysmmu@132B0000 { + sysmmu_fimc_mcuctl: sysmmu@132b0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x132B0000 0x1000>; interrupt-parent = <&combiner>; @@ -852,7 +859,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_odc: sysmmu@132C0000 { + sysmmu_fimc_odc: sysmmu@132c0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x132C0000 0x1000>; interrupt-parent = <&combiner>; @@ -862,7 +869,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_dis0: sysmmu@132D0000 { + sysmmu_fimc_dis0: sysmmu@132d0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x132D0000 0x1000>; interrupt-parent = <&combiner>; @@ -882,7 +889,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_3dnr: sysmmu@132F0000 { + sysmmu_fimc_3dnr: sysmmu@132f0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x132F0000 0x1000>; interrupt-parent = <&combiner>; @@ -892,7 +899,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_lite0: sysmmu@13C40000 { + sysmmu_fimc_lite0: sysmmu@13c40000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13C40000 0x1000>; interrupt-parent = <&combiner>; @@ -903,7 +910,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_lite1: sysmmu@13C50000 { + sysmmu_fimc_lite1: sysmmu@13c50000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13C50000 0x1000>; interrupt-parent = <&combiner>; @@ -914,7 +921,7 @@ #iommu-cells = <0>; }; - sysmmu_gsc0: sysmmu@13E80000 { + sysmmu_gsc0: sysmmu@13e80000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13E80000 0x1000>; interrupt-parent = <&combiner>; @@ -925,7 +932,7 @@ #iommu-cells = <0>; }; - sysmmu_gsc1: sysmmu@13E90000 { + sysmmu_gsc1: sysmmu@13e90000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13E90000 0x1000>; interrupt-parent = <&combiner>; @@ -936,7 +943,7 @@ #iommu-cells = <0>; }; - sysmmu_gsc2: sysmmu@13EA0000 { + sysmmu_gsc2: sysmmu@13ea0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13EA0000 0x1000>; interrupt-parent = <&combiner>; @@ -947,7 +954,7 @@ #iommu-cells = <0>; }; - sysmmu_gsc3: sysmmu@13EB0000 { + sysmmu_gsc3: sysmmu@13eb0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13EB0000 0x1000>; interrupt-parent = <&combiner>; @@ -1016,6 +1023,13 @@ iommus = <&sysmmu_fimd1>; }; +&g2d { + iommus = <&sysmmu_g2d>; + clocks = <&clock CLK_G2D>; + clock-names = "fimg2d"; + status = "okay"; +}; + &i2c_0 { clocks = <&clock CLK_I2C0>; clock-names = "i2c"; @@ -1044,6 +1058,11 @@ pinctrl-0 = <&i2c3_bus>; }; +&prng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &pwm { clocks = <&clock CLK_PWM>; clock-names = "timers"; @@ -1084,4 +1103,14 @@ dma-names = "rx", "tx"; }; +&sss { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&trng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + #include "exynos5250-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index 1b911a219a27..b1edb20b789e 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source * @@ -6,11 +7,7 @@ * * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 73b7cdd5f522..442eb0353f29 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG XYREF5260 board device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5260.dtsi" diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 5e88c9645975..55167850619c 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5260 SoC device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/clock/exynos5260-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -106,13 +103,13 @@ #clock-cells = <1>; }; - clock_g2d: clock-controller@10A00000 { + clock_g2d: clock-controller@10a00000 { compatible = "samsung,exynos5260-clock-g2d"; reg = <0x10A00000 0x10000>; #clock-cells = <1>; }; - clock_mif: clock-controller@10CE0000 { + clock_mif: clock-controller@10ce0000 { compatible = "samsung,exynos5260-clock-mif"; reg = <0x10CE0000 0x10000>; #clock-cells = <1>; @@ -130,25 +127,25 @@ #clock-cells = <1>; }; - clock_fsys: clock-controller@122E0000 { + clock_fsys: clock-controller@122e0000 { compatible = "samsung,exynos5260-clock-fsys"; reg = <0x122E0000 0x10000>; #clock-cells = <1>; }; - clock_aud: clock-controller@128C0000 { + clock_aud: clock-controller@128c0000 { compatible = "samsung,exynos5260-clock-aud"; reg = <0x128C0000 0x10000>; #clock-cells = <1>; }; - clock_isp: clock-controller@133C0000 { + clock_isp: clock-controller@133c0000 { compatible = "samsung,exynos5260-clock-isp"; reg = <0x133C0000 0x10000>; #clock-cells = <1>; }; - clock_gscl: clock-controller@13F00000 { + clock_gscl: clock-controller@13f00000 { compatible = "samsung,exynos5260-clock-gscl"; reg = <0x13F00000 0x10000>; #clock-cells = <1>; @@ -179,7 +176,7 @@ reg = <0x10000000 0x100>; }; - mct: mct@100B0000 { + mct: mct@100b0000 { compatible = "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; @@ -198,7 +195,7 @@ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; }; - cci: cci@10F00000 { + cci: cci@10f00000 { compatible = "arm,cci-400"; #address-cells = <1>; #size-cells = <1>; @@ -236,18 +233,18 @@ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; }; - pinctrl_2: pinctrl@128B0000 { + pinctrl_2: pinctrl@128b0000 { compatible = "samsung,exynos5260-pinctrl"; reg = <0x128B0000 0x1000>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; }; - pmu_system_controller: system-controller@10D50000 { + pmu_system_controller: system-controller@10d50000 { compatible = "samsung,exynos5260-pmu", "syscon"; reg = <0x10D50000 0x10000>; }; - uart0: serial@12C00000 { + uart0: serial@12c00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; @@ -256,7 +253,7 @@ status = "disabled"; }; - uart1: serial@12C10000 { + uart1: serial@12c10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; @@ -265,7 +262,7 @@ status = "disabled"; }; - uart2: serial@12C20000 { + uart2: serial@12c20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index c4de1353e5df..a2046f5f998c 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel Odroid XU board device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com * Copyright (c) 2016 Krzysztof Kozlowski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -54,7 +51,7 @@ #clock-cells = <0>; }; - firmware@02073000 { + firmware@2073000 { compatible = "samsung,secure-firmware"; reg = <0x02073000 0x1000>; }; @@ -164,7 +161,7 @@ samsung,i2c-max-bus-freq = <400000>; status = "okay"; - usb3503: usb-hub@08 { + usb3503: usb-hub@8 { compatible = "smsc,usb3503"; reg = <0x08>; @@ -178,7 +175,7 @@ refclk-frequency = <24000000>; }; - max77802: pmic@09 { + max77802: pmic@9 { compatible = "maxim,max77802"; reg = <0x9>; interrupt-parent = <&gpx0>; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index ff46a1c27182..369a8a7f2105 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Exynos5410 SoC pin-mux and pin-config device tree source * * Copyright (c) 2013 Hardkernel Co., Ltd. * http://www.hardkernel.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 9cb7726ef8d0..8fc8c841d34b 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG SMDK5410 board device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5410.dtsi" @@ -32,7 +29,7 @@ #clock-cells = <0>; }; - firmware@02037000 { + firmware@2037000 { compatible = "samsung,secure-firmware"; reg = <0x02037000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 7eab4bc07cec..1886aa00b2db 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5410 SoC device tree source * @@ -7,10 +8,6 @@ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. * EXYNOS5410 based board files can include this file and provide * values for board specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "exynos54xx.dtsi" @@ -187,7 +184,7 @@ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; - pinctrl_3: pinctrl@03860000 { + pinctrl_3: pinctrl@3860000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -223,7 +220,7 @@ }; }; - audi2s0: i2s@03830000 { + audi2s0: i2s@3830000 { compatible = "samsung,exynos5420-i2s"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 @@ -264,6 +261,11 @@ }; }; +&arm_a15_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; + &i2c_0 { clocks = <&clock CLK_I2C0>; clock-names = "i2c"; @@ -325,6 +327,11 @@ clock-names = "fin_pll", "mct"; }; +&prng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &pwm { clocks = <&clock CLK_PWM>; clock-names = "timers"; @@ -333,7 +340,6 @@ &rtc { clocks = <&clock CLK_RTC>; clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; status = "disabled"; }; @@ -379,6 +385,11 @@ 3 0 0x07000000 0x20000>; }; +&trng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &usbdrd3_0 { clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index ee1bb9b8b366..cdda614e417e 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos5420 based Arndale Octa board device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5420.dtsi" @@ -30,7 +27,7 @@ bootargs = "console=ttySAC3,115200"; }; - firmware@02073000 { + firmware@2073000 { compatible = "samsung,secure-firmware"; reg = <0x02073000 0x1000>; }; @@ -360,6 +357,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 5c052d7ff554..123f0cef658d 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5420 SoC cpu device tree source * @@ -14,10 +15,6 @@ * booting cluster (big or LITTLE) is chosen by IROM code by reading * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting * from the LITTLE: Cortex-A7. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ / { @@ -36,6 +33,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu1: cpu@1 { @@ -48,6 +46,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -60,6 +59,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -72,6 +72,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -85,6 +86,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -97,6 +99,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -109,6 +112,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -121,6 +125,17 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; }; }; + +&arm_a7_pmu { + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + status = "okay"; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 683a4cfb4a23..5a76ed77dda1 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Peach Pit Rev 6+ board device tree source * * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -696,6 +693,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + /* eMMC flash */ &mmc_0 { status = "okay"; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 65aa0e300c23..dda8ca2d2324 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source * @@ -6,11 +7,7 @@ * * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 08c8ab173e87..831c7336f237 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG SMDK5420 board device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5420.dtsi" @@ -130,6 +127,7 @@ &hdmi { status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; @@ -347,12 +345,12 @@ &i2c_2 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + /* used by HDMI DDC */ status = "okay"; +}; - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; +&mixer { + status = "okay"; }; &mmc_0 { diff --git a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi index c8771c660550..fbc77cb58473 100644 --- a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi +++ b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi @@ -1,13 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device tree sources for Exynos5420 TMU sensor configuration * * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #include <dt-bindings/thermal/thermal_exynos.h> diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/exynos5420-trip-points.dtsi index 2180a0152c9b..a67a380717ec 100644 --- a/arch/arm/boot/dts/exynos5420-trip-points.dtsi +++ b/arch/arm/boot/dts/exynos5420-trip-points.dtsi @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device tree sources for default Exynos5420 thermal zone definition * * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ polling-delay-passive = <0>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 02d2f898efa6..2f3cb2a97f71 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5420 SoC device tree source * @@ -7,10 +8,6 @@ * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. * EXYNOS5420 based board files can include this file and provide * values for board specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "exynos54xx.dtsi" @@ -188,6 +185,7 @@ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + power-domains = <&mau_pd>; }; mfc: codec@11000000 { @@ -237,37 +235,37 @@ status = "disabled"; }; - nocp_mem0_0: nocp@10CA1000 { + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; status = "disabled"; }; - nocp_mem0_1: nocp@10CA1400 { + nocp_mem0_1: nocp@10ca1400 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1400 0x200>; status = "disabled"; }; - nocp_mem1_0: nocp@10CA1800 { + nocp_mem1_0: nocp@10ca1800 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1800 0x200>; status = "disabled"; }; - nocp_mem1_1: nocp@10CA1C00 { + nocp_mem1_1: nocp@10ca1c00 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1C00 0x200>; status = "disabled"; }; - nocp_g3d_0: nocp@11A51000 { + nocp_g3d_0: nocp@11a51000 { compatible = "samsung,exynos5420-nocp"; reg = <0x11A51000 0x200>; status = "disabled"; }; - nocp_g3d_1: nocp@11A51400 { + nocp_g3d_1: nocp@11a51400 { compatible = "samsung,exynos5420-nocp"; reg = <0x11A51400 0x200>; status = "disabled"; @@ -309,7 +307,7 @@ label = "MSC"; }; - disp_pd: power-domain@100440C0 { + disp_pd: power-domain@100440c0 { compatible = "samsung,exynos4210-pd"; reg = <0x100440C0 0x20>; #power-domain-cells = <0>; @@ -322,6 +320,13 @@ clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; + mau_pd: power-domain@100440e0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440E0 0x20>; + #power-domain-cells = <0>; + label = "MAU"; + }; + pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; @@ -352,10 +357,11 @@ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; - pinctrl_4: pinctrl@03860000 { + pinctrl_4: pinctrl@3860000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mau_pd>; }; amba { @@ -365,7 +371,7 @@ interrupt-parent = <&gic>; ranges; - adma: adma@03880000 { + adma: adma@3880000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x03880000 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -374,9 +380,10 @@ #dma-cells = <1>; #dma-channels = <6>; #dma-requests = <16>; + power-domains = <&mau_pd>; }; - pdma0: pdma@121A0000 { + pdma0: pdma@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; @@ -387,7 +394,7 @@ #dma-requests = <32>; }; - pdma1: pdma@121B0000 { + pdma1: pdma@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -409,7 +416,7 @@ #dma-requests = <1>; }; - mdma1: mdma@11C10000 { + mdma1: mdma@11c10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; @@ -429,7 +436,7 @@ }; }; - i2s0: i2s@03830000 { + i2s0: i2s@3830000 { compatible = "samsung,exynos5420-i2s"; reg = <0x03830000 0x100>; dmas = <&adma 0 @@ -446,10 +453,11 @@ samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + power-domains = <&mau_pd>; status = "disabled"; }; - i2s1: i2s@12D60000 { + i2s1: i2s@12d60000 { compatible = "samsung,exynos5420-i2s"; reg = <0x12D60000 0x100>; dmas = <&pdma1 12 @@ -465,7 +473,7 @@ status = "disabled"; }; - i2s2: i2s@12D70000 { + i2s2: i2s@12d70000 { compatible = "samsung,exynos5420-i2s"; reg = <0x12D70000 0x100>; dmas = <&pdma0 12 @@ -554,7 +562,7 @@ status = "disabled"; }; - adc: adc@12D10000 { + adc: adc@12d10000 { compatible = "samsung,exynos-adc-v2"; reg = <0x12D10000 0x100>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -566,7 +574,7 @@ status = "disabled"; }; - hsi2c_8: i2c@12E00000 { + hsi2c_8: i2c@12e00000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; @@ -579,7 +587,7 @@ status = "disabled"; }; - hsi2c_9: i2c@12E10000 { + hsi2c_9: i2c@12e10000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E10000 0x1000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; @@ -592,7 +600,7 @@ status = "disabled"; }; - hsi2c_10: i2c@12E20000 { + hsi2c_10: i2c@12e20000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E20000 0x1000>; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; @@ -618,13 +626,14 @@ samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; power-domains = <&disp_pd>; + #sound-dai-cells = <0>; }; - hdmiphy: hdmiphy@145D0000 { + hdmiphy: hdmiphy@145d0000 { reg = <0x145D0000 0x20>; }; - hdmicec: cec@101B0000 { + hdmicec: cec@101b0000 { compatible = "samsung,s5p-cec"; reg = <0x101B0000 0x200>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -646,9 +655,10 @@ clock-names = "mixer", "hdmi", "sclk_hdmi"; power-domains = <&disp_pd>; iommus = <&sysmmu_tv>; + status = "disabled"; }; - rotator: rotator@11C00000 { + rotator: rotator@11c00000 { compatible = "samsung,exynos5250-rotator"; reg = <0x11C00000 0x64>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -658,7 +668,7 @@ }; gsc_0: video-scaler@13e00000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL0>; @@ -668,7 +678,7 @@ }; gsc_1: video-scaler@13e10000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL1>; @@ -677,7 +687,7 @@ iommus = <&sysmmu_gscl1>; }; - jpeg_0: jpeg@11F50000 { + jpeg_0: jpeg@11f50000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F50000 0x1000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; @@ -686,7 +696,7 @@ iommus = <&sysmmu_jpeg0>; }; - jpeg_1: jpeg@11F60000 { + jpeg_1: jpeg@11f60000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F60000 0x1000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; @@ -1348,6 +1358,13 @@ iommu-names = "m0", "m1"; }; +&g2d { + iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; + clocks = <&clock CLK_G2D>; + clock-names = "fimg2d"; + status = "okay"; +}; + &i2c_0 { clocks = <&clock CLK_I2C0>; clock-names = "i2c"; @@ -1409,6 +1426,11 @@ clock-names = "fin_pll", "mct"; }; +&prng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &pwm { clocks = <&clock CLK_PWM>; clock-names = "timers"; @@ -1454,6 +1476,11 @@ clock-names = "secss"; }; +&trng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &usbdrd3_0 { clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index bf3c6f1ec4ee..c593809c7f08 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5422 SoC cpu device tree source * @@ -13,10 +14,6 @@ * booting cluster (big or LITTLE) is chosen by IROM code by reading * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting * from the LITTLE: Cortex-A7. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ / { @@ -35,6 +32,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu1: cpu@101 { @@ -47,6 +45,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu2: cpu@102 { @@ -59,6 +58,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu3: cpu@103 { @@ -71,6 +71,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu4: cpu@0 { @@ -84,6 +85,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu5: cpu@1 { @@ -96,6 +98,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu6: cpu@2 { @@ -108,6 +111,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu7: cpu@3 { @@ -120,6 +124,17 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; }; }; + +&arm_a7_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi new file mode 100644 index 000000000000..d31249f25ccf --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU3/XU4/HC1 boards core device tree source + * + * Copyright (c) 2017 Marek Szyprowski + * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include <dt-bindings/clock/samsung,s2mps11.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x7EA00000>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + firmware@02073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; +}; + +&bus_wcore { + devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, + <&nocp_mem1_0>, <&nocp_mem1_1>; + vdd-supply = <&buck3_reg>; + exynos,saturation-ratio = <100>; + status = "okay"; +}; + +&bus_noc { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys_apb { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys2 { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_gen { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_g2d { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_g2d_acp { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_jpeg { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_jpeg_apb { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_disp1_fimd { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_disp1 { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_gscl_scaler { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_mscl { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&buck6_reg>; +}; + +&cpu4 { + cpu-supply = <&buck2_reg>; +}; + +&hsi2c_4 { + status = "okay"; + + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + samsung,s2mps11-acokb-ground; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vddq_mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vddq_mmc2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_ldo17"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "vdd_emmc_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo26_reg: LDO26 { + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.0v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_1.8v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + cap-sd-highspeed; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; +}; + +&nocp_mem0_0 { + status = "okay"; +}; + +&nocp_mem0_1 { + status = "okay"; +}; + +&nocp_mem1_0 { + status = "okay"; +}; + +&nocp_mem1_1 { + status = "okay"; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq { + samsung,pins = "gpx0-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo7_reg>; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +/* usbdrd_dwc3_1 mode customized in each board */ + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts new file mode 100644 index 000000000000..8f332be143f7 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid HC1 board device tree source + * + * Copyright (c) 2017 Marek Szyprowski + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5422-odroid-core.dtsi" + +/ { + model = "Hardkernel Odroid HC1"; + compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ + "samsung,exynos5"; + + pwmleds { + compatible = "pwm-leds"; + + blueled { + label = "blue:heartbeat"; + pwms = <&pwm 2 2000000 0>; + pwm-names = "pwm2"; + max_brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0 0>; + trips { + cpu0_alert0: cpu-alert-0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu0_alert1: cpu-alert-1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu0_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * When reaching cpu0_alert0, reduce CPU + * by 2 steps. On Exynos5422/5800 that would + * be: 1600 MHz and 1100 MHz. + */ + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu4 0 2>; + }; + /* + * When reaching cpu0_alert1, reduce CPU + * further, down to 600 MHz (12 steps for big, + * 7 steps for LITTLE). + */ + map2 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1 0>; + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu4 0 2>; + }; + map2 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2 0>; + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu4 0 2>; + }; + map2 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3 0>; + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu4 0 2>; + }; + map2 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + }; + +}; + +&pwm { + /* + * PWM 2 -- Blue LED + */ + pinctrl-0 = <&pwm2_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <2>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index c0b85981c6bf..03611d50c5a9 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -1,25 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Hardkernel Odroid XU3 Audio Codec device tree source + * Hardkernel Odroid XU3 audio subsystem device tree source * * Copyright (c) 2015 Krzysztof Kozlowski * Copyright (c) 2014 Collabora Ltd. * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ + +#include <dt-bindings/sound/samsung-i2s.h> / { sound: sound { - compatible = "simple-audio-card"; + compatible = "samsung,odroid-xu3-audio"; + model = "Odroid-XU3"; - simple-audio-card,name = "Odroid-XU3"; - simple-audio-card,widgets = + samsung,audio-widgets = "Headphone", "Headphone Jack", "Speakers", "Speakers"; - simple-audio-card,routing = + samsung,audio-routing = "Headphone Jack", "HPL", "Headphone Jack", "HPR", "Headphone Jack", "MICBIAS", @@ -27,22 +26,49 @@ "Speakers", "SPKL", "Speakers", "SPKR"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>, + <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; - simple-audio-card,cpu { + cpu { sound-dai = <&i2s0 0>; - system-clock-frequency = <19200000>; }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&max98090>; - clocks = <&i2s0 CLK_I2S_CDCLK>; + codec { + sound-dai = <&hdmi>, <&max98090>; }; }; }; +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, + <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <(196608000 / 256)>, + <196608000>; +}; + &hsi2c_5 { status = "okay"; max98090: max98090@10 { diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index a183b56283f8..96e281c0a118 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel Odroid XU3 board device tree source * @@ -6,38 +7,30 @@ * Copyright (c) 2014 Collabora Ltd. * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com> * Anand Moon <linux.amoon@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ -#include <dt-bindings/clock/samsung,s2mps11.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/sound/samsung-i2s.h> -#include "exynos5800.dtsi" -#include "exynos5422-cpus.dtsi" +#include <dt-bindings/input/input.h> +#include "exynos5422-odroid-core.dtsi" / { - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7EA00000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - firmware@02073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power_key { + /* + * The power button (SW2) is connected to the PWRON + * pin (active high) of the S2MPS11 PMIC, which acts + * as a 16ms debouce filter and signal inverter with + * output on ONOB pin (active low). ONOB PMIC pin is + * then connected to XEINT3 SoC pin. + */ + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "power key"; + debounce-interval = <0>; + wakeup-source; }; }; @@ -63,22 +56,22 @@ polling-delay-passive = <250>; polling-delay = <0>; trips { - cpu_alert0: cpu-alert-0 { + cpu0_alert0: cpu-alert-0 { temperature = <50000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; - cpu_alert1: cpu-alert-1 { + cpu0_alert1: cpu-alert-1 { temperature = <60000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; - cpu_alert2: cpu-alert-2 { + cpu0_alert2: cpu-alert-2 { temperature = <70000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; - cpu_crit0: cpu-crit-0 { + cpu0_crit0: cpu-crit-0 { temperature = <120000>; /* millicelsius */ hysteresis = <0>; /* millicelsius */ type = "critical"; @@ -87,59 +80,258 @@ * Exynos542x supports only 4 trip-points * so for these polling mode is required. * Start polling at temperature level of last - * interrupt-driven trip: cpu_alert2 + * interrupt-driven trip: cpu0_alert2 */ - cpu_alert3: cpu-alert-3 { + cpu0_alert3: cpu-alert-3 { temperature = <70000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; - cpu_alert4: cpu-alert-4 { + cpu0_alert4: cpu-alert-4 { temperature = <85000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; - }; cooling-maps { map0 { - trip = <&cpu_alert0>; + trip = <&cpu0_alert0>; cooling-device = <&fan0 0 1>; }; map1 { - trip = <&cpu_alert1>; + trip = <&cpu0_alert1>; cooling-device = <&fan0 1 2>; }; map2 { - trip = <&cpu_alert2>; + trip = <&cpu0_alert2>; cooling-device = <&fan0 2 3>; }; /* - * When reaching cpu_alert3, reduce CPU + * When reaching cpu0_alert3, reduce CPU * by 2 steps. On Exynos5422/5800 that would * be: 1600 MHz and 1100 MHz. */ map3 { - trip = <&cpu_alert3>; + trip = <&cpu0_alert3>; cooling-device = <&cpu0 0 2>; }; map4 { - trip = <&cpu_alert3>; + trip = <&cpu0_alert3>; cooling-device = <&cpu4 0 2>; }; - /* - * When reaching cpu_alert4, reduce CPU - * further, down to 600 MHz (11 steps for big, + * When reaching cpu0_alert4, reduce CPU + * further, down to 600 MHz (12 steps for big, * 7 steps for LITTLE). */ map5 { - trip = <&cpu_alert4>; + trip = <&cpu0_alert4>; + cooling-device = <&cpu0 3 7>; + }; + map6 { + trip = <&cpu0_alert4>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu1_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu1_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu1_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu1_alert3>; + cooling-device = <&cpu0 0 2>; + }; + map4 { + trip = <&cpu1_alert3>; + cooling-device = <&cpu4 0 2>; + }; + map5 { + trip = <&cpu1_alert4>; cooling-device = <&cpu0 3 7>; }; map6 { - trip = <&cpu_alert4>; - cooling-device = <&cpu4 3 11>; + trip = <&cpu1_alert4>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu2_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu2_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu2_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu2_alert3>; + cooling-device = <&cpu0 0 2>; + }; + map4 { + trip = <&cpu2_alert3>; + cooling-device = <&cpu4 0 2>; + }; + map5 { + trip = <&cpu2_alert4>; + cooling-device = <&cpu0 3 7>; + }; + map6 { + trip = <&cpu2_alert4>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu3_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu3_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu3_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu3_alert3>; + cooling-device = <&cpu0 0 2>; + }; + map4 { + trip = <&cpu3_alert3>; + cooling-device = <&cpu4 0 2>; + }; + map5 { + trip = <&cpu3_alert4>; + cooling-device = <&cpu0 3 7>; + }; + map6 { + trip = <&cpu3_alert4>; + cooling-device = <&cpu4 3 12>; }; }; }; @@ -151,110 +343,9 @@ status = "okay"; }; -&bus_wcore { - devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, - <&nocp_mem1_0>, <&nocp_mem1_1>; - vdd-supply = <&buck3_reg>; - exynos,saturation-ratio = <100>; - status = "okay"; -}; - -&bus_noc { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys_apb { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys2 { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gen { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d_acp { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg_apb { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1_fimd { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1 { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gscl_scaler { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mscl { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FIN_PLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <19200000>; -}; - -&cpu0 { - cpu-supply = <&buck6_reg>; -}; - -&cpu4 { - cpu-supply = <&buck2_reg>; -}; - &hdmi { status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; @@ -269,246 +360,15 @@ needs-hpd; }; -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - samsung,s2mps11-acokb-ground; - - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "vdd_adc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo18_reg: LDO18 { - regulator-name = "vdd_emmc_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo26_reg: LDO26 { - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - &i2c_2 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + /* used by HDMI DDC */ status = "okay"; +}; - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; +&mixer { + status = "okay"; }; &mmc_0 { @@ -530,48 +390,18 @@ vqmmc-supply = <&ldo3_reg>; }; -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; -}; - -&nocp_mem0_0 { - status = "okay"; -}; - -&nocp_mem0_1 { - status = "okay"; -}; - -&nocp_mem1_0 { - status = "okay"; -}; - -&nocp_mem1_1 { - status = "okay"; -}; - &pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; + power_key: power-key { + samsung,pins = "gpx0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - s2mps11_irq: s2mps11-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; @@ -584,45 +414,3 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; - -&tmu_cpu0 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo7_reg>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -/* usbdrd_dwc3_1 mode customized in each board */ - -&usbdrd3_0 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 03fa88c45426..0db935f2b836 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel Odroid XU3-Lite board device tree source * @@ -5,11 +6,7 @@ * Copyright (c) 2014 Collabora Ltd. * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5422-odroidxu3-common.dtsi" diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 9ed6564acfb0..0322f281912c 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -1,14 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel Odroid XU3 board device tree source * * Copyright (c) 2014 Collabora Ltd. * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5422-odroidxu3-common.dtsi" diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 2faf88627a48..4a30cc849b00 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel Odroid XU4 board device tree source * @@ -5,13 +6,10 @@ * Copyright (c) 2014 Collabora Ltd. * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; +#include <dt-bindings/sound/samsung-i2s.h> #include "exynos5422-odroidxu3-common.dtsi" / { @@ -30,6 +28,57 @@ linux,default-trigger = "heartbeat"; }; }; + + sound: sound { + compatible = "samsung,odroid-xu3-audio"; + model = "Odroid-XU4"; + + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>, + <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&hdmi>; + }; + }; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, + <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <(196608000 / 256)>, + <196608000>; +}; + +&i2s0 { + status = "okay"; }; &pwm { diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts index ad6f533b3f40..c4b8392d1ae1 100644 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG SD5v1 board device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5440.dtsi" diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index 92bd2c6f7631..a33c4fc29ae5 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG SSDK5440 board device tree source * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos5440.dtsi" @@ -56,7 +53,7 @@ samsung,spi-feedback-delay = <0>; }; - partition@00000 { + partition@0 { label = "BootLoader"; reg = <0x60000 0x80000>; read-only; diff --git a/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi index 7b2fba0ae92b..0421c3d42905 100644 --- a/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi +++ b/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device tree sources for Exynos5440 TMU sensor configuration * * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #include <dt-bindings/thermal/thermal_exynos.h> diff --git a/arch/arm/boot/dts/exynos5440-trip-points.dtsi b/arch/arm/boot/dts/exynos5440-trip-points.dtsi index 356e963edf11..a2b04fed7d0b 100644 --- a/arch/arm/boot/dts/exynos5440-trip-points.dtsi +++ b/arch/arm/boot/dts/exynos5440-trip-points.dtsi @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device tree sources for default Exynos5440 thermal zone definition * * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ polling-delay-passive = <0>; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 7a00be7ea6d7..fce9e26b5930 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5440 SoC device tree source * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/clock/exynos5440.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -35,7 +32,7 @@ #clock-cells = <1>; }; - gic: interrupt-controller@2E0000 { + gic: interrupt-controller@2e0000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -108,7 +105,7 @@ >; }; - serial_0: serial@B0000 { + serial_0: serial@b0000 { compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -116,7 +113,7 @@ clock-names = "uart", "clk_uart_baud0"; }; - serial_1: serial@C0000 { + serial_1: serial@c0000 { compatible = "samsung,exynos4210-uart"; reg = <0xC0000 0x1000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -124,7 +121,7 @@ clock-names = "uart", "clk_uart_baud0"; }; - spi_0: spi@D0000 { + spi_0: spi@d0000 { compatible = "samsung,exynos5440-spi"; reg = <0xD0000 0x100>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -136,7 +133,7 @@ clock-names = "spi", "spi_busclk0"; }; - pin_ctrl: pinctrl@E0000 { + pin_ctrl: pinctrl@e0000 { compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, @@ -168,7 +165,7 @@ }; }; - i2c@F0000 { + i2c@f0000 { compatible = "samsung,exynos5440-i2c"; reg = <0xF0000 0x1000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -196,7 +193,7 @@ clock-names = "watchdog"; }; - gmac: ethernet@00230000 { + gmac: ethernet@230000 { compatible = "snps,dwmac-3.70a", "snps,dwmac"; reg = <0x00230000 0x8000>; interrupt-parent = <&gic>; @@ -233,7 +230,7 @@ #include "exynos5440-tmu-sensor-conf.dtsi" }; - tmuctrl_1: tmuctrl@16011C { + tmuctrl_1: tmuctrl@16011c { compatible = "samsung,exynos5440-tmu"; reg = <0x16011C 0x230>, <0x160368 0x10>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 0ed30206625c..56acd832f0b3 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Hardkernel Odroid XU/XU3 LED device tree source * @@ -5,11 +6,7 @@ * Copyright (c) 2014 Collabora Ltd. * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 0389e8a10d0b..de26e5ee0d2d 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos54xx SoC series common device tree source * @@ -8,10 +9,6 @@ * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific * Exynos 54xx SoCs should include this file and customize it further * (e.g. with clocks). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "exynos5.dtsi" @@ -29,7 +26,27 @@ }; soc: soc { - sysram@02020000 { + arm_a7_pmu: arm-a7-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + arm_a15_pmu: arm-a15-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, + <7 0>, + <16 6>, + <19 2>; + status = "disabled"; + }; + + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>; #address-cells = <1>; @@ -79,12 +96,6 @@ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; }; - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; - /* i2c_0-3 are defined in exynos5.dtsi */ hsi2c_4: i2c@12ca0000 { compatible = "samsung,exynos5250-hsi2c"; @@ -134,6 +145,7 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; }; }; @@ -154,6 +166,7 @@ reg = <0x12400000 0x10000>; phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; }; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index b2b95ff205e8..0029ec27819c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -664,6 +664,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + /* eMMC flash */ &mmc_0 { status = "okay"; diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 8613944ea5c5..a7adbdc2f0c0 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -18,6 +18,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + dbgu: serial@fffff200 { status = "okay"; }; @@ -50,7 +62,7 @@ reg = <0x0 0x7c0000>; }; - root@07c0000 { + root@7c0000 { label = "root"; reg = <0x7c0000 0x7840000>; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index e75e2d44371c..cadde92bc6b5 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -45,6 +45,47 @@ }; }; + vdisp: regulator { + compatible = "regulator-fixed"; + regulator-name = "display-power"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + /* Collides with LCD E */ + gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Collides with IDE pins, that's cool (we do not use them) */ + gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; + /* Collides with pflash CE1, not so cool */ + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + panel: display@0 { + compatible = "dlink,dir-685-panel", "ilitek,ili9322"; + reg = <0>; + /* 50 ns min period = 20 MHz */ + spi-max-frequency = <20000000>; + spi-cpol; /* Clock active low */ + vcc-supply = <&vdisp>; + iovcc-supply = <&vdisp>; + vci-supply = <&vdisp>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + leds { compatible = "gpio-leds"; led-wps { @@ -99,8 +140,8 @@ gpio-i2c { compatible = "i2c-gpio"; /* Collides with ICE */ - gpios = <&gpio0 5 0>, /* SDA */ - <&gpio0 6 0>; /* SCL */ + sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; @@ -115,7 +156,16 @@ soc { flash@30000000 { - status = "okay"; + /* + * Flash access is by default disabled, because it + * collides with the Chip Enable signal for the display + * panel, that reuse the parallel flash Chip Select 1 + * (CS1). Enabling flash makes graphics stop working. + * + * We might be able to hack around this by letting + * GPIO poke around in the flash controller registers. + */ + /* status = "okay"; */ /* 32MB of flash */ reg = <0x30000000 0x02000000>; @@ -242,5 +292,16 @@ ata@63000000 { status = "okay"; }; + + display-controller@6a000000 { + status = "okay"; + + port@0 { + reg = <0>; + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts new file mode 100644 index 000000000000..da8bb9d60f99 --- /dev/null +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "D-Link DNS-313 1-Bay Network Storage Enclosure"; + compatible = "dlink,dir-313", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + chosen { + stdout-path = "uart0:19200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button-esc { + debounce_interval = <50>; + wakeup-source; + linux,code = <KEY_ESC>; + label = "reset"; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-power { + label = "dns313:blue:power"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-disk-blue { + label = "dns313:blue:disk"; + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-disk-green { + label = "dns313:green:disk"; + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "ide-disk"; + /* Ideally should activate while reading */ + }; + led-disk-red { + label = "dns313:red:disk"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + /* Ideally should activate while writing */ + }; + }; + + /* + * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM. + */ + fan0: gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, + <&gpio0 12 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>; + cooling-min-level = <0>; + cooling-max-level = <2>; + #cooling-cells = <2>; + }; + + + /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ + gpio-i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + g751: temperature-sensor@48 { + compatible = "gmt,g751"; + reg = <0x48>; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + chassis-thermal { + /* Poll every 20 seconds */ + polling-delay = <20000>; + /* Poll every 2nd second when cooling */ + polling-delay-passive = <2000>; + + thermal-sensors = <&g751>; + + /* Tripping points from the fan.script in the rootfs */ + trips { + chassis_alert0: chassis-alert0 { + /* At 43 degrees turn on low speed */ + temperature = <43000>; + hysteresis = <3000>; + type = "active"; + }; + chassis_alert1: chassis-alert1 { + /* At 47 degrees turn on high speed */ + temperature = <47000>; + hysteresis = <3000>; + type = "active"; + }; + chassis_crit: chassis-crit { + /* Just shut down at 60 degrees */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&chassis_alert0>; + cooling-device = <&fan0 1 1>; + }; + map1 { + trip = <&chassis_alert1>; + cooling-device = <&fan0 2 2>; + }; + }; + }; + }; + + mdio0: ethernet-phy { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Realtek RTL8211B Gigabit ethernet transceiver */ + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + soc { + flash@30000000 { + status = "okay"; + /* 512KB of flash */ + reg = <0x30000000 0x00080000>; + + /* + * This "RedBoot" is the Storlink derivative. + */ + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "MTD1"; + reg = <0x00040000 0x00020000>; + read-only; + }; + partition@60000 { + label = "MTD2"; + reg = <0x00060000 0x00020000>; + read-only; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = + /* Used by LEDs conflicts ICE */ + "gpio0bgrp", + /* Used by ? conflicts ICE */ + "gpio0cgrp", + /* + * Used by fan & G751, conflicts LPC, + * UART modem lines, SSP + */ + "gpio0egrp", + /* Used by G751 */ + "gpio0fgrp", + /* Used by MDIO */ + "gpio0igrp"; + }; + }; + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + /* Used by "reset" button */ + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + /* + * In the vendor Linux tree, these values are set for the C3 + * version of the SL3512 ASIC with the comment "benson suggest" + */ + conf0 { + pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "T8 GMAC0 RXC"; + skew-delay = <10>; + }; + conf2 { + pins = "T11 GMAC1 RXC"; + skew-delay = <15>; + }; + conf3 { + pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf4 { + pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; + skew-delay = <10>; + }; + conf5 { + /* The data lines all have default skew */ + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + skew-delay = <7>; + }; + conf6 { + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; + skew-delay = <5>; + }; + /* Set up drive strength on GMAC0 to 16 mA */ + conf7 { + groups = "gmii_gmac0_grp"; + drive-strength = <16>; + }; + }; + }; + }; + + sata: sata@46000000 { + /* The ROM uses this muxmode */ + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + ata@63000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index d6a22e677c7a..8bbb6f85d161 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -64,6 +64,19 @@ }; }; + mdio0: ethernet-phy { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + soc { flash@30000000 { status = "okay"; @@ -116,6 +129,50 @@ groups = "gpio1dgrp"; }; }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + /* Settings come from OpenWRT */ + conf0 { + pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC"; + skew-delay = <15>; + }; + conf2 { + pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf3 { + pins = "V7 GMAC0 TXC"; + skew-delay = <11>; + }; + conf4 { + pins = "P10 GMAC1 TXC"; + skew-delay = <10>; + }; + conf5 { + /* The data lines all have default skew */ + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", + "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3", + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Set up drive strength on GMAC0 to 16 mA */ + conf6 { + groups = "gmii_gmac0_grp"; + drive-strength = <16>; + }; + }; }; }; @@ -130,6 +187,18 @@ pinctrl-0 = <&gpio1_default_pins>; }; + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + ata@63000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index 500057b6570e..15f20178642c 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -58,6 +58,19 @@ }; }; + mdio0: ethernet-phy { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + soc { flash@30000000 { status = "okay"; @@ -101,5 +114,17 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio1_default_pins>; }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index b413fd12c5ba..b4ec9ad85d72 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -69,6 +69,19 @@ }; }; + mdio0: ethernet-phy { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + soc { flash@30000000 { status = "okay"; @@ -125,5 +138,39 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio0_default_pins>; }; + + pci@50000000 { + status = "okay"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4800 0 0 2 &pci_intc 1>, + <0x4800 0 0 3 &pci_intc 2>, + <0x4800 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ + <0x5000 0 0 2 &pci_intc 2>, + <0x5000 0 0 3 &pci_intc 3>, + <0x5000 0 0 4 &pci_intc 0>, + <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ + <0x5800 0 0 2 &pci_intc 3>, + <0x5800 0 0 3 &pci_intc 0>, + <0x5800 0 0 4 &pci_intc 1>, + <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ + <0x6000 0 0 2 &pci_intc 0>, + <0x6000 0 0 3 &pci_intc 1>, + <0x6000 0 0 4 &pci_intc 2>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index 3ba710538662..6d25bcc046e7 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -69,6 +69,24 @@ }; }; + mdio0: ethernet-phy { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + + phy1: ethernet-phy@3 { + reg = <3>; + device_type = "ethernet-phy"; + }; + }; + soc { flash@30000000 { status = "okay"; @@ -118,6 +136,13 @@ "gpio0bgrp"; }; }; + pinctrl-gmii { + /* This platform use both the ethernet ports */ + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + }; }; }; @@ -125,5 +150,40 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio0_default_pins>; }; + + pci@50000000 { + status = "okay"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4800 0 0 2 &pci_intc 1>, + <0x4800 0 0 3 &pci_intc 2>, + <0x4800 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ + <0x5000 0 0 2 &pci_intc 2>, + <0x5000 0 0 3 &pci_intc 3>, + <0x5000 0 0 4 &pci_intc 0>, + <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ + <0x5800 0 0 2 &pci_intc 3>, + <0x5800 0 0 3 &pci_intc 0>, + <0x5800 0 0 4 &pci_intc 1>, + <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ + <0x6000 0 0 2 &pci_intc 0>, + <0x6000 0 0 3 &pci_intc 1>, + <0x6000 0 0 4 &pci_intc 2>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index b9b07d0895cf..0568baca500a 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -114,9 +114,16 @@ }; }; gmii_default_pins: pinctrl-gmii { + /* + * Only activate GMAC0 by default since + * GMAC1 will overlap with 8 GPIO lines + * gpio2a, gpio2b. Overlay groups with + * "gmii_gmac0_grp", "gmii_gmac1_grp" for + * both ethernet interfaces. + */ mux { function = "gmii"; - groups = "gmiigrp"; + groups = "gmii_gmac0_grp"; }; }; pci_default_pins: pinctrl-pci { @@ -142,6 +149,12 @@ groups = "idegrp"; }; }; + tvc_default_pins: pinctrl-tvc { + mux { + function = "tvc"; + groups = "tvcgrp"; + }; + }; }; }; @@ -310,6 +323,41 @@ }; }; + ethernet@60000000 { + compatible = "cortina,gemini-ethernet"; + reg = <0x60000000 0x4000>, /* Global registers, queue */ + <0x60004000 0x2000>, /* V-bit */ + <0x60006000 0x2000>; /* A-bit */ + pinctrl-names = "default"; + pinctrl-0 = <&gmii_default_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gmac0: ethernet-port@0 { + compatible = "cortina,gemini-ethernet-port"; + reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ + <0x6000a000 0x2000>; /* Port 0 GMAC */ + interrupt-parent = <&intcon>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GMAC0>; + clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; + clock-names = "PCLK"; + }; + + gmac1: ethernet-port@1 { + compatible = "cortina,gemini-ethernet-port"; + reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ + <0x6000e000 0x2000>; /* Port 1 GMAC */ + interrupt-parent = <&intcon>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GMAC1>; + clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; + clock-names = "PCLK"; + }; + }; + ata@63000000 { compatible = "cortina,gemini-pata", "faraday,ftide010"; reg = <0x63000000 0x1000>; @@ -348,5 +396,20 @@ memcpy-bus-width = <32>; #dma-cells = <2>; }; + + display-controller@6a000000 { + compatible = "cortina,gemini-tvc", "faraday,tve200"; + reg = <0x6a000000 0x1000>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_TVC>; + clocks = <&syscon GEMINI_CLK_GATE_TVC>, + <&syscon GEMINI_CLK_TVC>; + clock-names = "PCLK", "TVE"; + pinctrl-names = "default"; + pinctrl-0 = <&tvc_default_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 9d5fd5cfefa6..f7cf4f53e764 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -91,14 +91,14 @@ reboot-offset = <0x4>; }; - global_timer@0a000200 { + global_timer@a000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x0a000200 0x100>; interrupts = <1 11 0xf04>; clocks = <&hisi_refclk144mhz>; }; - local_timer@0a000600 { + local_timer@a000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x0a000600 0x100>; interrupts = <1 13 0xf04>; diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts index 40a9e33c2654..ca48641d0f48 100644 --- a/arch/arm/boot/dts/hip04-d01.dts +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -18,7 +18,7 @@ model = "Hisilicon D01 Development Board"; compatible = "hisilicon,hip04-d01"; - memory@00000000,10000000 { + memory@0,10000000 { device_type = "memory"; reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, <0x00000004 0xc0000000 0x00000003 0x40000000>; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 6c712a97e1fe..50d3f8426da1 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -39,7 +39,7 @@ compatible = "simple-bus"; ranges; - timer0: timer@00002000 { + timer0: timer@2000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00002000 0x1000>; /* timer00 & timer01 */ @@ -48,7 +48,7 @@ status = "disabled"; }; - timer1: timer@00a29000 { + timer1: timer@a29000 { /* * Only used in NORMAL state, not available ins * SLOW or DOZE state. @@ -62,7 +62,7 @@ status = "disabled"; }; - timer2: timer@00a2a000 { + timer2: timer@a2a000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a2a000 0x1000>; /* timer20 & timer21 */ @@ -71,7 +71,7 @@ status = "disabled"; }; - timer3: timer@00a2b000 { + timer3: timer@a2b000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a2b000 0x1000>; /* timer30 & timer31 */ @@ -80,7 +80,7 @@ status = "disabled"; }; - timer4: timer@00a81000 { + timer4: timer@a81000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a81000 0x1000>; /* timer30 & timer31 */ @@ -89,7 +89,7 @@ status = "disabled"; }; - uart0: uart@00b00000 { + uart0: uart@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b00000 0x1000>; interrupts = <0 49 4>; @@ -98,7 +98,7 @@ status = "disabled"; }; - uart1: uart@00006000 { + uart1: uart@6000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00006000 0x1000>; interrupts = <0 50 4>; @@ -107,7 +107,7 @@ status = "disabled"; }; - uart2: uart@00b02000 { + uart2: uart@b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b02000 0x1000>; interrupts = <0 51 4>; @@ -116,7 +116,7 @@ status = "disabled"; }; - uart3: uart@00b03000 { + uart3: uart@b03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b03000 0x1000>; interrupts = <0 52 4>; @@ -125,7 +125,7 @@ status = "disabled"; }; - uart4: uart@00b04000 { + uart4: uart@b04000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 53 4>; @@ -199,7 +199,7 @@ status = "disabled"; }; - gpio5: gpio@004000 { + gpio5: gpio@4000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x004000 0x1000>; interrupts = <0 113 0x4>; @@ -378,7 +378,7 @@ }; }; - local_timer@00a00600 { + local_timer@a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; @@ -392,7 +392,7 @@ cache-level = <2>; }; - sysctrl: system-controller@00000000 { + sysctrl: system-controller@0 { compatible = "hisilicon,sysctrl", "syscon"; reg = <0x00000000 0x1000>; }; @@ -404,7 +404,7 @@ mask = <0xdeadbeef>; }; - cpuctrl@00a22000 { + cpuctrl@a22000 { compatible = "hisilicon,cpuctrl"; #address-cells = <1>; #size-cells = <1>; @@ -489,7 +489,7 @@ clocks = <&clock HIX5HD2_SATA_CLK>; }; - ir: ir@001000 { + ir: ir@1000 { compatible = "hisilicon,hix5hd2-ir"; reg = <0x001000 0x1000>; interrupts = <0 47 4>; diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index 38d712be5685..20f6565c337d 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -40,7 +40,7 @@ spi1 = &cspi2; }; - aitc: aitc-interrupt-controller@00223000 { + aitc: aitc-interrupt-controller@223000 { compatible = "fsl,imx1-aitc", "fsl,avic"; interrupt-controller; #interrupt-cells = <1>; @@ -69,14 +69,14 @@ interrupt-parent = <&aitc>; ranges; - aipi@00200000 { + aipi@200000 { compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x00200000 0x10000>; ranges; - gpt1: timer@00202000 { + gpt1: timer@202000 { compatible = "fsl,imx1-gpt"; reg = <0x00202000 0x1000>; interrupts = <59>; @@ -85,7 +85,7 @@ clock-names = "ipg", "per"; }; - gpt2: timer@00203000 { + gpt2: timer@203000 { compatible = "fsl,imx1-gpt"; reg = <0x00203000 0x1000>; interrupts = <58>; @@ -94,7 +94,7 @@ clock-names = "ipg", "per"; }; - fb: fb@00205000 { + fb: fb@205000 { compatible = "fsl,imx1-fb"; reg = <0x00205000 0x1000>; interrupts = <14>; @@ -105,7 +105,7 @@ status = "disabled"; }; - uart1: serial@00206000 { + uart1: serial@206000 { compatible = "fsl,imx1-uart"; reg = <0x00206000 0x1000>; interrupts = <30 29 26>; @@ -115,7 +115,7 @@ status = "disabled"; }; - uart2: serial@00207000 { + uart2: serial@207000 { compatible = "fsl,imx1-uart"; reg = <0x00207000 0x1000>; interrupts = <24 23 20>; @@ -125,7 +125,7 @@ status = "disabled"; }; - pwm: pwm@00208000 { + pwm: pwm@208000 { #pwm-cells = <2>; compatible = "fsl,imx1-pwm"; reg = <0x00208000 0x1000>; @@ -135,7 +135,7 @@ clock-names = "ipg", "per"; }; - dma: dma@00209000 { + dma: dma@209000 { compatible = "fsl,imx1-dma"; reg = <0x00209000 0x1000>; interrupts = <61 60>; @@ -145,7 +145,7 @@ #dma-cells = <1>; }; - uart3: serial@0020a000 { + uart3: serial@20a000 { compatible = "fsl,imx1-uart"; reg = <0x0020a000 0x1000>; interrupts = <54 4 1>; @@ -156,14 +156,14 @@ }; }; - aipi@00210000 { + aipi@210000 { compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x00210000 0x10000>; ranges; - cspi1: cspi@00213000 { + cspi1: cspi@213000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx1-cspi"; @@ -175,7 +175,7 @@ status = "disabled"; }; - i2c: i2c@00217000 { + i2c: i2c@217000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx1-i2c"; @@ -185,7 +185,7 @@ status = "disabled"; }; - cspi2: cspi@00219000 { + cspi2: cspi@219000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx1-cspi"; @@ -197,20 +197,20 @@ status = "disabled"; }; - clks: ccm@0021b000 { + clks: ccm@21b000 { compatible = "fsl,imx1-ccm"; reg = <0x0021b000 0x1000>; #clock-cells = <1>; }; - iomuxc: iomuxc@0021c000 { + iomuxc: iomuxc@21c000 { compatible = "fsl,imx1-iomuxc"; reg = <0x0021c000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; - gpio1: gpio@0021c000 { + gpio1: gpio@21c000 { compatible = "fsl,imx1-gpio"; reg = <0x0021c000 0x100>; interrupts = <11>; @@ -220,7 +220,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio@0021c100 { + gpio2: gpio@21c100 { compatible = "fsl,imx1-gpio"; reg = <0x0021c100 0x100>; interrupts = <12>; @@ -230,7 +230,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio@0021c200 { + gpio3: gpio@21c200 { compatible = "fsl,imx1-gpio"; reg = <0x0021c200 0x100>; interrupts = <13>; @@ -240,7 +240,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio@0021c300 { + gpio4: gpio@21c300 { compatible = "fsl,imx1-gpio"; reg = <0x0021c300 0x100>; interrupts = <62>; @@ -252,7 +252,7 @@ }; }; - weim: weim@00220000 { + weim: weim@220000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx1-weim"; @@ -269,7 +269,7 @@ status = "disabled"; }; - esram: esram@00300000 { + esram: esram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x20000>; }; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index db39bd6b8e00..0f053721d80f 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -64,7 +64,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 20>; + cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index c52692821fb1..2d15ce72d006 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -135,7 +135,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks 129>; @@ -295,6 +295,14 @@ status = "okay"; }; +&tsc { + status = "okay"; +}; + +&tscadc { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 09ce8b81fafa..9445f8e1473c 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -122,7 +122,7 @@ }; can1: can@43f88000 { - compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx25-flexcan"; reg = <0x43f88000 0x4000>; interrupts = <43>; clocks = <&clks 75>, <&clks 75>; @@ -131,7 +131,7 @@ }; can2: can@43f8c000 { - compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx25-flexcan"; reg = <0x43f8c000 0x4000>; interrupts = <44>; clocks = <&clks 76>, <&clks 76>; @@ -628,11 +628,13 @@ usbphy0: usb-phy@0 { reg = <0>; compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; usbphy1: usb-phy@1 { reg = <1>; compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 96f442ba6d22..2a140c8ae6d2 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -30,6 +30,7 @@ reg = <0>; clocks = <&clks IMX27_CLK_DUMMY>; clock-names = "main_clk"; + #phy-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 2a9198f99a8d..2ed2d73b087e 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -63,6 +63,7 @@ vcc-supply = <®_5v0>; clocks = <&clks IMX27_CLK_DUMMY>; clock-names = "main_clk"; + #phy-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index c973c5d91875..c9095b7654c6 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -53,6 +53,7 @@ vcc-supply = <&sw3_reg>; clocks = <&clks IMX27_CLK_DUMMY>; clock-names = "main_clk"; + #phy-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index d2a91976e67f..ae078341fb60 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -143,7 +143,7 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi index 581e85f4fd4c..49ab40838e69 100644 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi @@ -148,7 +148,7 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 5309bb90d7d5..7f5b80402c54 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -194,7 +194,7 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index dbfb8aab505f..22aa025cab1e 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -137,7 +137,7 @@ }; i2c0: i2c@80058000 { - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts new file mode 100644 index 000000000000..1e391c9f1b7a --- /dev/null +++ b/arch/arm/boot/dts/imx28-ts4600.dts @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2016 Savoir-Faire Linux + * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx28.dtsi" +#include "dt-bindings/gpio/gpio.h" + +/ { + + model = "Technologic Systems i.MX28 TS-4600"; + compatible = "technologic,imx28-ts4600", "fsl,imx28"; + + memory { + reg = <0x40000000 0x10000000>; /* 256MB */ + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_sck_cfg + &en_sd_pwr>; + broken-cd = <1>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + pinctrl@80018000 { + + en_sd_pwr: en-sd-pwr@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + }; + }; + + apbx@80040000 { + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; + }; + +}; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 0ebbc83852d0..152621ea37db 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -1,13 +1,43 @@ /* * Copyright 2012 Shawn Guo <shawn.guo@linaro.org> - * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -45,82 +75,69 @@ status = "disabled"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_2p5v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_3p3v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_can_xcvr: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_flexcan_xcvr_pins>; - }; + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_flexcan_xcvr_pins>; + }; - reg_lcd: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_lcd: regulator-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_lcd_reset: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - startup-delay-us = <300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; + reg_lcd_reset: regulator-lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; }; clocks { @@ -298,7 +315,7 @@ clock-frequency = <400000>; status = "okay"; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_2p5v>; @@ -312,7 +329,7 @@ pinctrl-names = "default"; pinctrl-0 = <&tx28_pca9554_pins>; interrupt-parent = <&gpio3>; - interrupts = <28 0>; + interrupts = <28 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -336,7 +353,7 @@ pinctrl-names = "default"; pinctrl-0 = <&tx28_tsc2007_pins>; interrupt-parent = <&gpio3>; - interrupts = <20 0>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = /bits/ 16 <660>; }; @@ -344,6 +361,8 @@ ds1339: rtc@68 { compatible = "mxim,ds1339"; reg = <0x68>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 2f4ebe0318d3..e52e05c0fe56 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -1038,7 +1038,7 @@ }; can0: can@80032000 { - compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx28-flexcan"; reg = <0x80032000 0x2000>; interrupts = <8>; clocks = <&clks 58>, <&clks 58>; @@ -1047,7 +1047,7 @@ }; can1: can@80034000 { - compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx28-flexcan"; reg = <0x80034000 0x2000>; interrupts = <9>; clocks = <&clks 59>, <&clks 59>; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index e9357131b026..ae98d6759074 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -65,7 +65,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 24>; + cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 6d5e6a60bee7..e08c0c193767 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -303,7 +303,7 @@ }; can1: can@53fe4000 { - compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx35-flexcan"; reg = <0x53fe4000 0x1000>; clocks = <&clks 33>, <&clks 33>; clock-names = "ipg", "per"; @@ -312,7 +312,7 @@ }; can2: can@53fe8000 { - compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx35-flexcan"; reg = <0x53fe8000 0x1000>; clocks = <&clks 34>, <&clks 34>; clock-names = "ipg", "per"; @@ -402,11 +402,13 @@ usbphy0: usb-phy@0 { reg = <0>; compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; usbphy1: usb-phy@1 { reg = <1>; compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 3747d80104f4..35955e63d6c5 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -52,7 +52,7 @@ }; }; - tzic: tz-interrupt-controller@0fffc000 { + tzic: tz-interrupt-controller@fffc000 { compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; @@ -443,6 +443,7 @@ clocks = <&clks IMX5_CLK_SDMA_GATE>, <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; + #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; }; diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index a5e6091c8729..3e1846a64d93 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -16,7 +16,7 @@ model = "Armadeus Systems APF51Dev docking/development board"; compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; - backlight@bl1{ + backlight { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; compatible = "gpio-backlight"; @@ -24,7 +24,7 @@ default-on; }; - display@di1 { + disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; @@ -51,7 +51,7 @@ port { display_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; + remote-endpoint = <&ipu_di0_disp1>; }; }; }; @@ -120,7 +120,7 @@ pinctrl-0 = <&pinctrl_hog>; imx51-apf51dev { - pinctrl_backlight: bl1grp { + pinctrl_backlight: backlightgrp { fsl,pins = < MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 >; @@ -218,6 +218,6 @@ }; }; -&ipu_di0_disp0 { +&ipu_di0_disp1 { remote-endpoint = <&display_in>; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 873cf242679c..4ac5ab614a7f 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -25,21 +25,44 @@ reg = <0x90000000 0x20000000>; }; - clocks { - ckih1 { - clock-frequency = <22579200>; - }; + ckih1 { + clock-frequency = <22579200>; + }; - clk_26M: codec_clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; + clk_osc: clk-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; }; - display0: display@di0 { + clk_osc_gate: clk-osc-gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz_osc>; + clocks = <&clk_osc>; + #clock-cells = <0>; + enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + clk_audio: clk-audio { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz_audio>; + clocks = <&clk_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; + + clk_usb: clk-usb { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz_usb>; + clocks = <&clk_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + display1: disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; @@ -61,12 +84,12 @@ port { display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; + remote-endpoint = <&ipu_di0_disp1>; }; }; }; - display1: display@di1 { + display2: disp2 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb565"; pinctrl-names = "default"; @@ -93,7 +116,7 @@ port { display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; + remote-endpoint = <&ipu_di1_disp2>; }; }; }; @@ -162,9 +185,11 @@ usbh1phy: usbh1phy@0 { compatible = "usb-nop-xceiv"; reg = <0>; - clocks = <&clks IMX5_CLK_DUMMY>; + clocks = <&clk_usb>; clock-names = "main_clk"; reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; }; }; }; @@ -240,6 +265,10 @@ regulator-max-microvolt = <3150000>; }; + vusb_reg: vusb { + regulator-boot-on; + }; + vusb2_reg: vusb2 { regulator-min-microvolt = <2400000>; regulator-max-microvolt = <2775000>; @@ -337,22 +366,20 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clkcodec>; reg = <0x0a>; - clocks = <&clk_26M>; + clocks = <&clk_audio>; VDDA-supply = <&vdig_reg>; VDDIO-supply = <&vvideo_reg>; }; }; -&ipu_di0_disp0 { +&ipu_di0_disp1 { remote-endpoint = <&display0_in>; }; -&ipu_di1_disp1 { +&ipu_di1_disp2 { remote-endpoint = <&display1_in>; }; @@ -413,6 +440,10 @@ status = "okay"; }; +&usbphy0 { + vcc-supply = <&vusb_reg>; +}; + &usbotg { dr_mode = "otg"; disable-over-current; @@ -431,9 +462,21 @@ >; }; - pinctrl_clkcodec: clkcodecgrp { + pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { + fsl,pins = < + MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 + >; + }; + + pinctrl_clk26mhz_osc: clk26mhzoscgrp { + fsl,pins = < + MX51_PAD_DI1_PIN12__GPIO3_1 0x85 + >; + }; + + pinctrl_clk26mhz_usb: clk26mhzusbgrp { fsl,pins = < - MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 + MX51_PAD_EIM_D17__GPIO2_1 0x85 >; }; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 1305b05c7ed9..b3d952f37cdc 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -94,6 +94,7 @@ clocks = <&clks IMX5_CLK_USB_PHY_GATE>; clock-names = "main_clk"; clock-frequency = <19200000>; + #phy-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index ca1cc5eca80f..f59b02bae68d 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -50,7 +50,7 @@ power-supply = <&backlight_reg>; }; - display0: display@di0 { + display1: disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; @@ -71,9 +71,9 @@ }; }; - port@0 { + port { display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; + remote-endpoint = <&ipu_di0_disp1>; }; }; }; @@ -107,7 +107,7 @@ }; }; -&ipu_di0_disp0 { +&ipu_di0_disp1 { remote-endpoint = <&display0_in>; }; @@ -149,18 +149,18 @@ #size-cells = <1>; ranges = <0 0 0 0x1d000>; - syscon: syscon@b0010000 { + syscon: syscon@10000 { compatible = "syscon", "simple-mfd"; reg = <0x10000 0x3d>; reg-io-width = <2>; - wdt@e { + wdt { compatible = "technologic,ts4800-wdt"; syscon = <&syscon 0xe>; }; }; - touchscreen { + touchscreen@12000 { compatible = "technologic,ts4800-ts"; reg = <0x12000 0x1000>; syscon = <&syscon 0x10 6>; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts new file mode 100644 index 000000000000..5306b78de0ca --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -0,0 +1,836 @@ +/* + * Copyright (C) 2017 Zodiac Inflight Innovations + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx51.dtsi" +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "ZII RDU1 Board"; + compatible = "zii,imx51-rdu1", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + aliases { + mdio-gpio0 = &mdio_gpio; + rtc0 = &ds1341; + }; + + clk_26M_osc: 26M_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_26M_osc_gate: 26M_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz>; + clocks = <&clk_26M_osc>; + #clock-cells = <0>; + enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + clk_26M_usb: usbhost_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbgate26mhz>; + clocks = <&clk_26M_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + }; + + clk_26M_snd: snd_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sndgate26mhz>; + clocks = <&clk_26M_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + disp0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu_di0_disp1>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + /* no compatible here, bootloader will patch in correct one */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + power-supply = <®_3p3v>; + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + i2c_gpio: i2c-gpio { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swi2c>; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <50>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clk_26M_snd>; + VDDA-supply = <&vdig_reg>; + VDDIO-supply = <&vvideo_reg>; + #sound-dai-cells = <0>; + }; + }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiospi0>; + status = "okay"; + + gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + + eeprom@0 { + compatible = "eeprom-93xx46"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cs-high; + data-size = <8>; + }; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swmdio>; + gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */ + + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "netaux"; + }; + + port@3 { + reg = <3>; + label = "netright"; + }; + + port@4 { + reg = <4>; + label = "netleft"; + }; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Front"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT"; + simple-audio-card,aux-devs = <&hpa1>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk_26M_snd>; + }; + }; + + usbh1phy: usbphy1 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1phy>; + clocks = <&clk_26M_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; + }; + + usbh2phy: usbphy2 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2phy>; + clocks = <&clk_26M_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCSEL(2) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled0@3 { + reg = <3>; + label = "system:green:status"; + linux,default-trigger = "default-on"; + }; + + sysled1@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-supply = <&vgen3_reg>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + + hpa1: amp@60 { + compatible = "ti,tpa6130a2"; + reg = <0x60>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ampgpio>; + power-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_3p3v>; + }; + + ds1341: rtc@68 { + compatible = "maxim,ds1341"; + reg = <0x68>; + }; + + /* touch nodes default disabled, bootloader will enable the right one */ + + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + touchscreen@4c { + compatible = "atmel,maxtouch"; + reg = <0x4c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + touchscreen@20 { + compatible = "syna,rmi4_i2c"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <2>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touch-inverted-y; + touch-swapped-x-y; + syna,sensor-type = <1>; + }; + }; + +}; + +&ipu_di0_disp1 { + remote-endpoint = <&display_in>; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + dr_mode = "host"; + phy_type = "ulpi"; + fsl,usbphy = <&usbh1phy>; + disable-over-current; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + dr_mode = "host"; + phy_type = "ulpi"; + fsl,usbphy = <&usbh2phy>; + disable-over-current; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb_reg>; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&iomuxc { + pinctrl_ampgpio: ampgpiogrp { + fsl,pins = < + MX51_PAD_GPIO1_9__GPIO1_9 0x5e + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85 + >; + }; + + pinctrl_clk26mhz: clk26mhzgrp { + fsl,pins = < + MX51_PAD_DI1_PIN12__GPIO3_1 0x85 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x180 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x180 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x180 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x180 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084 + MX51_PAD_EIM_CS5__FEC_CRS 0x180 + MX51_PAD_NANDF_RB2__FEC_COL 0x2180 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 + MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_EIM_A20__GPIO2_14 0x85 + >; + }; + + pinctrl_gpiospi0: gpiospi0grp { + fsl,pins = < + MX51_PAD_CSI2_D18__GPIO4_11 0x85 + MX51_PAD_CSI2_D19__GPIO4_12 0x85 + MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85 + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX51_PAD_DI1_D0_CS__GPIO3_3 0x85 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x1e0 + MX51_PAD_GPIO1_8__GPIO1_8 0x21e2 + >; + }; + + pinctrl_sndgate26mhz: sndgate26mhzgrp { + fsl,pins = < + MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 + >; + }; + + pinctrl_swi2c: swi2cgrp { + fsl,pins = < + MX51_PAD_GPIO1_2__GPIO1_2 0xc5 + MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5 + >; + }; + + pinctrl_swmdio: swmdiogrp { + fsl,pins = < + MX51_PAD_NANDF_D14__GPIO3_26 0x21e6 + MX51_PAD_NANDF_D15__GPIO3_25 0x21e6 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX51_PAD_CSI1_D8__GPIO3_12 0x85 + MX51_PAD_CSI1_D9__GPIO3_13 0x85 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c4 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0xc5 + MX51_PAD_UART2_TXD__UART2_TXD 0xc5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usbgate26mhz: usbgate26mhzgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT6__GPIO1_19 0x85 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_STP__USBH1_STP 0x0 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x0 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x0 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x0 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0 + >; + }; + + pinctrl_usbh1phy: usbh1phygrp { + fsl,pins = < + MX51_PAD_NANDF_D0__GPIO4_8 0x85 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX51_PAD_EIM_A26__USBH2_STP 0x0 + MX51_PAD_EIM_A24__USBH2_CLK 0x0 + MX51_PAD_EIM_A25__USBH2_DIR 0x0 + MX51_PAD_EIM_A27__USBH2_NXT 0x0 + MX51_PAD_EIM_D16__USBH2_DATA0 0x0 + MX51_PAD_EIM_D17__USBH2_DATA1 0x0 + MX51_PAD_EIM_D18__USBH2_DATA2 0x0 + MX51_PAD_EIM_D19__USBH2_DATA3 0x0 + MX51_PAD_EIM_D20__USBH2_DATA4 0x0 + MX51_PAD_EIM_D21__USBH2_DATA5 0x0 + MX51_PAD_EIM_D22__USBH2_DATA6 0x0 + MX51_PAD_EIM_D23__USBH2_DATA7 0x0 + >; + }; + + pinctrl_usbh2phy: usbh2phygrp { + fsl,pins = < + MX51_PAD_NANDF_D1__GPIO4_7 0x85 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 1ee1d542d9ad..00d30bd70068 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -113,6 +113,7 @@ reg = <0>; clocks = <&clks IMX5_CLK_USB_PHY_GATE>; clock-names = "main_clk"; + #phy-cells = <0>; }; }; @@ -148,14 +149,14 @@ ipu_di0: port@2 { reg = <2>; - ipu_di0_disp0: endpoint { + ipu_di0_disp1: endpoint { }; }; ipu_di1: port@3 { reg = <3>; - ipu_di1_disp1: endpoint { + ipu_di1_disp2: endpoint { }; }; }; diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts index 4f54fd4418a3..5e67e43004e7 100644 --- a/arch/arm/boot/dts/imx53-cx9020.dts +++ b/arch/arm/boot/dts/imx53-cx9020.dts @@ -152,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi index ec390aa562c3..7ce69c63510c 100644 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -64,7 +64,6 @@ stmpe_touchscreen { compatible = "st,stmpe-ts"; - reg = <0>; st,sample-time = <4>; st,mod-12b = <1>; st,ref-sel = <0>; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index 4347a321c782..e48525763b1b 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -16,7 +16,7 @@ model = "Aries/DENX M53EVK"; compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; - display1: display@di1 { + display1: disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; @@ -150,7 +150,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p2v>; @@ -183,7 +183,7 @@ >; }; - led_pin_gpio: led_gpio@0 { + led_pin_gpio: led_gpio { fsl,pins = < MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index df705ba48897..296dd74fc246 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@ -30,7 +30,7 @@ power-supply = <®_backlight>; }; - disp1: display@disp1 { + disp1: disp1 { compatible = "fsl,imx-parallel-display"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp1_1>; diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts new file mode 100644 index 000000000000..cce959438a79 --- /dev/null +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -0,0 +1,1042 @@ +/* + * Copyright 2014 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx53.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "General Electric CS ONE"; + compatible = "ge,imx53-cpuvo", "fsl,imx53"; + + aliases { + spi0 = &cspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + }; + + chosen { + stdout-path = "&uart1:115200n8"; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + cko2_11M: sgtl-clock-cko2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + sgtlsound: sound { + compatible = "fsl,imx53-cpuvo-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-cpuvo-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <6>; + }; + + reg_sgtl5k: regulator-sgtl5k { + compatible = "regulator-fixed"; + regulator-name = "regulator-sgtl5k"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-0 = <&pinctrl_usb_otg_vbus>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usbh2_vbus: regulator-usbh2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbh3_vbus: regulator-usbh3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh3_vbus>; + gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pwm_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 + 38 40 43 45 48 51 53 56 58 61 63 66 68 71 + 73 76 79 81 84 86 89 91 94 96 99 102 104 + 107 109 112 114 117 119 122 124 127 130 + 132 135 137 140 142 145 147 150 153 155 + 158 160 163 165 168 170 173 175 178 181 + 183 186 188 191 193 196 198 201 204 206 + 209 211 214 216 219 221 224 226 229 232 + 234 237 239 242 244 247 249 252 255>; + default-brightness-level = <0>; + enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "pwm-leds"; + + alarm-brightness { + pwms = <&pwm1 0 100000>; + max-brightness = <255>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + active-delay = <100>; + inactive-delay = <10>; + wait-delay = <100>; + }; + + power-gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + power-button { + label = "Power button"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; + }; + }; + + touch-lock-key { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + touch-lock-button { + label = "Touch lock button"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F12>; + }; + }; + + usbphy2: usbphy2 { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; + clock-names = "main_clk"; + clock-frequency = <24000000>; + clocks = <&clks IMX5_CLK_CKO2>; + assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; + assigned-clock-parents = <&clks IMX5_CLK_OSC>; + }; + + usbphy3: usbphy3 { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + clock-names = "main_clk"; + + clock-frequency = <24000000>; + clocks = <&clks IMX5_CLK_CKO2>; + assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; + assigned-clock-parents = <&clks IMX5_CLK_OSC>; + }; + + panel-lvds0 { + compatible = "nvd,9128"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&cpu0 { + /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ + operating-points = < + /* kHz uV */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + >; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW + &gpio4 11 GPIO_ACTIVE_LOW + &gpio4 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + compatible = "ge,achc"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + spidev1: spi@1 { + compatible = "ge,achc"; + reg = <1>; + spi-max-frequency = <1000000>; + }; + + gpioxra0: gpio@2 { + compatible = "exar,xra1403"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + }; + + gpioxra1: gpio@3 { + compatible = "exar,xra1403"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-chipselects = <1>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + status = "okay"; + + da9053@0 { + compatible = "dlg,da9053-aa"; + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <12 0x8>; + spi-max-frequency = <1000000>; + + regulators { + buck1_reg: buck1 { + regulator-name = "BUCKCORE"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "BUCKPRO"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "BUCKMEM"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-name = "BUCKPERI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1_1v3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2_1v3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3_3v3"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4_2v775"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5_3v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6_1v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7_2v75"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8_1v8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9_1v5"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3650000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-name = "ldo10_1v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + }; + }; + +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + bus-width = <8>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; + + i2c4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + VDDA-supply = <®_sgtl5k>; + VDDIO-supply = <®_sgtl5k>; + clocks = <&cko2_11M>; + status = "okay"; + }; + }; + + i2c5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + temp@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + + mma8453q: accelerometer@1c { + compatible = "fsl,mma8453"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupts = <6 0>; + interrupt-names = "INT1"; + }; + + mpl3115: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; + }; + + i2c6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c8: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c9: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c10: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c11: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio5>; + interrupts = <4 0x8>; + }; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + phy_type = "utmi"; + vbus-supply = <®_usb_otg_vbus>; + pinctrl-0 = <&pinctrl_usb_otg>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + phy_type = "ulpi"; + dr_mode = "host"; + fsl,usbphy = <&usbphy2>; + vbus-supply = <®_usbh2_vbus>; + status = "okay"; +}; + +&usbh3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh3>; + phy_type = "ulpi"; + dr_mode = "host"; + vbus-supply = <®_usbh3_vbus>; + fsl,usbphy = <&usbphy3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_rev6>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x400 + MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x400 + MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x400 + MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x400 + MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x400 + MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x400 + MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x400 + MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x400 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x400 + MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x400 + MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x400 + /* ECSPI1_SS0, must treat as GPIO for EzPort */ + MX53_PAD_DISP0_DAT23__GPIO5_17 0x400 + MX53_PAD_KEY_COL2__GPIO4_10 0x0 + MX53_PAD_KEY_ROW2__GPIO4_11 0x0 + MX53_PAD_KEY_COL3__GPIO4_12 0x0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x0 + MX53_PAD_EIM_OE__ECSPI2_MISO 0x0 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x0 + MX53_PAD_EIM_RW__GPIO2_26 0x0 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x0 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x0 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x0 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x0 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x0 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x0 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x0 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x0 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x0 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x0 + >; + }; + + pinctrl_hog_rev6: hoggrp { + fsl,pins = < + /* CKO2 */ + MX53_PAD_GPIO_3__CCM_CLKO2 0x4 + /* DEFIB_SYNC_MARKER_IN_IRQ */ + MX53_PAD_GPIO_5__GPIO1_5 0x0 + /* ACCELEROMETER_DATA_RDY_N */ + MX53_PAD_GPIO_6__GPIO1_6 0x0 + /* TEMPERATURE_ALERT_N */ + MX53_PAD_GPIO_7__GPIO1_7 0x0 + /* BAROMETRIC_PRESSURE_DATA_RDY_N */ + MX53_PAD_GPIO_8__GPIO1_8 0x0 + /* DOCKING_I2C_INTERFACE_IRQ_N */ + MX53_PAD_PATA_DATA4__GPIO2_4 0x0 + /* PWR_OUT_TO_DOCK_FAULT_N */ + MX53_PAD_PATA_DATA5__GPIO2_5 0x0 + /* ENABLE_PWR_TO_DOCK_N */ + MX53_PAD_PATA_DATA6__GPIO2_6 0x0 + /* HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ + MX53_PAD_PATA_DATA7__GPIO2_7 0x0 + /* REMOTE_ON_REQUEST_FROM_DOCKING_CONNECTOR_IS_ACTIVE_N */ + MX53_PAD_PATA_DATA12__GPIO2_12 0x0 + /* DOCK_PRESENT_N */ + MX53_PAD_PATA_DATA13__GPIO2_13 0x0 + /* ECG_MARKER_IN_FROM_DOCKING_CONNECTOR_IRQ */ + MX53_PAD_PATA_DATA14__GPIO2_14 0x0 + /* ENABLE_ECG_MARKER_INTERFACE_TO_DOCKING_CONNECTOR */ + MX53_PAD_PATA_DATA15__GPIO2_15 0x0 + /* RESET_IMX535_ETHERNET_PHY_N */ + MX53_PAD_EIM_A22__GPIO2_16 0x0 + /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ + MX53_PAD_EIM_A21__GPIO2_17 0x0 + /* RESET_I2C1_BUS_SEGMENT_MUX_N */ + MX53_PAD_EIM_A20__GPIO2_18 0x0 + /* RESET_IMX535_USB_HOST3_PHY_N */ + MX53_PAD_EIM_A19__GPIO2_19 0x0 + /* ESDHC3_EMMC_NAND_RST_N */ + MX53_PAD_EIM_A18__GPIO2_20 0x0 + /* LCD_AND_UI_INTERFACE_PWR_FAULT_N */ + MX53_PAD_EIM_A17__GPIO2_21 0x0 + /* POWER_DOWN_LVDS0_DESERIALIZER_N */ + MX53_PAD_EIM_A16__GPIO2_22 0x0 + /* POWER_DOWN_LVDS1_DESERIALIZER_N */ + MX53_PAD_EIM_LBA__GPIO2_27 0x0 + /* RESET_DP0_TRANSMITTER_N */ + MX53_PAD_EIM_EB0__GPIO2_28 0x0 + /* RESET_DP1_TRANSMITTER_N */ + MX53_PAD_EIM_EB1__GPIO2_29 0x0 + /* ENABLE_SPDIF_AUDIO_TO_DP0 */ + MX53_PAD_EIM_DA0__GPIO3_0 0x0 + /* ENABLE_SPDIF_AUDIO_TO_DP1 */ + MX53_PAD_EIM_DA1__GPIO3_1 0x0 + /* LVDS1_MUX_CTRL */ + MX53_PAD_EIM_DA2__GPIO3_2 0x0 + /* LVDS0_MUX_CTRL */ + MX53_PAD_EIM_DA3__GPIO3_3 0x0 + /* DP1_TRANSMITTER_IRQ */ + MX53_PAD_EIM_DA4__GPIO3_4 0x0 + /* DP0_TRANSMITTER_IRQ */ + MX53_PAD_EIM_DA5__GPIO3_5 0x0 + /* USB_RESET_N */ + MX53_PAD_EIM_DA6__GPIO3_6 0x0 + /* ENABLE_BATTERY_CHARGER */ + MX53_PAD_EIM_DA7__GPIO3_7 0x0 + /* SOFTWARE_CONTROLLED_PWR_CYCLE */ + MX53_PAD_EIM_DA8__GPIO3_8 0x0 + /* SOFTWARE_CONTROLLED_POWERDOWN */ + MX53_PAD_EIM_DA9__GPIO3_9 0x0 + /* DC_PWR_IN_OK */ + MX53_PAD_EIM_DA10__GPIO3_10 0x0 + /* BATT_PRESENT_N */ + MX53_PAD_EIM_DA11__GPIO3_11 0xe4 + /* PMIC_IRQ_N */ + MX53_PAD_EIM_DA12__GPIO3_12 0x0 + /* PMIC_VDD_FAULT_STATUS_N */ + MX53_PAD_EIM_DA13__GPIO3_13 0x0 + /* IMX535_ETHERNET_PHY_STATUS_IRQ_N */ + MX53_PAD_EIM_DA14__GPIO3_14 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_DA15__GPIO3_15 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_D22__GPIO3_22 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_D24__GPIO3_24 0x0 + /* NBP_PUMP_VALVE_PWR_ENABLE */ + MX53_PAD_EIM_D25__GPIO3_25 0x0 + /* NIBP_RESET_N */ + MX53_PAD_EIM_D26__GPIO3_26 0x0 + /* LATCHED_OVERPRESSURE_N */ + MX53_PAD_EIM_D27__GPIO3_27 0x0 + /* NBP_SBWTCLK */ + MX53_PAD_EIM_D29__GPIO3_29 0x0 + /* ENABLE_WIFI_MODULE */ + MX53_PAD_GPIO_11__GPIO4_1 0x400 + /* WIFI_MODULE_IRQ_N */ + MX53_PAD_GPIO_12__GPIO4_2 0x400 + /* ENABLE_BLUETOOTH_MODULE */ + MX53_PAD_GPIO_13__GPIO4_3 0x400 + /* RESET_IMX535_USB_HOST2_PHY_N */ + MX53_PAD_GPIO_14__GPIO4_4 0x400 + /* ONKEY_IS_DEPRESSED */ + MX53_PAD_KEY_ROW3__GPIO4_13 0x0 + /* UNUSED_GPIO_TO_ALARM_LIGHT_BOARD */ + MX53_PAD_EIM_WAIT__GPIO5_0 0x0 + /* DISPLAY_LOCK_BUTTON_IS_DEPRESSED_N */ + MX53_PAD_EIM_A25__GPIO5_2 0x0 + /* I2C_PCAP_TOUCHSCREEN_IRQ_N */ + MX53_PAD_EIM_A24__GPIO5_4 0x0 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT13__GPIO5_7 0x400 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT14__GPIO5_8 0x400 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT15__GPIO5_9 0x400 + /* HOST_CONTROLLED_RESET_TO_LCD_N */ + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0 + /* HOST_CONTROLLED_RESET_TO_PCAP_N */ + MX53_PAD_CSI0_MCLK__GPIO5_19 0x0 + /* LR_SCAN_CTRL */ + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0 + /* UD_SCAN_CTRL */ + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0 + /* DATA_WIDTH_CTRL */ + MX53_PAD_CSI0_DAT10__GPIO5_28 0x0 + /* BACKLIGHT_ENABLE */ + MX53_PAD_CSI0_DAT11__GPIO5_29 0x0 + /* MED_USB_PORT_1_HOST_SELECT */ + MX53_PAD_EIM_A23__GPIO6_6 0x0 + /* MED_USB_PORT_2_HOST_SELECT */ + MX53_PAD_NANDF_CLE__GPIO6_7 0x0 + /* MED_USB_PORT_3_HOST_SELECT */ + MX53_PAD_NANDF_ALE__GPIO6_8 0x0 + /* MED_USB_PORT_4_HOST_SELECT */ + MX53_PAD_NANDF_WP_B__GPIO6_9 0x0 + /* MED_USB_PORT_5_HOST_SELECT */ + MX53_PAD_NANDF_RB0__GPIO6_10 0x0 + /* MED_USB_PORT_6_HOST_SELECT */ + MX53_PAD_NANDF_CS0__GPIO6_11 0x0 + /* MED_USB_PORT_7_HOST_SELECT */ + MX53_PAD_NANDF_WE_B__GPIO6_12 0x0 + /* MED_USB_PORT_8_HOST_SELECT */ + MX53_PAD_NANDF_RE_B__GPIO6_13 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_0 */ + MX53_PAD_NANDF_CS1__GPIO6_14 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_1 */ + MX53_PAD_NANDF_CS2__GPIO6_15 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_2 */ + MX53_PAD_NANDF_CS3__GPIO6_16 0x0 + /* POWER_AND_BOOT_STATUS_INDICATOR */ + MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4 + /* ACTIVATE_ALARM_LIGHT_RED */ + MX53_PAD_PATA_DIOR__GPIO7_3 0x0 + /* ACTIVATE_ALARM_LIGHT_YELLOW */ + MX53_PAD_PATA_DA_1__GPIO7_7 0x0 + /* ACTIVATE_ALARM_LIGHT_CYAN */ + MX53_PAD_PATA_DA_2__GPIO7_8 0x0 + /* RUNNING_ON_BATTERY_INDICATOR_GREEN */ + MX53_PAD_GPIO_16__GPIO7_11 0x0 + /* BATTERY_STATUS_INDICATOR_AMBER */ + MX53_PAD_GPIO_17__GPIO7_12 0x0 + /* AUDIO_ALARMS_SILENCED_INDICATOR */ + MX53_PAD_GPIO_18__GPIO7_13 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D28__GPIO3_28 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 + MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D16__GPIO3_16 0x1e4 + MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4 + MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX53_PAD_GPIO_9__PWM1_PWMO 0x5 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_EIM_D23__UART3_CTS 0x1e4 + MX53_PAD_EIM_EB3__UART3_RTS 0x1e4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 + >; + }; + + pinctrl_usb_otg_vbus: usb-otg-vbusgrp { + fsl,pins = < + /* USB_HS_OTG_VBUS_ENABLE */ + MX53_PAD_KEY_ROW4__GPIO4_15 0x1c4 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + /* USB H2 */ + MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180 + MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180 + MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180 + MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180 + MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180 + MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180 + MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180 + MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180 + MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180 + MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180 + MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x180 + MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x5 + MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x180 + >; + }; + + pinctrl_usbh2_vbus: usbh2-vbusgrp { + fsl,pins = < + /* USB_HS_HOST2_VBUS_ENABLE */ + MX53_PAD_EIM_D31__GPIO3_31 0x0 + >; + }; + + pinctrl_usbh3_vbus: usbh3-vbusgrp { + fsl,pins = < + /* USB_HS_HOST3_VBUS_ENABLE */ + MX53_PAD_CSI0_DAT9__GPIO5_27 0x0 + >; + }; + + pinctrl_usbh3: usbh3grp { + fsl,pins = < + /* USB H3 */ + MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x180 + MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x180 + MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x180 + MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x180 + MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x180 + MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x180 + MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x180 + MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x180 + MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x5 + MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x180 + MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x180 + MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x180 + MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x180 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + /* USB_OTG_FAULT_N */ + MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index 683dcbe27cbd..41a2e2a2b079 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -22,7 +22,7 @@ <0xb0000000 0x20000000>; }; - display0: display@di0 { + display0: disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb565"; pinctrl-names = "default"; @@ -172,7 +172,7 @@ >; }; - led_pin_gpio7_7: led_gpio7_7@0 { + led_pin_gpio7_7: led_gpio7_7 { fsl,pins = < MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 >; @@ -314,7 +314,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p2v>; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 33cb64fc8372..51f4a42a55e2 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -232,12 +232,12 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; }; - magnetometer: mag3110@0e { + magnetometer: mag3110@e { compatible = "fsl,mag3110"; reg = <0x0e>; }; diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts index 0ecb43d88522..fe15c9555d6e 100644 --- a/arch/arm/boot/dts/imx53-tx53-x03x.dts +++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts @@ -1,12 +1,42 @@ /* - * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -23,132 +53,130 @@ display = &display; }; - soc { - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb24_vga1>; - status = "okay"; + display: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_vga1>; + status = "okay"; - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; }; + }; - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; @@ -173,28 +201,24 @@ default-brightness-level = <50>; }; - regulators { - reg_lcd_pwr: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; - reg_lcd_reset: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; + reg_lcd_reset: regulator-lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; }; }; @@ -203,7 +227,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_2v5>; @@ -228,7 +252,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc2007>; interrupt-parent = <&gpio3>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = <660>; wakeup-source; diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts index 3cf682a681f4..f2b2ad3ce9e5 100644 --- a/arch/arm/boot/dts/imx53-tx53-x13x.dts +++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts @@ -1,6 +1,42 @@ /* - * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de> * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 at the following locations: @@ -63,82 +99,46 @@ default-brightness-level = <50>; }; - regulators { - reg_lcd_pwr0: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LVDS0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_pwr1: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LVDS1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; + reg_lcd_pwr0: regulator-lvds0-pwr { + compatible = "regulator-fixed"; + regulator-name = "LVDS0 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; }; -}; -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - touchscreen2: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti2>; - interrupt-parent = <&gpio3>; - interrupts = <23 0>; - wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - wakeup-source; + reg_lcd_pwr1: regulator-lvds1-pwr { + compatible = "regulator-fixed"; + regulator-name = "LVDS1 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; }; }; &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_2v5>; VDDIO-supply = <®_3v3>; clocks = <&mclk>; }; - - touchscreen1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti1>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; }; &iomuxc { imx53-tx53-x13x { - pinctrl_i2c2: i2c2-grp1 { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - pinctrl_lvds0: lvds0grp { fsl,pins = < MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 7807c1fa1101..a22e461fc168 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -1,15 +1,45 @@ /* - * Copyright 2012 <LW@KARO-electronics.de> + * Copyright 2012-2017 <LW@KARO-electronics.de> * based on imx53-qsb.dts * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "imx53.dtsi" @@ -66,61 +96,50 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2v5: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; - reg_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - reg_can_xcvr: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; - reg_usbh1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usbotg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { @@ -206,16 +225,25 @@ mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ status = "okay"; - phy0: ethernet-phy@0 { - interrupt-parent = <&gpio2>; - interrupts = <4>; - device_type = "ethernet-phy"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + device_type = "ethernet-phy"; + }; }; }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-0 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; clock-frequency = <400000>; status = "okay"; @@ -225,7 +253,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ds1339>; interrupt-parent = <&gpio4>; - interrupts = <20 0>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; }; }; @@ -368,15 +398,29 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 + MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 + MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 >; }; diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts index fc51b87ad208..25c78f19826c 100644 --- a/arch/arm/boot/dts/imx53-voipac-bsb.dts +++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts @@ -130,7 +130,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 8bf0d89cdd35..1040251f2951 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -80,7 +80,7 @@ ports = <&ipu_di0>, <&ipu_di1>; }; - tzic: tz-interrupt-controller@0fffc000 { + tzic: tz-interrupt-controller@fffc000 { compatible = "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; @@ -116,6 +116,28 @@ }; }; + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + + usbphy1: usbphy-1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -299,20 +321,6 @@ reg = <0x53f00000 0x60>; }; - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; - clock-names = "main_clk"; - status = "okay"; - }; - - usbphy1: usbphy@1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - clock-names = "main_clk"; - status = "okay"; - }; - usbotg: usb@53f80000 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; @@ -433,13 +441,11 @@ clock-names = "ipg", "per"; }; - srtc: srtc@53fa4000 { - compatible = "fsl,imx53-rtc", "fsl,imx25-rtc"; + srtc: rtc@53fa4000 { + compatible = "fsl,imx53-rtc"; reg = <0x53fa4000 0x4000>; interrupts = <24>; - interrupt-parent = <&tzic>; clocks = <&clks IMX5_CLK_SRTC_GATE>; - clock-names = "ipg"; }; iomuxc: iomuxc@53fa8000 { @@ -545,7 +551,7 @@ }; can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx53-flexcan"; reg = <0x53fc8000 0x4000>; interrupts = <82>; clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, @@ -555,7 +561,7 @@ }; can2: can@53fcc000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx53-flexcan"; reg = <0x53fcc000 0x4000>; interrupts = <83>; clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, @@ -822,10 +828,5 @@ reg = <0xf8000000 0x20000>; clocks = <&clks IMX5_CLK_OCRAM>; }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <77>; - }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts index 0677625463d6..5f0d196495d0 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts @@ -52,7 +52,7 @@ reg = <0x10000000 0x40000000>; }; - display0: display@di0 { + display0: disp0 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx-parallel-display"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 32a812b1839e..3c9f4af9e9ff 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -31,35 +31,33 @@ reg = <0x10000000 0x40000000>; }; - soc { - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; + display0: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; - display-timings { - 480x800p60 { - native-mode; - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <59>; - hback-porch = <10>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; + display-timings { + 480x800p60 { + native-mode; + clock-frequency = <30000000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <59>; + hback-porch = <10>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; }; + }; - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 15203f0e9725..96cd835ccbf6 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -20,34 +20,32 @@ reg = <0x10000000 0x40000000>; }; - soc { - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; + display0: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <33246000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <88>; - hback-porch = <88>; - hsync-len = <80>; - vback-porch = <10>; - vfront-porch = <10>; - vsync-len = <25>; - vsync-active = <1>; - }; + display-timings { + 800x480p60 { + native-mode; + clock-frequency = <33246000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <88>; + hback-porch = <88>; + hsync-len = <80>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <25>; + vsync-active = <1>; }; + }; - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 26541538562c..dcf9206f3e0d 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -88,7 +88,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -163,7 +163,7 @@ /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts new file mode 100644 index 000000000000..2b2fc360b865 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts b/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts new file mode 100644 index 000000000000..e09c565d1d1f --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Solo/DualLite (1.5som)"; + compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts index f10a36b8647d..2b1b3e193f53 100644 --- a/arch/arm/boot/dts/imx6dl-cubox-i.dts +++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts @@ -41,6 +41,8 @@ /dts-v1/; #include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-cubox-i.dtsi" / { diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts new file mode 100644 index 000000000000..a63f742f20d9 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts new file mode 100644 index 000000000000..66a06cf3cdf3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Solo/DualLite (1.5som)"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 39c2602fa87c..cbd02eb486e1 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -42,6 +42,8 @@ /dts-v1/; #include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-hummingboard.dtsi" / { diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts new file mode 100644 index 000000000000..80313c13bcdb --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts @@ -0,0 +1,55 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts new file mode 100644 index 000000000000..e61ef1156f8b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts @@ -0,0 +1,54 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite (1.5som)"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2.dts b/arch/arm/boot/dts/imx6dl-hummingboard2.dts new file mode 100644 index 000000000000..b12cd87f3f94 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard2.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts index cf42c2f5cdc7..1281bc39b7ab 100644 --- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts +++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts @@ -42,7 +42,7 @@ /dts-v1/; -#include "imx6q.dtsi" +#include "imx6dl.dtsi" #include "imx6qdl-icore-rqs.dtsi" / { diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts index 6de83c72bd72..971f9fc39c66 100644 --- a/arch/arm/boot/dts/imx6dl-icore.dts +++ b/arch/arm/boot/dts/imx6dl-icore.dts @@ -57,3 +57,12 @@ &can2 { status = "okay"; }; + +&i2c1 { + max11801: touchscreen@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h index 0ead323fdbd2..37e430a261de 100644 --- a/arch/arm/boot/dts/imx6dl-pinfunc.h +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h @@ -668,6 +668,7 @@ #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 #define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 #define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1f8 0x5c8 0x000 0x0 0x0 #define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 #define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 275c6c05219d..23e108204e1e 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -157,7 +157,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -165,7 +165,7 @@ VDDIO-supply = <®_3p3v>; }; - pmic: pf0100@08 { + pmic: pf0100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/imx6dl-ts7970.dts new file mode 100644 index 000000000000..d104daf305d9 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-ts7970.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2015 Technologic Systems + * Copyright 2017 Savoir-faire Linux + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7970.dtsi" + +/ { + model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; + compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts index aac42ac465b6..51a9bb9d6bc2 100644 --- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,70 +42,16 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +}; - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; }; &can1 { @@ -116,14 +62,14 @@ xceiver-supply = <®_3v3>; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + ®_can_xcvr { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts new file mode 100644 index 000000000000..fc23b4d291a1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6s-8034.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6S-8034 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts index ff8f7b1c4282..9eb2ef17339c 100644 --- a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts +++ b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts @@ -1,5 +1,5 @@ /* - * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,174 +42,15 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6S-8034 Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - aliases { - display = &display; - ipu1 = &ipu1; - }; - cpus { /delete-node/ cpu@1; }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -227,11 +68,3 @@ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ >; }; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts new file mode 100644 index 000000000000..4101c6597721 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6s-8035.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8035 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts index f988950e9443..a5532ecc18c5 100644 --- a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts +++ b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts @@ -1,5 +1,5 @@ /* - * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,174 +42,15 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6S-8035 Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - aliases { - display = &display; - ipu1 = &ipu1; - }; - cpus { /delete-node/ cpu@1; }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -220,14 +61,6 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; - &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts index d1f1298ec55a..67ed0452f5de 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,166 +42,9 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6U-801x Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts new file mode 100644 index 000000000000..d34189fc52d9 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6u-8033.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8033 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts index 4d3204a56f46..7030b2654bbd 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,169 +42,11 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6U-8033 Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -215,14 +57,6 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; - &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts new file mode 100644 index 000000000000..aef5fcc42904 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6u-801x.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8030/-8010/-8012 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts index 5e0c6bb49f37..5342f2f5a8a8 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,137 +42,9 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" / { model = "Ka-Ro electronics TX6U-811x Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&i2c3 { - polytouch2: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds_timing0>; - lvds_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "disabled"; - - display-timings { - native-mode = <&lvds_timing1>; - lvds_timing1: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts index b9a783f7160e..c4588fb0bf6f 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2016-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,216 +40,9 @@ */ /dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" +#include "imx6dl-tx6u-811x.dts" +#include "imx6qdl-tx6-mb7.dtsi" / { - model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&kpp { - status = "disabled"; /* pads partially clash with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing1>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds0_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing2>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds1_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds1_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; + model = "Ka-Ro electronics TX6U-8130/-8110 Module on MB7 baseboard"; }; diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts new file mode 100644 index 000000000000..aa4d4faaaec4 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 Dual Lite Board revD1"; + compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 8475e6cc59ac..c01674fa098a 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -60,35 +60,35 @@ }; soc { - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips1: aips-bus@02000000 { - iomuxc: iomuxc@020e0000 { + aips1: aips-bus@2000000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6dl-iomuxc"; }; - pxp: pxp@020f0000 { + pxp: pxp@20f0000 { reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; }; - epdc: epdc@020f4000 { + epdc: epdc@20f4000 { reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; - lcdif: lcdif@020f8000 { + lcdif: lcdif@20f8000 { reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; }; }; - aips2: aips-bus@02100000 { - i2c4: i2c@021f8000 { + aips2: aips-bus@2100000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -170,7 +170,7 @@ }; &gpr { - ipu1_csi0_mux: ipu1_csi0_mux@34 { + ipu1_csi0_mux { compatible = "video-mux"; mux-controls = <&mux 0>; #address-cells = <1>; @@ -224,7 +224,7 @@ }; }; - ipu1_csi1_mux: ipu1_csi1_mux@34 { + ipu1_csi1_mux { compatible = "video-mux"; mux-controls = <&mux 1>; #address-cells = <1>; @@ -309,10 +309,12 @@ #size-cells = <0>; mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; }; mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; }; }; @@ -323,10 +325,12 @@ #size-cells = <0>; mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; }; mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; }; }; @@ -337,10 +341,12 @@ #size-cells = <0>; mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; }; mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; }; }; @@ -351,10 +357,12 @@ #size-cells = <0>; mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; }; mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index 4bbfe3d61027..aa0e631f3c0a 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -76,7 +76,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -158,7 +158,7 @@ /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index a35c7a54ad3b..e8dccf552122 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -77,7 +77,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -170,7 +170,7 @@ /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 60d33e99de76..6831dfd24cc1 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -76,7 +76,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -174,7 +174,7 @@ /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts index 404a93d9596b..3ec58500e9c2 100644 --- a/arch/arm/boot/dts/imx6q-b450v3.dts +++ b/arch/arm/boot/dts/imx6q-b450v3.dts @@ -112,3 +112,55 @@ line-name = "PCA9539-P07"; }; }; + +&pci_root { + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00010000 0 0 0 0>; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "enacq"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport1"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; + + port@5 { + reg = <5>; + label = "enembc"; + + /* connected to Ethernet MAC of AT91RM9200 in MII mode */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index 7f9f176901d4..5650a9b11091 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -111,3 +111,55 @@ fsl,tx-cal-45-dp-ohms = <55>; fsl,tx-d-cal = <100>; }; + +&pci_root { + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00010000 0 0 0 0>; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "enacq"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport1"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; + + port@5 { + reg = <5>; + label = "enembc"; + + /* connected to Ethernet MAC of AT91RM9200 in MII mode */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 46bdc6722715..35edbdc7bcd1 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -212,3 +212,78 @@ }; }; }; + +&pci_root { + /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ + bridge@1,0 { + compatible = "pci10b5,8605"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + bridge@2,1 { + compatible = "pci10b5,8605"; + reg = <0x00020800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Intel Corporation I210 Gigabit Network Connection */ + ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00030000 0 0 0 0>; + }; + }; + + bridge@2,2 { + compatible = "pci10b5,8605"; + reg = <0x00021000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@4,0 { + compatible = "pci8086,1533"; + reg = <0x00040000 0 0 0 0>; + }; + }; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "eneport1"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport2"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 1015e55ca8f7..916ea94d75ca 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -92,6 +92,56 @@ mux-int-port = <1>; mux-ext-port = <4>; }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + mdio0: mdio-gpio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */ + + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; /* 88e6240*/ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + }; + + switchphy1: switchphy@1 { + reg = <1>; + }; + + switchphy2: switchphy@2 { + reg = <2>; + }; + + switchphy3: switchphy@3 { + reg = <3>; + }; + + switchphy4: switchphy@4 { + reg = <4>; + }; + }; + }; + }; }; &ecspi5 { @@ -165,7 +215,7 @@ #size-cells = <0>; reg = <0x3>; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&mclk>; @@ -326,3 +376,15 @@ tcxo-clock-frequency = <26000000>; }; }; + +&pcie { + /* Synopsys, Inc. Device */ + pci_root: root@0,0 { + compatible = "pci16c3,abcd"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index fe6ab0aa34f9..bc7587c383f6 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -77,8 +77,7 @@ regulator-name = "regulator-pcie-power-on-gpio"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; }; reg_usb_h1_vbus: usb_h1_vbus { @@ -362,7 +361,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - vdd-supply = <®_pcie_power_on_gpio>; + vpcie-supply = <®_pcie_power_on_gpio>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts new file mode 100644 index 000000000000..3e59ebbb3608 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts b/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts new file mode 100644 index 000000000000..dab70d1230a2 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Dual/Quad (1.5som)"; + compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts index b68aa0e57f20..1c7b262e3709 100644 --- a/arch/arm/boot/dts/imx6q-cubox-i.dts +++ b/arch/arm/boot/dts/imx6q-cubox-i.dts @@ -41,6 +41,8 @@ /dts-v1/; #include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-cubox-i.dtsi" / { diff --git a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts new file mode 100644 index 000000000000..16658b76fc4e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-display5.dtsi" + +&panel { + compatible = "tianma,tm070jdhg30"; +}; + +&ldb { + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi new file mode 100644 index 000000000000..09085fde3341 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-display5.dtsi @@ -0,0 +1,596 @@ +/* + * Copyright 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Liebherr (LWN) display5 i.MX6 Quad Board"; + compatible = "lwn,display5", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 101 102 103 104 105 106 107 108 109 + 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 + 130 131 132 133 134 135 136 137 138 139 + 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 + 170 171 172 173 174 175 176 177 178 179 + 180 181 182 183 184 185 186 187 188 189 + 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 208 209 + 210 211 212 213 214 215 216 217 218 219 + 220 221 222 223 224 225 226 227 228 229 + 230 231 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 248 249 + 250 251 252 253 254 255>; + default-brightness-level = <250>; + enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "lvds_ppen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lvds>; + gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbh1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <300000>; + }; + + sound { + compatible = "simple-audio-card"; + label = "tfa9879-mono"; + + simple-audio-card,dai-link { + /* DAC */ + format = "i2s"; + bitclock-master = <&dailink_master>; + frame-master = <&dailink_master>; + + dailink_master: cpu { + sound-dai = <&ssi2>; + }; + codec { + sound-dai = <&codec>; + }; + }; + }; + + panel: panel-lvds0 { + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(5) | + IMX_AUDMUX_V2_PTCR_TCSEL(5) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(5) + >; + }; + + aud6 { + fsl,audmux-port = <5>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_RFSEL(8) | + IMX_AUDMUX_V2_PTCR_RCSEL(8) | + IMX_AUDMUX_V2_PTCR_TFSEL(1) | + IMX_AUDMUX_V2_PTCR_TCSEL(1) | + IMX_AUDMUX_V2_PTCR_RFSDIR | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; + status = "okay"; + + s25fl256s: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partition@0 { + label = "SPL (spi)"; + reg = <0x0 0x20000>; + read-only; + }; + partition@1 { + label = "u-boot (spi)"; + reg = <0x20000 0x100000>; + read-only; + }; + partition@2 { + label = "uboot-env (spi)"; + reg = <0x120000 0x10000>; + }; + partition@3 { + label = "uboot-envr (spi)"; + reg = <0x130000 0x10000>; + }; + partition@4 { + label = "linux-recovery (spi)"; + reg = <0x140000 0x800000>; + }; + partition@5 { + label = "swupdate-fitImg (spi)"; + reg = <0x940000 0x400000>; + }; + partition@6 { + label = "swupdate-initramfs (spi)"; + reg = <0xD40000 0x800000>; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðernet_phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { + compatible = "marvell,88E1510"; + device_type = "ethernet-phy"; + /* Set LED0 control: */ + /* On - Link, Blink - Activity, Off - No Link */ + marvell,reg-init = <3 0x10 0 0x1011>; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: tfa9879@6c { + #sound-dai-cells = <0>; + compatible = "nxp,tfa9879"; + reg = <0x6C>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + at24@50 { + compatible = "atmel,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pwm2 { + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* I2S OUTPUT AUD6*/ + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + >; + }; + + pinctrl_backlight: dispgrp { + fsl,pins = < + /* BLEN_OUT */ + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_ecspi2_flwp: ecspi2flwpgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3_cs: ecspi3csgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 + >; + }; + + pinctrl_ecspi3_flwp: ecspi3flwpgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_lvds: reqlvdsgrp { + fsl,pins = < + /* LVDS_PPEN_OUT */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 + >; + }; + + pinctrl_usbh1_vbus: usbh1_vbus_grp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 33eb7f180995..f0316ea96898 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -139,7 +139,7 @@ &pinctrl_pfuze>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio3>; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 9dbeea05a949..29adaa7c72f8 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -211,7 +211,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -322,7 +322,7 @@ reg = <0x1c>; }; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -330,7 +330,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; @@ -392,127 +392,124 @@ }; &iomuxc { - imx6q-gw5400-a { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ - >; - }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; }; }; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts index 8f9252889971..8a2ea6c58902 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -42,8 +42,8 @@ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" / { model = "Auvidea H100"; @@ -108,21 +108,6 @@ regulator-always-on; }; - reg_nvcc_sd2: regulator-nvcc-sd2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_reg_nvcc_sd2>; - compatible = "regulator-gpio"; - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; - }; - reg_usbh1_vbus: regulator-usb-h1-vbus { compatible = "regulator-fixed"; enable-active-high; @@ -185,7 +170,7 @@ reg = <0x68>; }; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; pinctrl-names = "default"; @@ -195,7 +180,7 @@ VDDIO-supply = <®_3p3v>; }; - tc358743: tc358743@0f { + tc358743: tc358743@f { compatible = "toshiba,tc358743"; reg = <0x0f>; pinctrl-names = "default"; @@ -205,7 +190,7 @@ reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; /* IRQ has a wrong pull resistor which renders it useless */ - port@0 { + port { tc358743_out: endpoint { remote-endpoint = <&mipi_csi2_in>; data-lanes = <1 2 3 4>; @@ -260,12 +245,6 @@ >; }; - pinctrl_h100_reg_nvcc_sd2: h100-reg-nvcc-sd2 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - pinctrl_h100_sgtl5000: h100-sgtl5000 { fsl,pins = < MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 @@ -316,6 +295,7 @@ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 >; }; @@ -328,6 +308,7 @@ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 >; }; @@ -340,6 +321,7 @@ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 >; }; }; @@ -348,7 +330,7 @@ &mipi_csi { status = "okay"; - port@0 { + port { mipi_csi2_in: endpoint { remote-endpoint = <&tc358743_out>; data-lanes = <1 2 3 4>; @@ -389,7 +371,6 @@ pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>; pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>; vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_nvcc_sd2>; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts new file mode 100644 index 000000000000..c51b4e4fd71e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts new file mode 100644 index 000000000000..e4132d62ffa2 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Dual/Quad (1.5som)"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts index 69a7a0a1cb21..8c9e94e648a7 100644 --- a/arch/arm/boot/dts/imx6q-hummingboard.dts +++ b/arch/arm/boot/dts/imx6q-hummingboard.dts @@ -42,6 +42,8 @@ /dts-v1/; #include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-hummingboard.dtsi" / { diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts new file mode 100644 index 000000000000..1998ebfa0fe0 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts @@ -0,0 +1,63 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts new file mode 100644 index 000000000000..d3ad7329cd6d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts @@ -0,0 +1,62 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Dual/Quad (1.5som)"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2.dts b/arch/arm/boot/dts/imx6q-hummingboard2.dts new file mode 100644 index 000000000000..5249f53dcdbc --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard2.dts @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" + +/ { + model = "SolidRun HummingBoard2 Dual/Quad"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts index e451b4ceb4d8..b81f48c6a8c6 100644 --- a/arch/arm/boot/dts/imx6q-icore-rqs.dts +++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts @@ -47,30 +47,6 @@ / { model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx-audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&i2c3 { - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; }; &sata { diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts index eedbe737420c..cab36f48d5f1 100644 --- a/arch/arm/boot/dts/imx6q-mccmon6.dts +++ b/arch/arm/boot/dts/imx6q-mccmon6.dts @@ -121,7 +121,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pfuze100: pmic@08 { + pfuze100: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index d83cfb6ec598..7d7dc59507cf 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -158,7 +158,6 @@ regulator-max-microvolt = <1500000>; gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; }; reg_sata: regulator-sata { @@ -255,7 +254,7 @@ reg = <0x68>; }; - sbs_battery: bq20z75@0b { + sbs_battery: bq20z75@b { compatible = "sbs,sbs-battery"; reg = <0x0b>; sbs,i2c-retry-count = <50>; @@ -295,7 +294,7 @@ pinctrl-0 = <&pinctrl_i2c2_novena>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -447,6 +446,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_novena>; reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index 9fc6120a1853..cfb11d3e739c 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h @@ -551,6 +551,7 @@ #define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 #define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 #define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0 #define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 #define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts new file mode 100644 index 000000000000..1effb58f304c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pistachio.dts @@ -0,0 +1,693 @@ +/* + * Copyright (C) 2017 NutsBoard.Org + * + * Author: Wig Cheng <onlywig@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "imx6q.dtsi" + +/ { + model = "NutsBoard i.MX6 Quad Pistachio board"; + compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q"; + + chosen { + stdout-path = &uart4; + }; + + memory: memory { + reg = <0x10000000 0x80000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + wlan_en_reg: regulator-wlan_en { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = <KEY_POWER>; + }; + }; + + sound { + compatible = "fsl,imx-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "audio-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + brightness-levels = < + 0 /*1 2 3 4 5 6*/ 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <94>; + status = "okay"; + }; + + panel { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ar1021@4d { + compatible = "microchip,ar1021-i2c"; + reg = <0x4d>; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/ + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + /* AR8035 reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0 + /* AR8035 interrupt */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 + /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00 + >; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <0x5>; +}; + +&usbphy2 { + fsl,tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + keep-power-in-suspend; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + vmmc-supply = <&wlan_en_reg>; + no-1-8-v; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 06f492e17ca7..a3cd7afac20a 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -158,7 +158,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { clocks = <&clks IMX6QDL_CLK_CKO>; compatible = "fsl,sgtl5000"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/imx6q-ts7970.dts new file mode 100644 index 000000000000..f19e18995e68 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ts7970.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2015 Technologic Systems + * Copyright 2017 Savoir-faire Linux + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7970.dtsi" + +/ { + model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)"; + compatible = "technologic,imx6q-ts7970", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts index 71746edc2ee9..ac3050a835e5 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,70 +42,16 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; }; &can1 { @@ -116,14 +62,14 @@ xceiver-supply = <®_3v3>; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + ®_can_xcvr { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts index f9cd21a41a79..4ee860b626ff 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,166 +42,13 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { - model = "Ka-Ro electronics TX6Q-1010 Module"; + model = "Ka-Ro electronics TX6Q-1010/-1030 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; +&ipu2 { + status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts index 959ff3fb7304..a773f252816c 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,70 +42,16 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; }; &can1 { @@ -124,14 +70,14 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + ®_can_xcvr { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts index b49133d25d80..0a4daec8d3ad 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,164 +42,11 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1020 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -210,14 +57,15 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; +&ipu2 { + status = "disabled"; }; &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <4>; + non-removable; no-1-8-v; fsl,wp-controller; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts new file mode 100644 index 000000000000..9ffbb0fe7df8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q-tx6q-1036.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1036 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/imx6q-tx6q-1036.dts index 7c152e32758c..cb2fcb4896c6 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1036.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1036.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,169 +42,11 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1036 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -215,18 +57,10 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &ipu2 { status = "disabled"; }; -®_lcd0_pwr { - status = "disabled"; -}; - &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; diff --git a/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts new file mode 100644 index 000000000000..d43a5d8f1749 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q-tx6q-1010.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1010/-1030 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/imx6q-tx6q-1110.dts index 0433e220a931..f7b0acb65352 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1110.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1110.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,141 +42,17 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" / { - model = "Ka-Ro electronics TX6Q-1110 Module"; + model = "Ka-Ro electronics TX6Q-1110/-1130 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; }; -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds_timing0>; - lvds_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "disabled"; - - display-timings { - native-mode = <&lvds_timing1>; - lvds_timing1: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; +&ipu2 { + status = "disabled"; }; &sata { status = "okay"; }; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts index d78b129d01ea..387edf2b3f96 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2016-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,225 +40,9 @@ */ /dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" +#include "imx6q-tx6q-1110.dts" +#include "imx6qdl-tx6-mb7.dtsi" / { model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &lvds0; - ipu1 = &ipu2; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&ipu2 { - status = "disabled"; -}; - -&kpp { - status = "disabled"; /* pads partially clash with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing1>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds0_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing2>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds1_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds1_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; }; diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts index 16d5be1aeb3c..f5d9c34b0d39 100644 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -188,6 +188,8 @@ /delete-node/&hdmi_mux_1; &hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmicec>; ddc-i2c-bus = <&i2c2>; status = "okay"; }; @@ -211,6 +213,12 @@ >; }; + pinctrl_hdmicec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_hpd: hpdgrp { fsl,pins = < MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts new file mode 100644 index 000000000000..e0728d475f6f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Support for Variscite DART-MX6 Carrier-board + * + * Copyright 2017 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-var-dart.dtsi" +#include <dt-bindings/input/linux-event-codes.h> + +/ { + model = "Variscite DART-MX6 Carrier-board"; + compatible = "variscite,dt6customboard", "fsl,imx6q"; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + brightness-levels = <0 4 8 16 32 64 128 248>; + default-brightness-level = <7>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + back { + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + label = "Key Back"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + + home { + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + label = "Key Home"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + + menu { + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + linux,code = <KEY_MENU>; + label = "Key Menu"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + panel1: lvds-panel { + compatible = "sgd,gktw70sdae4se", "panel-lvds"; + backlight = <&backlight_lvds>; + width-mm = <153>; + height-mm = <86>; + label = "gktw70sdae4se"; + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <32000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <39>; + hfront-porch = <39>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <47>; + vsync-len = <2>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + reg_usb_h1_vbus: regulator-usbh1vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "dt6-customboard-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&clks IMX6QDL_CLK_CKO>; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>, + <&gpio4 10 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + status = "okay"; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + + rtc@68 { + compatible = "isil,isl12057"; + reg = <0x68>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc2 { + cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts new file mode 100644 index 000000000000..e87ddb168669 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board revD1"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 90a741732f60..bc581aa5cf17 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -79,15 +79,15 @@ }; soc { - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x40000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@02000000 { /* AIPS1 */ - spba-bus@02000000 { - ecspi5: ecspi@02018000 { + aips-bus@2000000 { /* AIPS1 */ + spba-bus@2000000 { + ecspi5: ecspi@2018000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -102,12 +102,12 @@ }; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6q-iomuxc"; }; }; - sata: sata@02200000 { + sata: sata@2200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; @@ -118,7 +118,7 @@ status = "disabled"; }; - gpu_vg: gpu@02204000 { + gpu_vg: gpu@2204000 { compatible = "vivante,gc"; reg = <0x02204000 0x4000>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; @@ -128,7 +128,7 @@ power-domains = <&pd_pu>; }; - ipu2: ipu@02800000 { + ipu2: ipu@2800000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ipu"; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index ea339fa58f4a..4e776e036cbc 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -222,7 +222,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -313,7 +313,7 @@ }; }; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -338,7 +338,6 @@ stmpe_touchscreen { compatible = "st,stmpe-ts"; - reg = <0>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 8 sample average control */ diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index 9cd2a7477ed7..9fc1fa449f64 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -54,7 +54,7 @@ stdout-path = &uart4; }; - display@di0 { + disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; @@ -111,32 +111,28 @@ }; }; - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_usbh1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - reg_usb_otg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; }; sound { @@ -209,7 +205,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index 7d64075204ae..ee4d0f84eeb2 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -12,48 +12,43 @@ #include <dt-bindings/gpio/gpio.h> / { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_usbh1_vbus: regulator@2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_usbotg_vbus: regulator@3 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index 1b1872873207..376750882ed3 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -52,46 +52,42 @@ enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; }; - regulators { - compatible = "simple-bus"; - - reg_2p5v: 2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index ad84eddb6836..e4eb300549d4 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -167,7 +167,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -248,7 +248,7 @@ }; }; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -274,7 +274,6 @@ stmpe_touchscreen { compatible = "st,stmpe-ts"; - reg = <0>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 8 sample average control */ diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index 14fff4ee6516..d1cfdc264126 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -38,8 +38,6 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> @@ -64,38 +62,36 @@ }; }; - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_usb2: regulator-v-usb2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; }; sound-spdif { @@ -139,7 +135,7 @@ status = "okay"; - rtc: pcf8523@68 { + rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; @@ -243,21 +239,25 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_usbh1>; - vbus-supply = <®_usbh1_vbus>; + vbus-supply = <&v_usb2>; status = "okay"; }; &usbotg { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_usbotg>; - vbus-supply = <®_usbotg_vbus>; + vbus-supply = <&v_usb1>; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&vcc_3v3 { + vin-supply = <&v_5v0>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 885556260bd0..dea8fc43c692 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -332,175 +332,173 @@ }; &iomuxc { - imx6qdl-gw51xx { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 - >; - }; + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 115d706228ef..363a44394dad 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -303,7 +303,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -311,7 +311,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; @@ -423,213 +423,211 @@ }; &iomuxc { - imx6qdl-gw52xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 24be7965056c..c75385c0cad0 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -294,7 +294,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -302,7 +302,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; @@ -415,205 +415,203 @@ }; &iomuxc { - imx6qdl-gw53xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 4594b2279169..eab75f3dbaf3 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -223,7 +223,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -331,7 +331,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -339,7 +339,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; @@ -468,221 +468,219 @@ }; &iomuxc { - imx6qdl-gw54xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; - pinctrl_ecspi2: escpi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; + pinctrl_ecspi2: escpi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4_backlight: pwm4grpbacklight { - fsl,pins = < - /* LVDS_PWM J6.5 */ - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4_backlight: pwm4grpbacklight { + fsl,pins = < + /* LVDS_PWM J6.5 */ + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4_dio: pwm4grpdio { - fsl,pins = < - /* DIO3 J16.4 */ - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4_dio: pwm4grpdio { + fsl,pins = < + /* DIO3 J16.4 */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 405b40310ddf..30d4662d4480 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -320,110 +320,108 @@ }; &iomuxc { - imx6qdl-gw51xx { - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 67613dd7cc92..c67c10605070 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -270,105 +270,103 @@ }; &iomuxc { - imx6qdl-gw552x { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index 988334c889eb..92583238ca4a 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -38,8 +38,6 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" / { chosen { @@ -53,38 +51,58 @@ pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; }; - regulators { - compatible = "simple-bus"; + v_3v2: regulator-v-3v2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_3v2"; + vin-supply = <&v_5v0>; + }; - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_sd: regulator-v-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_vmmc>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_sd"; + startup-delay-us = <1000>; + vin-supply = <&v_3v2>; + }; - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_usb2: regulator-v-usb2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; + + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; }; sound-sgtl5000 { @@ -132,20 +150,20 @@ status = "okay"; /* Pro baseboard model */ - rtc: pcf8523@68 { + rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; /* Pro baseboard model */ - sgtl5000: sgtl5000@0a { + sgtl5000: codec@a { clocks = <&clks IMX6QDL_CLK_CKO>; compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <&v_3v2>; + VDDIO-supply = <&v_3v2>; }; }; @@ -247,6 +265,11 @@ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 >; }; + pinctrl_hummingboard_vmmc: hummingboard-vmmc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; }; }; @@ -280,7 +303,7 @@ &usbh1 { disable-over-current; - vbus-supply = <®_usbh1_vbus>; + vbus-supply = <&v_usb2>; status = "okay"; }; @@ -288,7 +311,7 @@ disable-over-current; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; + vbus-supply = <&v_usb1>; status = "okay"; }; @@ -298,7 +321,11 @@ &pinctrl_hummingboard_usdhc2_aux &pinctrl_hummingboard_usdhc2 >; - vmmc-supply = <®_3p3v>; + vmmc-supply = <&v_sd>; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&vcc_3v3 { + vin-supply = <&v_3v2>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi new file mode 100644 index 000000000000..f400405381a7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi @@ -0,0 +1,72 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&iomuxc { + hummingboard2 { + pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usdhc3>; + vmmc-supply = <&v_3v2>; + vqmmc-supply = <&v_3v2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi new file mode 100644 index 000000000000..dffbc92e0023 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi @@ -0,0 +1,540 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + chosen { + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + v_3v2: regulator-v-3v2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_3v2"; + }; + + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; + + vcc_1p8: regulator-vcc-1p8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1p8"; + vin-supply = <&v_3v2>; + }; + + v_sd: regulator-v-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_vmmc>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_sd"; + startup-delay-us = <1000>; + vin-supply = <&v_3v2>; + }; + + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; + }; + + v_usb2: regulator-v-usb2 { + /* USB hub port 1 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; + + v_usb3: regulator-v-usb3 { + /* USB hub port 3 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb3"; + vin-supply = <&v_5v0>; + }; + + v_usb4: regulator-v-usb4 { + /* USB hub port 4 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb4"; + vin-supply = <&v_5v0>; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <5>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; + cs-gpios = <&gpio2 26 0>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; + status = "okay"; + + pcf8523: rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + sgtl5000: codec@a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <&v_3v2>; + VDDD-supply = <&vcc_1p8>; + VDDIO-supply = <&v_3v2>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hummingboard2 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* + * 36 pin headers GPIO description. The pins + * numbering as following - + * + * 3.2v 5v 74 75 + * 73 72 71 70 + * 69 68 67 66 + * + * 77 78 79 76 + * 65 64 61 60 + * 53 52 51 50 + * 49 48 166 132 + * 95 94 90 91 + * GND 54 24 204 + * + * The GPIO numbers can be extracted using + * signal name from below. + * Example - + * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is + * GPIO(3,10) which is (3-1)*32+10 = gpio 74 + * + * i.e. The mapping of GPIO(X,Y) to Linux gpio + * number is : gpio number = (X-1) * 32 + Y + */ + /* DI1_PIN15 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 + /* DI1_PIN02 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 + /* DISP1_DATA00 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 + /* DISP1_DATA01 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 + /* DISP1_DATA02 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 + /* DISP1_DATA03 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 + /* DISP1_DATA04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 + /* DISP1_DATA05 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 + /* DISP1_DATA06 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 + /* DISP1_DATA07 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 + /* DI1_D0_CS */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 + /* DI1_D1_CS */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 + /* DI1_PIN01 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 + /* DI1_PIN03 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 + /* DISP1_DATA08 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 + /* DISP1_DATA09 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 + /* DISP1_DATA10 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 + /* DISP1_DATA11 */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 + /* DISP1_DATA12 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 + /* DISP1_DATA13 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 + /* DISP1_DATA14 */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 + /* DISP1_DATA15 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 + /* DISP1_DATA16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 + /* DISP1_DATA17 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 + /* DISP1_DATA18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 + /* DISP1_DATA19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 + /* DISP1_DATA20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 + /* DISP1_DATA21 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 + /* DISP1_DATA22 */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 + /* DISP1_DATA23 */ + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 + /* DI1_DISP_CLK */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 + /* SPDIF_IN */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 + /* SPDIF_OUT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 + + /* MikroBUS GPIO pin number 10 */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 + >; + }; + + pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ + >; + }; + + pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 + >; + }; + + pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_mipi: hummingboard2_mipi { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + + pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { + fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; + }; + + pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { + fsl,pins = <MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0>; + }; + + pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { + fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x1b0b0>; + }; + + pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { + /* + * Similar to pinctrl_usbotg_2, but we want it + * pulled down for a fixed host connection. + */ + fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; + }; + + pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { + fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; + }; + + pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 + >; + }; + + pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + + pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 + >; + }; + + pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 + >; + }; + + pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hummingboard2_uart3: hummingboard2-uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pcie_reset>; + reset-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pwm3>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; + vbus-supply = <&v_usb1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2 + >; + pinctrl-1 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_100mhz + >; + pinctrl-2 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_200mhz + >; + vmmc-supply = <&v_sd>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_uart3>; + status = "okay"; +}; + +&vcc_3v3 { + vin-supply = <&v_3v2>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi index 7ca291e9dbdb..b6220d62f6de 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi @@ -41,6 +41,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/imx6qdl-clock.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> / { memory { @@ -118,17 +119,77 @@ clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; clock-names = "refclk"; }; -}; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Speaker", "Line Out Jack", + "Speaker", "Ext Spk"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; }; &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; status = "okay"; + + audmux_ssi1 { + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + audmux_aud4 { + fsl,audmux-port = <MX51_AUDMUX_PORT4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; }; &fec { @@ -174,6 +235,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + sgtl5000: codec@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; }; &pcie { @@ -184,6 +255,7 @@ }; &ssi1 { + fsl,mode = "i2s-slave"; status = "okay"; }; @@ -270,6 +342,20 @@ >; }; + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 56d0c5d21cd0..a1b469c142f1 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -42,6 +42,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> / { memory { @@ -55,6 +56,25 @@ default-brightness-level = <7>; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + + reg_2p5v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -87,6 +107,59 @@ #clock-cells = <0>; clock-frequency = <25000000>; /* 25MHz for example */ }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6qdl-icore-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Speaker", "Line Out Jack", + "Speaker", "Ext Spk"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + + audmux_ssi1 { + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + audmux_aud4 { + fsl,audmux-port = <MX51_AUDMUX_PORT4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; }; &can1 { @@ -141,6 +214,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + sgtl5000: codec@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; }; &pwm3 { @@ -149,6 +232,11 @@ status = "okay"; }; +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -178,6 +266,15 @@ }; &iomuxc { + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 6b81580623ff..4cc4e23cf99c 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -255,7 +255,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; @@ -279,7 +279,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index b63134e3b51a..fd05f7caa472 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -172,7 +172,7 @@ }; }; - i2cmux@2 { + i2c2mux { compatible = "i2c-mux-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2mux>; @@ -183,20 +183,20 @@ i2c-parent = <&i2c2>; idle-state = <0>; - i2c2@1 { + i2c2mux@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; - i2c2@2 { + i2c2mux@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; }; - i2cmux@3 { + i2c3mux { compatible = "i2c-mux-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3mux>; @@ -206,7 +206,7 @@ i2c-parent = <&i2c3>; idle-state = <0>; - i2c3@1 { + i2c3mux@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -256,7 +256,7 @@ status = "okay"; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -397,7 +397,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; @@ -429,7 +429,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index a24e4f1911ab..40942d6b94b3 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -120,7 +120,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -315,7 +315,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; @@ -347,7 +347,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index d309a4d0eb08..919b6b7619a4 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -197,7 +197,7 @@ status = "okay"; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -276,6 +276,23 @@ compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "env"; + reg = <0xc0000 0x2000>; + }; + + partition@c2000 { + label = "splash"; + reg = <0xc2000 0x13e000>; + }; }; }; @@ -313,7 +330,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -340,7 +357,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi index 5cf90c24c707..6e9549ff11da 100644 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -121,7 +121,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 6a7594e5d183..82d6ccb46982 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -235,6 +235,9 @@ }; &hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c2>; status = "okay"; }; @@ -244,7 +247,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -453,6 +456,12 @@ >; }; + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 756c5054f047..35de7adc997b 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -221,7 +221,7 @@ status = "okay"; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -350,7 +350,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index b72b6fa47580..0a50705b9c18 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -67,7 +67,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 19 0>; - regulator-always-on; enable-active-high; }; }; @@ -214,6 +213,8 @@ }; &hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; ddc-i2c-bus = <&i2c2>; status = "okay"; }; @@ -304,7 +305,7 @@ }; }; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -411,7 +412,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - egalax_ts@04 { + egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio6>; @@ -486,6 +487,12 @@ >; }; + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 @@ -651,6 +658,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi index 6a410160c9ee..b55af61dfeca 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi @@ -40,7 +40,7 @@ */ #include <dt-bindings/gpio/gpio.h> / { - clk_sdio: sdio-clock { + clk_brcm: brcm-clock { compatible = "gpio-gate-clock"; #clock-cells = <0>; pinctrl-names = "default"; @@ -48,27 +48,23 @@ enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; }; - regulators { - compatible = "simple-bus"; - - reg_brcm: brcm-reg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; + reg_brcm: brcm-reg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; }; usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, <&gpio6 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_sdio>; + clocks = <&clk_brcm>; clock-names = "ext_clock"; }; }; @@ -104,13 +100,6 @@ >; }; - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - pinctrl_microsom_uart4: microsom-uart4 { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 @@ -133,12 +122,6 @@ }; }; -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; -}; - /* UART4 - Connected to optional BRCM Wifi/BT/FM */ &uart4 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi new file mode 100644 index 000000000000..5f3b8baab20f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&iomuxc { + microsom { + pinctrl_microsom_usdhc3: microsom-usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + }; +}; + +/* USDHC3 - eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_usdhc3>; + bus-width = <8>; + non-removable; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi new file mode 100644 index 000000000000..44a97ba93a95 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <dt-bindings/gpio/gpio.h> + +/ { + nvcc_sd1: regulator-nvcc-sd1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "nvcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + clk_ti_wifi: ti-wifi-clock { + /* This is a hack around the kernel - using "fixed clock" + * results in the "pinctrl" properties being ignored, and + * the clock not being output. Instead, use a gated clock + * and the unrouted WL_XTAL_PU gpio. + */ + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_clk>; + enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + pwrseq_ti_wifi: ti-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_wifi_en>; + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + clocks = <&clk_ti_wifi>; + clock-names = "ext_clock"; + }; +}; + +&iomuxc { + microsom { + pinctrl_microsom_ti_bt: microsom-ti-bt { + fsl,pins = < + /* BT_EN_SOC */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 + >; + }; + + pinctrl_microsom_ti_clk: microsom-ti-clk { + fsl,pins = < + /* EXT_32K */ + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 + /* WL_XTAL_PU (unrouted) */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 + >; + }; + + pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en { + fsl,pins = < + /* WLAN_EN_SOC */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 + >; + }; + + pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq { + fsl,pins = < + /* WLAN_IRQ */ + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 + >; + }; + + pinctrl_microsom_uart4: microsom-uart4 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_microsom_usdhc1: microsom-usdhc1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + }; +}; + +/* UART4 - Connected to optional TI Wi-Fi/BT/FM */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_uart4>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + clocks = <&clk_ti_wifi>; + clock-names = "ext_clock"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_bt>; + }; +}; + +/* USDHC1 - Connected to optional TI Wi-Fi/BT/FM */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_usdhc1>; + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&pwrseq_ti_wifi>; + non-removable; + vmmc-supply = <&vcc_3v3>; + /* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_wifi_irq>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi index 900e8c781f91..4ccb7afc4b35 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -1,9 +1,6 @@ /* * Copyright (C) 2013,2014 Russell King * - * This describes the hookup for an AR8035 to the iMX6 on the SolidRun - * MicroSOM. - * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a @@ -41,6 +38,18 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/gpio/gpio.h> + +/ { + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; @@ -51,7 +60,7 @@ }; &iomuxc { - enet { + microsom { pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 @@ -59,10 +68,10 @@ /* AR8035 reset */ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* AR8035 interrupt */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000 + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 @@ -95,5 +104,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 >; }; + + pinctrl_microsom_uart1: microsom-uart1 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; }; }; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_uart1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi new file mode 100644 index 000000000000..f0be516dc28e --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi @@ -0,0 +1,594 @@ +/* + * Copyright 2015 Technologic Systems + * Copyright 2017 Savoir-Faire Linux + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds1>; + compatible = "gpio-leds"; + + green-led { + label = "green-led"; + gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + red-led { + label = "red-led"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + yel-led { + label = "yellow-led"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-led { + label = "blue-led"; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + en-usb-5v { + label = "en-usb-5v"; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + sel_dc_usb { + label = "sel_dc_usb"; + gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can1_3v3: reg_can1_3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg_can1_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_3v3: en-reg_can2_3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg_can2_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator_wlan_vmmc { + compatible = "regulator-fixed"; + regulator-name = "wlan_vmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + n25q064: flash@0 { + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + cs-gpios = < + &gpio5 31 GPIO_ACTIVE_HIGH + &gpio7 12 GPIO_ACTIVE_HIGH + &gpio5 18 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + m41t00s: rtc@68 { + compatible = "m41t00"; + reg = <0x68>; + }; + + isl12022: rtc@6f { + compatible = "isl,isl12022"; + reg = <0x6f>; + }; + + gpio8: gpio@28 { + compatible = "technologic,ts7970-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + ngpio = <32>; + }; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */ + >; + }; + + pinctrl_ecspi2: ecspi2 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */ + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */ + >; + }; + + pinctrl_enet: enet { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088 + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Onboard */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */ + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */ + + /* Offboard */ + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */ + + /* Strapping only */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_leds1: leds1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */ + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; + +&pcie { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_wlan_vmmc>; + bus-width = <4>; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + fsl,wp-controller; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi new file mode 100644 index 000000000000..5102fc47380b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi @@ -0,0 +1,252 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_pwr>; + enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + turn-on-delay-ms = <35>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + lcd_panel: lcd-panel { + compatible = "edt,etm0700g0dh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + backlight = <&backlight>; + bus-format-override = "rgb24"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_out>; + }; + }; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + u-boot,panel-name = "edt,et057090dhu"; + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + u-boot,panel-name = "edt,et0350g0dh6"; + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + u-boot,panel-name = "edt,et0430g0dh6"; + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + u-boot,panel-name = "edt,etm0700g0dh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + CoMTFT { /* same as ET0700 but with inverted pixel clock */ + u-boot,panel-name = "edt,etm0700g0edh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_in>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi new file mode 100644 index 000000000000..2ca2eb37e14f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi @@ -0,0 +1,286 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_lcd0_pwr>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + power-supply = <®_lcd1_pwr>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + lvds0_panel: lvds0-panel { + compatible = "nlt,nl12880bc20-spwg-24"; + backlight = <&backlight0>; + power-supply = <®_3v3>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + lvds1_panel: lvds1-panel { + compatible = "nlt,nl12880bc20-spwg-24"; + backlight = <&backlight1>; + power-supply = <®_3v3>; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&kpp { + status = "disabled"; /* pad conflict with backlight1 PWM */ +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + display-timings { + hsd100pxn1 { + u-boot,panel-name = "hannstar,hsd100pxn1"; + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + nl12880bc20 { + u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0700 { + u-boot,panel-name = "edt,etm0700g0dh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + u-boot,panel-name = "edt,et057090dhu"; + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + + display-timings { + hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +®_lcd0_pwr { + status = "okay"; +}; + +®_lcd1_pwr { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi new file mode 100644 index 000000000000..4c4e2e1a931f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi @@ -0,0 +1,99 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + backlight0 { + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + turn-on-delay-ms = <35>; + power-supply = <®_lcd1_pwr>; + }; + + backlight1 { + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + turn-on-delay-ms = <35>; + power-supply = <®_lcd1_pwr>; + }; + + lcd-panel { + compatible = "edt,et057090dhu"; + bus-format-override = "rgb24"; + pixelclk-active = <0>; + }; + + lvds0-panel { + compatible = "edt,etml1010g0dka"; + bus-format-override = "spwg-18"; + pixelclk-active = <0>; + }; + + lvds1-panel { + compatible = "edt,etml1010g0dka"; + bus-format-override = "spwg-18"; + pixelclk-active = <0>; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ds1339 { + /* + * The backup voltage of the module internal RTC is not wired + * by default on the MB7, so disable that RTC chip. + */ + status = "disabled"; +}; + +&i2c3 { + rtc: mcp7940x@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +®_lcd0_pwr { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index c6bec97fbeaf..6abb66cd7d4a 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,6 +43,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> / { aliases { @@ -145,7 +146,7 @@ pinctrl-0 = <&pinctrl_lcd0_pwr>; gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-boot-on; + status = "disabled"; }; reg_lcd1_pwr: regulator-lcd1-pwr { @@ -157,7 +158,7 @@ pinctrl-0 = <&pinctrl_lcd1_pwr>; gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-boot-on; + status = "disabled"; }; reg_usbh1_vbus: regulator-usbh1-vbus { @@ -183,24 +184,56 @@ }; sound { - compatible = "karo,imx6qdl-tx6qdl-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; + compatible = "karo,imx6qdl-tx6-sgtl5000", + "simple-audio-card"; + simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <5>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; }; }; &audmux { status = "okay"; + + ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCSEL(4) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + pins5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0) + >; + }; }; &can1 { @@ -241,7 +274,7 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>, @@ -249,6 +282,7 @@ clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <10>; phy-handle = <&etnphy>; phy-supply = <®_3v3_etn>; status = "okay"; @@ -261,8 +295,9 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_mdio>; - interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_etnphy_int>; + interrupt-parent = <&gpio7>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; }; }; }; @@ -276,25 +311,34 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; clock-frequency = <400000>; status = "okay"; ds1339: rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; }; }; &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; clock-frequency = <400000>; status = "okay"; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; reg = <0x0a>; VDDA-supply = <®_2v5>; VDDIO-supply = <®_3v3>; @@ -332,8 +376,6 @@ pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ >; }; @@ -451,12 +493,24 @@ >; }; + pinctrl_etnphy_int: etnphy-intgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ + >; + }; + pinctrl_etnphy_power: etnphy-pwrgrp { fsl,pins = < MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ >; }; + pinctrl_etnphy_rst: etnphy-rstgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 @@ -504,6 +558,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -511,6 +572,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + pinctrl_kpp: kppgrp { fsl,pins = < MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index c96c91d83678..4161b7d4323a 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -28,6 +28,13 @@ status = "disabled"; }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio2 4 0>; + pinctrl-0 = <&pinctrl_power_off>; + pinctrl-names = "default"; + }; + memory { reg = <0x10000000 0x40000000>; }; @@ -172,6 +179,12 @@ >; }; + pinctrl_power_off: poweroffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 + >; + }; + pinctrl_touchscreenp7: touchscreenp7grp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 @@ -208,8 +221,8 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 >; }; @@ -218,8 +231,8 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 >; }; @@ -228,8 +241,8 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi new file mode 100644 index 000000000000..421d6f527609 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Support for Variscite DART-MX6 Module + * + * Copyright 2017 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + memory { + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(2)) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "disabled"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmicec>; + ddc-i2c-bus = <&i2c1>; + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + tlv320aic3106: codec@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + #sound-dai-cells = <0>; + DRVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + ai3x-ocmv = <0>; + gpio-reset = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + /* Audio Clock */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_bt: bt { + fsl,pins = < + /* Bluetooth enable */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1 + /* Bluetooth Slow Clock */ + MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + /* SPI1 CS0 */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + /* SPI1 CS1 */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_hdmicec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + /* PMIC INT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* WL_EN */ + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071 + /* WL_IRQ */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; + +&pcie { + fsl,tx-swing-full = <103>; + fsl,tx-swing-low = <103>; + reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbh1 { + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi new file mode 100644 index 000000000000..3a8a4952d45e --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi @@ -0,0 +1,201 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "imx6qdl-wandboard.dtsi" + +/ { + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + regulator-name = "ETH_PHY"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 13 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&fec { + phy-supply = <®_eth_phy>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index b4fa7f1d63da..ed96d7b5feab 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -82,7 +82,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index eeb7679fd348..72f52fcecee1 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -49,6 +49,7 @@ aliases { mdio-gpio0 = &mdio1; + rtc0 = &ds1341; }; mdio1: mdio { @@ -390,7 +391,7 @@ clock-frequency = <100000>; status = "okay"; - pmic@08 { + pmic@8 { compatible = "fsl,pfuze100"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pfuze100_irq>; @@ -501,7 +502,7 @@ reg = <0x54>; }; - rtc@68 { + ds1341: rtc@68 { compatible = "dallas,ds1341"; reg = <0x68>; }; @@ -543,7 +544,7 @@ rmi4-f01@1 { reg = <0x1>; - syna,nosleep-mode = <1>; + syna,nosleep-mode = <2>; }; rmi4-f11@11 { @@ -580,6 +581,17 @@ pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; status = "okay"; + + host@0 { + reg = <0 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + i210: i210@0 { + reg = <0 0 0 0 0>; + }; + }; }; &usdhc2 { @@ -728,6 +740,7 @@ &usbh1 { vbus-supply = <®_5p0v_main>; + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 8884b4a3cafb..59ff86695a14 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -80,6 +80,75 @@ }; }; + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + }; + + ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds0_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@1 { + reg = <1>; + + lvds0_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds1_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds1>; + }; + }; + + port@1 { + reg = <1>; + + lvds1_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds1>; + }; + }; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gpc>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -87,7 +156,7 @@ interrupt-parent = <&gpc>; ranges; - dma_apbh: dma-apbh@00110000 { + dma_apbh: dma-apbh@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, @@ -100,7 +169,7 @@ clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@00112000 { + gpmi: gpmi-nand@112000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -120,7 +189,7 @@ status = "disabled"; }; - hdmi: hdmi@0120000 { + hdmi: hdmi@120000 { #address-cells = <1>; #size-cells = <0>; reg = <0x00120000 0x9000>; @@ -148,7 +217,7 @@ }; }; - gpu_3d: gpu@00130000 { + gpu_3d: gpu@130000 { compatible = "vivante,gc"; reg = <0x00130000 0x4000>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; @@ -159,7 +228,7 @@ power-domains = <&pd_pu>; }; - gpu_2d: gpu@00134000 { + gpu_2d: gpu@134000 { compatible = "vivante,gc"; reg = <0x00134000 0x4000>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; @@ -169,7 +238,7 @@ power-domains = <&pd_pu>; }; - timer@00a00600 { + timer@a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; @@ -177,7 +246,7 @@ clocks = <&clks IMX6QDL_CLK_TWD>; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -186,7 +255,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@00a02000 { + L2: l2-cache@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -224,26 +293,21 @@ status = "disabled"; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - aips-bus@02000000 { /* AIPS1 */ + aips-bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - spdif: spdif@02004000 { + spdif: spdif@2004000 { compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; @@ -263,7 +327,7 @@ status = "disabled"; }; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -277,7 +341,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -291,7 +355,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -305,7 +369,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -319,7 +383,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; @@ -331,7 +395,7 @@ status = "disabled"; }; - esai: esai@02024000 { + esai: esai@2024000 { #sound-dai-cells = <0>; compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; @@ -347,7 +411,7 @@ status = "disabled"; }; - ssi1: ssi@02028000 { + ssi1: ssi@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; @@ -363,7 +427,7 @@ status = "disabled"; }; - ssi2: ssi@0202c000 { + ssi2: ssi@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; @@ -379,7 +443,7 @@ status = "disabled"; }; - ssi3: ssi@02030000 { + ssi3: ssi@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; @@ -395,7 +459,7 @@ status = "disabled"; }; - asrc: asrc@02034000 { + asrc: asrc@2034000 { compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; @@ -420,12 +484,12 @@ status = "okay"; }; - spba@0203c000 { + spba@203c000 { reg = <0x0203c000 0x4000>; }; }; - vpu: vpu@02040000 { + vpu: vpu@2040000 { compatible = "cnm,coda960"; reg = <0x02040000 0x3c000>; interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, @@ -439,11 +503,11 @@ iram = <&ocram>; }; - aipstz@0207c000 { /* AIPSTZ1 */ + aipstz@207c000 { /* AIPSTZ1 */ reg = <0x0207c000 0x4000>; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; @@ -454,7 +518,7 @@ status = "disabled"; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; @@ -465,7 +529,7 @@ status = "disabled"; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; @@ -476,7 +540,7 @@ status = "disabled"; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; @@ -487,7 +551,7 @@ status = "disabled"; }; - can1: flexcan@02090000 { + can1: flexcan@2090000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -497,7 +561,7 @@ status = "disabled"; }; - can2: flexcan@02094000 { + can2: flexcan@2094000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; @@ -507,7 +571,7 @@ status = "disabled"; }; - gpt: gpt@02098000 { + gpt: gpt@2098000 { compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; @@ -517,7 +581,7 @@ clock-names = "ipg", "per", "osc_per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, @@ -528,7 +592,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, @@ -539,7 +603,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, @@ -550,7 +614,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, @@ -561,7 +625,7 @@ #interrupt-cells = <2>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, @@ -572,7 +636,7 @@ #interrupt-cells = <2>; }; - gpio6: gpio@020b0000 { + gpio6: gpio@20b0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>; interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, @@ -583,7 +647,7 @@ #interrupt-cells = <2>; }; - gpio7: gpio@020b4000 { + gpio7: gpio@20b4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, @@ -594,7 +658,7 @@ #interrupt-cells = <2>; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; @@ -602,14 +666,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_DUMMY>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; @@ -617,7 +681,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, @@ -625,14 +689,17 @@ #clock-cells = <1>; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; - regulator-1p1 { + regulator-1p1@20c8110 { + reg = <0x20c8110>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <1000000>; @@ -647,7 +714,8 @@ anatop-enable-bit = <0>; }; - regulator-3p0 { + regulator-3p0@20c8120 { + reg = <0x20c8120>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -662,7 +730,8 @@ anatop-enable-bit = <0>; }; - regulator-2p5 { + regulator-2p5@20c8130 { + reg = <0x20c8130>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2250000>; @@ -677,7 +746,8 @@ anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore { + reg_arm: regulator-vddcore@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -694,7 +764,8 @@ anatop-max-voltage = <1450000>; }; - reg_pu: regulator-vddpu { + reg_pu: regulator-vddpu@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddpu"; regulator-min-microvolt = <725000>; @@ -711,7 +782,8 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc { + reg_soc: regulator-vddsoc@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -729,15 +801,7 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - }; - - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; @@ -745,7 +809,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; @@ -753,7 +817,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -773,19 +837,23 @@ mask = <0x60>; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6q-snvs-lpgpr"; + }; }; - epit1: epit@020d0000 { /* EPIT1 */ + epit1: epit@20d0000 { /* EPIT1 */ reg = <0x020d0000 0x4000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { /* EPIT2 */ + epit2: epit@20d4000 { /* EPIT2 */ reg = <0x020d4000 0x4000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6q-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -793,7 +861,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -826,9 +894,9 @@ }; }; - gpr: iomuxc-gpr@020e0000 { + gpr: iomuxc-gpr@20e0000 { compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; - reg = <0x020e0000 0x38>; + reg = <0x20e0000 0x38>; mux: mux-controller { compatible = "mmio-mux"; @@ -836,76 +904,22 @@ }; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - ldb: ldb { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; - gpr = <&gpr>; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@1 { - reg = <1>; - - lvds0_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds1_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds1>; - }; - }; - - port@1 { - reg = <1>; - - lvds1_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds1>; - }; - }; - }; + reg = <0x20e0000 0x4000>; }; - dcic1: dcic@020e4000 { + dcic1: dcic@20e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; }; - dcic2: dcic@020e8000 { + dcic2: dcic@20e8000 { reg = <0x020e8000 0x4000>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; @@ -917,7 +931,7 @@ }; }; - aips-bus@02100000 { /* AIPS2 */ + aips-bus@2100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -950,11 +964,11 @@ }; }; - aipstz@0217c000 { /* AIPSTZ2 */ + aipstz@217c000 { /* AIPSTZ2 */ reg = <0x0217c000 0x4000>; }; - usbotg: usb@02184000 { + usbotg: usb@2184000 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; @@ -967,7 +981,7 @@ status = "disabled"; }; - usbh1: usb@02184200 { + usbh1: usb@2184200 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; @@ -981,7 +995,7 @@ status = "disabled"; }; - usbh2: usb@02184400 { + usbh2: usb@2184400 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; @@ -994,7 +1008,7 @@ status = "disabled"; }; - usbh3: usb@02184600 { + usbh3: usb@2184600 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; @@ -1007,16 +1021,17 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6QDL_CLK_USBOH3>; }; - fec: ethernet@02188000 { + fec: ethernet@2188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; interrupts-extended = <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; @@ -1027,14 +1042,14 @@ status = "disabled"; }; - mlb@0218c000 { + mlb@218c000 { reg = <0x0218c000 0x4000>; interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; @@ -1046,7 +1061,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; @@ -1058,7 +1073,7 @@ status = "disabled"; }; - usdhc3: usdhc@02198000 { + usdhc3: usdhc@2198000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; @@ -1070,7 +1085,7 @@ status = "disabled"; }; - usdhc4: usdhc@0219c000 { + usdhc4: usdhc@219c000 { compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; @@ -1082,7 +1097,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -1092,7 +1107,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -1102,7 +1117,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -1112,20 +1127,20 @@ status = "disabled"; }; - romcp@021ac000 { + romcp@21ac000 { reg = <0x021ac000 0x4000>; }; - mmdc0: mmdc@021b0000 { /* MMDC0 */ + mmdc0: mmdc@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - mmdc1: mmdc@021b4000 { /* MMDC1 */ + mmdc1: mmdc@21b4000 { /* MMDC1 */ reg = <0x021b4000 0x4000>; }; - weim: weim@021b8000 { + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6q-weim"; @@ -1136,29 +1151,29 @@ status = "disabled"; }; - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6QDL_CLK_IIM>; }; - tzasc@021d0000 { /* TZASC1 */ + tzasc@21d0000 { /* TZASC1 */ reg = <0x021d0000 0x4000>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; }; - tzasc@021d4000 { /* TZASC2 */ + tzasc@21d4000 { /* TZASC2 */ reg = <0x021d4000 0x4000>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; }; - audmux: audmux@021d8000 { + audmux: audmux@21d8000 { compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; }; - mipi_csi: mipi@021dc000 { + mipi_csi: mipi@21dc000 { compatible = "fsl,imx6-mipi-csi2"; reg = <0x021dc000 0x4000>; #address-cells = <1>; @@ -1171,7 +1186,7 @@ status = "disabled"; }; - mipi_dsi: mipi@021e0000 { + mipi_dsi: mipi@21e0000 { #address-cells = <1>; #size-cells = <0>; reg = <0x021e0000 0x4000>; @@ -1199,14 +1214,14 @@ }; }; - vdoa@021e4000 { + vdoa@21e4000 { compatible = "fsl,imx6q-vdoa"; reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_VDOA>; }; - uart2: serial@021e8000 { + uart2: serial@21e8000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; @@ -1218,7 +1233,7 @@ status = "disabled"; }; - uart3: serial@021ec000 { + uart3: serial@21ec000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; @@ -1230,7 +1245,7 @@ status = "disabled"; }; - uart4: serial@021f0000 { + uart4: serial@21f0000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; @@ -1242,7 +1257,7 @@ status = "disabled"; }; - uart5: serial@021f4000 { + uart5: serial@21f4000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; @@ -1255,7 +1270,7 @@ }; }; - ipu1: ipu@02400000 { + ipu1: ipu@2400000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ipu"; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts new file mode 100644 index 000000000000..92b38e6699aa --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp-tx6qp-8037.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts new file mode 100644 index 000000000000..ffc0f2ee11d2 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6QP-8037 Module"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts new file mode 100644 index 000000000000..07ad70718aec --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp-tx6qp-8137.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ipu2 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts new file mode 100644 index 000000000000..dd494d587014 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts @@ -0,0 +1,90 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" + +/ { + model = "Ka-Ro electronics TX6QP-8137 Module"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts new file mode 100644 index 000000000000..f7badd82ce8a --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 QuadPlus Board revD1"; + compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 299d863690c5..5f4fdce715c1 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -44,19 +44,19 @@ / { soc { - ocram2: sram@00940000 { + ocram2: sram@940000 { compatible = "mmio-sram"; reg = <0x00940000 0x20000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - ocram3: sram@00960000 { + ocram3: sram@960000 { compatible = "mmio-sram"; reg = <0x00960000 0x20000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@02100000 { + aips-bus@2100000 { pre1: pre@21c8000 { compatible = "fsl,imx6qp-pre"; reg = <0x021c8000 0x1000>; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 0a90eea17018..2844ab541759 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -20,7 +20,7 @@ reg = <0x80000000 0x40000000>; }; - backlight { + backlight_display: backlight_display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -39,58 +39,54 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; - reg_usb_otg2_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; - reg_aud3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "wm8962-supply-3v15"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-boot-on; - }; + reg_aud3v: regulator-aud3v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; - reg_aud4v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "wm8962-supply-4v2"; - regulator-min-microvolt = <4325000>; - regulator-max-microvolt = <4325000>; - regulator-boot-on; - }; + reg_aud4v: regulator-aud4v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; - reg_lcd_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "lcd-3v3"; - gpio = <&gpio4 3 0>; - enable-active-high; - }; + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; sound { @@ -108,6 +104,19 @@ mux-int-port = <2>; mux-ext-port = <3>; }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; }; &audmux { @@ -145,7 +154,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -546,31 +555,11 @@ &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; status = "okay"; - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 3f76f980947e..ae8df3cf687e 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -76,7 +76,7 @@ }; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -102,6 +102,21 @@ }; }; + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gpc>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -109,13 +124,13 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; - L2: l2-cache@00a02000 { + L2: l2-cache@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -125,26 +140,21 @@ arm,data-latency = <4 2 3>; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba: spba-bus@02000000 { + spba: spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - spdif: spdif@02004000 { + spdif: spdif@2004000 { compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; @@ -165,7 +175,7 @@ status = "disabled"; }; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -177,7 +187,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -189,7 +199,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -201,7 +211,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -213,7 +223,7 @@ status = "disabled"; }; - uart5: serial@02018000 { + uart5: serial@2018000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; @@ -226,7 +236,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; @@ -239,7 +249,7 @@ status = "disabled"; }; - uart2: serial@02024000 { + uart2: serial@2024000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; @@ -252,7 +262,7 @@ status = "disabled"; }; - ssi1: ssi@02028000 { + ssi1: ssi@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; @@ -268,7 +278,7 @@ status = "disabled"; }; - ssi2: ssi@0202c000 { + ssi2: ssi@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; @@ -284,7 +294,7 @@ status = "disabled"; }; - ssi3: ssi@02030000 { + ssi3: ssi@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; @@ -300,7 +310,7 @@ status = "disabled"; }; - uart3: serial@02034000 { + uart3: serial@2034000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02034000 0x4000>; @@ -313,7 +323,7 @@ status = "disabled"; }; - uart4: serial@02038000 { + uart4: serial@2038000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02038000 0x4000>; @@ -327,7 +337,7 @@ }; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; @@ -337,7 +347,7 @@ clock-names = "ipg", "per"; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; @@ -347,7 +357,7 @@ clock-names = "ipg", "per"; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; @@ -357,7 +367,7 @@ clock-names = "ipg", "per"; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; @@ -367,7 +377,7 @@ clock-names = "ipg", "per"; }; - gpt: gpt@02098000 { + gpt: gpt@2098000 { compatible = "fsl,imx6sl-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; @@ -376,7 +386,7 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, @@ -393,7 +403,7 @@ <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, @@ -411,7 +421,7 @@ <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, @@ -430,7 +440,7 @@ <&iomuxc 31 102 1>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, @@ -456,7 +466,7 @@ <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, @@ -478,7 +488,7 @@ <&iomuxc 21 161 1>; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; @@ -486,14 +496,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_DUMMY>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; @@ -501,7 +511,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6sl-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, @@ -509,7 +519,7 @@ #clock-cells = <1>; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6sl-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; @@ -517,8 +527,11 @@ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; - regulator-1p1 { + regulator-1p1@20c8110 { + reg = <0x20c8110>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -533,7 +546,8 @@ anatop-enable-bit = <0>; }; - regulator-3p0 { + regulator-3p0@20c8120 { + reg = <0x20c8120>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -548,7 +562,8 @@ anatop-enable-bit = <0>; }; - regulator-2p5 { + regulator-2p5@20c8130 { + reg = <0x20c8130>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2100000>; @@ -563,7 +578,8 @@ anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore { + reg_arm: regulator-vddcore@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -580,7 +596,8 @@ anatop-max-voltage = <1450000>; }; - reg_pu: regulator-vddpu { + reg_pu: regulator-vddpu@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddpu"; regulator-min-microvolt = <725000>; @@ -597,7 +614,8 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc { + reg_soc: regulator-vddsoc@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -615,15 +633,7 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; - }; - - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; @@ -631,7 +641,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; @@ -639,7 +649,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -661,17 +671,17 @@ }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6sl-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -679,7 +689,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -692,28 +702,28 @@ #power-domain-cells = <1>; }; - gpr: iomuxc-gpr@020e0000 { + gpr: iomuxc-gpr@20e0000 { compatible = "fsl,imx6sl-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e0000 0x38>; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6sl-iomuxc"; reg = <0x020e0000 0x4000>; }; - csi: csi@020e4000 { + csi: csi@20e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; - spdc: spdc@020e8000 { + spdc: spdc@20e8000 { reg = <0x020e8000 0x4000>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; @@ -725,17 +735,17 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; - pxp: pxp@020f0000 { + pxp: pxp@20f0000 { reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; }; - epdc: epdc@020f4000 { + epdc: epdc@20f4000 { reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; - lcdif: lcdif@020f8000 { + lcdif: lcdif@20f8000 { compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; @@ -746,7 +756,7 @@ status = "disabled"; }; - dcp: dcp@020fc000 { + dcp: dcp@20fc000 { compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; reg = <0x020fc000 0x4000>; interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, @@ -755,14 +765,14 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - usbotg1: usb@02184000 { + usbotg1: usb@2184000 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; @@ -775,7 +785,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; @@ -788,7 +798,7 @@ status = "disabled"; }; - usbh: usb@02184400 { + usbh: usb@2184400 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; @@ -801,14 +811,14 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SL_CLK_USBOH3>; }; - fec: ethernet@02188000 { + fec: ethernet@2188000 { compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; reg = <0x02188000 0x4000>; interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; @@ -818,7 +828,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; @@ -830,7 +840,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; @@ -842,7 +852,7 @@ status = "disabled"; }; - usdhc3: usdhc@02198000 { + usdhc3: usdhc@2198000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; @@ -854,7 +864,7 @@ status = "disabled"; }; - usdhc4: usdhc@0219c000 { + usdhc4: usdhc@219c000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; @@ -866,7 +876,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; @@ -876,7 +886,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; @@ -886,7 +896,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; @@ -896,17 +906,17 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + mmdc: mmdc@21b0000 { compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - rngb: rngb@021b4000 { + rngb: rngb@21b4000 { reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; }; - weim: weim@021b8000 { + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; reg = <0x021b8000 0x4000>; @@ -915,13 +925,13 @@ status = "disabled"; }; - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SL_CLK_OCOTP>; }; - audmux: audmux@021d8000 { + audmux: audmux@21d8000 { compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index c5578d1c1ee4..f9d40ee14982 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -231,7 +231,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 71005478cdf0..e3533e74ccc8 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -18,7 +18,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index c0139d7e497a..6dd9bebfe027 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -18,7 +18,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze200"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index da815527a7f8..d35aa858f9db 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -24,7 +24,7 @@ reg = <0x80000000 0x40000000>; }; - backlight { + backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -49,86 +49,91 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + vcc_sd3: regulator-vcc-sd3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vcc_sd3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg2_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_psu_5v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "PSU-5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_lcd_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "lcd-3v3"; - gpio = <&gpio3 27 0>; - enable-active-high; - }; - - reg_peri_3v3: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_enet_3v3: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3v3>; - regulator-name = "enet_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - }; + reg_psu_5v: regulator-psu-5v { + compatible = "regulator-fixed"; + regulator-name = "PSU-5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + }; + + reg_peri_3v3: regulator-peri-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet_3v3: regulator-enet-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + }; + + reg_pcie_gpio: regulator-pcie-gpio { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; sound { @@ -146,6 +151,19 @@ mux-int-port = <2>; mux-ext-port = <6>; }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; }; &audmux { @@ -212,34 +230,22 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_gpio>; + status = "okay"; +}; + &lcdif1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; status = "okay"; - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; @@ -453,6 +459,18 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 + >; + }; + pinctrl_peri_3v3: peri3v3grp { fsl,pins = < MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts new file mode 100644 index 000000000000..4d8c6521845f --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -0,0 +1,572 @@ +/* + * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "imx6sx.dtsi" + +/ { + model = "Softing VIN|ING 2000"; + compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + reg_usb_otg1_vbus: regulator-usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_peri_3v3: regulator-peri_3v3 { + compatible = "regulator-fixed"; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pwmleds { + compatible = "pwm-leds"; + + red { + label = "red"; + max-brightness = <255>; + pwms = <&pwm6 0 50000>; + }; + + green { + label = "green"; + max-brightness = <255>; + pwms = <&pwm2 0 50000>; + }; + + blue { + label = "blue"; + max-brightness = <255>; + pwms = <&pwm1 0 50000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_peri_3v3>; + status = "okay"; +}; + +&cpu0 { + /* + * This board has a shared rail of reg_arm and reg_soc (supplied by + * sw1a_reg) which is modeled below, but still this module behaves + * unstable without higher voltages. Hence, set higher voltages here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <®_peri_3v3>; + phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet0-phy@0 { + reg = <0>; + max-speed = <100>; + interrupt-parent = <&gpio2>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-supply = <®_peri_3v3>; + phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet1-phy@0 { + reg = <0>; + max-speed = <100>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + proximity: sx9500@28 { + compatible = "semtech,sx9500"; + reg = <0x28>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sx9500>; + interrupt-parent = <&gpio2>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 + MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 + /* LAN8720 PHY Reset */ + MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 + /* MDIO */ + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 + /* IRQ from PHY */ + MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 + MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 + /* LAN8720 PHY Reset */ + MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 + /* MDIO */ + MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 + MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 + /* IRQ from PHY */ + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + /* reset external uC */ + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 + /* IRQ from external uC */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 + /* overcurrent detection */ + MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp-1 { + fsl,pins = < + /* blue LED */ + MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp-1 { + fsl,pins = < + /* green LED */ + MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm6: pwm6grp-1 { + fsl,pins = < + /* red LED */ + MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 + >; + }; + + pinctrl_sx9500: sx9500grp { + fsl,pins = < + /* Reset */ + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 + /* IRQ */ + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_soc { + vin-supply = <&sw1a_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + /* hs200-mode is currently unsupported because Vccq is on 3.1V, but + * not on necessary 1.8V. + */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + bus-width = <8>; + keep-power-in-suspend; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi index dcfc97591433..53b3eac94f0d 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -135,7 +135,7 @@ clock-frequency = <100000>; status = "okay"; - pmic: pmic@08 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 6c7eb54be9e2..fd7879342d0d 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -95,7 +95,7 @@ }; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -141,6 +141,22 @@ }; }; + tempmon: tempmon { + compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -148,18 +164,13 @@ interrupt-parent = <&gpc>; ranges; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; - L2: l2-cache@00a02000 { + L2: l2-cache@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; @@ -169,7 +180,7 @@ arm,data-latency = <4 2 3>; }; - gpu: gpu@01800000 { + gpu: gpu@1800000 { compatible = "vivante,gc"; reg = <0x01800000 0x4000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -179,7 +190,7 @@ clock-names = "bus", "core", "shader"; }; - dma_apbh: dma-apbh@01804000 { + dma_apbh: dma-apbh@1804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, @@ -192,7 +203,7 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@01806000{ + gpmi: gpmi-nand@1806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -212,21 +223,21 @@ status = "disabled"; }; - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - spdif: spdif@02004000 { + spdif: spdif@2004000 { compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -248,7 +259,7 @@ status = "disabled"; }; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -260,7 +271,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -272,7 +283,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -284,7 +295,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -296,7 +307,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; @@ -309,7 +320,7 @@ status = "disabled"; }; - esai: esai@02024000 { + esai: esai@2024000 { reg = <0x02024000 0x4000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -322,7 +333,7 @@ status = "disabled"; }; - ssi1: ssi@02028000 { + ssi1: ssi@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; @@ -336,7 +347,7 @@ status = "disabled"; }; - ssi2: ssi@0202c000 { + ssi2: ssi@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; @@ -350,7 +361,7 @@ status = "disabled"; }; - ssi3: ssi@02030000 { + ssi3: ssi@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; @@ -364,7 +375,7 @@ status = "disabled"; }; - asrc: asrc@02034000 { + asrc: asrc@2034000 { reg = <0x02034000 0x4000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_ASRC_MEM>, @@ -381,7 +392,7 @@ }; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -391,7 +402,7 @@ #pwm-cells = <2>; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -401,7 +412,7 @@ #pwm-cells = <2>; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -411,7 +422,7 @@ #pwm-cells = <2>; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -421,7 +432,7 @@ #pwm-cells = <2>; }; - flexcan1: can@02090000 { + flexcan1: can@2090000 { compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -431,7 +442,7 @@ status = "disabled"; }; - flexcan2: can@02094000 { + flexcan2: can@2094000 { compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; @@ -441,7 +452,7 @@ status = "disabled"; }; - gpt: gpt@02098000 { + gpt: gpt@2098000 { compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -450,7 +461,7 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, @@ -462,7 +473,7 @@ gpio-ranges = <&iomuxc 0 5 26>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, @@ -474,7 +485,7 @@ gpio-ranges = <&iomuxc 0 31 20>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, @@ -486,7 +497,7 @@ gpio-ranges = <&iomuxc 0 51 29>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -498,7 +509,7 @@ gpio-ranges = <&iomuxc 0 80 32>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, @@ -510,7 +521,7 @@ gpio-ranges = <&iomuxc 0 112 24>; }; - gpio6: gpio@020b0000 { + gpio6: gpio@20b0000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, @@ -522,7 +533,7 @@ gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; }; - gpio7: gpio@020b4000 { + gpio7: gpio@20b4000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, @@ -534,7 +545,7 @@ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -542,14 +553,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_DUMMY>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -557,7 +568,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6sx-ccm"; reg = <0x020c4000 0x4000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, @@ -567,15 +578,18 @@ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; - regulator-1p1 { + regulator-1p1@20c8110 { + reg = <0x20c8110>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -590,7 +604,8 @@ anatop-enable-bit = <0>; }; - regulator-3p0 { + regulator-3p0@20c8120 { + reg = <0x20c8120>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -605,7 +620,8 @@ anatop-enable-bit = <0>; }; - regulator-2p5 { + regulator-2p5@20c8130 { + reg = <0x20c8130>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2100000>; @@ -620,7 +636,8 @@ anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore { + reg_arm: regulator-vddcore@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -637,7 +654,8 @@ anatop-max-voltage = <1450000>; }; - reg_pcie: regulator-vddpcie { + reg_pcie: regulator-vddpcie@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddpcie"; regulator-min-microvolt = <725000>; @@ -653,7 +671,8 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc { + reg_soc: regulator-vddsoc@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -671,15 +690,7 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - }; - - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -687,7 +698,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -695,7 +706,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -724,17 +735,17 @@ }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6sx-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -742,27 +753,40 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; #interrupt-cells = <3>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; + clocks = <&clks IMX6SX_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pd_pci: power-domain@3 { + reg = <3>; + #power-domain-cells = <0>; + power-supply = <®_pcie>; + }; + }; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6sx-iomuxc"; reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@020e4000 { + gpr: iomuxc-gpr@20e4000 { compatible = "fsl,imx6sx-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -775,7 +799,7 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -809,7 +833,7 @@ }; }; - usbotg1: usb@02184000 { + usbotg1: usb@2184000 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -823,7 +847,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; @@ -836,7 +860,7 @@ status = "disabled"; }; - usbh: usb@02184400 { + usbh: usb@2184400 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; @@ -851,16 +875,17 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SX_CLK_USBOH3>; }; - fec1: ethernet@02188000 { + fec1: ethernet@2188000 { compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_ENET>, @@ -875,7 +900,7 @@ status = "disabled"; }; - mlb: mlb@0218c000 { + mlb: mlb@218c000 { reg = <0x0218c000 0x4000>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, @@ -884,7 +909,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02190000 0x4000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -896,7 +921,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02194000 0x4000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -908,7 +933,7 @@ status = "disabled"; }; - usdhc3: usdhc@02198000 { + usdhc3: usdhc@2198000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02198000 0x4000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; @@ -920,7 +945,7 @@ status = "disabled"; }; - usdhc4: usdhc@0219c000 { + usdhc4: usdhc@219c000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; @@ -932,7 +957,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -942,7 +967,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -952,7 +977,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -962,14 +987,15 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + mmdc: mmdc@21b0000 { compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - fec2: ethernet@021b4000 { + fec2: ethernet@21b4000 { compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; reg = <0x021b4000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_ENET>, @@ -982,7 +1008,7 @@ status = "disabled"; }; - weim: weim@021b8000 { + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; @@ -993,13 +1019,23 @@ status = "disabled"; }; - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6sx-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; - sai1: sai@021d4000 { + sai1: sai@21d4000 { compatible = "fsl,imx6sx-sai"; reg = <0x021d4000 0x4000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; @@ -1012,13 +1048,13 @@ status = "disabled"; }; - audmux: audmux@021d8000 { + audmux: audmux@21d8000 { compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; }; - sai2: sai@021dc000 { + sai2: sai@21dc000 { compatible = "fsl,imx6sx-sai"; reg = <0x021dc000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -1031,7 +1067,7 @@ status = "disabled"; }; - qspi1: qspi@021e0000 { + qspi1: qspi@21e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-qspi"; @@ -1044,7 +1080,7 @@ status = "disabled"; }; - qspi2: qspi@021e4000 { + qspi2: qspi@21e4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-qspi"; @@ -1057,7 +1093,7 @@ status = "disabled"; }; - uart2: serial@021e8000 { + uart2: serial@21e8000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; @@ -1070,7 +1106,7 @@ status = "disabled"; }; - uart3: serial@021ec000 { + uart3: serial@21ec000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; @@ -1083,7 +1119,7 @@ status = "disabled"; }; - uart4: serial@021f0000 { + uart4: serial@21f0000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; @@ -1096,7 +1132,7 @@ status = "disabled"; }; - uart5: serial@021f4000 { + uart5: serial@21f4000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; @@ -1109,7 +1145,7 @@ status = "disabled"; }; - i2c4: i2c@021f8000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -1120,21 +1156,21 @@ }; }; - aips3: aips-bus@02200000 { + aips3: aips-bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02200000 0x100000>; ranges; - spba-bus@02200000 { + spba-bus@2240000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02240000 0x40000>; ranges; - csi1: csi@02214000 { + csi1: csi@2214000 { reg = <0x02214000 0x4000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, @@ -1144,7 +1180,7 @@ status = "disabled"; }; - pxp: pxp@02218000 { + pxp: pxp@2218000 { reg = <0x02218000 0x4000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_PXP_AXI>, @@ -1153,7 +1189,7 @@ status = "disabled"; }; - csi2: csi@0221c000 { + csi2: csi@221c000 { reg = <0x0221c000 0x4000>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, @@ -1163,7 +1199,7 @@ status = "disabled"; }; - lcdif1: lcdif@02220000 { + lcdif1: lcdif@2220000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02220000 0x4000>; interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; @@ -1174,7 +1210,7 @@ status = "disabled"; }; - lcdif2: lcdif@02224000 { + lcdif2: lcdif@2224000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02224000 0x4000>; interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; @@ -1185,7 +1221,7 @@ status = "disabled"; }; - vadc: vadc@02228000 { + vadc: vadc@2228000 { reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; reg-names = "vadc-vafe", "vadc-vdec"; clocks = <&clks IMX6SX_CLK_VADC>, @@ -1195,7 +1231,7 @@ }; }; - adc1: adc@02280000 { + adc1: adc@2280000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; reg = <0x02280000 0x4000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; @@ -1206,7 +1242,7 @@ status = "disabled"; }; - adc2: adc@02284000 { + adc2: adc@2284000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; reg = <0x02284000 0x4000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; @@ -1217,7 +1253,7 @@ status = "disabled"; }; - wdog3: wdog@02288000 { + wdog3: wdog@2288000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x02288000 0x4000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; @@ -1225,7 +1261,7 @@ status = "disabled"; }; - ecspi5: ecspi@0228c000 { + ecspi5: ecspi@228c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -1237,7 +1273,7 @@ status = "disabled"; }; - uart6: serial@022a0000 { + uart6: serial@22a0000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x022a0000 0x4000>; @@ -1250,7 +1286,7 @@ status = "disabled"; }; - pwm5: pwm@022a4000 { + pwm5: pwm@22a4000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022a4000 0x4000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -1260,7 +1296,7 @@ #pwm-cells = <2>; }; - pwm6: pwm@022a8000 { + pwm6: pwm@22a8000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022a8000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -1270,7 +1306,7 @@ #pwm-cells = <2>; }; - pwm7: pwm@022ac000 { + pwm7: pwm@22ac000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022ac000 0x4000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -1280,7 +1316,7 @@ #pwm-cells = <2>; }; - pwm8: pwm@0022b0000 { + pwm8: pwm@22b0000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x0022b0000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -1293,25 +1329,29 @@ pcie: pcie@8ffc000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x4000>; /* DBI */ + reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 - /* downstream I/O */ - 0x81000000 0 0 0x08f80000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + power-domains = <&pd_pci>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 9c23e017d86a..18fdb088ba1e 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -30,19 +30,14 @@ status = "okay"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - reg_sd1_vmmc: sd1_regulator { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { @@ -147,6 +142,8 @@ &lcdif { + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 7d7254b12a75..3bf26ebd4df9 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -175,7 +175,7 @@ reg = <1>; max-speed = <100>; interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -186,7 +186,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -223,7 +223,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; clocks = <&sys_mclk>; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts index 28d055e3f301..2d80f7b50bc0 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts @@ -116,7 +116,7 @@ }; &i2c2 { - /delete-node/ codec@0a; + /delete-node/ codec@a; /delete-node/ touchscreen@48; rtc: mcp7940x@6f { diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index ec745eb3b6a8..65111f9843f4 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -362,7 +362,7 @@ clock-frequency = <400000>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; #sound-dai-cells = <0>; @@ -424,7 +424,7 @@ display = <&display>; status = "okay"; - display: display@di0 { + display: disp0 { bits-per-pixel = <32>; bus-width = <24>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index f11a241a340d..5d6c3ba36cd1 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -68,12 +68,14 @@ clock-latency = <61036>; /* two CLK32 periods */ operating-points = < /* kHz uV */ + 696000 1275000 528000 1175000 396000 1025000 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ + 696000 1275000 528000 1175000 396000 1175000 198000 1175000 @@ -98,7 +100,7 @@ }; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -136,6 +138,23 @@ clock-output-names = "ipp_di1"; }; + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -143,18 +162,12 @@ interrupt-parent = <&gpc>; ranges; - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; }; - dma_apbh: dma-apbh@01804000 { + dma_apbh: dma-apbh@1804000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, @@ -167,7 +180,7 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; - gpmi: gpmi-nand@01806000 { + gpmi: gpmi-nand@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -187,21 +200,21 @@ status = "disabled"; }; - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -213,7 +226,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -225,7 +238,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -237,7 +250,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -249,7 +262,7 @@ status = "disabled"; }; - uart7: serial@02018000 { + uart7: serial@2018000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02018000 0x4000>; @@ -260,7 +273,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02020000 0x4000>; @@ -271,7 +284,7 @@ status = "disabled"; }; - uart8: serial@02024000 { + uart8: serial@2024000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02024000 0x4000>; @@ -282,7 +295,7 @@ status = "disabled"; }; - sai1: sai@02028000 { + sai1: sai@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x02028000 0x4000>; @@ -297,7 +310,7 @@ status = "disabled"; }; - sai2: sai@0202c000 { + sai2: sai@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x0202c000 0x4000>; @@ -312,7 +325,7 @@ status = "disabled"; }; - sai3: sai@02030000 { + sai3: sai@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x02030000 0x4000>; @@ -328,7 +341,7 @@ }; }; - tsc: tsc@02040000 { + tsc: tsc@2040000 { compatible = "fsl,imx6ul-tsc"; reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, @@ -339,7 +352,7 @@ status = "disabled"; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; @@ -350,7 +363,7 @@ status = "disabled"; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; @@ -361,7 +374,7 @@ status = "disabled"; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; @@ -372,7 +385,7 @@ status = "disabled"; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -383,7 +396,7 @@ status = "disabled"; }; - can1: flexcan@02090000 { + can1: flexcan@2090000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -393,7 +406,7 @@ status = "disabled"; }; - can2: flexcan@02094000 { + can2: flexcan@2094000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; @@ -403,7 +416,7 @@ status = "disabled"; }; - gpt1: gpt@02098000 { + gpt1: gpt@2098000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x02098000 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -412,7 +425,7 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, @@ -425,7 +438,7 @@ <&iomuxc 16 33 16>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, @@ -437,7 +450,7 @@ gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, @@ -449,7 +462,7 @@ gpio-ranges = <&iomuxc 0 65 29>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -461,7 +474,7 @@ gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, @@ -473,9 +486,10 @@ gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; }; - fec2: ethernet@020b4000 { + fec2: ethernet@20b4000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x020b4000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_ENET>, @@ -490,7 +504,7 @@ status = "disabled"; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -498,14 +512,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_WDOG1>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -513,7 +527,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6ul-ccm"; reg = <0x020c4000 0x4000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, @@ -523,15 +537,18 @@ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; - reg_3p0: regulator-3p0 { + reg_3p0: regulator-3p0@20c8110 { + reg = <0x20c8110>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2625000>; @@ -545,7 +562,8 @@ anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore { + reg_arm: regulator-vddcore@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "cpu"; regulator-min-microvolt = <725000>; @@ -562,7 +580,8 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc { + reg_soc: regulator-vddsoc@20c8140 { + reg = <0x20c8140>; compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -580,7 +599,7 @@ }; }; - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -589,7 +608,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -598,7 +617,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -626,19 +645,23 @@ linux,keycode = <KEY_POWER>; wakeup-source; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6ul-snvs-lpgpr"; + }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6ul-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -646,7 +669,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -655,18 +678,18 @@ interrupt-parent = <&intc>; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6ul-iomuxc"; reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@020e4000 { + gpr: iomuxc-gpr@20e4000 { compatible = "fsl,imx6ul-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; - gpt2: gpt@020e8000 { + gpt2: gpt@20e8000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x020e8000 0x4000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; @@ -675,7 +698,7 @@ clock-names = "ipg", "per"; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; @@ -687,7 +710,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; - pwm5: pwm@020f0000 { + pwm5: pwm@20f0000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f0000 0x4000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -698,7 +721,7 @@ status = "disabled"; }; - pwm6: pwm@020f4000 { + pwm6: pwm@20f4000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f4000 0x4000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; @@ -709,7 +732,7 @@ status = "disabled"; }; - pwm7: pwm@020f8000 { + pwm7: pwm@20f8000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f8000 0x4000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; @@ -720,7 +743,7 @@ status = "disabled"; }; - pwm8: pwm@020fc000 { + pwm8: pwm@20fc000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020fc000 0x4000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; @@ -732,14 +755,14 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - usbotg1: usb@02184000 { + usbotg1: usb@2184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -753,7 +776,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; @@ -766,15 +789,16 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; }; - fec1: ethernet@02188000 { + fec1: ethernet@2188000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_ENET>, @@ -789,7 +813,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02190000 0x4000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -801,7 +825,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02194000 0x4000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -813,7 +837,7 @@ status = "disabled"; }; - adc1: adc@02198000 { + adc1: adc@2198000 { compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; reg = <0x02198000 0x4000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; @@ -825,7 +849,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -835,7 +859,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -845,7 +869,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -855,18 +879,28 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + mmdc: mmdc@21b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - ocotp: ocotp-ctrl@021bc000 { + ocotp: ocotp-ctrl@21bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6ul-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6UL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; - lcdif: lcdif@021c8000 { + lcdif: lcdif@21c8000 { compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; reg = <0x021c8000 0x4000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -877,7 +911,7 @@ status = "disabled"; }; - qspi: qspi@021e0000 { + qspi: qspi@21e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; @@ -890,7 +924,7 @@ status = "disabled"; }; - uart2: serial@021e8000 { + uart2: serial@21e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021e8000 0x4000>; @@ -901,7 +935,7 @@ status = "disabled"; }; - uart3: serial@021ec000 { + uart3: serial@21ec000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021ec000 0x4000>; @@ -912,7 +946,7 @@ status = "disabled"; }; - uart4: serial@021f0000 { + uart4: serial@21f0000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021f0000 0x4000>; @@ -923,7 +957,7 @@ status = "disabled"; }; - uart5: serial@021f4000 { + uart5: serial@21f4000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021f4000 0x4000>; @@ -934,7 +968,7 @@ status = "disabled"; }; - i2c4: i2c@021f8000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -944,7 +978,7 @@ status = "disabled"; }; - uart6: serial@021fc000 { + uart6: serial@21fc000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021fc000 0x4000>; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 18bebd6d8d47..3f2746169181 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -45,6 +45,13 @@ stdout-path = "serial0:115200n8"; }; + /* fixed crystal dedicated to mpc258x */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + panel: panel { compatible = "edt,et057090dhu"; backlight = <&bl>; @@ -70,6 +77,17 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; }; &bl { @@ -88,6 +106,24 @@ status = "okay"; }; +&ecspi3 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + status = "okay"; + }; +}; + &fec1 { status = "okay"; }; @@ -97,7 +133,7 @@ /* M41T0M6 real time clock on carrier board */ rtc: m41t0m6@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; @@ -147,5 +183,6 @@ &usdhc1 { keep-power-in-suspend; wakeup-source; + vmmc-supply = <®_3v3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 0a3915868aa3..895fbde4d433 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -43,7 +43,10 @@ / { bl: backlight { compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; pwms = <&pwm1 0 5000000 0>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; }; reg_module_3v3: regulator-module-3v3 { @@ -86,7 +89,13 @@ }; &cpu0 { - arm-supply = <®_DCDC2>; + cpu-supply = <®_DCDC2>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; }; &fec1 { @@ -112,7 +121,6 @@ fsl,use-minimum-ecc; nand-on-flash-bbt; nand-ecc-mode = "hw"; - status = "okay"; }; &i2c1 { @@ -121,7 +129,7 @@ pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; #sound-dai-cells = <0>; reg = <0x0a>; @@ -299,6 +307,22 @@ no-1-8-v; cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; disable-wp; + vqmmc-supply = <®_LDO2>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + max-frequency = <100000000>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <®_DCDC3>; + non-removable; }; &iomuxc { @@ -307,17 +331,16 @@ pinctrl_gpio1: gpio1-grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */ + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */ + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */ + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ @@ -329,11 +352,12 @@ MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */ MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ @@ -357,8 +381,7 @@ pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ fsl,pins = < MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ @@ -378,8 +401,8 @@ MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */ - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ >; }; @@ -396,6 +419,12 @@ >; }; + pinctrl_can_int: can-int-grp { + fsl,pins = < + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 @@ -434,12 +463,17 @@ >; }; + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ + >; + }; + pinctrl_gpmi_nand: gpmi-nand-grp { fsl,pins = < MX7D_PAD_SD3_CLK__NAND_CLE 0x71 MX7D_PAD_SD3_CMD__NAND_ALE 0x71 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 - MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 @@ -507,6 +541,7 @@ pinctrl_pwm1: pwm1-grp { fsl,pins = < MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 >; }; @@ -525,6 +560,7 @@ pinctrl_pwm4: pwm4-grp { fsl,pins = < MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 >; }; @@ -559,7 +595,7 @@ >; }; - pinctrl_usbotg2_reg: gpio-usbotg2-vbus { + pinctrl_usbh_reg: gpio-usbh-vbus { fsl,pins = < MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ >; @@ -576,6 +612,54 @@ >; }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + pinctrl_sai1: sai1-grp { fsl,pins = < MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts new file mode 100644 index 000000000000..8ee73c870b12 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 Toradex AG + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx7d-emmc-eval-v3", + "toradex,colibri-imx7d-emmc", "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi new file mode 100644 index 000000000000..9b63b9c89e4b --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 Toradex AG + */ + +#include "imx7d.dtsi" +#include "imx7-colibri.dtsi" + +/ { + memory { + reg = <0x80000000 0x40000000>; + }; +}; + +&usbotg2 { + dr_mode = "host"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts index a608a14d8c85..136e11ab4893 100644 --- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts @@ -48,20 +48,9 @@ model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", "fsl,imx7d"; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; }; &usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; + vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi index 3c2cb502b388..6f2bb70c1fbd 100644 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -49,6 +49,10 @@ }; }; +&gpmi { + status = "okay"; +}; + &usbotg2 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index e7998308861f..2b05898bb3f6 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -181,7 +181,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/imx7d-pico-pi.dts new file mode 100644 index 000000000000..ee02d931cf49 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-pico-pi.dts @@ -0,0 +1,181 @@ +/* + * Copyright 2017 NXP + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx7d-pico.dtsi" + +/ { + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + status = "okay"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_vref_1v8>; + }; +}; + + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f + MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 + MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 + >; + }; + + pinctrl_usbotg1_pwr: usbotg_pwr { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-pico.dts b/arch/arm/boot/dts/imx7d-pico.dtsi index e78c2c9cc28a..e307462a48ec 100644 --- a/arch/arm/boot/dts/imx7d-pico.dts +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -52,6 +52,17 @@ reg = <0x80000000 0x80000000>; }; + reg_ap6212: regulator-ap6212 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_ap6212>; + regulator-name = "AP6212"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; @@ -89,62 +100,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - status = "okay"; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_vref_1v8>; - }; }; &i2c4 { @@ -152,7 +107,7 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -242,32 +197,14 @@ }; }; -&sai1 { +&usdhc2 { /* Wifi SDIO */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_ap6212>; status = "okay"; }; @@ -293,32 +230,6 @@ }; &iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f - MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f - >; - }; - pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f @@ -326,25 +237,20 @@ >; }; - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - >; - }; - - pinctrl_uart5: uart5grp { + pinctrl_reg_ap6212: regap6212grp { fsl,pins = < - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 >; }; - pinctrl_usbotg1_pwr: usbotg_pwr { + pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 >; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 44637cabcc56..a7a5dc7b2700 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -241,7 +241,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 4d308d17f040..200714e3feea 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -63,6 +63,13 @@ }; }; + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + soc { etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; @@ -105,18 +112,14 @@ reg = <0x30b20200 0x200>; }; - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - }; - fec2: ethernet@30bf0000 { compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; reg = <0x30bf0000 0x10000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>, @@ -129,7 +132,7 @@ status = "disabled"; }; - pcie: pcie@0x33800000 { + pcie: pcie@33800000 { compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>; @@ -137,6 +140,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 07b63f8b7314..9bdf121f7e43 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -122,7 +122,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -226,7 +226,7 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 82ad26e766eb..9aa2bb998552 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -116,6 +116,66 @@ clock-output-names = "osc"; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + usbphynop3: usbphynop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -260,43 +320,6 @@ }; }; - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - intc: interrupt-controller@31001000 { compatible = "arm,cortex-a7-gic"; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -309,15 +332,6 @@ <0x31006000 0x2000>; }; - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&intc>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - aips1: aips-bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -508,8 +522,11 @@ reg = <0x30360000 0x10000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; - reg_1p0d: regulator-vdd1p0d { + reg_1p0d: regulator-vdd1p0d@30360210 { + reg = <0x30360210>; compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p0d"; regulator-min-microvolt = <800000>; @@ -583,9 +600,9 @@ #address-cells = <1>; #size-cells = <0>; - pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY { + pgc_pcie_phy: pgc-power-domain@1 { #power-domain-cells = <0>; - reg = <IMX7_POWER_DOMAIN_PCIE_PHY>; + reg = <1>; power-supply = <®_1p0d>; }; }; @@ -945,18 +962,6 @@ reg = <0x30b30200 0x200>; }; - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY1_CLK>; - clock-names = "main_clk"; - }; - - usbphynop3: usbphynop3 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; - clock-names = "main_clk"; - }; - usdhc1: usdhc@30b40000 { compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b40000 0x10000>; @@ -1007,9 +1012,11 @@ fec1: ethernet@30be0000 { compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 380f9ae60c78..4d58638d104b 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -11,7 +11,7 @@ reg = <0x10000000 0x200>; /* Use core module LED to indicate CPU load */ - led@0c.0 { + led@c.0 { compatible = "register-bit-led"; offset = <0x0c>; mask = <0x01>; @@ -100,7 +100,7 @@ compatible = "syscon", "simple-mfd"; reg = <0x1a000000 0x10>; - led@04.0 { + led@4.0 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x01>; @@ -108,21 +108,21 @@ linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@04.1 { + led@4.1 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x02>; label = "integrator:yellow"; default-state = "off"; }; - led@04.2 { + led@4.2 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x04>; label = "integrator:red"; default-state = "off"; }; - led@04.3 { + led@4.3 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x08>; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index a5d88a213dcd..94d2ff9836d0 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -154,21 +154,26 @@ }; pci: pciv3@62000000 { - compatible = "v3,v360epc-pci"; + compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <0x62000000 0x10000>; + /* Bridge registers and config access space */ + reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; interrupt-parent = <&pic>; interrupts = <17>; /* Bus error IRQ */ - ranges = <0x00000000 0 0x61000000 /* config space */ - 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ - 0x01000000 0 0x0 /* I/O space */ - 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ - 0x02000000 0 0x00000000 /* non-prefectable memory */ - 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ - 0x42000000 0 0x10000000 /* prefetchable memory */ - 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ + clocks = <&pciclk>; + bus-range = <0x00 0xff>; + ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */ + 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ + 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ + 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ + 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ + dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ + 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ + 0x02000000 0 0x80000000 /* Core module alias memory */ + 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ interrupt-map-mask = <0xf800 0 0 0x7>; interrupt-map = < /* IDSEL 9 */ diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi new file mode 100644 index 000000000000..66954aaf2c47 --- /dev/null +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -0,0 +1,274 @@ +/* + * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/* + * SSI-SGTL5000 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/ { + aliases { + serial0 = &scif0; + serial3 = &scifb1; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + reg_1p5v: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p5v>; + }; +}; + +&pci0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + status = "okay"; +}; + +&pfc { + can0_pins: can0 { + groups = "can0_data_d"; + function = "can0"; + }; + + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + scifb1_pins: scifb1 { + groups = "scifb1_data_d", "scifb1_ctrl"; + function = "scifb1"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi1 &src3 &dvc1>; + capture = <&ssi0 &src2 &dvc0>; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scifb1 { + pinctrl-0 = <&scifb1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi new file mode 100644 index 000000000000..476273b3f994 --- /dev/null +++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi @@ -0,0 +1,130 @@ +/* + * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + aliases { + serial1 = &scif1; + serial4 = &hscif1; + }; + + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&pfc { + can1_pins: can1 { + groups = "can1_data_d"; + function = "can1"; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; + function = "du"; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data_c", "hscif1_ctrl_c"; + function = "hscif1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_d"; + function = "scif1"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi index 0c334b25781e..457515b0736a 100644 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 clock tree * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -51,7 +48,7 @@ clocks { clock-output-names = "gemtraceclk"; }; - chipstmxptclk: chipstmxptclk { + chipstmxptclk: chipstmxptclk@2310164 { #clock-cells = <0>; compatible = "ti,keystone,pll-divider-clock"; clocks = <&mainmuxclk>; @@ -160,7 +157,7 @@ clocks { clock-output-names = "chipclk1rstiso112"; }; - clkmodrst0: clkmodrst0 { + clkmodrst0: clkmodrst0@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -171,7 +168,7 @@ clocks { }; - clkusb: clkusb { + clkusb: clkusb@2350008 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -181,7 +178,7 @@ clocks { domain-id = <0>; }; - clkaemifspi: clkaemifspi { + clkaemifspi: clkaemifspi@235000c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -192,7 +189,7 @@ clocks { }; - clkdebugsstrc: clkdebugsstrc { + clkdebugsstrc: clkdebugsstrc@2350014 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -202,7 +199,7 @@ clocks { domain-id = <1>; }; - clktetbtrc: clktetbtrc { + clktetbtrc: clktetbtrc@2350018 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -212,7 +209,7 @@ clocks { domain-id = <1>; }; - clkpa: clkpa { + clkpa: clkpa@235001c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&paclk13>; @@ -222,7 +219,7 @@ clocks { domain-id = <2>; }; - clkcpgmac: clkcpgmac { + clkcpgmac: clkcpgmac@2350020 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkpa>; @@ -232,7 +229,7 @@ clocks { domain-id = <2>; }; - clksa: clksa { + clksa: clksa@2350024 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkpa>; @@ -242,7 +239,7 @@ clocks { domain-id = <2>; }; - clkpcie: clkpcie { + clkpcie: clkpcie@2350028 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -252,7 +249,7 @@ clocks { domain-id = <3>; }; - clksr: clksr { + clksr: clksr@2350034 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1rstiso112>; @@ -262,7 +259,7 @@ clocks { domain-id = <6>; }; - clkgem0: clkgem0 { + clkgem0: clkgem0@235003c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -272,7 +269,7 @@ clocks { domain-id = <8>; }; - clkddr30: clkddr30 { + clkddr30: clkddr30@235005c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -282,7 +279,7 @@ clocks { domain-id = <16>; }; - clkwdtimer0: clkwdtimer0 { + clkwdtimer0: clkwdtimer0@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -292,7 +289,7 @@ clocks { domain-id = <0>; }; - clkwdtimer1: clkwdtimer1 { + clkwdtimer1: clkwdtimer1@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -302,7 +299,7 @@ clocks { domain-id = <0>; }; - clkwdtimer2: clkwdtimer2 { + clkwdtimer2: clkwdtimer2@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -312,7 +309,7 @@ clocks { domain-id = <0>; }; - clkwdtimer3: clkwdtimer3 { + clkwdtimer3: clkwdtimer3@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -322,7 +319,7 @@ clocks { domain-id = <0>; }; - clktimer15: clktimer15 { + clktimer15: clktimer15@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -332,7 +329,7 @@ clocks { domain-id = <0>; }; - clkuart0: clkuart0 { + clkuart0: clkuart0@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -342,7 +339,7 @@ clocks { domain-id = <0>; }; - clkuart1: clkuart1 { + clkuart1: clkuart1@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -352,7 +349,7 @@ clocks { domain-id = <0>; }; - clkaemif: clkaemif { + clkaemif: clkaemif@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkaemifspi>; @@ -362,7 +359,7 @@ clocks { domain-id = <0>; }; - clkusim: clkusim { + clkusim: clkusim@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -372,7 +369,7 @@ clocks { domain-id = <0>; }; - clki2c: clki2c { + clki2c: clki2c@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -382,7 +379,7 @@ clocks { domain-id = <0>; }; - clkspi: clkspi { + clkspi: clkspi@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkaemifspi>; @@ -392,7 +389,7 @@ clocks { domain-id = <0>; }; - clkgpio: clkgpio { + clkgpio: clkgpio@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -402,7 +399,7 @@ clocks { domain-id = <0>; }; - clkkeymgr: clkkeymgr { + clkkeymgr: clkkeymgr@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi index d56d68fe7ffc..5e0e7d232161 100644 --- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Keystone 2 Edison SoC specific device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -35,7 +32,7 @@ clocks { reg-names = "control"; }; - clkusb1: clkusb1 { + clkusb1: clkusb1@2350004 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -45,7 +42,7 @@ clocks { domain-id = <0>; }; - clkhyperlink0: clkhyperlink0 { + clkhyperlink0: clkhyperlink02350030 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -55,7 +52,7 @@ clocks { domain-id = <5>; }; - clkpcie1: clkpcie1 { + clkpcie1: clkpcie1@235006c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -65,7 +62,7 @@ clocks { domain-id = <18>; }; - clkxge: clkxge { + clkxge: clkxge@23500c8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index f1f32c54e72f..66fec5f5d081 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Edison EVM device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -28,8 +25,9 @@ status = "okay"; }; }; +}; - soc { +&soc0 { clocks { refclksys: refclksys { @@ -53,7 +51,6 @@ clock-output-names = "refclk-ddr3a"; }; }; - }; }; &usb_phy { @@ -82,7 +79,7 @@ &i2c0 { dtt@50 { - compatible = "at,24c1024"; + compatible = "atmel,24c1024"; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index ba828cb59587..a17311c602aa 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 Edison Netcp driver * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 819ab8345916..0bcd3f8a9c45 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Edison soc device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include <dt-bindings/reset/ti-syscon.h> @@ -48,8 +45,9 @@ aliases { rproc0 = &dsp0; }; +}; - soc { +&soc0 { /include/ "keystone-k2e-clocks.dtsi" usb: usb@2680000 { @@ -88,7 +86,7 @@ }; }; - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; @@ -100,7 +98,7 @@ }; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { pscrst: reset-controller { compatible = "ti,k2e-pscrst", "ti,syscon-reset"; #reset-cells = <1>; @@ -111,7 +109,7 @@ }; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; @@ -194,5 +192,4 @@ bus_freq = <2500000>; }; /include/ "keystone-k2e-netcp.dtsi" - }; }; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index f462f1043531..6a4657799b99 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for K2G EVM * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -81,6 +73,47 @@ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ >; }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + >; + }; + + ecap0_pins: ecap0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ + K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ + K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ + K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ + >; + }; + + qspi_pins: pinmux_qspi_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ + K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ + K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ + K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ + K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ + K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ + K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ + K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ + >; + }; }; &uart0 { @@ -105,6 +138,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ + ti,non-removable; status = "okay"; }; @@ -112,3 +146,125 @@ memory-region = <&dsp_common_memory>; status = "okay"; }; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + +&keystone_usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&keystone_usb1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <5000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x100000 0xf00000>; + }; + }; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + cdns,rclk-en; + + flash0: m25p80@0 { + compatible = "s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <96000000>; + #address-cells = <1>; + #size-cells = <1>; + cdns,read-delay = <5>; + cdns,tshsl-ns = <500>; + cdns,tsd2d-ns = <500>; + cdns,tchsh-ns = <119>; + cdns,tslch-ns = <119>; + + partition@0 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "QSPI.u-boot-env"; + reg = <0x00100000 0x00040000>; + }; + partition@2 { + label = "QSPI.skern"; + reg = <0x00140000 0x0040000>; + }; + partition@3 { + label = "QSPI.pmmc-firmware"; + reg = <0x00180000 0x0040000>; + }; + partition@4 { + label = "QSPI.kernel"; + reg = <0x001C0000 0x0800000>; + }; + partition@5 { + label = "QSPI.file-system"; + reg = <0x009C0000 0x3640000>; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts index 78692745e0af..d820ed2474bb 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for K2G Industrial Communication Engine EVM * * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0 */ /dts-v1/; @@ -30,6 +29,191 @@ status = "okay"; }; }; + + vmain: fixedregulator-vmain { + compatible = "regulator-fixed"; + regulator-name = "vmain_fixed"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + v5_0: fixedregulator-v5_0 { + /* TPS54531 */ + compatible = "regulator-fixed"; + regulator-name = "v5_0_fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain>; + regulator-always-on; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + /* TLV62084 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vdd_1v8: fixedregulator-vdd_1v8 { + /* TLV62084 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vdds_ddr: fixedregulator-vdds_ddr { + /* TLV62080 */ + compatible = "regulator-fixed"; + regulator-name = "vdds_ddr_fixed"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vref_ddr: fixedregulator-vref_ddr { + /* LP2996A */ + compatible = "regulator-fixed"; + regulator-name = "vref_ddr_fixed"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + vtt_ddr: fixedregulator-vtt_ddr { + /* LP2996A */ + compatible = "regulator-fixed"; + regulator-name = "vtt_ddr_fixed"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + vdd_0v9: fixedregulator-vdd_0v9 { + /* TPS62180 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_fixed"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vddb: fixedregulator-vddb { + /* TPS22945 */ + compatible = "regulator-fixed"; + regulator-name = "vddb_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-decoder { + compatible = "gpio-decoder"; + gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, + <&pca9536 2 GPIO_ACTIVE_HIGH>, + <&pca9536 1 GPIO_ACTIVE_HIGH>, + <&pca9536 0 GPIO_ACTIVE_HIGH>; + linux,axis = <0>; /* ABS_X */ + decoder-max-value = <9>; + }; + + leds1 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + led0 { + label = "status0:red:cpu0"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led1 { + label = "status0:green:usr"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "status0:yellow:usr"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + label = "status1:red:mmc0"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led4 { + label = "status1:green:usr"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led5 { + label = "status1:yellow:usr"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led6 { + label = "status2:red:usr"; + gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led7 { + label = "status2:green:usr"; + gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led8 { + label = "status2:yellow:usr"; + gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led9 { + label = "status3:red:usr"; + gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led10 { + label = "status3:green:usr"; + gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led11 { + label = "status3:yellow:usr"; + gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led12 { + label = "status4:green:heartbeat"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; }; &k2g_pinctrl { @@ -39,6 +223,64 @@ K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; + + qspi_pins: pinmux_qspi_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ + K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ + K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ + K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ + K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ + K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ + K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ + K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ + K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + user_leds: pinmux_user_leds { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */ + K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */ + K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */ + K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */ + K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */ + K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */ + K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */ + K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */ + K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */ + K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */ + K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */ + K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */ + K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */ + >; + }; }; &uart0 { @@ -51,3 +293,96 @@ memory-region = <&dsp_common_memory>; status = "okay"; }; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + cdns,rclk-en; + status = "okay"; + + flash0: m25p80@0 { + compatible = "s25fl256s1", "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <96000000>; + #address-cells = <1>; + #size-cells = <1>; + cdns,read-delay = <5>; + cdns,tshsl-ns = <500>; + cdns,tsd2d-ns = <500>; + cdns,tchsh-ns = <119>; + cdns,tslch-ns = <119>; + + partition@0 { + label = "QSPI.u-boot"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "QSPI.u-boot-env"; + reg = <0x00100000 0x00040000>; + }; + partition@2 { + label = "QSPI.skern"; + reg = <0x00140000 0x0040000>; + }; + partition@3 { + label = "QSPI.pmmc-firmware"; + reg = <0x00180000 0x0040000>; + }; + partition@4 { + label = "QSPI.kernel"; + reg = <0x001c0000 0x0800000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x009c0000 0x0040000>; + }; + partition@6 { + label = "QSPI.file-system"; + reg = <0x00a00000 0x1600000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vdd_3v3>; + cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <400000>; + + pca9536: gpio@41 { + compatible = "ti,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vdd_3v3>; + }; +}; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 826b286665e6..fd061718dc0a 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for K2G SOC * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -28,6 +20,11 @@ aliases { serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; rproc0 = &dsp0; }; @@ -42,7 +39,7 @@ }; }; - gic: interrupt-controller@02561000 { + gic: interrupt-controller@2561000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -72,7 +69,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; }; - soc { + soc0: soc@0 { #address-cells = <1>; #size-cells = <1>; #pinctrl-cells = <1>; @@ -80,7 +77,7 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x100000>; ranges = <0x0 0x0c000000 0x100000>; @@ -92,30 +89,55 @@ }; }; - k2g_pinctrl: pinmux@02621000 { + k2g_pinctrl: pinmux@2621000 { compatible = "pinctrl-single"; reg = <0x02621000 0x410>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x001b0007>; }; - devctrl: device-state-control@02620000 { + devctrl: device-state-control@2620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; }; - uart0: serial@02530c00 { + uart0: serial@2530c00 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; reg = <0x02530c00 0x100>; interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; - clock-frequency = <200000000>; + clocks = <&k2g_clks 0x2c 0>; + power-domains = <&k2g_pds 0x2c>; + status = "disabled"; + }; + + uart1: serial@02531000 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>; + clocks = <&k2g_clks 0x2d 0>; + power-domains = <&k2g_pds 0x2d>; + status = "disabled"; + }; + + uart2: serial@02531400 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531400 0x100>; + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; + clocks = <&k2g_clks 0x2e 0>; + power-domains = <&k2g_pds 0x2e>; status = "disabled"; }; - dcan0: can@0260B200 { + dcan0: can@260b200 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0260B200 0x200>; interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; @@ -124,7 +146,7 @@ clocks = <&k2g_clks 0x0008 1>; }; - dcan1: can@0260B400 { + dcan1: can@260b400 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0260B400 0x200>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; @@ -133,7 +155,40 @@ clocks = <&k2g_clks 0x0009 1>; }; - kirq0: keystone_irq@026202a0 { + i2c0: i2c@2530000 { + compatible = "ti,keystone-i2c"; + reg = <0x02530000 0x400>; + clocks = <&k2g_clks 0x003a 0>; + power-domains = <&k2g_pds 0x003a>; + interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@2530400 { + compatible = "ti,keystone-i2c"; + reg = <0x02530400 0x400>; + clocks = <&k2g_clks 0x003b 0>; + power-domains = <&k2g_pds 0x003b>; + interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@2530800 { + compatible = "ti,keystone-i2c"; + reg = <0x02530800 0x400>; + clocks = <&k2g_clks 0x003c 0>; + power-domains = <&k2g_pds 0x003c>; + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + kirq0: keystone_irq@26202a0 { compatible = "ti,keystone-irq"; interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>; interrupt-controller; @@ -141,7 +196,7 @@ ti,syscon-dev = <&devctrl 0x2a0>; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; @@ -164,7 +219,7 @@ status = "disabled"; }; - msgmgr: msgmgr@02a00000 { + msgmgr: msgmgr@2a00000 { compatible = "ti,k2g-message-manager"; #mbox-cells = <2>; reg-names = "queue_proxy_region", @@ -176,7 +231,7 @@ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; }; - pmmc: pmmc@02921c00 { + pmmc: pmmc@2921c00 { compatible = "ti,k2g-sci"; /* * In case of rare platforms that does not use k2g as @@ -246,7 +301,7 @@ clock-names = "gpio"; }; - edma0: edma@02700000 { + edma0: edma@2700000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02700000 0x8000>; reg-names = "edma3_cc"; @@ -265,19 +320,19 @@ power-domains = <&k2g_pds 0x3f>; }; - edma0_tptc0: tptc@02760000 { + edma0_tptc0: tptc@2760000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x02760000 0x400>; power-domains = <&k2g_pds 0x3f>; }; - edma0_tptc1: tptc@02768000 { + edma0_tptc1: tptc@2768000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x02768000 0x400>; power-domains = <&k2g_pds 0x3f>; }; - edma1: edma@02728000 { + edma1: edma@2728000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02728000 0x8000>; reg-names = "edma3_cc"; @@ -300,13 +355,13 @@ power-domains = <&k2g_pds 0x4f>; }; - edma1_tptc0: tptc@027b0000 { + edma1_tptc0: tptc@27b0000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x027b0000 0x400>; power-domains = <&k2g_pds 0x4f>; }; - edma1_tptc1: tptc@027b8000 { + edma1_tptc1: tptc@27b8000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x027b8000 0x400>; power-domains = <&k2g_pds 0x4f>; @@ -336,12 +391,197 @@ dma-names = "tx", "rx"; bus-width = <8>; ti,needs-special-reset; - ti,non-removable; max-frequency = <96000000>; power-domains = <&k2g_pds 0xc>; clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; clock-names = "fck", "mmchsdb_fck"; + }; + + qspi: qspi@2940000 { + compatible = "ti,k2g-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02940000 0x1000>, + <0x24000000 0x4000000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x24000000>; + clocks = <&k2g_clks 0x43 0x0>; + power-domains = <&k2g_pds 0x43>; + status = "disabled"; + }; + + mcasp0: mcasp@2340000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02340000 0x2000>, + <0x21804000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma0 24 1>, <&edma0 25 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x4>; + clocks = <&k2g_clks 0x4 0>; + clock-names = "fck"; status = "disabled"; }; + + mcasp1: mcasp@2342000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02342000 0x2000>, + <0x21804400 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma1 48 1>, <&edma1 49 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x5>; + clocks = <&k2g_clks 0x5 0>; + clock-names = "fck"; + status = "disabled"; + }; + + mcasp2: mcasp@2344000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02344000 0x2000>, + <0x21804800 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma1 50 1>, <&edma1 51 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x6>; + clocks = <&k2g_clks 0x6 0>; + clock-names = "fck"; + status = "disabled"; + }; + + usb0_phy: usb-phy@0 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb0: keystone-dwc3@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds 0x0016>; + + usb0: usb@2690000 { + compatible = "snps,dwc3"; + reg = <0x2690000 0x10000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb0_phy>; + status = "disabled"; + }; + }; + + usb1_phy: usb-phy@1 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb1: keystone-dwc3@2580000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2580000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds 0x0017>; + + usb1: usb@2590000 { + compatible = "snps,dwc3"; + reg = <0x2590000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb1_phy>; + status = "disabled"; + }; + }; + + ecap0: pwm@21d1800 { + compatible = "ti,k2g-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x021d1800 0x60>; + power-domains = <&k2g_pds 0x38>; + clocks = <&k2g_clks 0x38 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@21d1c00 { + compatible = "ti,k2g-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x021d1c00 0x60>; + power-domains = <&k2g_pds 0x39>; + clocks = <&k2g_clks 0x39 0x0>; + clock-names = "fck"; + status = "disabled"; + }; + + spi0: spi@21805400 { + compatible = "ti,keystone-spi"; + reg = <0x21805400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0010>; + clocks = <&k2g_clks 0x0010 0>; + }; + + spi1: spi@21805800 { + compatible = "ti,keystone-spi"; + reg = <0x21805800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0011>; + clocks = <&k2g_clks 0x0011 0>; + }; + + spi2: spi@21805c00 { + compatible = "ti,keystone-spi"; + reg = <0x21805C00 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0012>; + clocks = <&k2g_clks 0x0012 0>; + }; + + spi3: spi@21806000 { + compatible = "ti,keystone-spi"; + reg = <0x21806000 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0013>; + clocks = <&k2g_clks 0x0013 0>; + }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi b/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi index af9b7190533a..4ba6912176ef 100644 --- a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Kepler/Hawking SoC clock nodes * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -53,7 +50,7 @@ clocks { reg-names = "control"; }; - clktsip: clktsip { + clktsip: clktsip@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -63,7 +60,7 @@ clocks { domain-id = <0>; }; - clksrio: clksrio { + clksrio: clksrio@235002c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1rstiso13>; @@ -73,7 +70,7 @@ clocks { domain-id = <4>; }; - clkhyperlink0: clkhyperlink0 { + clkhyperlink0: clkhyperlink0@2350030 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -83,7 +80,7 @@ clocks { domain-id = <5>; }; - clkgem1: clkgem1 { + clkgem1: clkgem1@2350040 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -93,7 +90,7 @@ clocks { domain-id = <9>; }; - clkgem2: clkgem2 { + clkgem2: clkgem2@2350044 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -103,7 +100,7 @@ clocks { domain-id = <10>; }; - clkgem3: clkgem3 { + clkgem3: clkgem3@2350048 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -113,7 +110,7 @@ clocks { domain-id = <11>; }; - clkgem4: clkgem4 { + clkgem4: clkgem4@235004c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -123,7 +120,7 @@ clocks { domain-id = <12>; }; - clkgem5: clkgem5 { + clkgem5: clkgem5@2350050 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -133,7 +130,7 @@ clocks { domain-id = <13>; }; - clkgem6: clkgem6 { + clkgem6: clkgem6@2350054 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -143,7 +140,7 @@ clocks { domain-id = <14>; }; - clkgem7: clkgem7 { + clkgem7: clkgem7@2350058 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -153,7 +150,7 @@ clocks { domain-id = <15>; }; - clkddr31: clkddr31 { + clkddr31: clkddr31@2350060 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -163,7 +160,7 @@ clocks { domain-id = <16>; }; - clktac: clktac { + clktac: clktac@2350064 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -173,7 +170,7 @@ clocks { domain-id = <17>; }; - clkrac01: clkrac01 { + clkrac01: clkrac01@2350068 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -183,7 +180,7 @@ clocks { domain-id = <17>; }; - clkrac23: clkrac23 { + clkrac23: clkrac23@235006c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -193,7 +190,7 @@ clocks { domain-id = <18>; }; - clkfftc0: clkfftc0 { + clkfftc0: clkfftc0@2350070 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -203,7 +200,7 @@ clocks { domain-id = <19>; }; - clkfftc1: clkfftc1 { + clkfftc1: clkfftc1@2350074 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -213,7 +210,7 @@ clocks { domain-id = <19>; }; - clkfftc2: clkfftc2 { + clkfftc2: clkfftc2@2350078 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -223,7 +220,7 @@ clocks { domain-id = <20>; }; - clkfftc3: clkfftc3 { + clkfftc3: clkfftc3@235007c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -233,7 +230,7 @@ clocks { domain-id = <20>; }; - clkfftc4: clkfftc4 { + clkfftc4: clkfftc4@2350080 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -243,7 +240,7 @@ clocks { domain-id = <20>; }; - clkfftc5: clkfftc5 { + clkfftc5: clkfftc5@2350084 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -253,7 +250,7 @@ clocks { domain-id = <20>; }; - clkaif: clkaif { + clkaif: clkaif@2350088 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -263,7 +260,7 @@ clocks { domain-id = <21>; }; - clktcp3d0: clktcp3d0 { + clktcp3d0: clktcp3d0@235008c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -273,7 +270,7 @@ clocks { domain-id = <22>; }; - clktcp3d1: clktcp3d1 { + clktcp3d1: clktcp3d1@2350090 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -283,7 +280,7 @@ clocks { domain-id = <22>; }; - clktcp3d2: clktcp3d2 { + clktcp3d2: clktcp3d2@2350094 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -293,7 +290,7 @@ clocks { domain-id = <23>; }; - clktcp3d3: clktcp3d3 { + clktcp3d3: clktcp3d3@2350098 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -303,7 +300,7 @@ clocks { domain-id = <23>; }; - clkvcp0: clkvcp0 { + clkvcp0: clkvcp0@235009c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -313,7 +310,7 @@ clocks { domain-id = <24>; }; - clkvcp1: clkvcp1 { + clkvcp1: clkvcp1@23500a0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -323,7 +320,7 @@ clocks { domain-id = <24>; }; - clkvcp2: clkvcp2 { + clkvcp2: clkvcp2@23500a4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -333,7 +330,7 @@ clocks { domain-id = <24>; }; - clkvcp3: clkvcp3 { + clkvcp3: clkvcp3@23500a8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -343,7 +340,7 @@ clocks { domain-id = <24>; }; - clkvcp4: clkvcp4 { + clkvcp4: clkvcp4@23500ac { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -353,7 +350,7 @@ clocks { domain-id = <25>; }; - clkvcp5: clkvcp5 { + clkvcp5: clkvcp5@23500b0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -363,7 +360,7 @@ clocks { domain-id = <25>; }; - clkvcp6: clkvcp6 { + clkvcp6: clkvcp6@23500b4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -373,7 +370,7 @@ clocks { domain-id = <25>; }; - clkvcp7: clkvcp7 { + clkvcp7: clkvcp7@23500b8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -383,7 +380,7 @@ clocks { domain-id = <25>; }; - clkbcp: clkbcp { + clkbcp: clkbcp@23500bc { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -393,7 +390,7 @@ clocks { domain-id = <26>; }; - clkdxb: clkdxb { + clkdxb: clkdxb@23500c0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -403,7 +400,7 @@ clocks { domain-id = <27>; }; - clkhyperlink1: clkhyperlink1 { + clkhyperlink1: clkhyperlink1@23500c4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -413,7 +410,7 @@ clocks { domain-id = <28>; }; - clkxge: clkxge { + clkxge: clkxge@23500c8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index 6dd13b98aaba..ad4e22afe133 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Kepler/Hawking EVM device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -29,7 +26,31 @@ }; }; - soc { + leds { + compatible = "gpio-leds"; + debug1_1 { + label = "keystone:green:debug1"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ + }; + + debug1_2 { + label = "keystone:red:debug1"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ + }; + + debug2 { + label = "keystone:blue:debug2"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ + }; + + debug3 { + label = "keystone:blue:debug3"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ + }; + }; +}; + +&soc0 { clocks { refclksys: refclksys { #clock-cells = <0>; @@ -66,30 +87,6 @@ clock-output-names = "refclk-ddr3b"; }; }; - }; - - leds { - compatible = "gpio-leds"; - debug1_1 { - label = "keystone:green:debug1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ - }; - - debug1_2 { - label = "keystone:red:debug1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ - }; - - debug2 { - label = "keystone:blue:debug2"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ - }; - - debug3 { - label = "keystone:blue:debug3"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ - }; - }; }; &usb_phy { @@ -158,7 +155,7 @@ &i2c0 { dtt@50 { - compatible = "at,24c1024"; + compatible = "atmel,24c1024"; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index a5ac845464bf..b88c0689c285 100644 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 Hawking Netcp driver * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index 31dc00e4e5fd..ed59474522cb 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Kepler/Hawking soc specific device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include <dt-bindings/reset/ti-syscon.h> @@ -55,11 +52,12 @@ rproc6 = &dsp6; rproc7 = &dsp7; }; +}; - soc { +&soc0 { /include/ "keystone-k2hk-clocks.dtsi" - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x600000>; ranges = <0x0 0x0c000000 0x600000>; @@ -71,7 +69,7 @@ }; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { pscrst: reset-controller { compatible = "ti,k2hk-pscrst", "ti,syscon-reset"; #reset-cells = <1>; @@ -89,7 +87,7 @@ }; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; @@ -273,7 +271,7 @@ status = "disabled"; }; - mdio: mdio@02090300 { + mdio: mdio@2090300 { compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; @@ -284,5 +282,4 @@ bus_freq = <2500000>; }; /include/ "keystone-k2hk-netcp.dtsi" - }; }; diff --git a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi b/arch/arm/boot/dts/keystone-k2l-clocks.dtsi index ef8464bb11ff..635528064dea 100644 --- a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 lamarr SoC clock nodes * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -44,7 +41,7 @@ clocks { reg-names = "control"; }; - clkdfeiqnsys: clkdfeiqnsys { + clkdfeiqnsys: clkdfeiqnsys@2350004 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -54,7 +51,7 @@ clocks { domain-id = <0>; }; - clkpcie1: clkpcie1 { + clkpcie1: clkpcie1@235002c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -64,7 +61,7 @@ clocks { domain-id = <4>; }; - clkgem1: clkgem1 { + clkgem1: clkgem1@2350040 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -74,7 +71,7 @@ clocks { domain-id = <9>; }; - clkgem2: clkgem2 { + clkgem2: clkgem2@2350044 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -84,7 +81,7 @@ clocks { domain-id = <10>; }; - clkgem3: clkgem3 { + clkgem3: clkgem3@2350048 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -94,7 +91,7 @@ clocks { domain-id = <11>; }; - clktac: clktac { + clktac: clktac@2350064 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -104,7 +101,7 @@ clocks { domain-id = <17>; }; - clkrac: clkrac { + clkrac: clkrac@2350068 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -114,7 +111,7 @@ clocks { domain-id = <17>; }; - clkdfepd0: clkdfepd0 { + clkdfepd0: clkdfepd0@235006c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -124,7 +121,7 @@ clocks { domain-id = <18>; }; - clkfftc0: clkfftc0 { + clkfftc0: clkfftc0@2350070 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -134,7 +131,7 @@ clocks { domain-id = <19>; }; - clkosr: clkosr { + clkosr: clkosr@2350088 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -144,7 +141,7 @@ clocks { domain-id = <21>; }; - clktcp3d0: clktcp3d0 { + clktcp3d0: clktcp3d0@235008c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -154,7 +151,7 @@ clocks { domain-id = <22>; }; - clktcp3d1: clktcp3d1 { + clktcp3d1: clktcp3d1@2350094 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -164,7 +161,7 @@ clocks { domain-id = <23>; }; - clkvcp0: clkvcp0 { + clkvcp0: clkvcp0@235009c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -174,7 +171,7 @@ clocks { domain-id = <24>; }; - clkvcp1: clkvcp1 { + clkvcp1: clkvcp1@23500a0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -184,7 +181,7 @@ clocks { domain-id = <24>; }; - clkvcp2: clkvcp2 { + clkvcp2: clkvcp2@23500a4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -194,7 +191,7 @@ clocks { domain-id = <24>; }; - clkvcp3: clkvcp3 { + clkvcp3: clkvcp3@23500a8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -204,7 +201,7 @@ clocks { domain-id = <24>; }; - clkbcp: clkbcp { + clkbcp: clkbcp@23500bc { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -214,7 +211,7 @@ clocks { domain-id = <26>; }; - clkdfepd1: clkdfepd1 { + clkdfepd1: clkdfepd1@23500c0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -224,7 +221,7 @@ clocks { domain-id = <27>; }; - clkfftc1: clkfftc1 { + clkfftc1: clkfftc1@23500c4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -234,7 +231,7 @@ clocks { domain-id = <28>; }; - clkiqnail: clkiqnail { + clkiqnail: clkiqnail@23500c8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -244,7 +241,7 @@ clocks { domain-id = <29>; }; - clkuart2: clkuart2 { + clkuart2: clkuart2@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -254,7 +251,7 @@ clocks { domain-id = <0>; }; - clkuart3: clkuart3 { + clkuart3: clkuart3@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index 528667618db4..e200533d26a4 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Keystone 2 Lamarr EVM device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -28,8 +25,9 @@ status = "okay"; }; }; +}; - soc { +&soc0 { clocks { refclksys: refclksys { #clock-cells = <0>; @@ -38,7 +36,6 @@ clock-output-names = "refclk-sys"; }; }; - }; }; &usb_phy { @@ -55,7 +52,7 @@ &i2c0 { dtt@50 { - compatible = "at,24c1024"; + compatible = "atmel,24c1024"; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi index 66f615a74118..9ec84228bc16 100644 --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 Lamarr Netcp driver * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 4431310bc922..b61a830f4a4d 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Keystone 2 Lamarr SoC specific device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include <dt-bindings/reset/ti-syscon.h> @@ -39,11 +36,12 @@ rproc2 = &dsp2; rproc3 = &dsp3; }; +}; - soc { +&soc0 { /include/ "keystone-k2l-clocks.dtsi" - uart2: serial@02348400 { + uart2: serial@2348400 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -53,7 +51,7 @@ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; }; - uart3: serial@02348800 { + uart3: serial@2348800 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -63,7 +61,51 @@ interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; }; - k2l_pmx: pinmux@02620690 { + gpio1: gpio@2348000 { + compatible = "ti,keystone-gpio"; + reg = <0x02348000 0x100>; + gpio-controller; + #gpio-cells = <2>; + /* HW Interrupts mapped to GPIO pins */ + interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 401 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 402 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 403 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 404 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 405 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkgpio>; + clock-names = "gpio"; + ti,ngpio = <32>; + ti,davinci-gpio-unbanked = <32>; + }; + + k2l_pmx: pinmux@2620690 { compatible = "pinctrl-single"; reg = <0x02620690 0xc>; #address-cells = <1>; @@ -213,7 +255,7 @@ }; }; - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; @@ -225,7 +267,7 @@ }; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { pscrst: reset-controller { compatible = "ti,k2l-pscrst", "ti,syscon-reset"; #reset-cells = <1>; @@ -247,7 +289,7 @@ clocks = <&clkosr>; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; @@ -350,7 +392,6 @@ bus_freq = <2500000>; }; /include/ "keystone-k2l-netcp.dtsi" - }; }; &spi0 { diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 8dd74f48a6d3..93ea5c69ea77 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -1,16 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> -#include "skeleton.dtsi" - / { compatible = "ti,keystone"; model = "Texas Instruments Keystone 2 SoC"; @@ -25,11 +20,14 @@ spi2 = &spi2; }; - memory { + chosen { }; + + memory: memory@80000000 { + device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; - gic: interrupt-controller { + gic: interrupt-controller@2561000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -70,7 +68,7 @@ cpu_on = <0x84000003>; }; - soc { + soc0: soc@0 { #address-cells = <1>; #size-cells = <1>; compatible = "ti,keystone","simple-bus"; @@ -78,17 +76,17 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - pllctrl: pll-controller@02310000 { + pllctrl: pll-controller@2310000 { compatible = "ti,keystone-pllctrl", "syscon"; reg = <0x02310000 0x200>; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { compatible = "syscon", "simple-mfd"; reg = <0x02350000 0x1000>; }; - devctrl: device-state-control@02620000 { + devctrl: device-state-control@2620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; }; @@ -102,7 +100,7 @@ /include/ "keystone-clocks.dtsi" - uart0: serial@02530c00 { + uart0: serial@2530c00 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -112,7 +110,7 @@ interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; }; - uart1: serial@02531000 { + uart1: serial@2531000 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -214,7 +212,7 @@ }; }; - wdt: wdt@022f0080 { + wdt: wdt@22f0080 { compatible = "ti,keystone-wdt","ti,davinci-wdt"; reg = <0x022f0080 0x80>; clocks = <&clkwdtimer0>; diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts index df7851820507..f21a50dd9869 100644 --- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts @@ -157,7 +157,7 @@ reg = <0x80000 0x20000>; }; - partition@A0000 { + partition@a0000 { label = "s_env"; reg = <0xA0000 0x20000>; }; @@ -167,17 +167,17 @@ reg = <0x200000 0x2A0000>; }; - partition@4A0000 { + partition@4a0000 { label = "rootfs"; reg = <0x4A0000 0x1760000>; }; - partition@1C00000 { + partition@1c00000 { label = "alt_kernel"; reg = <0x1C00000 0x2A0000>; }; - partition@1EA0000 { + partition@1ea0000 { label = "alt_rootfs"; reg = <0x1EA0000 0x1760000>; }; @@ -187,7 +187,7 @@ reg = <0x3600000 0x4A00000>; }; - partition@C0000 { + partition@c0000 { label = "unused"; reg = <0xC0000 0x140000>; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index cf2f5240e176..27cc913ca0f5 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -53,7 +53,8 @@ }; pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; + pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header + &pmx_gpio_header_gpo>; pinctrl-names = "default"; pmx_uart0: pmx-uart0 { @@ -85,11 +86,16 @@ * ground. */ pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28", + marvell,pins = "mpp17", "mpp29", "mpp28", "mpp35", "mpp34", "mpp40"; marvell,function = "gpio"; }; + pmx_gpio_header_gpo: pxm-gpio-header-gpo { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + pmx_gpio_init: pmx-init { marvell,pins = "mpp38"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 65e9524e852a..210d21a65bd1 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -208,32 +208,32 @@ spi-max-frequency = <20000000>; mode = <0>; - partition@00000000 { + partition@0 { reg = <0x00000000 0x00080000>; label = "RedBoot"; }; - partition@00080000 { + partition@80000 { reg = <0x00080000 0x00200000>; label = "zImage"; }; - partition@00280000 { + partition@280000 { reg = <0x00280000 0x00140000>; label = "rd.gz"; }; - partition@003c0000 { + partition@3c0000 { reg = <0x003c0000 0x00010000>; label = "vendor"; }; - partition@003d0000 { + partition@3d0000 { reg = <0x003d0000 0x00020000>; label = "RedBoot config"; }; - partition@003f0000 { + partition@3f0000 { reg = <0x003f0000 0x00010000>; label = "FIS directory"; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 4faea1d9facf..a88eb22070a1 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -45,29 +45,29 @@ spi-max-frequency = <20000000>; mode = <0>; - partition@0000000 { + partition@0 { reg = <0x00000000 0x00080000>; label = "U-Boot"; }; - partition@00200000 { + partition@200000 { reg = <0x00200000 0x00200000>; label = "Kernel"; }; - partition@00400000 { + partition@400000 { reg = <0x00400000 0x00900000>; label = "RootFS1"; }; - partition@00d00000 { + partition@d00000 { reg = <0x00d00000 0x00300000>; label = "RootFS2"; }; - partition@00040000 { + partition@40000 { reg = <0x00080000 0x00040000>; label = "U-Boot Config"; }; - partition@000c0000 { + partition@c0000 { reg = <0x000c0000 0x00140000>; label = "NAS Config"; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index a70fc7f01fc3..eb2bf7409655 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -41,7 +41,7 @@ pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - nand: nand@012f { + nand: nand@12f { #address-cells = <1>; #size-cells = <1>; cle = <0>; @@ -57,7 +57,7 @@ status = "disabled"; }; - crypto_sram: sa-sram@0301 { + crypto_sram: sa-sram@301 { compatible = "mmio-sram"; reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>; clocks = <&gate_clk 17>; diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts new file mode 100644 index 000000000000..32d0dc371fc3 --- /dev/null +++ b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts @@ -0,0 +1,17 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "omap34xx.dtsi" +#include "logicpd-som-lv.dtsi" +#include "logicpd-som-lv-baseboard.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; + compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts index 38faa90007d7..24283739526c 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts @@ -8,256 +8,10 @@ #include "omap36xx.dtsi" #include "logicpd-som-lv.dtsi" +#include "logicpd-som-lv-baseboard.dtsi" #include "omap-gpmc-smsc9221.dtsi" / { model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - sysboot2 { - label = "gpio3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ - linux,code = <BTN_0>; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &led_pins_wkup>; - - led1 { - label = "led1"; - gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ - linux,default-trigger = "none"; - }; - }; -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ - reg = <1 0 0xff>; - }; -}; - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&video_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - video_reg: video_reg { - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lcd0: display@0 { - compatible = "panel-dpi"; - label = "28"; - status = "okay"; - /* default-on; */ - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_pin>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <2>; - vsync-len = <11>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&twl_pwm 0 5000000>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ - >; - }; - - lcd_enable_pin: pinmux_lcd_enable_pin { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; -}; - -&omap3_pmx_wkup { - led_pins_wkup: pinmux_led_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; -}; - - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; }; diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi new file mode 100644 index 000000000000..4990ed90dcea --- /dev/null +++ b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi @@ -0,0 +1,256 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + + sysboot2 { + label = "gpio3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ + linux,code = <BTN_0>; + wakeup-source; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3logic"; + ti,mcbsp = <&mcbsp2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins &led_pins_wkup>; + + led1 { + label = "led1"; + gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ + linux,default-trigger = "cpu0"; + }; + + led2 { + label = "led2"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ + linux,default-trigger = "none"; + }; + }; +}; + +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&vaux4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mcbsp2 { + status = "okay"; +}; + +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ + 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ + reg = <1 0 0xff>; + }; +}; + +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&video_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins1>; + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <16>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + video_reg: video_reg { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lcd0: display@0 { + compatible = "panel-dpi"; + label = "28"; + status = "okay"; + /* default-on; */ + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_pin>; + enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <2>; + vsync-len = <11>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + pwms = <&twl_pwm 0 5000000>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ + }; +}; + +&mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ + cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */ + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cap-power-off-card; +}; + +&omap3_pmx_core { + gpio_key_pins: pinmux_gpio_key_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ + >; + }; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ + >; + }; + + lan9221_pins: pinmux_lan9221_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ + OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ + >; + }; + + lcd_enable_pin: pinmux_lcd_enable_pin { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ + >; + }; + + dss_dpi_pins1: pinmux_dss_dpi_pins1 { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ + >; + }; +}; + +&omap3_pmx_wkup { + led_pins_wkup: pinmux_led_pins_wkup { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ + >; + }; +}; + + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index 26cce4d18405..a30ee9fcb3ae 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -33,11 +33,12 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ + #phy-cells = <0>; }; }; &gpmc { - ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */ + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; @@ -66,37 +67,12 @@ gpmc,device-width = <2>; #address-cells = <1>; #size-cells = <1>; - - /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */ - - x-loader@0 { - label = "x-loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "u-boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "u-boot-env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "fs"; - reg = <0x680000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; }; }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; clock-frequency = <2600000>; twl: twl@48 { @@ -121,7 +97,7 @@ &mmc3 { interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; - pinctrl-0 = <&mmc3_pins>; + pinctrl-0 = <&mmc3_pins &wl127x_gpio>; pinctrl-names = "default"; vmmc-supply = <&wl12xx_vmmc>; non-removable; @@ -132,8 +108,8 @@ wlcore: wlcore@2 { compatible = "ti,wl1273"; reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */ ref-clock-frequency = <26000000>; }; }; @@ -157,8 +133,6 @@ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - OMAP3_CORE1_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ >; @@ -217,7 +191,12 @@ >; }; - + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; }; &omap3_pmx_wkup { @@ -228,6 +207,12 @@ OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; + wl127x_gpio: pinmux_wl127x_gpio_pin { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + >; + }; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts new file mode 100644 index 000000000000..d7cb659656ce --- /dev/null +++ b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts @@ -0,0 +1,17 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "omap34xx.dtsi" +#include "logicpd-torpedo-som.dtsi" +#include "logicpd-torpedo-baseboard.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; + compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index b4575bbaf085..234afd6d60ec 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -9,396 +9,69 @@ #include "omap36xx.dtsi" #include "logicpd-torpedo-som.dtsi" #include "omap-gpmc-smsc9221.dtsi" +#include "logicpd-torpedo-baseboard.dtsi" / { model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit"; compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; - - sysboot2 { - label = "sysboot2"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ - linux,code = <BTN_0>; - wakeup-source; - }; - - sysboot5 { - label = "sysboot5"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ - linux,code = <BTN_1>; - wakeup-source; - }; - - gpio1 { - label = "gpio1"; - gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ - linux,code = <BTN_2>; - wakeup-source; - }; - - gpio2 { - label = "gpio2"; - gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ - linux,code = <BTN_3>; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "led1"; - gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ - linux,default-trigger = "none"; - }; - }; - - pwm10: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer10>; - #pwm-cells = <3>; - }; - -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ - reg = <1 0 0xff>; - }; -}; - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&video_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - video_reg: video_reg { - pinctrl-names = "default"; - pinctrl-0 = <&panel_pwr_pins>; + wl12xx_vmmc: wl12xx_vmmc { compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "15"; - status = "okay"; - /* default-on; */ - pinctrl-names = "default"; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <4>; - vsync-len = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm10 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 29 0>; /* gpio157 */ + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&vmmc2>; }; }; -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; +/* + * Only found on the wireless SOM. For the SOM without wireless, the pins for + * MMC3 can be routed with jumpers to the second MMC slot on the devkit and + * gpio157 is not connected. So this should be OK to keep common for now, + * probably device tree overlays is the way to go with the various SOM and + * jumpering combinations for the long run. + */ +&mmc3 { + interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; + pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd>; - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ - vmmc-supply = <&vmmc1>; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; bus-width = <4>; cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; }; &omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ - >; - }; - - pwm_pins: pinmux_pwm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ - >; - }; - - led_pins: pinmux_led_pins { + mmc3_pins: pinmux_mm3_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ - >; - }; - - isp_pins: pinmux_isp_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ - - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ - >; - }; - - panel_pwr_pins: pinmux_panel_pwr_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ >; }; }; -&omap3_pmx_wkup { - gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - mmc1_cd: pinmux_mmc1_cd { +&omap3_pmx_core2 { + mmc3_core2_pins: pinmux_mmc3_core2_pins { pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ >; }; }; - -&i2c2 { - mt9p031@48 { - compatible = "aptina,mt9p031"; - reg = <0x48>; - clocks = <&isp 0>; - vaa-supply = <&vaux4>; - vdd-supply = <&vaux4>; - vdd_io-supply = <&vaux4>; - port { - mt9p031_out: endpoint { - input-clock-frequency = <24000000>; - pixel-clock-frequency = <72000000>; - remote-endpoint = <&ccdc_ep>; - }; - }; - }; -}; - -&i2c3 { - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mcspi1 { - at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; -}; - -&isp { - pinctrl-names = "default"; - pinctrl-0 = <&isp_pins>; - ports { - port@0 { - reg = <0>; - ccdc_ep: endpoint { - remote-endpoint = <&mt9p031_out>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi new file mode 100644 index 000000000000..86c5644f558c --- /dev/null +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -0,0 +1,395 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; + + sysboot2 { + label = "sysboot2"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ + linux,code = <BTN_0>; + wakeup-source; + }; + + sysboot5 { + label = "sysboot5"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ + linux,code = <BTN_1>; + wakeup-source; + }; + + gpio1 { + label = "gpio1"; + gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ + linux,code = <BTN_2>; + wakeup-source; + }; + + gpio2 { + label = "gpio2"; + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ + linux,code = <BTN_3>; + wakeup-source; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3logic"; + ti,mcbsp = <&mcbsp2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led1 { + label = "led1"; + gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ + linux,default-trigger = "cpu0"; + }; + + led2 { + label = "led2"; + gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ + linux,default-trigger = "none"; + }; + }; + + pwm10: dmtimer-pwm { + compatible = "ti,omap-dmtimer-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + ti,timers = <&timer10>; + #pwm-cells = <3>; + }; + +}; + +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&vaux4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mcbsp2 { + status = "okay"; +}; + +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ + reg = <1 0 0xff>; + }; +}; + +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&video_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins1>; + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <16>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + video_reg: video_reg { + pinctrl-names = "default"; + pinctrl-0 = <&panel_pwr_pins>; + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ + }; + + lcd0: display { + compatible = "panel-dpi"; + label = "15"; + status = "okay"; + /* default-on; */ + pinctrl-names = "default"; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <4>; + vsync-len = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + pwms = <&pwm10 0 5000000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ + }; +}; + +&mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1_cd>; + cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cap-power-off-card; +}; + +&omap3_pmx_core { + gpio_key_pins: pinmux_gpio_key_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ + >; + }; + + pwm_pins: pinmux_pwm_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ + >; + }; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + tsc2004_pins: pinmux_tsc2004_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ + >; + }; + + isp_pins: pinmux_isp_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ + OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ + OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ + + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ + >; + }; + + panel_pwr_pins: pinmux_panel_pwr_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ + >; + }; + + dss_dpi_pins1: pinmux_dss_dpi_pins1 { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; +}; + +&omap3_pmx_wkup { + gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ + >; + }; + + lan9221_pins: pinmux_lan9221_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ + >; + }; + + mmc1_cd: pinmux_mmc1_cd { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ + >; + }; +}; + +&i2c2 { + mt9p031@48 { + compatible = "aptina,mt9p031"; + reg = <0x48>; + clocks = <&isp 0>; + vaa-supply = <&vaux4>; + vdd-supply = <&vaux4>; + vdd_io-supply = <&vaux4>; + port { + mt9p031_out: endpoint { + input-clock-frequency = <24000000>; + pixel-clock-frequency = <72000000>; + remote-endpoint = <&ccdc_ep>; + }; + }; + }; +}; + +&i2c3 { + touchscreen: tsc2004@48 { + compatible = "ti,tsc2004"; + reg = <0x48>; + vio-supply = <&vaux1>; + pinctrl-names = "default"; + pinctrl-0 = <&tsc2004_pins>; + interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ + + touchscreen-fuzz-x = <4>; + touchscreen-fuzz-y = <7>; + touchscreen-fuzz-pressure = <2>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + touchscreen-max-pressure = <2048>; + + ti,x-plate-ohms = <280>; + ti,esd-recovery-timeout-ms = <8000>; + }; +}; + +&mcspi1 { + at25@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + + pagesize = <64>; + size = <32768>; + address-width = <16>; + }; +}; + +&isp { + pinctrl-names = "default"; + pinctrl-0 = <&isp_pins>; + ports { + port@0 { + reg = <0>; + ccdc_ep: endpoint { + remote-endpoint = <&mt9p031_out>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; + }; + }; +}; + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 6d89736c7b44..47915447a826 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -30,17 +30,6 @@ linux,default-trigger = "none"; }; }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 29 0>; /* gpio157 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; }; &gpmc { @@ -73,37 +62,12 @@ gpmc,device-width = <2>; #address-cells = <1>; #size-cells = <1>; - - /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */ - - x-loader@0 { - label = "x-loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "u-boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "u-boot-env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "fs"; - reg = <0x680000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; }; }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; clock-frequency = <2600000>; twl: twl@48 { @@ -131,44 +95,7 @@ }; }; -/* - * Only found on the wireless SOM. For the SOM without wireless, the pins for - * MMC3 can be routed with jumpers to the second MMC slot on the devkit and - * gpio157 is not connected. So this should be OK to keep common for now, - * probably device tree overlays is the way to go with the various SOM and - * jumpering combinations for the long run. - */ -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; - pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1283"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - &omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ - >; - }; mcbsp2_pins: pinmux_mcbsp2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ @@ -211,6 +138,12 @@ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ >; }; + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; }; &uart2 { @@ -224,15 +157,6 @@ pinctrl-0 = <&mcspi1_pins>; }; -&omap3_pmx_core2 { - mmc3_core2_pins: pinmux_mmc3_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - >; - }; -}; - #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index 52b3ed10283a..58ea0a4e7afa 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -156,8 +156,8 @@ uda1380: uda1380@18 { compatible = "nxp,uda1380"; reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; + power-gpio = <&gpio 3 10 0>; + reset-gpio = <&gpio 3 2 0>; dac-clk = "wspll"; }; @@ -231,24 +231,24 @@ #address-cells = <1>; #size-cells = <1>; - mtd0@00000000 { + mtd0@0 { label = "ea3250-boot"; reg = <0x00000000 0x00080000>; read-only; }; - mtd1@00080000 { + mtd1@80000 { label = "ea3250-uboot"; reg = <0x00080000 0x000c0000>; read-only; }; - mtd2@00140000 { + mtd2@140000 { label = "ea3250-kernel"; reg = <0x00140000 0x00400000>; }; - mtd3@00540000 { + mtd3@540000 { label = "ea3250-rootfs"; reg = <0x00540000 0x07ac0000>; }; diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index fd95e2b10357..1e1c2f517a82 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -81,8 +81,8 @@ uda1380: uda1380@18 { compatible = "nxp,uda1380"; reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; + power-gpio = <&gpio 3 10 0>; + reset-gpio = <&gpio 3 2 0>; dac-clk = "wspll"; }; @@ -154,29 +154,29 @@ #address-cells = <1>; #size-cells = <1>; - mtd0@00000000 { + mtd0@0 { label = "phy3250-boot"; reg = <0x00000000 0x00064000>; read-only; }; - mtd1@00064000 { + mtd1@64000 { label = "phy3250-uboot"; reg = <0x00064000 0x00190000>; read-only; }; - mtd2@001f4000 { + mtd2@1f4000 { label = "phy3250-ubt-prms"; reg = <0x001f4000 0x00010000>; }; - mtd3@00204000 { + mtd3@204000 { label = "phy3250-kernel"; reg = <0x00204000 0x00400000>; }; - mtd4@00604000 { + mtd4@604000 { label = "phy3250-rootfs"; reg = <0x00604000 0x039fc000>; }; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index d81fe433e3c8..abff7ef7c9cd 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -55,7 +55,7 @@ <0x20000000 0x20000000 0x30000000>, <0xe0000000 0xe0000000 0x04000000>; - iram: sram@08000000 { + iram: sram@8000000 { compatible = "mmio-sram"; reg = <0x08000000 0x20000>; diff --git a/arch/arm/boot/dts/lpc4337-ciaa.dts b/arch/arm/boot/dts/lpc4337-ciaa.dts index 7c16d639a1b4..beddaba85393 100644 --- a/arch/arm/boot/dts/lpc4337-ciaa.dts +++ b/arch/arm/boot/dts/lpc4337-ciaa.dts @@ -174,17 +174,17 @@ clock-frequency = <400000>; eeprom@50 { - compatible = "microchip,24c512"; + compatible = "microchip,24c512", "atmel,24c512"; reg = <0x50>; }; eeprom@51 { - compatible = "microchip,24c02"; + compatible = "microchip,24c02", "atmel,24c02"; reg = <0x51>; }; eeprom@54 { - compatible = "microchip,24c512"; + compatible = "microchip,24c512", "atmel,24c512"; reg = <0x54>; }; }; diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index 874c75d44013..8b973f537d3a 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -429,7 +429,7 @@ }; eeprom@50 { - compatible = "nxp,24c02"; + compatible = "nxp,24c02", "atmel,24c02"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 9b5fad622522..02b23fa29d75 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -490,7 +490,7 @@ }; eeprom@57 { - compatible = "microchip,24c64"; + compatible = "microchip,24c64", "atmel,24c64"; reg = <0x57>; }; }; diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts new file mode 100644 index 000000000000..d01f64b252b1 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/ + * + * Author: Harry YJ Jhou (周亞諄) <harryyj.jhou@moxa.com> + * Jimmy Chen (陳永達) <jimmy.chen@moxa.com> + * SZ Lin (林上智) <sz.lin@moxa.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "ls1021a.dtsi" + +/ { + model = "Moxa UC-8410A"; + + aliases { + enet0_rgmii_phy = &rgmii_phy0; + enet1_rgmii_phy = &rgmii_phy1; + enet2_rgmii_phy = &rgmii_phy2; + }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + cel-pwr { + label = "UC8410A:CEL-PWR"; + gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + cel-reset { + label = "UC8410A:CEL-RESET"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + str-led { + label = "UC8410A:RED:PROG"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + sw-ready { + label = "UC8410A:GREEN:SWRDY"; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + beeper { + label = "UC8410A:BEEP"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + prog-led0 { + label = "UC8410A:GREEN:PROG2"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + prog-led1 { + label = "UC8410A:GREEN:PROG1"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + prog-led2 { + label = "UC8410A:GREEN:PROG0"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + wifi-signal0 { + label = "UC8410A:GREEN:CEL2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + wifi-signal1 { + label = "UC8410A:GREEN:CEL1"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + wifi-signal2 { + label = "UC8410A:GREEN:CEL0"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + cpu-diag-red { + label = "UC8410A:RED:DIA"; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + cpu-diag-green { + label = "UC8410A:GREEN:DIA"; + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + cpu-diag-yellow { + label = "UC8410A:YELLOW:DIA"; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pushbtn-key { + label = "push button key"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,code = <BTN_MISC>; + default-state = "on"; + }; + }; +}; + +&enet0 { + phy-handle = <&rgmii_phy0>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&enet1 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + tpm@20 { + compatible = "infineon,slb9635tt"; + reg = <0x20>; + }; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "marvell,88e1118"; + reg = <0x0>; + marvell,reg-init = + <3 0x11 0 0x4415>, /* Reg 3,17 */ + <3 0x10 0 0x77>; /* Reg 3,16 */ + }; + + rgmii_phy1: ethernet-phy@1 { + compatible = "marvell,88e1118"; + reg = <0x1>; + marvell,reg-init = + <3 0x11 0 0x4415>, /* Reg 3,17 */ + <3 0x10 0 0x77>; /* Reg 3,16 */ + }; + + rgmii_phy2: ethernet-phy@2 { + compatible = "marvell,88e1118"; + reg = <0x2>; + marvell,reg-init = + <3 0x11 0 0x4415>, /* Reg 3,17 */ + <3 0x10 0 0x77>; /* Reg 3,16 */ + }; +}; + +&qspi { + bus-num = <0>; + fsl,spi-num-chipselects = <2>; + fsl,spi-flash-chipselects = <0>; + fsl,qspi-has-second-chip; + status = "okay"; + + flash: flash@0 { + compatible = "spansion,s25fl064l", "spansion,s25fl164k"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + + partitions@0 { + label = "U-Boot"; + reg = <0x0 0x180000>; + }; + + partitions@180000 { + label = "U-Boot Env"; + reg = <0x180000 0x680000>; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 940875316d0f..499f41a2c6f0 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -215,7 +215,7 @@ reg = <0x2a>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk 1>; + clocks = <&sys_mclk>; }; }; }; @@ -239,6 +239,11 @@ device-width = <1>; }; + nand@2,0 { + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + }; + fpga: board-control@3,0 { #address-cells = <1>; #size-cells = <1>; @@ -331,3 +336,19 @@ &uart1 { status = "okay"; }; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "disabled"; +}; + +&can3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index a8b148ad1dd2..f0c949d74833 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -187,7 +187,7 @@ reg = <0x0a>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk 1>; + clocks = <&sys_mclk>; }; }; @@ -228,6 +228,10 @@ }; }; +&esdhc { + status = "okay"; +}; + &sai1 { status = "okay"; }; @@ -243,3 +247,19 @@ &uart1 { status = "okay"; }; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "disabled"; +}; + +&can3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 9319e1f0f1d8..c31dad98f989 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -106,6 +106,14 @@ compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&dcfg>; + offset = <0xb0>; + mask = <0x02>; }; soc { @@ -154,8 +162,22 @@ big-endian; }; + qspi: quadspi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x40000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + esdhc: esdhc@1560000 { - compatible = "fsl,esdhc"; + compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <0>; @@ -575,7 +597,7 @@ fsl,tclk-period = <5>; fsl,tmr-prsc = <2>; fsl,tmr-add = <0xaaaaaaab>; - fsl,tmr-fiper1 = <999999990>; + fsl,tmr-fiper1 = <999999995>; fsl,tmr-fiper2 = <99990>; fsl,max-adj = <499999999>; }; @@ -668,7 +690,7 @@ }; }; - usb@8600000 { + usb2: usb@8600000 { compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; reg = <0x0 0x8600000 0x0 0x1000>; interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; @@ -676,7 +698,7 @@ phy_type = "ulpi"; }; - usb3@3100000 { + usb3: usb3@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; @@ -730,5 +752,41 @@ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; }; + + can0: can@2a70000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a70000 0x0 0x1000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + }; + + can1: can@2a80000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a80000 0x0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + }; + + can2: can@2a90000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a90000 0x0 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + }; + + can3: can@2aa0000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2aa0000 0x0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + }; }; }; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index cd6ad072e72c..0d9faf1a51ea 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -80,6 +80,11 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + assist: assist@7c00 { + compatible = "amlogic,meson-mx-assist", "syscon"; + reg = <0x7c00 0x200>; + }; + hwrng: rng@8100 { compatible = "amlogic,meson-rng"; reg = <0x8100 0x8>; @@ -160,6 +165,15 @@ status = "disabled"; }; + sdio: mmc@8c20 { + compatible = "amlogic,meson-mx-sdio"; + reg = <0x8c20 0x20>; + interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spifc: spi@8c80 { compatible = "amlogic,meson6-spifc"; reg = <0x8c80 0x80>; @@ -168,6 +182,15 @@ status = "disabled"; }; + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0x9880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + wdt: watchdog@9900 { compatible = "amlogic,meson6-wdt"; reg = <0x9900 0x8>; @@ -217,7 +240,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xc9040000 0x40000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb0_phy>; phy-names = "usb2-phy"; dr_mode = "host"; @@ -229,7 +252,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xc90c0000 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb1_phy>; phy-names = "usb2-phy"; dr_mode = "host"; @@ -252,5 +275,25 @@ #size-cells = <1>; ranges = <0 0xd9000000 0x20000>; }; + + bootrom: bootrom@d9040000 { + compatible = "amlogic,meson-mx-bootrom", "syscon"; + reg = <0xd9040000 0x10000>; + }; + + secbus: secbus@da000000 { + compatible = "simple-bus"; + reg = <0xda000000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xda000000 0x6000>; + + efuse: nvmem@0 { + compatible = "amlogic,meson6-efuse"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index ef281d290052..9b463211339f 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -84,6 +84,9 @@ }; }; /* end of / */ +&efuse { + status = "disabled"; +}; &uart_AO { clocks = <&xtal>, <&clk81>, <&clk81>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index b98d44fde6b6..d2e3eeaa1a5f 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -45,6 +45,7 @@ #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> +#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include "meson.dtsi" / { @@ -60,6 +61,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x200>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; }; cpu@201 { @@ -67,6 +70,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x201>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; }; cpu@202 { @@ -74,6 +79,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x202>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; }; cpu@203 { @@ -81,6 +88,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x203>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; }; }; @@ -118,6 +127,11 @@ }; /* end of / */ &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8-pmu", "syscon"; + reg = <0xe0 0x8>; + }; + pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8-aobus-pinctrl"; reg = <0x84 0xc>; @@ -132,7 +146,7 @@ reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 120 16>; + gpio-ranges = <&pinctrl_aobus 0 0 16>; }; uart_ao_a_pins: uart_ao_a { @@ -173,6 +187,11 @@ reg = <0x8000 0x4>, <0x4000 0x460>; }; + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; + pwm_ef: pwm@86c0 { compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; reg = <0x86c0 0x10>; @@ -249,11 +268,29 @@ }; }; +&ahb_sram { + smp-sram@1ff80 { + compatible = "amlogic,meson8-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + +&efuse { + compatible = "amlogic,meson8-efuse"; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; +}; + ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; }; +&gpio_intc { + compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; + status = "okay"; +}; + &hwrng { compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; @@ -276,6 +313,9 @@ arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; &pwm_ab { @@ -289,9 +329,14 @@ &saradc { compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>; - clock-names = "clkin", "core", "sana"; + <&clkc CLKID_SAR_ADC>; + clock-names = "clkin", "core"; +}; + +&sdio { + compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; + clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; + clock-names = "core", "clkin"; }; &spifc { @@ -299,19 +344,27 @@ }; &uart_AO { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clock-names = "baud", "xtal", "pclk"; }; &uart_A { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clock-names = "baud", "xtal", "pclk"; }; &uart_B { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clock-names = "baud", "xtal", "pclk"; }; &uart_C { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clock-names = "baud", "xtal", "pclk"; }; &usb0 { diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index e50f1a1fdbc7..9ff6ca4e20d0 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -76,3 +76,26 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +&gpio_ao { + /* + * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal + * to be turned high in order to be detected by the USB Controller. + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index bc278da7df0d..7cd03ed3742e 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8b-gpio.h> #include <dt-bindings/reset/amlogic,meson8b-reset.h> +#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include "meson.dtsi" / { @@ -59,6 +60,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x200>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; }; cpu@201 { @@ -66,6 +69,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x201>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; }; cpu@202 { @@ -73,6 +78,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x202>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; }; cpu@203 { @@ -80,6 +87,20 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x203>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom@0 { + reg = <0x0 0x200000>; + no-map; }; }; @@ -90,6 +111,11 @@ }; /* end of / */ &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xe0 0x18>; + }; + pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8b-aobus-pinctrl"; reg = <0x84 0xc>; @@ -104,7 +130,7 @@ reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 130 16>; + gpio-ranges = <&pinctrl_aobus 0 0 16>; }; uart_ao_a_pins: uart_ao_a { @@ -130,6 +156,11 @@ #reset-cells = <1>; }; + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8b-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; + pwm_ef: pwm@86c0 { compatible = "amlogic,meson8b-pwm"; reg = <0x86c0 0x10>; @@ -157,11 +188,31 @@ }; }; +&ahb_sram { + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + + +&efuse { + compatible = "amlogic,meson8b-efuse"; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; +}; + ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; }; +&gpio_intc { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson8b-gpio-intc"; + status = "okay"; +}; + &hwrng { compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; @@ -172,6 +223,9 @@ arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; &pwm_ab { @@ -185,25 +239,38 @@ &saradc { compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>; - clock-names = "clkin", "core", "sana"; + <&clkc CLKID_SAR_ADC>; + clock-names = "clkin", "core"; +}; + +&sdio { + compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; + clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; + clock-names = "core", "clkin"; }; &uart_AO { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clock-names = "baud", "xtal", "pclk"; }; &uart_A { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clock-names = "baud", "xtal", "pclk"; }; &uart_B { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clock-names = "baud", "xtal", "pclk"; }; &uart_C { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clock-names = "baud", "xtal", "pclk"; }; &usb0 { diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index 116ce78bea4f..43aaa67fcd87 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -32,6 +32,18 @@ status = "okay"; }; + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + macb0: ethernet@fffbc000 { phy-mode = "rmii"; status = "okay"; @@ -46,7 +58,7 @@ }; }; - usb0: ohci@00300000 { + usb0: ohci@300000 { num-ports = <1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index f48497354221..63af4b13a36f 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -56,12 +56,29 @@ bt_sco_codec:bt_sco_codec { compatible = "linux,bt-sco"; }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&bls 0 100000>; + brightness-levels = < + 0 16 32 48 64 80 96 112 + 128 144 160 176 192 208 224 240 + 255 + >; + default-brightness-level = <9>; + }; }; &auxadc { status = "okay"; }; +&bls { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_bls_gpio>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -111,6 +128,12 @@ }; }; + pwm_bls_gpio: pwm_bls_gpio { + pins_cmd_dat { + pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>; + }; + }; + spi_pins_a: spi0@0 { pins_spi { pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>, diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index afe12e5b51f9..05557fce0f1d 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -430,7 +430,9 @@ compatible = "mediatek,mt2701-audio"; reg = <0 0x11220000 0 0x2000>, <0 0x112a0000 0 0x20000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, @@ -530,6 +532,15 @@ #clock-cells = <1>; }; + bls: pwm@1400a000 { + compatible = "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + larb0: larb@14010000 { compatible = "mediatek,mt2701-smi-larb"; reg = <0 0x14010000 0 0x1000>; @@ -593,6 +604,7 @@ compatible = "mediatek,mt2701-hifsys", "syscon"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; usb0: usb@1a1c0000 { @@ -677,6 +689,7 @@ compatible = "mediatek,mt2701-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; eth: ethernet@1b100000 { diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 0d6f60af7640..41df742d7891 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -139,7 +139,7 @@ status = "disabled"; }; - wdt: watchdog@010000000 { + wdt: watchdog@10000000 { compatible = "mediatek,mt6589-wdt"; reg = <0x10000000 0x44>; }; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index ec8a07415cb3..b750da5362f7 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -227,8 +227,7 @@ }; pio: pinctrl@10005000 { - compatible = "mediatek,mt7623-pinctrl", - "mediatek,mt2701-pinctrl"; + compatible = "mediatek,mt7623-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; pins-are-numbered; @@ -544,7 +543,9 @@ "mediatek,mt2701-audio"; reg = <0 0x11220000 0 0x2000>, <0 0x112a0000 0 0x20000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, @@ -640,7 +641,7 @@ mmc0: mmc@11230000 { compatible = "mediatek,mt7623-mmc", - "mediatek,mt8135-mmc"; + "mediatek,mt2701-mmc"; reg = <0 0x11230000 0 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; clocks = <&pericfg CLK_PERI_MSDC30_0>, @@ -651,7 +652,7 @@ mmc1: mmc@11240000 { compatible = "mediatek,mt7623-mmc", - "mediatek,mt8135-mmc"; + "mediatek,mt2701-mmc"; reg = <0 0x11240000 0 0x1000>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>; clocks = <&pericfg CLK_PERI_MSDC30_1>, @@ -678,7 +679,7 @@ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; status = "disabled"; @@ -688,8 +689,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a1c4000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -697,12 +696,16 @@ u2port0: usb-phy@1a1c4800 { reg = <0 0x1a1c4800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port0: usb-phy@1a1c4900 { reg = <0 0x1a1c4900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -717,7 +720,7 @@ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; status = "disabled"; @@ -727,8 +730,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a244000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -736,12 +737,16 @@ u2port1: usb-phy@1a244800 { reg = <0 0x1a244800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port1: usb-phy@1a244900 { reg = <0 0x1a244900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -753,6 +758,7 @@ "syscon"; reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; eth: ethernet@1b100000 { @@ -782,16 +788,15 @@ }; crypto: crypto@1b240000 { - compatible = "mediatek,mt7623-crypto"; + compatible = "mediatek,eip97-crypto"; reg = <0 0x1b240000 0 0x20000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "ethif","cryp"; + clocks = <ðsys CLK_ETHSYS_CRYPTO>; + clock-names = "cryp"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 688a86378cee..7bf5aa2237c9 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -204,7 +204,7 @@ bus-width = <4>; max-frequency = <50000000>; cap-sd-highspeed; - cd-gpios = <&pio 261 0>; + cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; vmmc-supply = <&mt6323_vmch_reg>; vqmmc-supply = <&mt6323_vio18_reg>; }; diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts index 17c578f0d261..e66de8611650 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts @@ -51,7 +51,7 @@ reg = <0x40000 0x80000>; }; - partition@C0000 { + partition@c0000 { label = "uboot-env"; reg = <0xC0000 0x40000>; }; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index ee5a0bb22354..1a5ae4cd107f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -20,7 +20,7 @@ }; }; - bootrom: bootrom@00000000 { + bootrom: bootrom@0 { reg = <0x00000000 0x80000>; }; @@ -56,6 +56,7 @@ usb_phy: usb_phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; vbus_reg: vbus_reg { diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 1de80c7886ab..63b0b4921e4e 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -7,6 +7,10 @@ reg = <0x80000000 0x8000000>; /* 128 MB */ }; + chosen { + stdout-path = &uart3; + }; + ocp { i2c0 { compatible = "i2c-cbus-gpio"; @@ -48,6 +52,7 @@ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; + compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 683b96a8f73e..0349fcc9dc26 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -90,6 +90,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; tfp410: encoder0 { diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 4d2eaf843fa9..3ca8991a6c3e 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -64,6 +64,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; sound { diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index 31d5ebf38892..9dcb18d22cde 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -43,12 +43,14 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <&hsusb1_power>; + #phy-cells = <0>; }; /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; ads7846reg: ads7846-reg { @@ -304,19 +306,19 @@ label = "xloader"; reg = <0 0x80000>; }; - partition@0x80000 { + partition@80000 { label = "uboot"; reg = <0x80000 0x1e0000>; }; - partition@0x260000 { + partition@260000 { label = "uboot environment"; reg = <0x260000 0x40000>; }; - partition@0x2a0000 { + partition@2a0000 { label = "linux"; reg = <0x2a0000 0x400000>; }; - partition@0x6a0000 { + partition@6a0000 { label = "rootfs"; reg = <0x6a0000 0x1f880000>; }; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index c963b31ec3b3..a14303b09ae2 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -9,146 +9,11 @@ #include "omap36xx.dtsi" #include "omap3-evm-common.dtsi" - +#include "omap3-evm-processor-common.dtsi" / { model = "TI OMAP37XX EVM (TMDSEVM3730)"; compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&ehci_phy_pins>; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; - - dss_dpi_pins1: pinmux_dss_dpi_pins2 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ - on_board_gpio_61: pinmux_ehci_port_select_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - - /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ - >; - }; - - smsc911x_pins: pinmux_smsc911x_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; }; &omap3_pmx_core2 { @@ -191,74 +56,7 @@ }; }; -&omap3_pmx_wkup { - dss_dpi_pins2: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -/* - * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface - * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. - */ -&gpio2 { - en_usb2_port { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ - output-low; - line-name = "enable usb2 port"; - }; -}; - -/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ -&twl_gpio { - en_on_board_gpio_61 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "en_hsusb2_clk"; - }; -}; - &gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; - nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ @@ -292,26 +90,21 @@ label = "X-Loader"; reg = <0 0x80000>; }; - partition@0x80000 { + partition@80000 { label = "U-Boot"; reg = <0x80000 0x1c0000>; }; - partition@0x1c0000 { + partition@1c0000 { label = "Environment"; reg = <0x240000 0x40000>; }; - partition@0x280000 { + partition@280000 { label = "Kernel"; reg = <0x280000 0x500000>; }; - partition@0x780000 { + partition@780000 { label = "Filesystem"; reg = <0x780000 0x1f880000>; }; }; - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc911x_pins>; - }; }; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index dbc3f030a16c..ee64191e41ca 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -29,6 +29,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; leds { diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi new file mode 100644 index 000000000000..ce7f42f9448c --- /dev/null +++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi @@ -0,0 +1,216 @@ +/* + * Common support for omap3 EVM 35xx/37xx processor modules + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + }; +}; + +&dss { + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&lcd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins1 + &dss_dpi_pins2 + >; +}; + +&hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&ehci_phy_pins>; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; + + dss_dpi_pins1: pinmux_dss_dpi_pins2 { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ + on_board_gpio_61: pinmux_ehci_port_select_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + + /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ + OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ + >; + }; + + smsc911x_pins: pinmux_smsc911x_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ + >; + }; +}; + +&omap3_pmx_wkup { + dss_dpi_pins2: pinmux_dss_dpi_pins1 { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +/* + * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface + * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. + */ +&gpio2 { + en_usb2_port { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ + output-low; + line-name = "enable usb2 port"; + }; +}; + +/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ +&twl_gpio { + en_on_board_gpio_61 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "en_hsusb2_clk"; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ + <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&smsc911x_pins>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 99b2bfcd1059..21a3b88aef0c 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -9,13 +9,81 @@ #include "omap34xx.dtsi" #include "omap3-evm-common.dtsi" +#include "omap3-evm-processor-common.dtsi" / { model = "TI OMAP35XX EVM (TMDSEVM3530)"; - compatible = "ti,omap3-evm", "ti,omap3"; + compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + + ehci_phy_pins: pinmux_ehci_phy_pins { + pinctrl-single,pins = < + + /* EHCI PHY reset GPIO etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) + + /* EHCI VBUS etk_d8.gpio_22 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + + /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) + + /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) + + /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d15.hsusb2_data1 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +&gpmc { + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name= "micron,mt29f2g16abdhc"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ + #address-cells = <1>; + #size-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 4504908c23fe..4170be70460e 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -86,7 +86,7 @@ /* lcd panel */ lcd: td028ttec1@0 { - compatible = "toppoly,td028ttec1"; + compatible = "tpo,td028ttec1"; reg = <0>; spi-max-frequency = <100000>; spi-cpol; @@ -120,6 +120,7 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + #phy-cells = <0>; }; tv0: connector { diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 4ad7d5565906..f33cc80c9dbc 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -147,32 +147,32 @@ gpmc,sync-read; gpmc,sync-write; gpmc,burst-length = <16>; - gpmc,burst-read; gpmc,burst-wrap; + gpmc,burst-read; gpmc,burst-write; gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; + gpmc,cs-rd-off-ns = <96>; + gpmc,cs-wr-off-ns = <96>; gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <18>; + gpmc,oe-off-ns = <96>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; + gpmc,we-off-ns = <96>; + gpmc,rd-cycle-ns = <114>; + gpmc,wr-cycle-ns = <114>; + gpmc,access-ns = <90>; + gpmc,page-burst-access-ns = <12>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; + gpmc,clk-activation-ns = <6>; gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; + gpmc,wr-access-ns = <90>; + gpmc,sync-clk-ps = <12000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi index 667f96245729..ecbec23af49f 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -58,6 +58,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ vcc-supply = <&hsusb1_power>; + #phy-cells = <0>; }; tfp410: encoder { diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi index e94d9427450c..443f71707437 100644 --- a/arch/arm/boot/dts/omap3-igep0030-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi @@ -37,6 +37,7 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ + #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index fa611a5e4850..cf7a2a72348d 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -51,6 +51,7 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_vcc3>; + #phy-cells = <0>; }; }; @@ -257,7 +258,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; gpiom1: gpio@20 { - compatible = "mcp,mcp23017"; + compatible = "microchip,mcp23017"; gpio-controller; #gpio-cells = <2>; reg = <0x20>; @@ -404,22 +405,22 @@ reg = <0 0x80000>; }; - partition@0x80000 { + partition@80000 { label = "u-boot"; reg = <0x80000 0x1e0000>; }; - partition@0x260000 { + partition@260000 { label = "u-boot-environment"; reg = <0x260000 0x20000>; }; - partition@0x280000 { + partition@280000 { label = "kernel"; reg = <0x280000 0x500000>; }; - partition@0x780000 { + partition@780000 { label = "filesystem"; reg = <0x780000 0xf880000>; }; diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index b9e58c536afd..e44d93fc644c 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "omap3-n950-n9.dtsi" +#include <dt-bindings/input/input.h> / { model = "Nokia N9"; @@ -26,6 +27,7 @@ clocks = <&isp 0>; clock-frequency = <9600000>; nokia,nvm-size = <(16 * 64)>; + flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { link-frequencies = /bits/ 64 <199200000 210000000 499200000>; @@ -71,3 +73,9 @@ st,max-limit-y = <46>; st,max-limit-z = <46>; }; + +&twl_keypad { + linux,keymap = < MATRIX_KEY(6, 8, KEY_VOLUMEUP) + MATRIX_KEY(7, 8, KEY_VOLUMEDOWN) + >; +}; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 4acd32a1c4ef..ab930581fc7a 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -35,6 +35,8 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + display0 = &lcd; + display1 = &tv; }; cpus { @@ -558,7 +560,7 @@ tlv320aic3x: tlv320aic3x@18 { compatible = "ti,tlv320aic3x"; reg = <0x18>; - gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ ai3x-gpio-func = < 0 /* AIC3X_GPIO1_FUNC_DISABLED */ 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ @@ -575,7 +577,7 @@ tlv320aic3x_aux: tlv320aic3x@19 { compatible = "ti,tlv320aic3x"; reg = <0x19>; - gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ AVDD-supply = <&vmmc2>; DRVDD-supply = <&vmmc2>; @@ -778,6 +780,8 @@ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ + lens-focus = <&ad5820>; + port { csi_cam1: endpoint { bus-type = <3>; /* CCP2 */ @@ -791,7 +795,7 @@ }; /* D/A converter for auto-focus */ - ad5820: dac@0c { + ad5820: dac@c { compatible = "adi,ad5820"; reg = <0x0c>; @@ -838,6 +842,7 @@ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; + compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; @@ -965,7 +970,7 @@ ti,esd-recovery-timeout-ms = <8000>; }; - acx565akm@2 { + lcd: acx565akm@2 { compatible = "sony,acx565akm"; spi-max-frequency = <6000000>; reg = <2>; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 1b0bd72945f2..0d9b85317529 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -271,14 +271,14 @@ #size-cells = <0>; reg = <0x30>; compatible = "ams,as3645a"; - flash@0 { + as3645a_flash: flash@0 { reg = <0x0>; flash-timeout-us = <150000>; flash-max-microamp = <320000>; led-max-microamp = <60000>; ams,input-max-microamp = <1750000>; }; - indicator@1 { + as3645a_indicator: indicator@1 { reg = <0x1>; led-max-microamp = <10000>; }; @@ -367,6 +367,7 @@ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; + compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 646601a3ebd8..2354e09343f3 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -51,6 +51,26 @@ }; }; +&omap3_pmx_core { + dsi_pins: pinmux_dsi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - clk+ */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - clk- */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE1) /* dsi_dx2 - data1+ */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - data1- */ + >; + }; + + display_pins: pinmux_display_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ + >; + }; +}; + &i2c2 { smia_1: camera@10 { compatible = "nokia,smia"; @@ -60,6 +80,7 @@ clocks = <&isp 0>; clock-frequency = <9600000>; nokia,nvm-size = <(16 * 64)>; + flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { link-frequencies = /bits/ 64 <210000000 333600000 398400000>; @@ -185,3 +206,71 @@ st,max-limit-y = <32>; st,max-limit-z = <32>; }; + +&dss { + status = "ok"; + + vdda_video-supply = <&vdac>; +}; + +&dsi { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dsi_pins>; + + vdd-supply = <&vpll2>; + + port { + dsi_out_ep: endpoint { + remote-endpoint = <&lcd0_in>; + lanes = <2 3 0 1 4 5>; + }; + }; + + lcd0: display { + compatible = "nokia,himalaya", "panel-dsi-cm"; + label = "lcd0"; + + pinctrl-names = "default"; + pinctrl-0 = <&display_pins>; + + vpnl-supply = <&vmmc2>; + vddi-supply = <&vio>; + + reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ + te-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; /* 62 */ + + width-mm = <49>; /* 48.960 mm */ + height-mm = <88>; /* 88.128 mm */ + + /* TODO: + * - panel is upside-down + * - top + bottom 5px are not visible + */ + panel-timing { + clock-frequency = <0>; /* Calculated by dsi */ + + hback-porch = <2>; + hactive = <480>; + hfront-porch = <0>; + hsync-len = <2>; + + vback-porch = <1>; + vactive = <864>; + vfront-porch = <0>; + vsync-len = <1>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd0_in: endpoint { + remote-endpoint = <&dsi_out_ep>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index f25e158e7163..ac141fcd1742 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -51,6 +51,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; /* Regulator to trigger the nPoweron signal of the Wifi module */ diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 53e007abdc71..f83b1029b3b7 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -205,6 +205,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ vcc-supply = <&vaux2>; + #phy-cells = <0>; }; /* HS USB Host VBUS supply @@ -626,7 +627,7 @@ lcd: lcd@1 { reg = <1>; /* CS1 */ - compatible = "omapdss,tpo,td043mtea1"; + compatible = "tpo,td043mtea1"; spi-max-frequency = <100000>; spi-cpol; spi-cpha; diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi index 25e100db7b1a..b8b9fcc41ef1 100644 --- a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi @@ -30,6 +30,7 @@ compatible = "sharp,ls037v7dw01"; label = "lcd"; power-supply = <&lcd_3v3>; + envdd-supply = <&lcd_3v3>; port { lcd_in: endpoint { diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index 9a601d15247b..6f5bd027b717 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -46,6 +46,7 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; }; sound { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index bdaf30c8c405..a005802cd52b 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -215,6 +215,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <96>; + ti,hwmods = "dma"; }; gpio1: gpio@48310000 { @@ -586,20 +587,6 @@ dma-names = "rx"; }; - smartreflex_core: smartreflex@480cb000 { - compatible = "ti,omap3-smartreflex-core"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb000 0x400>; - interrupts = <19>; - }; - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-iva"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9000 0x400>; - interrupts = <18>; - }; - timer1: timer@48318000 { compatible = "ti,omap3430-timer"; reg = <0x48318000 0x400>; @@ -714,6 +701,7 @@ compatible = "ti,ohci-omap3"; reg = <0x48064400 0x400>; interrupts = <76>; + remote-wakeup-connected; }; usbhsehci: ehci@48064800 { diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 908951eb5943..d652708f6bef 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -154,6 +154,7 @@ linux,mtd-name= "samsung,kfm2g16q2m-deb8"; #address-cells = <1>; #size-cells = <1>; + compatible = "ti,omap2-onenand"; reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ gpmc,device-width = <2>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index ac4f8795b756..f572a477f74c 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/media/omap3-isp.h> #include "omap3.dtsi" @@ -61,6 +62,44 @@ compatible = "ti,omap34xx-bandgap"; #thermal-sensor-cells = <0>; }; + + target-module@480cb000 { + compatible = "ti,sysc-omap3430-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x480cb024 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>; + clocks = <&sr2_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480cb000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap3-smartreflex-core"; + reg = <0 0x400>; + interrupts = <19>; + }; + }; + + target-module@480c9000 { + compatible = "ti,sysc-omap3430-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu_iva"; + reg = <0x480c9024 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>; + clocks = <&sr1_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c9000 0x001000>; + + smartreflex_mpu_iva: smartreflex@480c9000 { + compatible = "ti,omap3-smartreflex-mpu-iva"; + reg = <0 0x400>; + interrupts = <18>; + }; + }; }; thermal_zones: thermal-zones { diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index ade31d74c70c..6fb23ada1f64 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/media/omap3-isp.h> #include "omap3.dtsi" @@ -93,6 +94,51 @@ compatible = "ti,omap36xx-bandgap"; #thermal-sensor-cells = <0>; }; + + target-module@480cb000 { + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x480cb038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + clocks = <&sr2_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480cb000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap3-smartreflex-core"; + reg = <0 0x400>; + interrupts = <19>; + }; + }; + + target-module@480c9000 { + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu_iva"; + reg = <0x480c9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + clocks = <&sr1_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c9000 0x001000>; + + + smartreflex_mpu_iva: smartreflex@480c9000 { + compatible = "ti,omap3-smartreflex-mpu-iva"; + reg = <0 0x400>; + interrupts = <18>; + }; + }; }; thermal_zones: thermal-zones { diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 8b93d37310f2..b21084da490b 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -73,6 +73,7 @@ /* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; /* LCD regulator from sw5 source */ @@ -176,6 +177,10 @@ vddi-supply = <&lcd_regulator>; reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ + width-mm = <50>; + height-mm = <89>; + backlight = <&lcd_backlight>; + panel-timing { clock-frequency = <0>; /* Calculated by dsi */ @@ -345,7 +350,7 @@ enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - backlight { + lcd_backlight: backlight { compatible = "ti,lm3532-backlight"; lcd { diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index 6e6810c258eb..eb123b24c8e3 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -43,6 +43,7 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + #phy-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsusb1phy_pins>; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 2b48e51c372a..5501d1b4e6cd 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -13,6 +13,10 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; + chosen { + stdout-path = &uart3; + }; + aliases { display0 = &dvi0; display1 = &hdmi0; @@ -85,6 +89,7 @@ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + #phy-cells = <0>; vcc-supply = <&hsusb1_power>; clocks = <&auxclk3_ck>; clock-names = "main_clk"; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 6500bfc8d130..10fce28ceb5b 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -44,6 +44,7 @@ reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ vcc-supply = <&vbat>; + #phy-cells = <0>; clocks = <&auxclk3_ck>; clock-names = "main_clk"; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 64d00f5893a6..475904894b86 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -6,9 +6,12 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/bus/ti-sysc.h> +#include <dt-bindings/clock/omap4.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/omap.h> +#include <dt-bindings/clock/omap4.h> / { compatible = "ti,omap4430", "ti,omap4"; @@ -51,6 +54,17 @@ }; }; + /* + * Note that 4430 needs cross trigger interface (CTI) supported + * before we can configure the interrupts. This means sampling + * events are not supported for pmu. Note that 4460 does not use + * CTI, see also 4460.dtsi. + */ + pmu { + compatible = "arm,cortex-a9-pmu"; + ti,hwmods = "debugss"; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -132,8 +146,11 @@ ranges = <0 0x4a000000 0x1000000>; cm1: cm1@4000 { - compatible = "ti,omap4-cm1"; + compatible = "ti,omap4-cm1", "simple-bus"; reg = <0x4000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4000 0x2000>; cm1_clocks: clocks { #address-cells = <1>; @@ -145,8 +162,11 @@ }; cm2: cm2@8000 { - compatible = "ti,omap4-cm2"; + compatible = "ti,omap4-cm2", "simple-bus"; reg = <0x8000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8000 0x3000>; cm2_clocks: clocks { #address-cells = <1>; @@ -163,6 +183,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2000 0x1000>; + ti,hwmods = "ctrl_module_core"; scm_conf: scm_conf@0 { compatible = "syscon"; @@ -175,9 +196,11 @@ omap4_padconf_core: scm@100000 { compatible = "ti,omap4-scm-padconf-core", "simple-bus"; + reg = <0x100000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x100000 0x1000>; + ti,hwmods = "ctrl_module_pad_core"; omap4_pmx_core: pinmux@40 { compatible = "ti,omap4-padconf", @@ -229,6 +252,9 @@ compatible = "ti,omap4-prm"; reg = <0x6000 0x3000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x6000 0x3000>; prm_clocks: clocks { #address-cells = <1>; @@ -252,17 +278,33 @@ }; }; - omap4_pmx_wkup: pinmux@1e040 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x1e040 0x0038>; + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + ti,hwmods = "ctrl_module_wkup"; + }; + + omap4_padconf_wkup: padconf@1e000 { + compatible = "ti,omap4-scm-padconf-wkup", + "simple-bus"; + reg = <0x1e000 0x1000>; #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; + #size-cells = <1>; + ranges = <0 0x1e000 0x1000>; + ti,hwmods = "ctrl_module_pad_wkup"; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; }; @@ -282,6 +324,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4a310000 { @@ -351,10 +394,30 @@ #interrupt-cells = <2>; }; + target-module@48076000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "slimbus2"; + reg = <0x48076000 0x4>, + <0x48076010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48076000 0x001000>; + + /* No child device binding or driver in mainline */ + }; + elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0x2000>; - interrupts = <4>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "elm"; status = "disabled"; }; @@ -411,6 +474,75 @@ clock-frequency = <48000000>; }; + target-module@4a0db000 { + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_iva"; + reg = <0x4a0db038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0db000 0x001000>; + + smartreflex_iva: smartreflex@0 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0 0x80>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@4a0dd000 { + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x4a0dd038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0dd000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0 0x80>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@4a0d9000 { + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu"; + reg = <0x4a0d9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0d9000 0x001000>; + + smartreflex_mpu: smartreflex@0 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0 0x80>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + hwspinlock: spinlock@4a0f6000 { compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; @@ -489,6 +621,13 @@ dma-names = "tx0", "rx0", "tx1", "rx1"; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "hdq1w"; + }; + mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; @@ -565,6 +704,40 @@ dma-names = "tx", "rx"; }; + hsi: hsi@4a058000 { + compatible = "ti,omap4-hsi"; + reg = <0x4a058000 0x4000>, + <0x4a05c000 0x1000>; + reg-names = "sys", "gdd"; + ti,hwmods = "hsi"; + + clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; + clock-names = "hsi_fck"; + + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a058000 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; @@ -573,6 +746,31 @@ #iommu-cells = <0>; }; + target-module@52000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "iss"; + reg = <0x52000000 0x4>, + <0x52000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-delay-us = <2>; + clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x52000000 0x1000000>; + + /* No child device binding, driver in staging */ + }; + mmu_ipu: mmu@55082000 { compatible = "ti,omap4-iommu"; reg = <0x55082000 0x100>; @@ -589,6 +787,14 @@ ti,hwmods = "wd_timer2"; }; + wdt3: wdt@40130000 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x40130000 0x80>, /* MPU private access */ + <0x49030000 0x80>; /* L3 Interconnect */ + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "wd_timer3"; + }; + mcpdm: mcpdm@40132000 { compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ @@ -659,6 +865,79 @@ status = "disabled"; }; + target-module@40128000 { + compatible = "ti,sysc-mcasp", "ti,sysc"; + ti,hwmods = "mcasp"; + reg = <0x40128000 0x4>, + <0x40128004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40128000 0x1000>, /* MPU */ + <0x49028000 0x49028000 0x1000>; /* L3 */ + + /* + * Child device unsupported by davinci-mcasp. At least + * RX path is disabled for omap4, and only DIT mode + * works with no I2S. See also old Android kernel + * omap-mcasp driver for more information. + */ + }; + + target-module@4012c000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "slimbus1"; + reg = <0x4012c000 0x4>, + <0x4012c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ + <0x4902c000 0x4902c000 0x1000>; /* L3 */ + + /* No child device binding or driver in mainline */ + }; + + target-module@401f1000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "aess"; + reg = <0x401f1000 0x4>, + <0x401f1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */ + <0x490f1000 0x490f1000 0x1000>; /* L3 */ + + /* + * No child device binding or driver in mainline. + * See Android tree and related upstreaming efforts + * for the old driver. + */ + }; + mcbsp4: mcbsp@48096000 { compatible = "ti,omap4-mcbsp"; reg = <0x48096000 0xff>; /* L4 Interconnect */ @@ -747,12 +1026,37 @@ }; }; + target-module@4a10a000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "fdif"; + reg = <0x4a10a000 0x4>, + <0x4a10a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-delay-us = <2>; + clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a10a000 0x1000>; + + /* No child device binding or driver in mainline */ + }; + timer1: timer@4a318000 { compatible = "ti,omap3430-timer"; reg = <0x4a318000 0x80>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer1"; ti,timer-alwon; + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; + clock-names = "fck"; }; timer2: timer@48032000 { @@ -861,14 +1165,13 @@ usbhsohci: ohci@4a064800 { compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + remote-wakeup-connected; }; usbhsehci: ehci@4a064c00 { compatible = "ti,ehci-omap"; reg = <0x4a064c00 0x400>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -962,12 +1265,38 @@ status = "disabled"; }; + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "gpu"; + reg = <0x5601fc00 0x4>, + <0x5601fc10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + dss: dss@58000000 { compatible = "ti,omap4-dss"; reg = <0x58000000 0x80>; status = "disabled"; ti,hwmods = "dss_core"; - clocks = <&dss_dss_clk>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -978,7 +1307,7 @@ reg = <0x58001000 0x1000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "dss_dispc"; - clocks = <&dss_dss_clk>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; }; @@ -987,7 +1316,7 @@ reg = <0x58002000 0x1000>; status = "disabled"; ti,hwmods = "dss_rfbi"; - clocks = <&dss_dss_clk>, <&l3_div_ck>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; clock-names = "fck", "ick"; }; @@ -996,7 +1325,7 @@ reg = <0x58003000 0x1000>; status = "disabled"; ti,hwmods = "dss_venc"; - clocks = <&dss_tv_clk>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; clock-names = "fck"; }; @@ -1009,7 +1338,8 @@ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ti,hwmods = "dss_dsi1"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; @@ -1022,7 +1352,8 @@ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ti,hwmods = "dss_dsi2"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; @@ -1036,7 +1367,8 @@ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ti,hwmods = "dss_hdmi"; - clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; dmas = <&sdma 76>; dma-names = "audio_tx"; @@ -1045,4 +1377,4 @@ }; }; -/include/ "omap44xx-clocks.dtsi" +#include "omap44xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 05732ed4f50f..279ff2f419df 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -174,14 +174,6 @@ ti,index-power-of-two; }; - aess_fclk: aess_fclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x0528>; - }; dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; @@ -464,7 +456,7 @@ ocp_abe_iclk: ocp_abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; + clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; ti,bit-shift = <24>; reg = <0x0528>; ti,dividers = <2>, <1>; @@ -478,156 +470,13 @@ clock-div = <4>; }; - dmic_sync_mux_ck: dmic_sync_mux_ck@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0538>; - }; - - func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0538>; - }; - - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0540>; - }; - - func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0540>; - }; - - mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0548>; - }; - - func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0548>; - }; - - mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0550>; - }; - - func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0550>; - }; - - mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0558>; - }; - - func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0558>; - }; - - slimbus1_fclk_1: slimbus1_fclk_1@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_24m_clk>; - ti,bit-shift = <9>; - reg = <0x0560>; - }; - - slimbus1_fclk_0: slimbus1_fclk_0@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&abe_24m_fclk>; - ti,bit-shift = <8>; - reg = <0x0560>; - }; - - slimbus1_fclk_2: slimbus1_fclk_2@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_ck>; - ti,bit-shift = <10>; - reg = <0x0560>; - }; - - slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; - }; - - timer5_sync_mux: timer5_sync_mux@568 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0568>; - }; - - timer6_sync_mux: timer6_sync_mux@570 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0570>; - }; - - timer7_sync_mux: timer7_sync_mux@578 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0578>; - }; - - timer8_sync_mux: timer8_sync_mux@580 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0580>; - }; - dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; + &prm_clocks { sys_clkin_ck: sys_clkin_ck@110 { #clock-cells = <0>; @@ -675,22 +524,6 @@ ti,max-div = <2>; }; - gpio1_dbclk: gpio1_dbclk@1838 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1838>; - }; - - dmt1_clk_mux: dmt1_clk_mux@1840 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1840>; - }; - usim_ck: usim_ck@1858 { #clock-cells = <0>; compatible = "ti,divider-clock"; @@ -708,45 +541,10 @@ reg = <0x1858>; }; - pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; - ti,bit-shift = <20>; - reg = <0x1a20>; - }; - - pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; - ti,bit-shift = <22>; - reg = <0x1a20>; - }; - - stm_clk_div_ck: stm_clk_div_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&pmd_stm_clock_mux_ck>; - ti,bit-shift = <27>; - ti,max-div = <64>; - reg = <0x1a20>; - ti,index-power-of-two; - }; - - trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&pmd_trace_clk_mux_ck>; - ti,bit-shift = <24>; - reg = <0x1a20>; - ti,dividers = <0>, <1>, <2>, <0>, <4>; - }; - trace_clk_div_ck: trace_clk_div_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; - clocks = <&trace_clk_div_div_ck>; + clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; }; }; @@ -975,155 +773,6 @@ ti,max-div = <2>; }; - dss_sys_clk: dss_sys_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&syc_clk_div_ck>; - ti,bit-shift = <10>; - reg = <0x1120>; - }; - - dss_tv_clk: dss_tv_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&extalt_clkin_ck>; - ti,bit-shift = <11>; - reg = <0x1120>; - }; - - dss_dss_clk: dss_dss_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_m5x2_ck>; - ti,bit-shift = <8>; - reg = <0x1120>; - ti,set-rate-parent; - }; - - dss_48mhz_clk: dss_48mhz_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48mc_fclk>; - ti,bit-shift = <9>; - reg = <0x1120>; - }; - - fdif_fck: fdif_fck@1028 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m4x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <4>; - reg = <0x1028>; - ti,index-power-of-two; - }; - - gpio2_dbclk: gpio2_dbclk@1460 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1460>; - }; - - gpio3_dbclk: gpio3_dbclk@1468 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1468>; - }; - - gpio4_dbclk: gpio4_dbclk@1470 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1470>; - }; - - gpio5_dbclk: gpio5_dbclk@1478 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1478>; - }; - - gpio6_dbclk: gpio6_dbclk@1480 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1480>; - }; - - sgx_clk_mux: sgx_clk_mux@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>; - ti,bit-shift = <24>; - reg = <0x1220>; - }; - - hsi_fck: hsi_fck@1338 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <4>; - reg = <0x1338>; - ti,index-power-of-two; - }; - - iss_ctrlclk: iss_ctrlclk@1020 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_fclk>; - ti,bit-shift = <8>; - reg = <0x1020>; - }; - - mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>; - ti,bit-shift = <25>; - reg = <0x14e0>; - }; - - per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>; - ti,bit-shift = <24>; - reg = <0x14e0>; - }; - - hsmmc1_fclk: hsmmc1_fclk@1328 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_64m_fclk>, <&func_96m_fclk>; - ti,bit-shift = <24>; - reg = <0x1328>; - }; - - hsmmc2_fclk: hsmmc2_fclk@1330 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_64m_fclk>, <&func_96m_fclk>; - ti,bit-shift = <24>; - reg = <0x1330>; - }; - - ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48m_fclk>; - ti,bit-shift = <8>; - reg = <0x13e0>; - }; - sha2md5_fck: sha2md5_fck@15c8 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -1132,222 +781,6 @@ reg = <0x15c8>; }; - slimbus2_fclk_1: slimbus2_fclk_1@1538 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_abe_24m_fclk>; - ti,bit-shift = <9>; - reg = <0x1538>; - }; - - slimbus2_fclk_0: slimbus2_fclk_0@1538 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_24mc_fclk>; - ti,bit-shift = <8>; - reg = <0x1538>; - }; - - slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_slimbus_core_clks_ck>; - ti,bit-shift = <10>; - reg = <0x1538>; - }; - - smartreflex_core_fck: smartreflex_core_fck@638 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0638>; - }; - - smartreflex_iva_fck: smartreflex_iva_fck@630 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0630>; - }; - - smartreflex_mpu_fck: smartreflex_mpu_fck@628 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0628>; - }; - - cm2_dm10_mux: cm2_dm10_mux@1428 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1428>; - }; - - cm2_dm11_mux: cm2_dm11_mux@1430 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1430>; - }; - - cm2_dm2_mux: cm2_dm2_mux@1438 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1438>; - }; - - cm2_dm3_mux: cm2_dm3_mux@1440 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1440>; - }; - - cm2_dm4_mux: cm2_dm4_mux@1448 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1448>; - }; - - cm2_dm9_mux: cm2_dm9_mux@1450 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1450>; - }; - - usb_host_fs_fck: usb_host_fs_fck@13d0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48mc_fclk>; - ti,bit-shift = <1>; - reg = <0x13d0>; - }; - - utmi_p1_gfclk: utmi_p1_gfclk@1358 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>; - ti,bit-shift = <24>; - reg = <0x1358>; - }; - - usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p1_gfclk>; - ti,bit-shift = <8>; - reg = <0x1358>; - }; - - utmi_p2_gfclk: utmi_p2_gfclk@1358 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>; - ti,bit-shift = <25>; - reg = <0x1358>; - }; - - usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p2_gfclk>; - ti,bit-shift = <9>; - reg = <0x1358>; - }; - - usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1358>; - }; - - usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <13>; - reg = <0x1358>; - }; - - usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <11>; - reg = <0x1358>; - }; - - usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <12>; - reg = <0x1358>; - }; - - usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <14>; - reg = <0x1358>; - }; - - usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48mc_fclk>; - ti,bit-shift = <15>; - reg = <0x1358>; - }; - - usb_host_hs_fck: usb_host_hs_fck@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <1>; - reg = <0x1358>; - }; - - otg_60m_gfclk: otg_60m_gfclk@1360 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>; - ti,bit-shift = <24>; - reg = <0x1360>; - }; - - usb_otg_hs_xclk: usb_otg_hs_xclk@1360 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&otg_60m_gfclk>; - ti,bit-shift = <8>; - reg = <0x1360>; - }; - - usb_otg_hs_ick: usb_otg_hs_ick@1360 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <0>; - reg = <0x1360>; - }; - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -1355,44 +788,12 @@ ti,bit-shift = <8>; reg = <0x0640>; }; - - usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1368>; - }; - - usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <8>; - reg = <0x1368>; - }; - - usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <9>; - reg = <0x1368>; - }; - - usb_tll_hs_ick: usb_tll_hs_ick@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_div_ck>; - ti,bit-shift = <0>; - reg = <0x1368>; - }; }; &cm2_clockdomains { l3_init_clkdm: l3_init_clkdm { compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>; + clocks = <&dpll_usb_ck>; }; }; @@ -1631,3 +1032,291 @@ reg = <0x0224>; }; }; + +&cm1 { + mpuss_cm: mpuss_cm@300 { + compatible = "ti,omap4-cm"; + reg = <0x300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300 0x100>; + + mpuss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + tesla_cm: tesla_cm@400 { + compatible = "ti,omap4-cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + tesla_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + abe_cm: abe_cm@500 { + compatible = "ti,omap4-cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + abe_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x6c>; + #clock-cells = <2>; + }; + }; + +}; + +&cm2 { + l4_ao_cm: l4_ao_cm@600 { + compatible = "ti,omap4-cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + l4_ao_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + l3_1_cm: l3_1_cm@700 { + compatible = "ti,omap4-cm"; + reg = <0x700 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x100>; + + l3_1_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_2_cm: l3_2_cm@800 { + compatible = "ti,omap4-cm"; + reg = <0x800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x100>; + + l3_2_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + ducati_cm: ducati_cm@900 { + compatible = "ti,omap4-cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + ducati_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_dma_cm: l3_dma_cm@a00 { + compatible = "ti,omap4-cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + l3_dma_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_emif_cm: l3_emif_cm@b00 { + compatible = "ti,omap4-cm"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb00 0x100>; + + l3_emif_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + d2d_cm: d2d_cm@c00 { + compatible = "ti,omap4-cm"; + reg = <0xc00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xc00 0x100>; + + d2d_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l4_cfg_cm: l4_cfg_cm@d00 { + compatible = "ti,omap4-cm"; + reg = <0xd00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd00 0x100>; + + l4_cfg_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + l3_instr_cm: l3_instr_cm@e00 { + compatible = "ti,omap4-cm"; + reg = <0xe00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe00 0x100>; + + l3_instr_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x24>; + #clock-cells = <2>; + }; + }; + + ivahd_cm: ivahd_cm@f00 { + compatible = "ti,omap4-cm"; + reg = <0xf00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xf00 0x100>; + + ivahd_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + iss_cm: iss_cm@1000 { + compatible = "ti,omap4-cm"; + reg = <0x1000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x100>; + + iss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + l3_dss_cm: l3_dss_cm@1100 { + compatible = "ti,omap4-cm"; + reg = <0x1100 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1100 0x100>; + + l3_dss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_gfx_cm: l3_gfx_cm@1200 { + compatible = "ti,omap4-cm"; + reg = <0x1200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1200 0x100>; + + l3_gfx_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_init_cm: l3_init_cm@1300 { + compatible = "ti,omap4-cm"; + reg = <0x1300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1300 0x100>; + + l3_init_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xc4>; + #clock-cells = <2>; + }; + }; + + l4_per_cm: l4_per_cm@1400 { + compatible = "ti,omap4-cm"; + reg = <0x1400 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x200>; + + l4_per_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x144>; + #clock-cells = <2>; + }; + }; + +}; + +&prm { + l4_wkup_cm: l4_wkup_cm@1800 { + compatible = "ti,omap4-cm"; + reg = <0x1800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1800 0x100>; + + l4_wkup_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x5c>; + #clock-cells = <2>; + }; + }; + + emu_sys_cm: emu_sys_cm@1a00 { + compatible = "ti,omap4-cm"; + reg = <0x1a00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1a00 0x100>; + + emu_sys_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 7824b2631cb6..1b20838bb9a4 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -14,6 +14,10 @@ display0 = &hdmi0; }; + chosen { + stdout-path = &uart3; + }; + vmain: fixedregulator-vmain { compatible = "regulator-fixed"; regulator-name = "vmain"; @@ -69,12 +73,14 @@ clocks = <&auxclk1_ck>; clock-names = "main_clk"; clock-frequency = <19200000>; + #phy-cells = <0>; }; /* HS USB Host PHY on PORT 3 */ hsusb3_phy: hsusb3_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ + #phy-cells = <0>; }; tpd12s015: encoder { diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 5b172a04b6f1..5e21fb430a65 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -63,12 +63,14 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ + #phy-cells = <0>; }; /* HS USB Host PHY on PORT 3 */ hsusb3_phy: hsusb3_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ + #phy-cells = <0>; }; leds { diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index ec2c8baef62a..592e17fd4eeb 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -47,7 +47,7 @@ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ wakeup-source; autorepeat; - debounce_interval = <50>; + debounce-interval = <50>; }; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index eaff2a5751dd..35d4298da83d 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/omap.h> +#include <dt-bindings/clock/omap5.h> / { #address-cells = <2>; @@ -194,15 +195,19 @@ pbias_mmc_reg: pbias_mmc_omap5 { regulator-name = "pbias_mmc_omap5"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; }; }; }; }; cm_core_aon: cm_core_aon@4000 { - compatible = "ti,omap5-cm-core-aon"; + compatible = "ti,omap5-cm-core-aon", + "simple-bus"; reg = <0x4000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4000 0x2000>; cm_core_aon_clocks: clocks { #address-cells = <1>; @@ -214,8 +219,11 @@ }; cm_core: cm_core@8000 { - compatible = "ti,omap5-cm-core"; + compatible = "ti,omap5-cm-core", "simple-bus"; reg = <0x8000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8000 0x3000>; cm_core_clocks: clocks { #address-cells = <1>; @@ -240,9 +248,12 @@ }; prm: prm@6000 { - compatible = "ti,omap5-prm"; + compatible = "ti,omap5-prm", "simple-bus"; reg = <0x6000 0x3000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x6000 0x3000>; prm_clocks: clocks { #address-cells = <1>; @@ -295,6 +306,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4ae10000 { @@ -733,6 +745,8 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer1"; ti,timer-alwon; + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; + clock-names = "fck"; }; timer2: timer@48032000 { @@ -892,7 +906,8 @@ compatible = "ti,omap-usb2"; reg = <0x4a084000 0x7c>; syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; + clocks = <&usb_phy_cm_clk32k>, + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; }; @@ -906,7 +921,7 @@ syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>, - <&usb_otg_ss_refclk960m>; + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; clock-names = "wkupclk", "sysclk", "refclk"; @@ -939,6 +954,7 @@ compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + remote-wakeup-connected; }; usbhsehci: ehci@4a064c00 { @@ -974,7 +990,8 @@ <0x4A096800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, <&sata_ref_clk>; + clocks = <&sys_clkin>, + <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; clock-names = "sysclk", "refclk"; #phy-cells = <0>; }; @@ -986,7 +1003,7 @@ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; phys = <&sata_phy>; phy-names = "sata-phy"; - clocks = <&sata_ref_clk>; + clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; ti,hwmods = "sata"; ports-implemented = <0x1>; }; @@ -996,7 +1013,7 @@ reg = <0x58000000 0x80>; status = "disabled"; ti,hwmods = "dss_core"; - clocks = <&dss_dss_clk>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -1007,7 +1024,7 @@ reg = <0x58001000 0x1000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "dss_dispc"; - clocks = <&dss_dss_clk>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; }; @@ -1016,7 +1033,7 @@ reg = <0x58002000 0x100>; status = "disabled"; ti,hwmods = "dss_rfbi"; - clocks = <&dss_dss_clk>, <&l3_iclk_div>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; clock-names = "fck", "ick"; }; @@ -1029,7 +1046,8 @@ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ti,hwmods = "dss_dsi1"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; @@ -1042,7 +1060,8 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ti,hwmods = "dss_dsi2"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; @@ -1056,7 +1075,8 @@ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ti,hwmods = "dss_hdmi"; - clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; dmas = <&sdma 76>; dma-names = "audio_tx"; @@ -1130,7 +1150,7 @@ coefficients = <65 (-1791)>; }; -/include/ "omap54xx-clocks.dtsi" +#include "omap54xx-clocks.dtsi" &gpu_thermal { coefficients = <117 (-2992)>; diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 529193442620..9619a746d657 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -432,22 +432,6 @@ reg = <0x0528>; }; - dmic_sync_mux_ck: dmic_sync_mux_ck@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0538>; - }; - - dmic_gfclk: dmic_gfclk@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0538>; - }; - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -464,86 +448,6 @@ reg = <0x0540>; }; - mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0548>; - }; - - mcbsp1_gfclk: mcbsp1_gfclk@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0548>; - }; - - mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0550>; - }; - - mcbsp2_gfclk: mcbsp2_gfclk@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0550>; - }; - - mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0558>; - }; - - mcbsp3_gfclk: mcbsp3_gfclk@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0558>; - }; - - timer5_gfclk_mux: timer5_gfclk_mux@568 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0568>; - }; - - timer6_gfclk_mux: timer6_gfclk_mux@570 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0570>; - }; - - timer7_gfclk_mux: timer7_gfclk_mux@578 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0578>; - }; - - timer8_gfclk_mux: timer8_gfclk_mux@580 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0580>; - }; - dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; @@ -603,23 +507,8 @@ clock-mult = <1>; clock-div = <1>; }; - - gpio1_dbclk: gpio1_dbclk@1938 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1938>; - }; - - timer1_gfclk_mux: timer1_gfclk_mux@1940 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1940>; - }; }; + &cm_core_clocks { dpll_per_byp_mux: dpll_per_byp_mux@14c { @@ -825,95 +714,6 @@ ti,dividers = <1>, <8>; }; - dss_32khz_clk: dss_32khz_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <11>; - reg = <0x1420>; - }; - - dss_48mhz_clk: dss_48mhz_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48m_fclk>; - ti,bit-shift = <9>; - reg = <0x1420>; - }; - - dss_dss_clk: dss_dss_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_h12x2_ck>; - ti,bit-shift = <8>; - reg = <0x1420>; - ti,set-rate-parent; - }; - - dss_sys_clk: dss_sys_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dss_syc_gfclk_div>; - ti,bit-shift = <10>; - reg = <0x1420>; - }; - - gpio2_dbclk: gpio2_dbclk@1060 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1060>; - }; - - gpio3_dbclk: gpio3_dbclk@1068 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1068>; - }; - - gpio4_dbclk: gpio4_dbclk@1070 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1070>; - }; - - gpio5_dbclk: gpio5_dbclk@1078 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1078>; - }; - - gpio6_dbclk: gpio6_dbclk@1080 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1080>; - }; - - gpio7_dbclk: gpio7_dbclk@1110 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1110>; - }; - - gpio8_dbclk: gpio8_dbclk@1118 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1118>; - }; - iss_ctrlclk: iss_ctrlclk@1320 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -938,118 +738,6 @@ reg = <0x0f20>; }; - mmc1_32khz_clk: mmc1_32khz_clk@1628 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1628>; - }; - - sata_ref_clk: sata_ref_clk@1688 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin>; - ti,bit-shift = <8>; - reg = <0x1688>; - }; - - usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <13>; - reg = <0x1658>; - }; - - usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <14>; - reg = <0x1658>; - }; - - usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <7>; - reg = <0x1658>; - }; - - usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <11>; - reg = <0x1658>; - }; - - usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <12>; - reg = <0x1658>; - }; - - usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <6>; - reg = <0x1658>; - }; - - utmi_p1_gfclk: utmi_p1_gfclk@1658 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; - ti,bit-shift = <24>; - reg = <0x1658>; - }; - - usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p1_gfclk>; - ti,bit-shift = <8>; - reg = <0x1658>; - }; - - utmi_p2_gfclk: utmi_p2_gfclk@1658 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; - ti,bit-shift = <25>; - reg = <0x1658>; - }; - - usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p2_gfclk>; - ti,bit-shift = <9>; - reg = <0x1658>; - }; - - usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1658>; - }; - - usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x16f0>; - }; - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -1058,30 +746,6 @@ reg = <0x0640>; }; - usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <8>; - reg = <0x1668>; - }; - - usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <9>; - reg = <0x1668>; - }; - - usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1668>; - }; - fdif_fclk: fdif_fclk@1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; @@ -1115,88 +779,6 @@ ti,max-div = <2>; reg = <0x1638>; }; - - mmc1_fclk_mux: mmc1_fclk_mux@1628 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1628>; - }; - - mmc1_fclk: mmc1_fclk@1628 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc1_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <2>; - reg = <0x1628>; - }; - - mmc2_fclk_mux: mmc2_fclk_mux@1630 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1630>; - }; - - mmc2_fclk: mmc2_fclk@1630 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc2_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <2>; - reg = <0x1630>; - }; - - timer10_gfclk_mux: timer10_gfclk_mux@1028 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1028>; - }; - - timer11_gfclk_mux: timer11_gfclk_mux@1030 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1030>; - }; - - timer2_gfclk_mux: timer2_gfclk_mux@1038 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1038>; - }; - - timer3_gfclk_mux: timer3_gfclk_mux@1040 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1040>; - }; - - timer4_gfclk_mux: timer4_gfclk_mux@1048 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1048>; - }; - - timer9_gfclk_mux: timer9_gfclk_mux@1050 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1050>; - }; }; &cm_core_clockdomains { @@ -1394,3 +976,206 @@ reg = <0x021c>; }; }; + +&cm_core_aon { + mpu_cm: mpu_cm@300 { + compatible = "ti,omap4-cm"; + reg = <0x300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300 0x100>; + + mpu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + dsp_cm: dsp_cm@400 { + compatible = "ti,omap4-cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + dsp_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + abe_cm: abe_cm@500 { + compatible = "ti,omap4-cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + abe_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x64>; + #clock-cells = <2>; + }; + }; + +}; + +&cm_core { + l3main1_cm: l3main1_cm@700 { + compatible = "ti,omap4-cm"; + reg = <0x700 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x100>; + + l3main1_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3main2_cm: l3main2_cm@800 { + compatible = "ti,omap4-cm"; + reg = <0x800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x100>; + + l3main2_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + ipu_cm: ipu_cm@900 { + compatible = "ti,omap4-cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + ipu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + dma_cm: dma_cm@a00 { + compatible = "ti,omap4-cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + dma_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + emif_cm: emif_cm@b00 { + compatible = "ti,omap4-cm"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb00 0x100>; + + emif_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + l4cfg_cm: l4cfg_cm@d00 { + compatible = "ti,omap4-cm"; + reg = <0xd00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd00 0x100>; + + l4cfg_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + l3instr_cm: l3instr_cm@e00 { + compatible = "ti,omap4-cm"; + reg = <0xe00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe00 0x100>; + + l3instr_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + l4per_cm: l4per_cm@1000 { + compatible = "ti,omap4-cm"; + reg = <0x1000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x200>; + + l4per_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x15c>; + #clock-cells = <2>; + }; + }; + + dss_cm: dss_cm@1400 { + compatible = "ti,omap4-cm"; + reg = <0x1400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x100>; + + dss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3init_cm: l3init_cm@1600 { + compatible = "ti,omap4-cm"; + reg = <0x1600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1600 0x100>; + + l3init_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xd4>; + #clock-cells = <2>; + }; + }; +}; + +&prm { + wkupaon_cm: wkupaon_cm@1900 { + compatible = "ti,omap4-cm"; + reg = <0x1900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1900 0x100>; + + wkupaon_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x5c>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi new file mode 100644 index 000000000000..6c26524e93e1 --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; + }; + + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "u-boot-env"; + }; + + kernel@80000 { + reg = <0x80000 0x440000>; + label = "kernel"; + }; + + rofs@c0000 { + reg = <0x4c0000 0x1740000>; + label = "rofs"; + }; + + rwfs@1c00000 { + reg = <0x1c00000 0x400000>; + label = "rwfs"; + }; +}; diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts new file mode 100644 index 000000000000..ea4e01bce8d1 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts @@ -0,0 +1,44 @@ +/* + * Cubietech CubieBoard6 + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "cubietech,cubieboard6", "actions,s500"; + model = "CubieBoard6"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + uart3_clk: uart3-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart3_clk>; +}; diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts index 521463d4cac6..7be1d2eaf3f0 100644 --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts @@ -19,8 +19,15 @@ chosen { stdout-path = "serial3:115200n8"; }; + + uart3_clk: uart3-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; }; &uart3 { status = "okay"; + clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts new file mode 100644 index 000000000000..c665ce8b88b4 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-sparky.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Allo.com Sparky + * + * Copyright (c) 2017 Andreas Färber + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "allo,sparky", "actions,s500"; + model = "Allo.com Sparky"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 or 2 GiB */ + }; + + uart3_clk: uart3-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart3_clk>; +}; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 51a48741d4c0..43c9980a4260 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -7,6 +7,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/owl-s500-powergate.h> / { compatible = "actions,s500"; @@ -43,6 +44,7 @@ compatible = "arm,cortex-a9"; reg = <0x2>; enable-method = "actions,s500-smp"; + power-domains = <&sps S500_PD_CPU2>; }; cpu3: cpu@3 { @@ -50,6 +52,7 @@ compatible = "arm,cortex-a9"; reg = <0x3>; enable-method = "actions,s500-smp"; + power-domains = <&sps S500_PD_CPU3>; }; }; diff --git a/arch/arm/boot/dts/wd-mbwe.dts b/arch/arm/boot/dts/ox810se-wd-mbwe.dts index ac3250ae8fc4..ac3250ae8fc4 100644 --- a/arch/arm/boot/dts/wd-mbwe.dts +++ b/arch/arm/boot/dts/ox810se-wd-mbwe.dts diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi index 46aa6db8353a..c2b48a1838eb 100644 --- a/arch/arm/boot/dts/ox810se.dtsi +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -207,7 +207,7 @@ }; }; - gpio0: gpio@000000 { + gpio0: gpio@0 { compatible = "oxsemi,ox810se-gpio"; reg = <0x000000 0x100000>; interrupts = <21>; @@ -296,7 +296,7 @@ compatible = "simple-bus"; ranges = <0 0x45000000 0x1000000>; - sys: sys-ctrl@000000 { + sys: sys-ctrl@0 { compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; reg = <0x000000 0x100000>; diff --git a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts index bfde32e37123..bfde32e37123 100644 --- a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts +++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi index 459207536a46..085bbd33eadc 100644 --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -173,7 +173,7 @@ }; }; - gpio0: gpio@000000 { + gpio0: gpio@0 { compatible = "oxsemi,ox820-gpio"; reg = <0x000000 0x100000>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index 533919e96eae..a1266cf8776c 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi @@ -124,7 +124,7 @@ #size-cells = <1>; ranges = <0 0x200000 0x80000>; - rtc0: rtc@00000 { + rtc0: rtc@0 { compatible = "picochip,pc3x2-rtc"; clock-freq = <200000000>; reg = <0x00000 0xf>; diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index ab3e80085511..d78cd207eca1 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi @@ -223,7 +223,7 @@ #size-cells = <1>; ranges = <0 0x200000 0x80000>; - rtc0: rtc@00000 { + rtc0: rtc@0 { compatible = "picochip,pc3x2-rtc"; clock-freq = <200000000>; reg = <0x00000 0xf>; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 3139221737ee..927d00cab014 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -52,6 +52,18 @@ }; }; + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + mmc0: mmc@fff80000 { pinctrl-0 = < &pinctrl_board_mmc @@ -127,12 +139,12 @@ }; }; - usb0: ohci@00700000 { + usb0: ohci@700000 { status = "okay"; num-ports = <2>; }; - usb1: ehci@00800000 { + usb1: ehci@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 9d725f983282..497bb065eb9d 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -397,23 +397,23 @@ xoadc-ref-supply = <&pm8058_l18>; /* Board-specific channels */ - mpp5@05 { + mpp5@5 { /* Connected to AOUT of ALS sensor */ reg = <0x00 0x05>; }; - mpp6@06 { + mpp6@6 { /* Connected to test point TP43 */ reg = <0x00 0x06>; }; - mpp7@07 { + mpp7@7 { /* Connected to battery thermistor */ reg = <0x00 0x07>; }; - mpp8@08 { + mpp8@8 { /* Connected to battery ID detector */ reg = <0x00 0x08>; }; - mpp9@09 { + mpp9@9 { /* Connected to XO thermistor */ reg = <0x00 0x09>; }; @@ -512,7 +512,7 @@ pinctrl-names = "default"; pinctrl-0 = <&dragon_gsbi12_i2c_pins>; - ak8975@0c { + ak8975@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; /* FIXME: GPIO33 has interrupt 224 on the PM8058 */ diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 6089c8d56cd5..3ca96e361878 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -591,6 +591,7 @@ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; + status = "disabled"; }; }; @@ -907,11 +908,11 @@ usb_hs1_phy: phy { compatible = "qcom,usb-hs-phy-apq8064", "qcom,usb-hs-phy"; - #phy-cells = <0>; clocks = <&sleep_clk>, <&cxo_board>; clock-names = "sleep", "ref"; resets = <&usb1 0>; reset-names = "por"; + #phy-cells = <0>; }; }; }; @@ -1264,6 +1265,7 @@ dsi0_phy: dsi-phy@4700200 { compatible = "qcom,dsi-phy-28nm-8960"; #clock-cells = <1>; + #phy-cells = <0>; reg = <0x04700200 0x100>, <0x04700300 0x200>, @@ -1418,6 +1420,7 @@ clocks = <&mmcc HDMI_S_AHB_CLK>; clock-names = "slave_iface_clk"; + #phy-cells = <0>; }; mdp: mdp@5100000 { diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 221c4584552f..33030f9419fe 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -124,6 +124,73 @@ reg = <0x900000 0x4000>; }; + gsbi6: gsbi@16500000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16500000 0x100>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi6_serial: serial@16540000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16540000 0x1000>, + <0x16500000 0x1000>; + interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi7: gsbi@16600000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; gsbi8: gsbi@19800000 { compatible = "qcom,gsbi-v1.0.0"; @@ -317,37 +384,37 @@ #size-cells = <0>; #io-channel-cells = <2>; - vcoin: adc-channel@00 { + vcoin: adc-channel@0 { reg = <0x00 0x00>; }; - vbat: adc-channel@01 { + vbat: adc-channel@1 { reg = <0x00 0x01>; }; - dcin: adc-channel@02 { + dcin: adc-channel@2 { reg = <0x00 0x02>; }; - ichg: adc-channel@03 { + ichg: adc-channel@3 { reg = <0x00 0x03>; }; - vph_pwr: adc-channel@04 { + vph_pwr: adc-channel@4 { reg = <0x00 0x04>; }; - usb_vbus: adc-channel@0a { + usb_vbus: adc-channel@a { reg = <0x00 0x0a>; }; - die_temp: adc-channel@0b { + die_temp: adc-channel@b { reg = <0x00 0x0b>; }; - ref_625mv: adc-channel@0c { + ref_625mv: adc-channel@c { reg = <0x00 0x0c>; }; - ref_1250mv: adc-channel@0d { + ref_1250mv: adc-channel@d { reg = <0x00 0x0d>; }; - ref_325mv: adc-channel@0e { + ref_325mv: adc-channel@e { reg = <0x00 0x0e>; }; - ref_muxoff: adc-channel@0f { + ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts new file mode 100644 index 000000000000..643c57f84818 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -0,0 +1,355 @@ +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + + +/ { + model = "Fairphone 2"; + compatible = "fairphone,fp2", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA>; + wakeup-source; + debounce-interval = <15>; + }; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + wakeup-source; + debounce-interval = <15>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + debounce-interval = <15>; + }; + }; + + smd { + rpm { + rpm_requests { + pm8841-regulators { + s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + + regulator-always-on; + regulator-boot-on; + }; + + s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + + regulator-boot-on; + }; + + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + }; + }; + }; + }; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; + + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_cd_pin_a: sdhc2-cd-pin-active { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + + sdhci@f98a4900 { + status = "ok"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + bus-width = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; + }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; +}; + +&spmi_bus { + pm8941@0 { + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio1", "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts new file mode 100644 index 000000000000..e87f2c99060d --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts @@ -0,0 +1,641 @@ +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "Sony Xperia Z2 Tablet"; + compatible = "sony,xperia-castor", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA>; + }; + + camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA_FOCUS>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + smd { + rpm { + rpm_requests { + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-system-load = <154000>; + }; + + s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <500000>; + }; + + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + }; + }; + }; + }; + + vreg_bl_vddio: lcd-backlight-vddio { + compatible = "regulator-fixed"; + regulator-name = "vreg_bl_vddio"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + gpio = <&msmgpio 69 0>; + enable-active-high; + + vin-supply = <&pm8941_s3>; + startup-delay-us = <70000>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_backlight_en_pin_a>; + }; + + vreg_vsp: lcd-dcdc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_vsp"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + + gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_dcdc_en_pin_a>; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_pin>; + }; +}; + +&soc { + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + + sdhci@f9864900 { + status = "ok"; + + max-frequency = <100000000>; + non-removable; + vmmc-supply = <&vreg_wlan>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_pin_a>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; + }; + + sdhci@f98a4900 { + status = "ok"; + + bus-width = <4>; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; + }; + + serial@f991e000 { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_pin_a>; + }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; + + pinctrl@fd510000 { + blsp1_uart2_pin_a: blsp1-uart2-pin-active { + rx { + pins = "gpio5"; + function = "blsp_uart2"; + + drive-strength = <2>; + bias-pull-up; + }; + + tx { + pins = "gpio4"; + function = "blsp_uart2"; + + drive-strength = <4>; + bias-disable; + }; + }; + + i2c8_pins: i2c8 { + mux { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + + drive-strength = <2>; + bias-disable; + }; + }; + + lcd_backlight_en_pin_a: lcd-backlight-vddio { + pins = "gpio69"; + drive-strength = <10>; + output-low; + bias-disable; + }; + + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_cd_pin_a: sdhc2-cd-pin-active { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + sdhc3_pin_a: sdhc3-pin-active { + clk { + pins = "gpio40"; + function = "sdc3"; + + drive-strength = <10>; + bias-disable; + }; + + cmd { + pins = "gpio39"; + function = "sdc3"; + + drive-strength = <10>; + bias-pull-up; + }; + + data { + pins = "gpio35", "gpio36", "gpio37", "gpio38"; + function = "sdc3"; + + drive-strength = <10>; + bias-pull-up; + }; + }; + + ts_int_pin: synaptics { + pin { + pins = "gpio86"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + }; + + i2c@f9964000 { + status = "ok"; + + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_pins>; + + synaptics@2c { + compatible = "syna,rmi-i2c"; + reg = <0x2c>; + + interrupt-parent = <&msmgpio>; + interrupts = <86 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + rmi-f01@1 { + reg = <0x1>; + syna,nosleep = <1>; + }; + + rmi-f11@11 { + reg = <0x11>; + syna,f11-flip-x = <1>; + syna,sensor-type = <1>; + }; + }; + }; + + i2c@f9967000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c11_pins>; + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + lp8566_wled: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + power-supply = <&vreg_bl_vddio>; + + bl-name = "backlight"; + dev-ctrl = /bits/ 8 <0x05>; + init-brt = /bits/ 8 <0x3f>; + rom_a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; + }; + rom_a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; + }; + rom_a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + rom_a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + rom_a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x02>; + }; + rom_a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x04>; + }; + rom_a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + rom_a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf7>; + }; + rom_a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0x80>; + }; + rom_aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x0f>; + }; + rom_aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; + }; +}; + +&spmi_bus { + pm8941@0 { + charger@1000 { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; + }; + + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; + + wlan_sleep_clk_pin: wl-sleep-clk { + pins = "gpio17"; + function = "func2"; + + output-high; + power-source = <PM8941_GPIO_S3>; + }; + + wlan_regulator_pin: wl-reg-active { + pins = "gpio18"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + }; + + lcd_dcdc_en_pin_a: lcd-dcdc-en-active { + pins = "gpio20"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + input-disable; + output-low; + }; + + }; + + coincell@2800 { + status = "ok"; + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 33002fed8cc3..d9019a49b292 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -18,27 +18,27 @@ #size-cells = <1>; ranges; - mpss@08000000 { + mpss@8000000 { reg = <0x08000000 0x5100000>; no-map; }; - mba@00d100000 { + mba@d100000 { reg = <0x0d100000 0x100000>; no-map; }; - reserved@0d200000 { + reserved@d200000 { reg = <0x0d200000 0xa00000>; no-map; }; - adsp_region: adsp@0dc00000 { + adsp_region: adsp@dc00000 { reg = <0x0dc00000 0x1900000>; no-map; }; - venus@0f500000 { + venus@f500000 { reg = <0x0f500000 0x500000>; no-map; }; @@ -48,17 +48,17 @@ no-map; }; - tz@0fc00000 { + tz@fc00000 { reg = <0x0fc00000 0x160000>; no-map; }; - rfsa@0fd60000 { + rfsa@fd60000 { reg = <0x0fd60000 0x20000>; no-map; }; - rmtfs@0fd80000 { + rmtfs@fd80000 { reg = <0x0fd80000 0x180000>; no-map; }; @@ -614,6 +614,20 @@ status = "disabled"; }; + sdhci@f9864900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>, + <GIC_SPI 224 IRQ_TYPE_NONE>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC3_APPS_CLK>, + <&gcc GCC_SDCC3_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + status = "disabled"; + }; + sdhci@f98a4900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi new file mode 100644 index 000000000000..6740a4cb7da8 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -0,0 +1,18 @@ +#include "qcom-msm8974.dtsi" + +/ { + soc { + sdhci@f9824900 { + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, + <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; + clock-names = "core", "iface", "xo", "cal", "sleep"; + }; + + clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974pro"; + }; + }; +}; diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index cd4d5ff7749e..5af2a0116ff2 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -123,7 +123,7 @@ pinctrl-0 = <&i2c2_pins>; eeprom@50 { - compatible = "renesas,24c128", "atmel,24c128"; + compatible = "renesas,r1ex24128", "atmel,24c128"; reg = <0x50>; pagesize = <64>; }; diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index a1b2aef984f6..779f724b4531 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -11,6 +11,8 @@ /dts-v1/; #include "r7s72100.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> / { model = "GR-Peach"; @@ -28,7 +30,6 @@ memory@20000000 { device_type = "memory"; reg = <0x20000000 0x00a00000>; - }; lbsc { @@ -51,6 +52,44 @@ reg = <0x00600000 0x00200000>; }; }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led1 { + gpios = <&port6 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + scif2_pins: serial2 { + /* P6_2 as RxD2; P6_3 as TxD2 */ + pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>; + }; + + ether_pins: ether { + /* Ethernet on Ports 1,3,5,10 */ + pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */ + <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */ + <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */ + <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */ + <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */ + <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */ + <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */ + <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */ + <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */ + <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */ + <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */ + <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */ + <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */ + <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */ + <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */ + <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */ + <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */ + <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */ + }; }; &extal_clk { @@ -61,6 +100,38 @@ clock-frequency = <48000000>; }; +&mtu2 { + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + &scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + + status = "okay"; +}; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + status = "okay"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + + phy0: ethernet-phy@0 { + reg = <0>; + + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <5>; + }; }; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 4ed12a4d9d51..ab9645a42eca 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -203,6 +203,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; next-level-cache = <&L2>; }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 310222634570..8e48090e4fdc 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -27,6 +27,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; next-level-cache = <&L2_CA15>; @@ -131,15 +132,12 @@ }; cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; + compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; clock-names = "fck"; power-domains = <&pd_c5>; - - renesas,channels-mask = <0xff>; - status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 1788e186a512..03b00d87b39b 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -131,9 +131,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; - gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */ - &pfc 91 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index d37d22682a63..afd3bc5e6cf2 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -74,9 +74,6 @@ clocks = <&mstp3_clks R8A7740_CLK_CMT1>; clock-names = "fck"; power-domains = <&pd_c5>; - - renesas,channels-mask = <0x3f>; - status = "disabled"; }; @@ -320,7 +317,7 @@ tpu: pwm@e6600000 { compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x100>; + reg = <0xe6600000 0x148>; clocks = <&mstp3_clks R8A7740_CLK_TPU0>; power-domains = <&pd_a3sp>; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..d90eb8464222 --- /dev/null +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts @@ -0,0 +1,19 @@ +/* + * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" +#include "iwg20d-q7-dbcm-ca.dtsi" + +/ { + model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; +}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 081af0192851..6aa6b7467704 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for the iWave-RZG1M Qseven carrier board + * Device Tree Source for the iWave-RZ/G1M Qseven board * * Copyright (C) 2017 Renesas Electronics Corp. * @@ -10,47 +10,9 @@ /dts-v1/; #include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" / { model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; - - aliases { - serial0 = &scif0; - ethernet0 = &avb; - }; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - reg = <3>; - micrel,led-mode = <1>; - }; }; diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index ff7993818637..75a8ca571846 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -9,6 +9,7 @@ */ #include "r8a7743.dtsi" +#include <dt-bindings/gpio/gpio.h> / { compatible = "iwave,g20m", "renesas,r8a7743"; @@ -42,6 +43,17 @@ groups = "mmc_data8_b", "mmc_ctrl"; function = "mmc"; }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; }; &mmcif0 { @@ -53,3 +65,34 @@ non-removable; status = "okay"; }; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 14222c72f0e0..0b74c6c7d21d 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -25,6 +25,47 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + i2c6 = &iic0; + i2c7 = &iic1; + i2c8 = &iic3; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; cpus { @@ -56,6 +97,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; power-domains = <&sysc R8A7743_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -68,6 +110,29 @@ }; }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -101,7 +166,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -116,7 +181,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -131,7 +196,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -146,7 +211,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -161,7 +226,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -176,7 +241,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -191,7 +256,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -206,7 +271,7 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -239,16 +304,48 @@ resets = <&cpg 407>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7743", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7743-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7743-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; }; cpg: clock-controller@e6150000 { @@ -348,6 +445,96 @@ dma-channels = <15>; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + /* The memory map in the User's Manual maps the cores to bus * numbers */ @@ -436,6 +623,58 @@ status = "disabled"; }; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7743", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -739,7 +978,8 @@ }; ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7743"; + compatible = "renesas,ether-r8a7743", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 813>; @@ -779,14 +1019,656 @@ max-frequency = <97500000>; status = "disabled"; }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7743", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + /* + * pci1 and xhci share the same phy, therefore only one of them + * can be active at any one time. If both of them are enabled, + * a race condition will determine who'll control the phy. + * A firmware file is needed by the xhci driver in order for + * USB 3.0 to work properly. + */ + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7743", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7743", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7743", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7743", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7743", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7743", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7743", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7743"; + reg = <0 0xfeb00000 0 0x40000>, + <0 0xfeb90000 0 0x1c>; + reg-names = "du", "lvds.0"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; + clock-names = "du.0", "du.1", "lvds.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7743", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7743_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7743", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7743_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7743", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7743", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7743_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */ @@ -795,12 +1677,4 @@ #clock-cells = <0>; clock-frequency = <48000000>; }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; }; diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts new file mode 100644 index 000000000000..d34de8266ccd --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts @@ -0,0 +1,158 @@ +/* + * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter + * board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7745-iwg22d-sodimm.dts" + +/ { + model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on"; + compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; + + aliases { + serial0 = &scif1; + serial4 = &scif5; + serial6 = &hscif2; + }; + + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&hscif2 { + pinctrl-0 = <&hscif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&pfc { + can1_pins: can1 { + groups = "can1_data_b"; + function = "can1"; + }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + + hscif2_pins: hscif2 { + groups = "hscif2_data"; + function = "hscif2"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1_d"; + function = "i2c1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data"; + function = "scif1"; + }; + + scif5_pins: scif5 { + groups = "scif5_data_d"; + function = "scif5"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif5 { + pinctrl-0 = <&scif5_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts new file mode 100644 index 000000000000..a4058f4cfbcd --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -0,0 +1,238 @@ +/* + * Device Tree Source for the iWave-RZG1E SODIMM carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/* + * SSI-SGTL5000 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7745-iwg22m.dtsi" + +/ { + model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; + compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; + + aliases { + ethernet0 = &avb; + serial3 = &scif4; + serial5 = &hscif1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial3:115200n8"; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + /* + * On some older versions of the platform (before R4.0) the phy address + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. + */ + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&i2c5 { + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + can0_pins: can0 { + groups = "can0_data"; + function = "can0"; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; + + i2c5_pins: i2c5 { + groups = "i2c5_b"; + function = "i2c5"; + }; + + scif4_pins: scif4 { + groups = "scif4_data_b"; + function = "scif4"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sound_pins: sound { + groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; + function = "ssi"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi3 &src3 &dvc0>; + capture = <&ssi4 &src4 &dvc1>; + }; + }; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ssi4 { + shared-pin; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi new file mode 100644 index 000000000000..ed9a8cf3fe36 --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -0,0 +1,111 @@ +/* + * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7745.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "iwave,g22m", "renesas,r8a7745"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + i2c3_pins: i2c3 { + groups = "i2c3_b"; + function = "i2c3"; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index aff90dfb8b32..ae918e9cce21 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -18,9 +18,56 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &iic0; + i2c7 = &iic1; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + vin0 = &vin0; + vin1 = &vin1; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -32,6 +79,16 @@ next-level-cache = <&L2_CA7>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; + power-domains = <&sysc R8A7745_PD_CA7_CPU1>; + next-level-cache = <&L2_CA7>; + }; + L2_CA7: cache-controller-0 { compatible = "cache"; cache-unified; @@ -40,6 +97,22 @@ }; }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -48,6 +121,12 @@ #size-cells = <2>; ranges; + apmu@e6151000 { + compatible = "renesas,r8a7745-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -65,6 +144,111 @@ resets = <&cpg 408>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + irqc: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7745", "renesas,irqc"; #interrupt-cells = <2>; @@ -85,16 +269,36 @@ resets = <&cpg 407>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7745-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7745-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; }; cpg: clock-controller@e6150000 { @@ -194,6 +398,65 @@ dma-channels = <15>; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7745-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7745-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7745", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -497,7 +760,8 @@ }; ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7745"; + compatible = "renesas,ether-r8a7745", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 813>; @@ -508,14 +772,716 @@ #size-cells = <0>; status = "disabled"; }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7745", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7745", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7745", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7745", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7745", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7745", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7745", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7745"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7745", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7745", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7745", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7745", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&cpg CPG_CORE R8A7745_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", + "src.2", "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, + <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, + <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src-0 { + status = "disabled"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */ @@ -524,12 +1490,4 @@ #clock-cells = <0>; clock-frequency = <48000000>; }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 8f3156c0e575..3b49f9ed2e2b 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -33,6 +33,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <800000000>; + clocks = <&z_clk>; }; }; @@ -50,7 +51,8 @@ }; ether: ethernet@fde00000 { - compatible = "renesas,ether-r8a7778"; + compatible = "renesas,ether-r8a7778", + "renesas,rcar-gen1-ether"; reg = <0xfde00000 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7778_CLK_ETHER>; @@ -88,7 +90,7 @@ }; gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc40000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -99,7 +101,7 @@ }; gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc41000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -110,7 +112,7 @@ }; gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc42000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -121,7 +123,7 @@ }; gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc43000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -132,7 +134,7 @@ }; gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc44000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -378,7 +380,8 @@ }; sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7778"; + compatible = "renesas,sdhi-r8a7778", + "renesas,rcar-gen1-sdhi"; reg = <0xffe4c000 0x100>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; @@ -387,7 +390,8 @@ }; sdhi1: sd@ffe4d000 { - compatible = "renesas,sdhi-r8a7778"; + compatible = "renesas,sdhi-r8a7778", + "renesas,rcar-gen1-sdhi"; reg = <0xffe4d000 0x100>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; @@ -396,7 +400,8 @@ }; sdhi2: sd@ffe4f000 { - compatible = "renesas,sdhi-r8a7778"; + compatible = "renesas,sdhi-r8a7778", + "renesas,rcar-gen1-sdhi"; reg = <0xffe4f000 0x100>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8ee0b2ca5d39..e79ae306eedd 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -29,12 +29,14 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM1>; }; cpu@2 { @@ -42,6 +44,7 @@ compatible = "arm,cortex-a9"; reg = <2>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM2>; }; cpu@3 { @@ -49,6 +52,7 @@ compatible = "arm,cortex-a9"; reg = <3>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM3>; }; }; @@ -76,7 +80,7 @@ }; gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc40000 0x2c>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -87,7 +91,7 @@ }; gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc41000 0x2c>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -98,7 +102,7 @@ }; gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc42000 0x2c>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -109,7 +113,7 @@ }; gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc43000 0x2c>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -120,7 +124,7 @@ }; gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc44000 0x2c>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -131,7 +135,7 @@ }; gpio5: gpio@ffc45000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc45000 0x2c>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -142,7 +146,7 @@ }; gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc46000 0x2c>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -351,7 +355,8 @@ }; sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7779"; + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; reg = <0xffe4c000 0x100>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; @@ -360,7 +365,8 @@ }; sdhi1: sd@ffe4d000 { - compatible = "renesas,sdhi-r8a7779"; + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; reg = <0xffe4d000 0x100>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; @@ -369,7 +375,8 @@ }; sdhi2: sd@ffe4e000 { - compatible = "renesas,sdhi-r8a7779"; + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; reg = <0xffe4e000 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; @@ -378,7 +385,8 @@ }; sdhi3: sd@ffe4f000 { - compatible = "renesas,sdhi-r8a7779"; + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; reg = <0xffe4f000 0x100>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index ba100a6f67ca..f2ea632381e7 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -272,9 +272,8 @@ #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */ - &gpio1 16 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; @@ -316,11 +315,8 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 16358bf8d1db..ed9a68538a55 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -10,7 +10,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7790-clock.h> +#include <dt-bindings/clock/r8a7790-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7790-sysc.h> @@ -52,10 +52,11 @@ reg = <0>; clock-frequency = <1300000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7790_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -71,8 +72,10 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -80,8 +83,10 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -89,8 +94,10 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -98,8 +105,10 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -107,8 +116,10 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -116,8 +127,10 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -125,8 +138,10 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; L2_CA15: cache-controller-0 { @@ -153,7 +168,7 @@ trips { cpu-crit { - temperature = <115000>; + temperature = <95000>; hysteresis = <0>; type = "critical"; }; @@ -185,13 +200,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -199,12 +215,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -212,12 +229,13 @@ gpio-ranges = <&pfc 0 32 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -225,12 +243,13 @@ gpio-ranges = <&pfc 0 64 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -238,12 +257,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -251,12 +271,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -264,8 +285,9 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; thermal: thermal@e61f0000 { @@ -274,8 +296,9 @@ "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -288,21 +311,20 @@ }; cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; + resets = <&cpg 124>; status = "disabled"; }; cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -312,11 +334,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; + resets = <&cpg 329>; status = "disabled"; }; @@ -330,8 +351,9 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7790_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -358,9 +380,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -389,9 +412,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -418,9 +442,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -447,9 +472,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -460,8 +486,9 @@ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; }; @@ -472,8 +499,9 @@ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; }; @@ -484,8 +512,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -496,8 +525,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -508,8 +538,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -520,8 +551,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -533,11 +565,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -548,11 +581,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -563,11 +597,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x425>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC2>; + clocks = <&cpg CPG_MOD 300>; dmas = <&dmac0 0x69>, <&dmac0 0x6a>, <&dmac1 0x69>, <&dmac1 0x6a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 300>; status = "disabled"; }; @@ -578,11 +613,12 @@ "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -590,11 +626,12 @@ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -604,11 +641,12 @@ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; + clocks = <&cpg CPG_MOD 305>; dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, <&dmac1 0xe1>, <&dmac1 0xe2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 305>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -620,54 +658,62 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee120000 0 0x328>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 313>; dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; status = "disabled"; }; sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -676,12 +722,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -690,12 +737,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -704,12 +752,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -718,12 +767,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -732,12 +782,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -746,12 +797,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -760,13 +812,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -775,13 +828,14 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -790,13 +844,14 @@ "renesas,scif"; reg = <0 0xe6e56000 0 64>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 310>; status = "disabled"; }; @@ -805,13 +860,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -820,13 +876,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -849,11 +906,13 @@ }; ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7790"; + compatible = "renesas,ether-r8a7790", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -865,8 +924,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -876,8 +936,9 @@ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_SATA0>; + clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 815>; status = "disabled"; }; @@ -885,8 +946,9 @@ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_SATA1>; + clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 814>; status = "disabled"; }; @@ -894,11 +956,12 @@ compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -911,9 +974,10 @@ reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -930,8 +994,9 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -939,8 +1004,9 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -948,8 +1014,9 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -957,41 +1024,46 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN3>; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 808>; status = "disabled"; }; - vsp1@fe920000 { + vsp@fe920000 { compatible = "renesas,vsp1"; reg = <0 0xfe920000 0 0x8000>; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; + clocks = <&cpg CPG_MOD 130>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 130>; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; du: display@feb00000 { @@ -1003,11 +1075,9 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>, + <&cpg CPG_MOD 725>; clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; status = "disabled"; @@ -1037,10 +1107,11 @@ compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -1048,10 +1119,11 @@ compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1059,443 +1131,78 @@ compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7790-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "sd1", - "z", "rcan", "adsp"; - #power-domain-cells = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc1_clk: mmc1@e6150244 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150244 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z2_clk: z2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - imp_clk: imp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7790_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, - <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 - R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 - R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC - R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 - R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 - R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 - R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S - >; - clock-output-names = - "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", - "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", - "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", - "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 - R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 - R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 - R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "msiof3", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>, - <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 - R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 - >; - clock-output-names = - "iic2", "tpu0", "mmcif1", "scif2", "sdhi3", - "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "pciec", "iic1", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 - R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL - R8A7790_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, - <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 - R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 - R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 - R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif1", "hscif0", "scif1", - "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 - R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 - R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER - R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 - >; - clock-output-names = - "mlb", "vin3", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 - R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS - R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 - >; - clock-output-names = - "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "iic3", - "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SSI_ALL - R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 - R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 - R8A7790_CLK_SCU_ALL - R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 - R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 - R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 - R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7790-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; }; prr: chipid@ff000044 { @@ -1518,11 +1225,12 @@ compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1534,11 +1242,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1549,11 +1258,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1564,11 +1274,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e00000 0 0x0064>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + clocks = <&cpg CPG_MOD 205>; dmas = <&dmac0 0x41>, <&dmac0 0x42>, <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1579,11 +1290,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6c90000 0 0x0064>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + clocks = <&cpg CPG_MOD 215>; dmas = <&dmac0 0x45>, <&dmac0 0x46>, <&dmac1 0x45>, <&dmac1 0x46>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 215>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1593,8 +1305,9 @@ compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 328>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1606,8 +1319,9 @@ reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -1639,8 +1353,9 @@ reg = <0 0xee0b0000 0 0xc00>, <0 0xee0a0000 0 0x1100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -1657,8 +1372,9 @@ pci2: pci@ee0d0000 { compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; device_type = "pci"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; @@ -1707,9 +1423,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; }; @@ -1728,21 +1445,22 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, - <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, - <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, - <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, - <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, - <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, - <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, - <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, - <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, - <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7790_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1753,6 +1471,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 0ce0b278e1cb..a50924d12b6f 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -278,6 +278,12 @@ }; }; + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -306,9 +312,8 @@ #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */ - &gpio7 15 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; @@ -330,9 +335,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; @@ -642,12 +645,6 @@ }; }; - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - hdmi@39 { compatible = "adi,adv7511w"; reg = <0x39>; @@ -710,7 +707,7 @@ }; eeprom@50 { - compatible = "renesas,24c02", "atmel,24c02"; + compatible = "renesas,r1ex24002", "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 95da5cb9d37a..eb374956294f 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -419,9 +419,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x3_clk>, <&x16_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f1d1a9772153..008a260f86a5 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -10,7 +10,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7791-clock.h> +#include <dt-bindings/clock/r8a7791-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7791-sysc.h> @@ -51,7 +51,7 @@ reg = <0>; clock-frequency = <1500000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7791_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; @@ -70,6 +70,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -91,7 +92,7 @@ trips { cpu-crit { - temperature = <115000>; + temperature = <95000>; hysteresis = <0>; type = "critical"; }; @@ -117,13 +118,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -131,12 +133,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -144,12 +147,13 @@ gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -157,12 +161,13 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -170,12 +175,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -183,12 +189,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -196,12 +203,13 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -209,12 +217,13 @@ gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -222,8 +231,9 @@ gpio-ranges = <&pfc 0 224 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; thermal: thermal@e61f0000 { @@ -232,8 +242,9 @@ "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -246,21 +257,20 @@ }; cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; + resets = <&cpg 124>; status = "disabled"; }; cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -270,11 +280,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; + resets = <&cpg 329>; status = "disabled"; }; @@ -294,8 +303,9 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7791_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -322,9 +332,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -353,9 +364,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -382,9 +394,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -411,9 +424,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -424,8 +438,9 @@ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; }; @@ -436,8 +451,9 @@ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; }; @@ -449,8 +465,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -461,8 +478,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -473,8 +491,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -485,8 +504,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -497,8 +517,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -510,8 +531,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -524,11 +546,12 @@ "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -539,11 +562,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -554,11 +578,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -571,52 +596,59 @@ compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7791"; + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7791"; + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7791"; + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -625,12 +657,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -639,12 +672,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -653,12 +687,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -667,12 +702,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -681,12 +717,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -695,12 +732,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -709,12 +747,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -723,12 +762,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -737,12 +777,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -751,13 +792,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -766,22 +808,24 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; adc: adc@e6e54000 { compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; reg = <0 0xe6e54000 0 64>; - clocks = <&mstp9_clks R8A7791_CLK_GYROADC>; + clocks = <&cpg CPG_MOD 901>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 901>; status = "disabled"; }; @@ -790,13 +834,14 @@ "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -805,13 +850,14 @@ "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -820,13 +866,14 @@ "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -835,13 +882,14 @@ "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -850,13 +898,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -865,13 +914,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -880,13 +930,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -909,11 +960,13 @@ }; ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7791"; + compatible = "renesas,ether-r8a7791", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -925,8 +978,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -936,8 +990,9 @@ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_SATA0>; + clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; status = "disabled"; }; @@ -945,8 +1000,9 @@ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_SATA1>; + clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 814>; status = "disabled"; }; @@ -954,11 +1010,12 @@ compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -971,9 +1028,10 @@ reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -990,8 +1048,9 @@ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -999,8 +1058,9 @@ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -1008,33 +1068,37 @@ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; du: display@feb00000 { @@ -1044,9 +1108,9 @@ reg-names = "du", "lvds.0"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; clock-names = "du.0", "du.1", "lvds.0"; status = "disabled"; @@ -1071,10 +1135,11 @@ compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -1082,10 +1147,11 @@ compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1093,435 +1159,78 @@ compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7791-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7791_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU - R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG - R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 - R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 - R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 - R8A7791_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", - "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", - "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 - R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 - R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 - R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 - R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 - R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 - R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL - R8A7791_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 - R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 - R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 - R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 - R8A7791_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB - R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 - R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER - R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_GYROADC - R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 - R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 - R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 - R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 - R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 - >; - clock-output-names = - "gyroadc", - "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SSI_ALL - R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 - R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 - R8A7791_CLK_SCU_ALL - R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 - R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 - R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 - R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7791-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; }; rst: reset-controller@e6160000 { @@ -1544,11 +1253,12 @@ compatible = "renesas,qspi-r8a7791", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1560,11 +1270,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 000>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1575,11 +1286,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1590,11 +1302,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e00000 0 0x0064>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + clocks = <&cpg CPG_MOD 205>; dmas = <&dmac0 0x41>, <&dmac0 0x42>, <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1604,8 +1317,9 @@ compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 328>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1617,8 +1331,9 @@ reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -1650,8 +1365,9 @@ reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -1697,9 +1413,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; }; @@ -1778,21 +1495,22 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, - <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, - <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, - <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, - <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, - <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, - <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, - <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, - <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, - <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7791_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1803,6 +1521,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index f3ea43b7b724..9b67dca6c9ef 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -310,8 +310,7 @@ pinctrl-0 = <&du0_pins &du1_pins>; pinctrl-names = "default"; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, - <&x1_clk>, <&x2_clk>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; status = "okay"; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index c24f26fdab1f..b9471b67b728 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -305,8 +305,7 @@ pinctrl-0 = <&du0_pins &du1_pins>; pinctrl-names = "default"; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, - <&osc2_clk>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>; clock-names = "du.0", "du.1", "dclkin.0"; status = "okay"; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 2623f39bed2b..3be15a158bad 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7792-clock.h> +#include <dt-bindings/clock/r8a7792-cpg-mssr.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7792-sysc.h> @@ -36,6 +36,14 @@ vin5 = &vin5; }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -46,7 +54,7 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&z_clk>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; }; @@ -56,6 +64,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -68,6 +77,22 @@ }; }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -92,9 +117,10 @@ <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; irqc: interrupt-controller@e61c0000 { @@ -106,20 +132,9 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7792_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>; + resets = <&cpg 407>; }; rst: reset-controller@e6160000 { @@ -145,7 +160,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -153,13 +168,14 @@ gpio-ranges = <&pfc 0 0 29>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -167,13 +183,14 @@ gpio-ranges = <&pfc 0 32 23>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -181,13 +198,14 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -195,13 +213,14 @@ gpio-ranges = <&pfc 0 96 28>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -209,13 +228,14 @@ gpio-ranges = <&pfc 0 128 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -223,13 +243,14 @@ gpio-ranges = <&pfc 0 160 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055100 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055100 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -237,13 +258,14 @@ gpio-ranges = <&pfc 0 192 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055200 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055200 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -251,13 +273,14 @@ gpio-ranges = <&pfc 0 224 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; gpio8: gpio@e6055300 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055300 0 0x50>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -265,13 +288,14 @@ gpio-ranges = <&pfc 0 256 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; + clocks = <&cpg CPG_MOD 921>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 921>; }; gpio9: gpio@e6055400 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -279,13 +303,14 @@ gpio-ranges = <&pfc 0 288 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; + clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 919>; }; gpio10: gpio@e6055500 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055500 0 0x50>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -293,13 +318,14 @@ gpio-ranges = <&pfc 0 320 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; + clocks = <&cpg CPG_MOD 914>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 914>; }; gpio11: gpio@e6055600 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055600 0 0x50>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -307,8 +333,9 @@ gpio-ranges = <&pfc 0 352 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; + clocks = <&cpg CPG_MOD 913>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 913>; }; dmac0: dma-controller@e6700000 { @@ -336,9 +363,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -368,9 +396,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -380,13 +409,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -395,13 +425,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -410,13 +441,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -425,13 +457,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -440,13 +473,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -455,13 +489,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -484,14 +519,16 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7792"; + compatible = "renesas,sdhi-r8a7792", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; - clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -500,8 +537,9 @@ "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; avb: ethernet@e6800000 { @@ -509,8 +547,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -522,8 +561,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -535,8 +575,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -548,8 +589,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -561,8 +603,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -574,8 +617,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -587,8 +631,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; @@ -599,11 +644,12 @@ compatible = "renesas,qspi-r8a7792", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -615,11 +661,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 000>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -630,11 +677,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -646,8 +694,8 @@ reg-names = "du"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, - <&mstp7_clks R8A7792_CLK_DU1>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; status = "disabled"; @@ -673,10 +721,11 @@ "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_CAN0>, - <&rcan_clk>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -685,10 +734,11 @@ "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_CAN1>, - <&rcan_clk>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -697,8 +747,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -707,8 +758,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -717,8 +769,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -727,8 +780,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN3>; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 808>; status = "disabled"; }; @@ -737,8 +791,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN4>; + clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 805>; status = "disabled"; }; @@ -747,277 +802,55 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN5>; + clocks = <&cpg CPG_MOD 804>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 804>; status = "disabled"; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7792-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7792-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi"; + clock-names = "extal"; + #clock-cells = <2>; #power-domain-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z_clk: z { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - sd_clk: sd { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rcan_clk: rcan { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <49>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7792_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_JPU - R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 - R8A7792_CLK_VSP1_SY - >; - clock-output-names = "jpu", "vsp1du1", "vsp1du0", - "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_MSIOF1 - R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 - >; - clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd_clk>; - #clock-cells = <1>; - renesas,clock-indices = <R8A7792_CLK_SDHI0>; - clock-output-names = "sdhi0"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS - >; - clock-output-names = "irqc", "intc-sys"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 - R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 - R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 - R8A7792_CLK_DU1 R8A7792_CLK_DU0 - >; - clock-output-names = "hscif1", "hscif0", "scif3", - "scif2", "scif1", "scif0", - "du1", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&zg_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 - R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 - R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 - R8A7792_CLK_ETHERAVB - >; - clock-output-names = "vin5", "vin4", "vin3", "vin2", - "vin1", "vin0", "etheravb"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7792_CLK_QSPI>, - <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 - R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 - R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 - R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 - R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 - R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 - R8A7792_CLK_QSPI_MOD - R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 - R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 - R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 - R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "gpio11", "gpio10", "can1", "can0", - "qspi_mod", "gpio9", "gpio8", - "i2c5", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; + #reset-cells = <1>; }; }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 76e3aca2029e..51b3ffac8efa 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -303,9 +303,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 497716b6fbe2..039b22517526 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7793-clock.h> +#include <dt-bindings/clock/r8a7793-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7793-sysc.h> @@ -43,7 +43,7 @@ reg = <0>; clock-frequency = <1500000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7793_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7793_PD_CA15_CPU0>; @@ -62,6 +62,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; }; @@ -88,7 +89,7 @@ trips { cpu-crit { - temperature = <115000>; + temperature = <95000>; hysteresis = <0>; type = "critical"; }; @@ -108,13 +109,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -122,12 +124,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -135,12 +138,13 @@ gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -148,12 +152,13 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -161,12 +166,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -174,12 +180,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -187,12 +194,13 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -200,12 +208,13 @@ gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -213,8 +222,9 @@ gpio-ranges = <&pfc 0 224 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; thermal: thermal@e61f0000 { @@ -223,8 +233,9 @@ "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -237,21 +248,20 @@ }; cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7793_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; + resets = <&cpg 124>; status = "disabled"; }; cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -261,11 +271,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; + resets = <&cpg 329>; status = "disabled"; }; @@ -285,8 +294,9 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7793_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -313,9 +323,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -344,9 +355,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -373,9 +385,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -402,9 +415,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -416,8 +430,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -428,8 +443,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -440,8 +456,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -452,8 +469,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -464,8 +482,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -477,8 +496,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -491,11 +511,12 @@ "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -506,11 +527,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -521,11 +543,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -535,41 +558,47 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7793"; + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7793"; + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7793"; + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -577,11 +606,12 @@ compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -592,12 +622,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -606,12 +637,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -620,12 +652,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -634,12 +667,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -648,12 +682,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -662,12 +697,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -676,12 +712,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -690,12 +727,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -704,12 +742,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -718,13 +757,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -733,13 +773,14 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -748,13 +789,14 @@ "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -763,13 +805,14 @@ "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -778,13 +821,14 @@ "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -793,13 +837,14 @@ "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -808,13 +853,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -823,13 +869,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -838,13 +885,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -867,11 +915,13 @@ }; ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7793"; + compatible = "renesas,ether-r8a7793", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -882,8 +932,9 @@ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -891,8 +942,9 @@ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -900,8 +952,9 @@ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -909,11 +962,12 @@ compatible = "renesas,qspi-r8a7793", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -927,9 +981,9 @@ reg-names = "du", "lvds.0"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; clock-names = "du.0", "du.1", "lvds.0"; status = "disabled"; @@ -954,10 +1008,11 @@ compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -965,376 +1020,75 @@ compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7793-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, - <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 - R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 - R8A7793_CLK_3DG R8A7793_CLK_2DDMAC - R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 - R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 - R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 - R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 - R8A7793_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "ssp_dev", "tmu1", - "pvrsrvkm", "tddmac", "fdp1", "fdp0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0 - R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2 - R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "scifb0", - "scifb1", "scifb2", "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, - <&rclk_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 - R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 - R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 - R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 - R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 - R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS - >; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>; - #clock-cells = <1>; - clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1 - R8A7793_CLK_THERMAL>; - clock-output-names = "audmac0", "audmac1", "thermal"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, - <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_EHCI R8A7793_CLK_HSUSB - R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 - R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 - R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 - R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 - R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 - R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", - "hscif1", "hscif0", "scif3", "scif2", - "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 - R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 - R8A7793_CLK_ETHER R8A7793_CLK_SATA1 - R8A7793_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", - "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6 - R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 - R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 - R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 - R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1 - R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5 - R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 - R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 - R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", - "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", - "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SSI_ALL - R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5 - R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0 - R8A7793_CLK_SCU_ALL - R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0 - R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0 - R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5 - R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; + /* Special CPG clocks */ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7793-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; }; rst: reset-controller@e6160000 { @@ -1428,19 +1182,20 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>, - <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>, - <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>, - <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>, - <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>, - <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>, - <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>, - <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>, - <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>, - <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>, - <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7793_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1449,6 +1204,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index f1eea13cdf44..60c6515c4996 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -143,9 +143,8 @@ #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */ - &gpio4 8 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; @@ -167,8 +166,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; @@ -305,7 +303,7 @@ vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; sd-uhs-sdr50; sd-uhs-sdr104; status = "okay"; @@ -319,7 +317,7 @@ vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; sd-uhs-sdr50; status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 4cb5278d104d..edfad0e5ac53 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -423,8 +423,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x2_clk>, <&x3_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 26535414203a..106b4e1649ff 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -9,7 +9,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7794-clock.h> +#include <dt-bindings/clock/r8a7794-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7794-sysc.h> @@ -37,13 +37,14 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&z2_clk>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; }; @@ -53,6 +54,7 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; @@ -65,6 +67,12 @@ }; }; + apmu@e6151000 { + compatible = "renesas,r8a7794-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -75,13 +83,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -89,12 +98,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -102,12 +112,13 @@ gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -115,12 +126,13 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -128,12 +140,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -141,12 +154,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -154,12 +168,13 @@ gpio-ranges = <&pfc 0 160 28>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -167,26 +182,26 @@ gpio-ranges = <&pfc 0 192 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7794_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; + resets = <&cpg 124>; status = "disabled"; }; cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -196,11 +211,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; + resets = <&cpg 329>; status = "disabled"; }; @@ -228,8 +242,9 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7794_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; pfc: pin-controller@e6060000 { @@ -261,9 +276,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -292,9 +308,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -320,9 +337,10 @@ "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -332,12 +350,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -346,12 +365,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -360,12 +380,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -374,12 +395,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -388,12 +410,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -402,12 +425,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -416,12 +440,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -430,12 +455,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -444,12 +470,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -458,13 +485,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -473,13 +501,14 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -488,13 +517,14 @@ "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -503,13 +533,14 @@ "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -518,13 +549,14 @@ "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -533,13 +565,14 @@ "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -548,13 +581,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -563,13 +597,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -578,13 +613,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -607,11 +643,13 @@ }; ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794"; + compatible = "renesas,ether-r8a7794", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -623,8 +661,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -635,8 +674,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 931>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -647,8 +687,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 930>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -659,8 +700,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 929>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -671,8 +713,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 928>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -683,8 +726,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 927>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -695,8 +739,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 925>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -708,11 +753,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 318>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -723,11 +769,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 323>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -737,51 +784,58 @@ compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7794"; + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7794"; + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7794"; + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -789,11 +843,12 @@ compatible = "renesas,qspi-r8a7794", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -804,8 +859,9 @@ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -813,8 +869,9 @@ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -824,8 +881,9 @@ reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -857,8 +915,9 @@ reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -888,8 +947,9 @@ compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -902,9 +962,10 @@ reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -917,20 +978,22 @@ }; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; du: display@feb00000 { @@ -939,8 +1002,7 @@ reg-names = "du"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; status = "disabled"; @@ -965,10 +1027,11 @@ compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -976,434 +1039,74 @@ compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7794-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "rcan"; - #power-domain-cells = <0>; - }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z2_clk: z2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - acp_clk: acp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 - R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 - R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 - R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 - R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 - R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 - R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 - R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 - R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 - R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 - >; - clock-output-names = - "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c6", "i2c7", - "cmt1", "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_AUDIO_DMAC0 - R8A7794_CLK_PWM>; - clock-output-names = "audmac0", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_EHCI R8A7794_CLK_HSUSB - R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 - R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 - R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 - R8A7794_CLK_SCIF0 - R8A7794_CLK_DU1 R8A7794_CLK_DU0 - >; - clock-output-names = - "ehci", "hsusb", - "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", - "du1", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 - R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER - >; - clock-output-names = - "vin1", "vin0", "etheravb", "ether"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, - <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 - R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 - R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 - R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1 - R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD - R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 - R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 - R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; - clock-output-names = - "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", - "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", - "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7794-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_SSI_ALL - R8A7794_CLK_SSI9 R8A7794_CLK_SSI8 - R8A7794_CLK_SSI7 R8A7794_CLK_SSI6 - R8A7794_CLK_SSI5 R8A7794_CLK_SSI4 - R8A7794_CLK_SSI3 R8A7794_CLK_SSI2 - R8A7794_CLK_SSI1 R8A7794_CLK_SSI0 - R8A7794_CLK_SCU_ALL - R8A7794_CLK_SCU_DVC1 - R8A7794_CLK_SCU_DVC0 - R8A7794_CLK_SCU_CTU1_MIX1 - R8A7794_CLK_SCU_CTU0_MIX0 - R8A7794_CLK_SCU_SRC6 - R8A7794_CLK_SCU_SRC5 - R8A7794_CLK_SCU_SRC4 - R8A7794_CLK_SCU_SRC3 - R8A7794_CLK_SCU_SRC2 - R8A7794_CLK_SCU_SRC1>; - clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", - "ssi6", "ssi5", "ssi4", "ssi3", - "ssi2", "ssi1", "ssi0", - "scu-all", "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src6", "scu-src5", "scu-src4", - "scu-src3", "scu-src2", "scu-src1"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7794-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; }; rst: reset-controller@e6160000 { @@ -1490,31 +1193,20 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI9>, - <&mstp10_clks R8A7794_CLK_SSI8>, - <&mstp10_clks R8A7794_CLK_SSI7>, - <&mstp10_clks R8A7794_CLK_SSI6>, - <&mstp10_clks R8A7794_CLK_SSI5>, - <&mstp10_clks R8A7794_CLK_SSI4>, - <&mstp10_clks R8A7794_CLK_SSI3>, - <&mstp10_clks R8A7794_CLK_SSI2>, - <&mstp10_clks R8A7794_CLK_SSI1>, - <&mstp10_clks R8A7794_CLK_SSI0>, - <&mstp10_clks R8A7794_CLK_SCU_SRC6>, - <&mstp10_clks R8A7794_CLK_SCU_SRC5>, - <&mstp10_clks R8A7794_CLK_SCU_SRC4>, - <&mstp10_clks R8A7794_CLK_SCU_SRC3>, - <&mstp10_clks R8A7794_CLK_SCU_SRC2>, - <&mstp10_clks R8A7794_CLK_SCU_SRC1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_DVC0>, - <&mstp10_clks R8A7794_CLK_SCU_DVC1>, + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&m2_clk>; + <&cpg CPG_CORE R8A7794_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1525,6 +1217,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index fdb1570bc7d3..e2a0f576946f 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -135,6 +135,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 4916c65e0ace..a97458112ff6 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -152,6 +152,25 @@ }; }; + gpu: gpu@10090000 { + compatible = "rockchip,rk3036-mali", "arm,mali-400"; + reg = <0x10090000 0x10000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0"; + assigned-clocks = <&cru SCLK_GPU>; + assigned-clock-rates = <100000000>; + clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; + clock-names = "core", "bus"; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + vop: vop@10118000 { compatible = "rockchip,rk3036-vop"; reg = <0x10118000 0x19c>; @@ -261,7 +280,7 @@ max-frequency = <37500000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; resets = <&cru SRST_SDIO>; @@ -279,7 +298,7 @@ max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; default-sample-phase = <158>; disable-wp; dmas = <&pdma 12>; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index c6d92c25df42..d23ee6d911ac 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -83,6 +83,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 400cbf9609e3..4d7057a10a4c 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -177,6 +177,7 @@ phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; }; }; @@ -196,7 +197,7 @@ clock-frequency = <400000>; status = "okay"; - ak8963: ak8963@0d { + ak8963: ak8963@d { compatible = "asahi-kasei,ak8975"; reg = <0x0d>; interrupt-parent = <&gpio4>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index f50481fd8e5c..06523caca27d 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -610,6 +610,30 @@ }; }; +&gpu { + compatible = "rockchip,rk3066-mali", "arm,mali-400"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 53d6fc2fdbce..00e05a6662ac 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -176,6 +176,10 @@ cpu0-supply = <&vdd_arm>; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 1399bc04ea77..aa10caae51c3 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -553,6 +553,30 @@ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; }; +&gpu { + compatible = "rockchip,rk3188-mali", "arm,mali-400"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; +}; + &i2c0 { compatible = "rockchip,rk3188-i2c"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 06814421eed2..341deaf62ff6 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -558,6 +558,27 @@ status = "disabled"; }; + gpu: gpu@20000000 { + compatible = "rockchip,rk3228-mali", "arm,mali-400"; + reg = <0x20000000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "core", "bus"; + resets = <&cru SRST_GPU_A>; + status = "disabled"; + }; + vpu_mmu: iommu@20020800 { compatible = "rockchip,iommu"; reg = <0x20020800 0x100>; @@ -600,7 +621,7 @@ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; @@ -613,7 +634,7 @@ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; @@ -628,7 +649,7 @@ max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; default-sample-phase = <158>; fifo-depth = <0x100>; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index 5f05815f47e0..5f1e336dbaac 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -184,6 +184,7 @@ regulator-name = "vdd10_lcd"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-always-on; }; vcca_18: REG7 { @@ -223,6 +224,7 @@ regulator-name = "vcc18_lcd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 7da0947ababb..eab176e3dfc3 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -226,6 +226,13 @@ }; }; +&hdmi { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; + status = "okay"; +}; + &i2c0 { hym8563: hym8563@51 { compatible = "haoyu,hym8563"; @@ -255,6 +262,10 @@ }; }; +&i2c5 { + status = "okay"; +}; + &i2s { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index 99cfae875e12..5eae4776ffde 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -110,26 +110,6 @@ }; }; -&cpu0 { - cpu0-supply = <&vdd_cpu>; - operating-points = < - /* KHz uV */ - 1800000 1400000 - 1608000 1350000 - 1512000 1300000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 312000 900000 - 216000 900000 - 126000 900000 - >; -}; - &emmc { status = "okay"; bus-width = <8>; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index f084e0c8dcb3..c06d0f4ceb81 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -384,7 +384,7 @@ status = "okay"; clock-frequency = <400000>; - ak8963: ak8963@0d { + ak8963: ak8963@d { compatible = "asahi-kasei,ak8975"; reg = <0x0d>; interrupt-parent = <&gpio8>; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts new file mode 100644 index 000000000000..9842a006e823 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -0,0 +1,498 @@ +/* + * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288.dtsi" + +/ { + model = "Amarula Vyasa-RK3288"; + compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + + dc12_vbat: dc12-vbat { + compatible = "regulator-fixed"; + regulator-name = "dc12_vbat"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vboot_3v3: vboot-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vboot_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vboot_5v: vboot-5v { + compatible = "regulator-fixed"; + regulator-name = "vboot_sv"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + v3g_3v3: v3g-3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3g_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vsus_5v: vsus-5v { + compatible = "regulator-fixed"; + regulator-name = "vsus_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vusb1_5v: vusb1-5v { + compatible = "regulator-fixed"; + regulator-name = "vusb1_5v"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsus_5v>; + }; + + vusb2_5v: vusb2-5v { + compatible = "regulator-fixed"; + regulator-name = "vusb2_5v"; + enable-active-high; + gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pwr_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsus_5v>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_tp: LDO_REG1 { + regulator-name = "vcc_tp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_codec: LDO_REG2 { + regulator-name = "vcc_codec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_gps: LDO_REG4 { + regulator-name = "vcc_gps"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc10_lcd: LDO_REG6 { + regulator-name = "vcc10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcc_18>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc_io>; + flash0-suuply = <&vcc_18>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830 = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + pinctrl-names = "default"; + pinctrl-0 = <&phy_pwr_en>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb_host { + phy_pwr_en: phy-pwr-en { + rockchip,pins = <RK_GPIO2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + usb2_pwr_en: usb2-pwr-en { + rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <RK_GPIO0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 356ed1e62452..6102e4e7f35c 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -956,7 +956,7 @@ iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; reg = <0x0 0xff900800 0x0 0x40>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "iep_mmu"; #iommu-cells = <0>; status = "disabled"; @@ -972,6 +972,17 @@ status = "disabled"; }; + rga: rga@ff920000 { + compatible = "rockchip,rk3288-rga"; + reg = <0x0 0xff920000 0x0 0x180>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; + reset-names = "core", "axi", "ahb"; + }; + vopb: vop@ff930000 { compatible = "rockchip,rk3288-vop"; reg = <0x0 0xff930000 0x0 0x19c>; @@ -1002,6 +1013,11 @@ reg = <2>; remote-endpoint = <&mipi_in_vopb>; }; + + vopb_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopb>; + }; }; }; @@ -1045,6 +1061,11 @@ reg = <2>; remote-endpoint = <&mipi_in_vopl>; }; + + vopl_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopl>; + }; }; }; @@ -1086,6 +1107,39 @@ }; }; + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + reg = <0x0 0xff96c000 0x0 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + pinctrl-names = "lcdc"; + pinctrl-0 = <&lcdc_ctl>; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + }; + }; + edp: dp@ff970000 { compatible = "rockchip,rk3288-dp"; reg = <0x0 0xff970000 0x0 0x4000>; @@ -1124,8 +1178,8 @@ reg-io-width = <4>; rockchip,grf = <&grf>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; power-domains = <&power RK3288_PD_VIO>; status = "disabled"; @@ -1427,6 +1481,14 @@ }; hdmi { + hdmi_cec_c0: hdmi-cec-c0 { + rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; + }; + + hdmi_cec_c7: hdmi-cec-c7 { + rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>; + }; + hdmi_ddc: hdmi-ddc { rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, <7 20 RK_FUNC_2 &pcfg_pull_none>; @@ -1527,6 +1589,15 @@ }; }; + lcdc { + lcdc_ctl: lcdc-ctl { + rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, + <1 25 RK_FUNC_1 &pcfg_pull_none>, + <1 26 RK_FUNC_1 &pcfg_pull_none>, + <1 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 4aa6f60d6a22..49584b6a4195 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -117,6 +117,17 @@ clock-output-names = "xin24m"; }; + gpu: gpu@10090000 { + compatible = "arm,mali-400"; + reg = <0x10090000 0x10000>; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "core", "bus"; + assigned-clocks = <&cru ACLK_GPU>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + L2: l2-cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 86a57f823616..70f0106d1252 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -222,6 +222,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy { status = "okay"; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index e7cd1315db1b..76ea24636feb 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -43,6 +43,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/rv1108-cru.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/thermal/thermal.h> / { #address-cells = <1>; #size-cells = <1>; @@ -70,6 +71,8 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <75>; operating-points-v2 = <&cpu_opp_table>; }; }; @@ -329,6 +332,60 @@ status = "disabled"; }; + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <50>; + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + }; + + tsadc: tsadc@10370000 { + compatible = "rockchip,rv1108-tsadc"; + reg = <0x10370000 0x100>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,hw-tshut-temp = <120000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + adc: adc@1038c000 { compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; reg = <0x1038c000 0x100>; @@ -740,6 +797,16 @@ }; }; + tsadc { + otp_out: otp-out { + rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; + }; + + otp_gpio: otp-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi index 6274359fb323..92439ee5d7de 100644 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung S3C2416 pinctrl settings * * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index f257926c13b7..a1c9d8c695cc 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG SMDK2416 board device tree source * * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index 80f007550324..3c7385cab248 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S3C2416 SoC device tree source * * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/clock/s3c2443.h> diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi index 5ed43b857cc4..34c7fe6751cf 100644 --- a/arch/arm/boot/dts/s3c24xx.dtsi +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S3C24XX family device tree source * * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "skeleton.dtsi" diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi index a7d1c8ec150d..8c28e8a0c824 100644 --- a/arch/arm/boot/dts/s3c6400.dtsi +++ b/arch/arm/boot/dts/s3c6400.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S3C6400 SoC device tree source * @@ -10,11 +11,7 @@ * Note: This file does not include device nodes for all the controllers in * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include "s3c64xx.dtsi" diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index f4afda3594f8..f68601bd9c91 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S3C6410 based Mini6410 board device tree source * @@ -5,11 +6,7 @@ * * Device tree source file for FriendlyARM Mini6410 board which is based on * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts index ecf35ec466f7..b6b5afcd7602 100644 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung S3C6410 based SMDK6410 board device tree source. * @@ -5,11 +6,7 @@ * * Device tree source file for SAMSUNG SMDK6410 board which is based on * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi index eb4226b3407c..a766d6de696c 100644 --- a/arch/arm/boot/dts/s3c6410.dtsi +++ b/arch/arm/boot/dts/s3c6410.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S3C6410 SoC device tree source * @@ -10,11 +11,7 @@ * Note: This file does not include device nodes for all the controllers in * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include "s3c64xx.dtsi" diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index 4e8e802b4ee1..8e9594d64b57 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S3C64xx SoC series common device tree source * - pin control-related definitions @@ -6,10 +7,6 @@ * * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are * listed as device tree nodes in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index c55cbb3af2c0..e2be3fbdd3f3 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S3C64xx SoC series common device tree source * @@ -10,10 +11,6 @@ * Note: This file does not include device nodes for all the controllers in * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "skeleton.dtsi" diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 40139923eef0..14969b6529e8 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S5PV210 SoC device tree source * @@ -7,10 +8,6 @@ * Tomasz Figa <t.figa@samsung.com> * * Board device tree source for Samsung Aquila board. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index c56f51ee7897..eb6d1926c0d6 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S5PV210 SoC device tree source * @@ -7,10 +8,6 @@ * Tomasz Figa <t.figa@samsung.com> * * Board device tree source for Samsung Goni board. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 9a3e851e2e22..3a79feab11c3 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S5PV210 SoC device tree source * @@ -13,10 +14,6 @@ * Note: This file does not include device nodes for all the controllers in * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts index 5d14da911aa5..e5aec6c526fb 100644 --- a/arch/arm/boot/dts/s5pv210-smdkc110.dts +++ b/arch/arm/boot/dts/s5pv210-smdkc110.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S5PV210 SoC device tree source * @@ -11,10 +12,6 @@ * NOTE: This file is completely based on original board file for mach-smdkc110 * available in Linux 3.15 and intends to provide equivalent level of hardware * support. Due to lack of hardware, _no_ testing has been performed. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 75398318ed57..84b38f185199 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S5PV210 SoC device tree source * @@ -11,10 +12,6 @@ * NOTE: This file is completely based on original board file for mach-smdkv210 * available in Linux 3.15 and intends to provide equivalent level of hardware * support. Due to lack of hardware, _no_ testing has been performed. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts index 7cb50bcee888..cd25e72ccd84 100644 --- a/arch/arm/boot/dts/s5pv210-torbreck.dts +++ b/arch/arm/boot/dts/s5pv210-torbreck.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S5PV210 SoC device tree source * @@ -11,10 +12,6 @@ * NOTE: This file is completely based on original board file for mach-torbreck * available in Linux 3.15 and intends to provide equivalent level of hardware * support. Due to lack of hardware, _no_ testing has been performed. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 726c5d0dbd5b..67358562a6ea 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's S5PV210 SoC device tree source * @@ -13,11 +14,7 @@ * Note: This file does not include device nodes for all the controllers in * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include <dt-bindings/clock/s5pv210.h> #include <dt-bindings/clock/s5pv210-audss.h> @@ -463,6 +460,7 @@ compatible = "samsung,exynos4210-ohci"; reg = <0xec300000 0x100>; interrupts = <23>; + interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index b1a26b42d190..61f68e5c48e9 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -124,7 +124,7 @@ }; }; - ns_sram: sram@00200000 { + ns_sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x20000>; }; @@ -135,13 +135,13 @@ #size-cells = <1>; ranges; - nfc_sram: sram@00100000 { + nfc_sram: sram@100000 { compatible = "mmio-sram"; no-memory-wc; reg = <0x00100000 0x2400>; }; - usb0: gadget@00300000 { + usb0: gadget@300000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,sama5d3-udc"; @@ -271,7 +271,7 @@ }; }; - usb1: ohci@00400000 { + usb1: ohci@400000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00400000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; @@ -280,7 +280,7 @@ status = "disabled"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00500000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; @@ -289,7 +289,7 @@ status = "disabled"; }; - L2: cache-controller@00a00000 { + L2: cache-controller@a00000 { compatible = "arm,pl310-cache"; reg = <0x00a00000 0x1000>; interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; @@ -1094,7 +1094,9 @@ }; tcb0: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>, <&clk32k>; @@ -1102,7 +1104,9 @@ }; tcb1: timer@f8010000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf8010000 0x100>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb1_clk>, <&clk32k>; @@ -1427,6 +1431,8 @@ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&adc_clk>; clock-names = "adc_clk"; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; + dma-names = "rx"; atmel,min-sample-rate-hz = <200000>; atmel,max-sample-rate-hz = <20000000>; atmel,startup-time-ms = <4>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 554d0bdedc7a..b9c05b57735e 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -79,7 +79,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x20000>; }; @@ -142,7 +142,9 @@ }; tcb0: timer@f0010000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>, <&clk32k>; @@ -1408,7 +1410,7 @@ reg = <0x200000 0x2400>; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,sama5d3-udc"; @@ -1525,7 +1527,7 @@ }; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1534,7 +1536,7 @@ status = "disabled"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 801f9745e82f..cb30bdb1a9ca 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -28,7 +28,9 @@ }; tcb1: timer@f8014000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb1_clk>, <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 9506daf5efb6..3311a882458b 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -34,6 +34,18 @@ spi0: spi@f0004000 { cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; }; + + tcb0: timer@f0010000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; }; ebi@10000000 { diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi index 75cbf4d4ab1a..a02f59021364 100644 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi @@ -69,6 +69,18 @@ cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; }; + tcb0: timer@f0010000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + macb0: ethernet@f0028000 { phy-mode = "rgmii"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 6d252ad050f6..ef0f2d049e15 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -53,7 +53,7 @@ }; i2c1: i2c@f0018000 { - ov2640: camera@0x30 { + ov2640: camera@30 { compatible = "ovti,ov2640"; reg = <0x30>; pinctrl-names = "default"; @@ -166,14 +166,14 @@ }; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { num-ports = <3>; atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH &pioD 26 GPIO_ACTIVE_LOW @@ -182,7 +182,7 @@ status = "okay"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi index 252e0d35f846..97e171db5970 100644 --- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi @@ -88,7 +88,7 @@ }; i2c1: i2c@f0018000 { - ov2640: camera@0x30 { + ov2640: camera@30 { compatible = "ovti,ov2640"; reg = <0x30>; pinctrl-names = "default"; @@ -253,7 +253,7 @@ }; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 2fa36c525957..373b3621b536 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -113,7 +113,7 @@ }; }; - ns_sram: sram@00210000 { + ns_sram: sram@210000 { compatible = "mmio-sram"; reg = <0x00210000 0x10000>; }; @@ -130,7 +130,7 @@ reg = <0x100000 0x2400>; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,sama5d3-udc"; @@ -260,7 +260,7 @@ }; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; @@ -269,7 +269,7 @@ status = "disabled"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; @@ -278,7 +278,7 @@ status = "disabled"; }; - L2: cache-controller@00a00000 { + L2: cache-controller@a00000 { compatible = "arm,pl310-cache"; reg = <0x00a00000 0x1000>; interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; @@ -960,7 +960,9 @@ }; tcb0: timer@f801c000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xf801c000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>, <&clk32k>; @@ -1188,13 +1190,25 @@ }; tcb1: timer@fc020000 { - compatible = "atmel,at91sam9x5-tcb"; + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xfc020000 0x100>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb1_clk>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; + tcb2: timer@fc024000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc024000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb2_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + macb1: ethernet@fc028000 { compatible = "atmel,sama5d4-gem"; reg = <0xfc028000 0x100>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 4ea5c5a16c57..914a7c2a584f 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -27,6 +27,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; power-domains = <&pd_a2sl>; next-level-cache = <&L2>; }; @@ -35,6 +36,7 @@ compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; power-domains = <&pd_a2sl>; next-level-cache = <&L2>; }; @@ -98,9 +100,6 @@ clocks = <&mstp3_clks SH73A0_CLK_CMT1>; clock-names = "fck"; power-domains = <&pd_c5>; - - renesas,channels-mask = <0x3f>; - status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7e24dc8e82d4..c42ca7022e8c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -651,6 +651,7 @@ #size-cells = <0>; compatible = "snps,designware-i2c"; reg = <0xffc04000 0x1000>; + resets = <&rst I2C0_RESET>; clocks = <&l4_sp_clk>; interrupts = <0 158 0x4>; status = "disabled"; @@ -661,6 +662,7 @@ #size-cells = <0>; compatible = "snps,designware-i2c"; reg = <0xffc05000 0x1000>; + resets = <&rst I2C1_RESET>; clocks = <&l4_sp_clk>; interrupts = <0 159 0x4>; status = "disabled"; @@ -671,6 +673,7 @@ #size-cells = <0>; compatible = "snps,designware-i2c"; reg = <0xffc06000 0x1000>; + resets = <&rst I2C2_RESET>; clocks = <&l4_sp_clk>; interrupts = <0 160 0x4>; status = "disabled"; @@ -681,6 +684,7 @@ #size-cells = <0>; compatible = "snps,designware-i2c"; reg = <0xffc07000 0x1000>; + resets = <&rst I2C3_RESET>; clocks = <&l4_sp_clk>; interrupts = <0 161 0x4>; status = "disabled"; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 3a32de9ded3b..64cc86a98771 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -163,6 +163,7 @@ &usb0 { status = "okay"; + disable-over-current; }; &watchdog1 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index 655fe87e272d..2459d133f1be 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -237,7 +237,7 @@ clock-frequency = <100000>; at24@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; pagesize = <8>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts index 84101e4eebbf..0f5f379323a8 100644 --- a/arch/arm/boot/dts/spear1310-evb.dts +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -349,7 +349,7 @@ spi0: spi@e0100000 { status = "okay"; num-cs = <3>; - cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>; + cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>; stmpe610@0 { compatible = "st,stmpe610"; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index 5f347054527d..d4dbc4098653 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -142,8 +142,8 @@ reg = <0xb4100000 0x1000>; interrupts = <0 105 0x4>; status = "disabled"; - dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */ - <&dwdma0 0x680 0 1 0>; /* 0xD << 7 */ + dmas = <&dwdma0 12 0 1>, + <&dwdma0 13 1 0>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 17ea0abcdbd7..086b4b333249 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -100,7 +100,7 @@ reg = <0xb2800000 0x1000>; interrupts = <0 29 0x4>; status = "disabled"; - dmas = <&dwdma0 0 0 0 0>; + dmas = <&dwdma0 0 0 0>; dma-names = "data"; }; @@ -290,8 +290,8 @@ #size-cells = <0>; interrupts = <0 31 0x4>; status = "disabled"; - dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */ - <&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */ + dmas = <&dwdma0 4 0 0>, + <&dwdma0 5 0 0>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index 6b32d20acc9f..00166eb9be86 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -194,6 +194,7 @@ rtc: rtc@fc900000 { compatible = "st,spear600-rtc"; reg = <0xfc900000 0x1000>; + interrupt-parent = <&vic0>; interrupts = <10>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 6f720756057d..35e944d8b5c4 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -92,7 +92,7 @@ interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>; }; - ak8974@0f { + ak8974@f { /* Magnetometer */ compatible = "asahi-kasei,ak8974"; reg = <0x0f>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 3c9f2f068c2f..0e7d77d719d7 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -143,7 +143,7 @@ interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>; }; - ak8974@0f { + ak8974@f { /* Magnetometer */ compatible = "asahi-kasei,ak8974"; reg = <0x0f>; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 68aab50a73ab..733678b75b88 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -750,6 +750,7 @@ reg = <0x10120000 0x1000>; interrupt-names = "combined"; interrupts = <14>; + interrupt-parent = <&vica>; clocks = <&clcdclk>, <&hclkclcd>; clock-names = "clcdclk", "apb_pclk"; status = "disabled"; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 34c119a66f14..d0a24d9e517a 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -90,7 +90,7 @@ clock-output-names = "clk-s-icn-reg-0"; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -131,7 +131,7 @@ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -220,7 +220,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 12c0757594d7..cf3756976c39 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -72,19 +72,19 @@ }; }; - intc: interrupt-controller@08761000 { + intc: interrupt-controller@8761000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x08761000 0x1000>, <0x08760100 0x100>; }; - scu@08760000 { + scu@8760000 { compatible = "arm,cortex-a9-scu"; reg = <0x08760000 0x1000>; }; - timer@08760200 { + timer@8760200 { interrupt-parent = <&intc>; compatible = "arm,cortex-a9-global-timer"; reg = <0x08760200 0x100>; @@ -555,7 +555,7 @@ status = "disabled"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09060000 0x7ff>, <0x9061008 0x20>; @@ -570,7 +570,7 @@ bus-width = <8>; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09080000 0x7ff>; @@ -715,14 +715,14 @@ status = "disabled"; }; - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; @@ -756,14 +756,14 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index bd1a82e8fffe..a29090077fdf 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -56,7 +56,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09610000 0x6000>; - pio0: gpio@09610000 { + pio0: gpio@9610000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -64,7 +64,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO0"; }; - pio1: gpio@09611000 { + pio1: gpio@9611000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -72,7 +72,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - pio2: gpio@09612000 { + pio2: gpio@9612000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -80,7 +80,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - pio3: gpio@09613000 { + pio3: gpio@9613000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -88,7 +88,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - pio4: gpio@09614000 { + pio4: gpio@9614000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -97,7 +97,7 @@ st,bank-name = "PIO4"; }; - pio5: gpio@09615000 { + pio5: gpio@9615000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -380,7 +380,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09200000 0x10000>; - pio10: pio@09200000 { + pio10: pio@9200000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -388,7 +388,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO10"; }; - pio11: pio@09201000 { + pio11: pio@9201000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -396,7 +396,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO11"; }; - pio12: pio@09202000 { + pio12: pio@9202000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -404,7 +404,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO12"; }; - pio13: pio@09203000 { + pio13: pio@9203000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -412,7 +412,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO13"; }; - pio14: pio@09204000 { + pio14: pio@9204000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -420,7 +420,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO14"; }; - pio15: pio@09205000 { + pio15: pio@9205000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -428,7 +428,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO15"; }; - pio16: pio@09206000 { + pio16: pio@9206000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -436,7 +436,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO16"; }; - pio17: pio@09207000 { + pio17: pio@9207000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -444,7 +444,7 @@ reg = <0x7000 0x100>; st,bank-name = "PIO17"; }; - pio18: pio@09208000 { + pio18: pio@9208000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -452,7 +452,7 @@ reg = <0x8000 0x100>; st,bank-name = "PIO18"; }; - pio19: pio@09209000 { + pio19: pio@9209000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -940,7 +940,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09210000 0x10000>; - pio20: pio@09210000 { + pio20: pio@9210000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -973,7 +973,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09220000 0x6000>; - pio30: gpio@09220000 { + pio30: gpio@9220000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -981,7 +981,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO30"; }; - pio31: gpio@09221000 { + pio31: gpio@9221000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -989,7 +989,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO31"; }; - pio32: gpio@09222000 { + pio32: gpio@9222000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -997,7 +997,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO32"; }; - pio33: gpio@09223000 { + pio33: gpio@9223000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1005,7 +1005,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO33"; }; - pio34: gpio@09224000 { + pio34: gpio@9224000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1013,7 +1013,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO34"; }; - pio35: gpio@09225000 { + pio35: gpio@9225000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1168,7 +1168,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09230000 0x3000>; - pio40: gpio@09230000 { + pio40: gpio@9230000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1176,7 +1176,7 @@ reg = <0 0x100>; st,bank-name = "PIO40"; }; - pio41: gpio@09231000 { + pio41: gpio@9231000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1184,7 +1184,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO41"; }; - pio42: gpio@09232000 { + pio42: gpio@9232000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index fa149837df14..11fdecd9312e 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -8,6 +8,7 @@ */ #include "stih407-clock.dtsi" #include "stih407-family.dtsi" +#include <dt-bindings/gpio/gpio.h> / { soc { sti-display-subsystem { @@ -122,7 +123,7 @@ <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; - hdmi,hpd-gpio = <&pio5 3>; + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; reset-names = "hdmi"; resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; ddc = <&hdmiddc>; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts index 83313b51915d..9830be577433 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -30,7 +30,7 @@ soc { - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { max-frequency = <200000000>; sd-uhs-sdr50; sd-uhs-sdr104; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 93c14d183e29..c663b70c43a7 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -109,14 +109,14 @@ status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { pinctrl-0 = <&pinctrl_sd0>; bus-width = <4>; status = "okay"; }; /* high speed expansion connector */ - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 07c8ef9d77f6..fde5df17f575 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -92,7 +92,7 @@ clock-output-names = "clk-s-icn-reg-0"; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -134,7 +134,7 @@ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -230,7 +230,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 21fe72b183d8..68b5ff91d6a7 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -9,6 +9,7 @@ #include "stih410-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> / { aliases { bdisp0 = &bdisp0; @@ -213,7 +214,7 @@ <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; - hdmi,hpd-gpio = <&pio5 3>; + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; reset-names = "hdmi"; resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; ddc = <&hdmiddc>; @@ -282,7 +283,7 @@ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; }; - sti-cec@094a087c { + sti-cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 438e54c585b1..4e6d915c85ff 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -75,11 +75,11 @@ st,i2c-min-sda-pulse-width-us = <5>; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { status = "okay"; max-frequency = <200000000>; sd-uhs-sdr50; diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index ee6614b79f7d..9a157c1a99b1 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -92,7 +92,7 @@ clock-output-names = "clk-s-icn-reg-0"; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -131,7 +131,7 @@ "clk-s-c0-fs0-ch3"; }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -223,7 +223,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 965f88160718..e6525ab4d9bb 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -100,7 +100,7 @@ phy-names = "usb"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; assigned-clock-parents = <&clk_s_c0_pll1 0>; assigned-clock-rates = <200000000>; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 4b8f62f89664..7f80c2c414c8 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -62,12 +62,12 @@ status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { non-removable; status = "okay"; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; @@ -102,7 +102,7 @@ fixed-link = <0 1 1000 0 0>; }; - demux@08a20000 { + demux@8a20000 { compatible = "st,stih407-c8sectpfe"; status = "okay"; reg = <0x08a20000 0x10000>, diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 69a957963fa8..2d4e71717694 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -83,6 +83,13 @@ gpios = <&gpioc 13 0>; }; }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; }; &clk_hse { @@ -93,6 +100,14 @@ status = "okay"; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + &rtc { status = "okay"; }; @@ -102,3 +117,12 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 7f3560c0211d..ae94d86c53c4 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <dt-bindings/mfd/stm32f4-rcc.h> / { @@ -165,35 +165,35 @@ usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ bias-disable; }; }; usart3_pins_a: usart3@0 { pins1 { - pinmux = <STM32F429_PB10_FUNC_USART3_TX>; + pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PB11_FUNC_USART3_RX>; + pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ bias-disable; }; }; usbotg_fs_pins_a: usbotg_fs@0 { pins { - pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>, - <STM32F429_PA11_FUNC_OTG_FS_DM>, - <STM32F429_PA12_FUNC_OTG_FS_DP>; + pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ + <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ + <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -202,9 +202,9 @@ usbotg_fs_pins_b: usbotg_fs@1 { pins { - pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>, - <STM32F429_PB14_FUNC_OTG_HS_DM>, - <STM32F429_PB15_FUNC_OTG_HS_DP>; + pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */ + <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */ + <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -213,18 +213,18 @@ usbotg_hs_pins_a: usbotg_hs@0 { pins { - pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>, - <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>, - <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>, - <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>, - <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>, - <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>, - <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>, - <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>, - <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>, - <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>, - <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>, - <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>; + pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/ + <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ + <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ + <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ + <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ + <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ + <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ + <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ + <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ + <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ + <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ + <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -233,49 +233,49 @@ ethernet_mii: mii@0 { pins { - pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, - <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, - <STM32F429_PC2_FUNC_ETH_MII_TXD2>, - <STM32F429_PB8_FUNC_ETH_MII_TXD3>, - <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>, - <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, - <STM32F429_PA2_FUNC_ETH_MDIO>, - <STM32F429_PC1_FUNC_ETH_MDC>, - <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, - <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, - <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, - <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, - <STM32F429_PH6_FUNC_ETH_MII_RXD2>, - <STM32F429_PH7_FUNC_ETH_MII_RXD3>; + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */ + <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */ + <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */ + <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ + <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */ + <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */ + <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */ slew-rate = <2>; }; }; adc3_in8_pin: adc@200 { pins { - pinmux = <STM32F429_PF10_FUNC_ANALOG>; + pinmux = <STM32_PINMUX('F', 10, ANALOG)>; }; }; pwm1_pins: pwm@1 { pins { - pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>, - <STM32F429_PB13_FUNC_TIM1_CH1N>, - <STM32F429_PB12_FUNC_TIM1_BKIN>; + pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ + <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */ + <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */ }; }; pwm3_pins: pwm@3 { pins { - pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>, - <STM32F429_PB5_FUNC_TIM3_CH2>; + pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */ + <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ }; }; i2c1_pins: i2c1@0 { pins { - pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>, - <STM32F429_PB6_FUNC_I2C1_SCL>; + pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */ + <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */ bias-disable; drive-open-drain; slew-rate = <3>; @@ -284,55 +284,55 @@ ltdc_pins: ltdc@0 { pins { - pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>, - <STM32F429_PI13_FUNC_LCD_VSYNC>, - <STM32F429_PI14_FUNC_LCD_CLK>, - <STM32F429_PI15_FUNC_LCD_R0>, - <STM32F429_PJ0_FUNC_LCD_R1>, - <STM32F429_PJ1_FUNC_LCD_R2>, - <STM32F429_PJ2_FUNC_LCD_R3>, - <STM32F429_PJ3_FUNC_LCD_R4>, - <STM32F429_PJ4_FUNC_LCD_R5>, - <STM32F429_PJ5_FUNC_LCD_R6>, - <STM32F429_PJ6_FUNC_LCD_R7>, - <STM32F429_PJ7_FUNC_LCD_G0>, - <STM32F429_PJ8_FUNC_LCD_G1>, - <STM32F429_PJ9_FUNC_LCD_G2>, - <STM32F429_PJ10_FUNC_LCD_G3>, - <STM32F429_PJ11_FUNC_LCD_G4>, - <STM32F429_PJ12_FUNC_LCD_B0>, - <STM32F429_PJ13_FUNC_LCD_B1>, - <STM32F429_PJ14_FUNC_LCD_B2>, - <STM32F429_PJ15_FUNC_LCD_B3>, - <STM32F429_PK0_FUNC_LCD_G5>, - <STM32F429_PK1_FUNC_LCD_G6>, - <STM32F429_PK2_FUNC_LCD_G7>, - <STM32F429_PK3_FUNC_LCD_B4>, - <STM32F429_PK4_FUNC_LCD_B5>, - <STM32F429_PK5_FUNC_LCD_B6>, - <STM32F429_PK6_FUNC_LCD_B7>, - <STM32F429_PK7_FUNC_LCD_DE>; + pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ + <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/ + <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/ + <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ + <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ + <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */ + <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */ slew-rate = <2>; }; }; dcmi_pins: dcmi@0 { pins { - pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>, - <STM32F429_PB7_FUNC_DCMI_VSYNC>, - <STM32F429_PA6_FUNC_DCMI_PIXCLK>, - <STM32F429_PC6_FUNC_DCMI_D0>, - <STM32F429_PC7_FUNC_DCMI_D1>, - <STM32F429_PC8_FUNC_DCMI_D2>, - <STM32F429_PC9_FUNC_DCMI_D3>, - <STM32F429_PC11_FUNC_DCMI_D4>, - <STM32F429_PD3_FUNC_DCMI_D5>, - <STM32F429_PB8_FUNC_DCMI_D6>, - <STM32F429_PE6_FUNC_DCMI_D7>, - <STM32F429_PC10_FUNC_DCMI_D8>, - <STM32F429_PC12_FUNC_DCMI_D9>, - <STM32F429_PD6_FUNC_DCMI_D10>, - <STM32F429_PD2_FUNC_DCMI_D11>; + pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */ + <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */ + <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */ + <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */ + <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */ + <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */ + <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */ + <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */ + <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */ + <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */ + <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */ + <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */ bias-disable; drive-push-pull; slew-rate = <3>; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 5b36eb114ddc..10099df8b73e 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -314,7 +314,7 @@ }; usart2: serial@40004400 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; @@ -322,7 +322,7 @@ }; usart3: serial@40004800 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; @@ -386,7 +386,7 @@ }; usart7: serial@40007800 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40007800 0x400>; interrupts = <82>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; @@ -394,7 +394,7 @@ }; usart8: serial@40007c00 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; @@ -444,7 +444,7 @@ }; usart1: serial@40011000 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; @@ -455,7 +455,7 @@ }; usart6: serial@40011400 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40011400 0x400>; interrupts = <71>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index 18f656074437..4d85dba59e1d 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -61,6 +61,20 @@ serial0 = &usart1; }; + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + /* This turns on vbus for otg fs for host mode (dwc2) */ + vcc5v_otg_fs: vcc5v-otg-fs-regulator { + compatible = "regulator-fixed"; + gpio = <&gpiod 5 0>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &clk_hse { @@ -72,3 +86,19 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5633860037d2..5f66d151eedb 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -42,7 +42,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" -#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <dt-bindings/clock/stm32fx-clock.h> #include <dt-bindings/mfd/stm32f7-rcc.h> @@ -82,6 +82,27 @@ status = "disabled"; }; + timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + timer3: timer@40000400 { compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; @@ -90,6 +111,27 @@ status = "disabled"; }; + timers3: timers@40000400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + timer4: timer@40000800 { compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; @@ -98,6 +140,27 @@ status = "disabled"; }; + timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,6 +168,27 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; + timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + timer6: timer@40001000 { compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; @@ -113,6 +197,22 @@ status = "disabled"; }; + timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + clock-names = "int"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + timer7: timer@40001400 { compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; @@ -121,6 +221,73 @@ status = "disabled"; }; + timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + clock-names = "int"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timers@40001c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers14: timers@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; @@ -136,7 +303,7 @@ }; usart2: serial@40004400 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; clocks = <&rcc 1 CLK_USART2>; @@ -144,7 +311,7 @@ }; usart3: serial@40004800 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40004800 0x400>; interrupts = <39>; clocks = <&rcc 1 CLK_USART3>; @@ -167,6 +334,18 @@ status = "disabled"; }; + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F7_APB1_RESET(I2C1)>; + clocks = <&rcc 1 CLK_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cec: cec@40006c00 { compatible = "st,stm32-cec"; reg = <0x40006C00 0x400>; @@ -177,7 +356,7 @@ }; usart7: serial@40007800 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40007800 0x400>; interrupts = <82>; clocks = <&rcc 1 CLK_UART7>; @@ -185,15 +364,57 @@ }; usart8: serial@40007c00 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; clocks = <&rcc 1 CLK_UART8>; status = "disabled"; }; + timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + }; + usart1: serial@40011000 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&rcc 1 CLK_USART1>; @@ -201,7 +422,7 @@ }; usart6: serial@40011400 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40011400 0x400>; interrupts = <71>; clocks = <&rcc 1 CLK_USART6>; @@ -221,6 +442,57 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; }; + timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; @@ -347,7 +619,7 @@ cec_pins_a: cec@0 { pins { - pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>; + pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */ slew-rate = <0>; drive-open-drain; bias-disable; @@ -356,27 +628,88 @@ usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ bias-disable; }; }; usart1_pins_b: usart1@1 { pins1 { - pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F746_PB7_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */ + bias-disable; + }; + }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */ + <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ + <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ + <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ + <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ + <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ + <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ + <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ + <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ + <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ + <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ + <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ + <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs@1 { + pins { + pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ + <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */ + <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ + <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ + <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ + <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ + <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ + <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ + <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ + <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ + <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ + <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_a: usbotg-fs@0 { + pins { + pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ + <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ + <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; }; }; }; @@ -431,6 +764,24 @@ st,mem2mem; status = "disabled"; }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; + clock-names = "otg"; + status = "disabled"; + }; + + usbotg_fs: usb@50000000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; + clock-names = "otg"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi index 76bbd6575fae..65c1cd043987 100644 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/pinctrl/stm32h7-pinfunc.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> / { soc { @@ -55,7 +55,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x0 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; }; @@ -63,7 +63,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; }; @@ -71,7 +71,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; }; @@ -79,7 +79,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0xc00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; }; @@ -87,7 +87,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; }; @@ -95,7 +95,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; }; @@ -103,7 +103,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; }; @@ -111,7 +111,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1c00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; }; @@ -119,7 +119,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; }; @@ -127,7 +127,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; }; @@ -135,32 +135,32 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; }; usart1_pins: usart1@0 { pins1 { - pinmux = <STM32H7_PB14_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32H7_PB15_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */ bias-disable; }; }; usart2_pins: usart2@0 { pins1 { - pinmux = <STM32H7_PD5_FUNC_USART2_TX>; + pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32H7_PD6_FUNC_USART2_RX>; + pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ bias-disable; }; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 58ec2275181e..bbfcbaca0b36 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -42,6 +42,8 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" +#include <dt-bindings/clock/stm32h7-clks.h> +#include <dt-bindings/mfd/stm32h7-rcc.h> / { clocks { @@ -51,10 +53,16 @@ clock-frequency = <0>; }; - timer_clk: timer-clk { + clk_lse: clk-lse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <125000000>; + clock-frequency = <32768>; + }; + + clk_i2s: i2s_ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; }; }; @@ -63,21 +71,47 @@ compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; - clocks = <&timer_clk>; + clocks = <&rcc TIM5_CK>; + }; + + lptimer1: timer@40002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + clocks = <&rcc LPTIM1_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; }; usart2: serial@40004400 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; - clocks = <&timer_clk>; + clocks = <&rcc USART2_CK>; }; dac: dac@40007400 { compatible = "st,stm32h7-dac-core"; reg = <0x40007400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc DAC12_CK>; clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; @@ -99,12 +133,11 @@ }; usart1: serial@40011000 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; - clocks = <&timer_clk>; - + clocks = <&rcc USART1_CK>; }; dma1: dma@40020000 { @@ -118,9 +151,10 @@ <16>, <17>, <47>; - clocks = <&timer_clk>; + clocks = <&rcc DMA1_CK>; #dma-cells = <4>; st,mem2mem; + dma-requests = <8>; status = "disabled"; }; @@ -135,17 +169,28 @@ <68>, <69>, <70>; - clocks = <&timer_clk>; + clocks = <&rcc DMA2_CK>; #dma-cells = <4>; st,mem2mem; + dma-requests = <8>; status = "disabled"; }; + dmamux1: dma-router@40020800 { + compatible = "st,stm32h7-dmamux"; + reg = <0x40020800 0x1c>; + #dma-cells = <3>; + dma-channels = <16>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + clocks = <&rcc DMA1_CK>; + }; + adc_12: adc@40022000 { compatible = "st,stm32h7-adc-core"; reg = <0x40022000 0x400>; interrupts = <18>; - clocks = <&timer_clk>; + clocks = <&rcc ADC12_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; @@ -172,11 +217,121 @@ }; }; + mdma1: dma@52000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x52000000 0x1000>; + interrupts = <122>; + clocks = <&rcc MDMA_CK>; + #dma-cells = <5>; + dma-channels = <16>; + dma-requests = <32>; + }; + + lptimer2: timer@58002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002400 0x400>; + clocks = <&rcc LPTIM2_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@58002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002800 0x400>; + clocks = <&rcc LPTIM3_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@58002c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002c00 0x400>; + clocks = <&rcc LPTIM4_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + }; + + lptimer5: timer@58003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58003000 0x400>; + clocks = <&rcc LPTIM5_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + }; + + vrefbuf: regulator@58003C00 { + compatible = "st,stm32-vrefbuf"; + reg = <0x58003C00 0x8>; + clocks = <&rcc VREF_CK>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + status = "disabled"; + }; + + rcc: reset-clock-controller@58024400 { + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg = <&pwrcfg>; + }; + + pwrcfg: power-config@58024800 { + compatible = "syscon"; + reg = <0x58024800 0x400>; + }; + adc_3: adc@58026000 { compatible = "st,stm32h7-adc-core"; reg = <0x58026000 0x400>; interrupts = <127>; - clocks = <&timer_clk>; + clocks = <&rcc ADC3_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 6c07786e7ddb..9f0e72c67219 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -81,7 +81,7 @@ }; &clk_hse { - clock-frequency = <125000000>; + clock-frequency = <25000000>; }; &usart1 { diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index f80d37ddc4c6..09e909576c61 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a1000>; red { label = "a1000:red:usr"; @@ -79,8 +77,6 @@ reg_emac_3v3: emac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_a1000>; regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -129,8 +125,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -140,8 +134,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -156,7 +148,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -170,8 +162,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -187,18 +177,6 @@ status = "okay"; }; -&pio { - emac_power_pin_a1000: emac_power_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - led_pins_a1000: led_pins@0 { - pins = "PH10", "PH20"; - function = "gpio_out"; - }; -}; - #include "axp209.dtsi" ®_dcdc2 { @@ -236,13 +214,13 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index 6b02de592a02..39ba4ccb9e2e 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -68,8 +68,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -79,8 +77,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -95,7 +91,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -108,8 +104,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -125,12 +119,6 @@ status = "okay"; }; -&pio { - usb2_vbus_pin_a: usb2_vbus_pin@0 { - pins = "PH12"; - }; -}; - ®_usb0_vbus { regulator-boot-on; status = "okay"; @@ -147,7 +135,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index a7d61994b8fd..dfc88aee4fe3 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -65,8 +65,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -80,14 +78,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5306de4: touchscreen@38 { @@ -104,21 +98,21 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@800 { + button-800 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Back"; linux,code = <KEY_BACK>; channel = <0>; @@ -127,8 +121,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -141,13 +133,13 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -164,7 +156,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 404ce7694899..1982c8c238c5 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -59,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -90,6 +101,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -99,8 +114,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -109,9 +122,17 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -121,14 +142,12 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -141,8 +160,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -163,13 +180,13 @@ }; &pio { - led_pins_cubieboard: led_pins@0 { + led_pins_cubieboard: led-pins { pins = "PH20", "PH21"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; @@ -221,14 +238,14 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index e0777ae808c7..147cbc5e08ac 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -58,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_dsrv9703c>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -77,10 +75,8 @@ max-microvolt = <3000000>; }; - reg_motor: reg_motor { + reg_motor: reg-motor { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&motor_pins>; regulator-name = "vcc-motor"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; @@ -90,8 +86,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; @@ -105,8 +99,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -118,15 +110,11 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; /* pull-ups and devices require AXP209 LDO3 */ status = "failed"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -134,8 +122,6 @@ reg = <0x38>; interrupt-parent = <&pio>; interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; touchscreen-size-x = <1024>; touchscreen-size-y = <768>; @@ -146,14 +132,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@400 { + button-400 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <400000>; }; - button@800 { + button-800 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; @@ -162,8 +148,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -176,33 +160,13 @@ }; &pio { - bl_en_pin_dsrv9703c: bl_en_pin@0 { - pins = "PH7"; - function = "gpio_out"; - }; - - codec_pa_pin: codec_pa_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - motor_pins: motor_pins@0 { - pins = "PB3"; - function = "gpio_out"; - }; - - touchscreen_pins: touchscreen_pins@0 { - pins = "PB13"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -211,7 +175,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -250,7 +214,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts index d8bfd7b74916..41ca8bded89f 100644 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts @@ -72,8 +72,6 @@ */ &codec { /* PH15 controls power to external amplifier (ft2012q) */ - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -91,8 +89,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -104,8 +100,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -122,21 +116,21 @@ status = "okay"; - button@158 { + button-158 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <158730>; }; - button@349 { + button-349 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <349206>; }; - button@1142 { + button-1142 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -145,8 +139,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ @@ -154,13 +146,6 @@ status = "okay"; }; -&pio { - codec_pa_pin: codec_pa_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -197,7 +182,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 856cfc9128e6..f33e42d6ce8b 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -80,8 +80,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy0>; status = "okay"; }; @@ -92,7 +90,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -106,8 +104,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -123,27 +119,11 @@ status = "okay"; }; -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&hackberry_hogs>; - - hackberry_hogs: hogs@0 { - pins = "PH19"; - function = "gpio_out"; - }; - - usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { - pins = "PH12"; - function = "gpio_out"; - }; -}; - ®_usb1_vbus { status = "okay"; }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_hackberry>; gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -156,6 +136,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index 6506595268b2..35c57d065dd8 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -63,8 +63,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -78,8 +76,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -92,13 +88,13 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -116,7 +112,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index d51d8c302daf..9482e831a9a1 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -58,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_inet>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -88,8 +86,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -101,8 +97,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -115,8 +109,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5x: touchscreen@38 { @@ -124,8 +116,6 @@ reg = <0x38>; interrupt-parent = <&pio>; interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_wake_pin>; wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ touchscreen-size-x = <600>; touchscreen-size-y = <1024>; @@ -137,21 +127,21 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <200000>; }; - button@1000 { + button-1000 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; @@ -160,8 +150,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -178,23 +166,13 @@ }; &pio { - bl_en_pin_inet: bl_en_pin@0 { - pins = "PH7"; - function = "gpio_out"; - }; - - touchscreen_wake_pin: touchscreen_wake_pin@0 { - pins = "PB13"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -203,7 +181,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -246,7 +224,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index a8e479fe43ca..4b5c91c8e85b 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -72,8 +72,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -85,14 +83,10 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -109,35 +103,35 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Menu"; linux,code = <KEY_MENU>; channel = <0>; voltage = <200000>; }; - button@600 { + button-600 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -146,8 +140,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -160,13 +152,13 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -208,7 +200,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 2acb89a87d41..13224f5ac166 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -59,7 +59,7 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys-polled"; pinctrl-names = "default"; pinctrl-0 = <&key_pins_inet9f>; @@ -67,7 +67,7 @@ #size-cells = <0>; poll-interval = <20>; - button@0 { + left-joystick-left { label = "Left Joystick Left"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -75,7 +75,7 @@ gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ }; - button@1 { + left-joystick-right { label = "Left Joystick Right"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -83,7 +83,7 @@ gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ }; - button@2 { + left-joystick-up { label = "Left Joystick Up"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -91,7 +91,7 @@ gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ }; - button@3 { + left-joystick-down { label = "Left Joystick Down"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -99,7 +99,7 @@ gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ }; - button@4 { + right-joystick-left { label = "Right Joystick Left"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -107,7 +107,7 @@ gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ }; - button@5 { + right-joystick-right { label = "Right Joystick Right"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -115,7 +115,7 @@ gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ }; - button@6 { + right-joystick-up { label = "Right Joystick Up"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -123,7 +123,7 @@ gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ }; - button@7 { + right-joystick-down { label = "Right Joystick Down"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -131,7 +131,7 @@ gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ }; - button@8 { + dpad-left { label = "DPad Left"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -139,7 +139,7 @@ gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */ }; - button@9 { + dpad-right { label = "DPad Right"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -147,7 +147,7 @@ gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ }; - button@10 { + dpad-up { label = "DPad Up"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -155,7 +155,7 @@ gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ }; - button@11 { + dpad-down { label = "DPad Down"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -163,49 +163,49 @@ gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ }; - button@12 { + x { label = "Button X"; linux,code = <BTN_X>; gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */ }; - button@13 { + y { label = "Button Y"; linux,code = <BTN_Y>; gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */ }; - button@14 { + a { label = "Button A"; linux,code = <BTN_A>; gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ }; - button@15 { + b { label = "Button B"; linux,code = <BTN_B>; gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */ }; - button@16 { + select { label = "Select Button"; linux,code = <BTN_SELECT>; gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ }; - button@17 { + start { label = "Start Button"; linux,code = <BTN_START>; gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ }; - button@18 { + top-left { label = "Top Left Button"; linux,code = <BTN_TL>; gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ }; - button@19 { + top-right { label = "Top Right Button"; linux,code = <BTN_TR>; gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */ @@ -222,8 +222,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -235,8 +233,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -249,8 +245,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -267,35 +261,35 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Menu"; linux,code = <KEY_MENU>; channel = <0>; voltage = <200000>; }; - button@600 { + button-600 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -304,8 +298,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -318,7 +310,7 @@ }; &pio { - key_pins_inet9f: key_pins@0 { + key_pins_inet9f: key-pins { pins = "PA0", "PA1", "PA3", "PA4", "PA5", "PA6", "PA8", "PA9", "PA11", "PA12", "PA13", @@ -328,13 +320,13 @@ bias-pull-up; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -376,7 +368,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts index 92e3e030ced3..d22bd79562d8 100644 --- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts +++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -57,7 +57,7 @@ &emac { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; + pinctrl-0 = <&emac_pins>; phy = <&phy1>; status = "okay"; }; @@ -67,6 +67,9 @@ }; &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + axp209: pmic@34 { interrupts = <0>; }; @@ -74,19 +77,19 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -100,7 +103,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -114,7 +117,11 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; +}; diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts index 92b2d4af3d21..879141ca6027 100644 --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_q5>; green { label = "q5:green:usr"; @@ -74,8 +72,6 @@ reg_emac_3v3: emac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_q5>; regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -98,8 +94,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -109,8 +103,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -125,7 +117,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -139,8 +131,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -160,18 +150,6 @@ status = "okay"; }; -&pio { - emac_power_pin_q5: emac_power_pin@0 { - pins = "PH19"; - function = "gpio_out"; - }; - - led_pins_q5: led_pins@0 { - pins = "PH20"; - function = "gpio_out"; - }; -}; - ®_usb0_vbus { regulator-boot-on; status = "okay"; @@ -187,7 +165,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts index 0f927da28ee1..435c551aef0f 100644 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts @@ -61,8 +61,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_marsboard>; red1 { label = "marsboard:red1:usr"; @@ -107,27 +105,19 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; }; @@ -140,8 +130,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -162,12 +150,7 @@ }; &pio { - led_pins_marsboard: led_pins@0 { - pins = "PB5", "PB6", "PB7", "PB8"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; @@ -184,14 +167,14 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index a5ed9e4e22c6..1b639e5f9172 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -70,8 +70,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -86,18 +84,16 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; -&ir0_rx_pins_a { +&ir0_rx_pins { /* The ir receiver is not always populated */ bias-pull-up; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -132,7 +128,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts index 81db6824a2c7..7198b34e2e50 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts @@ -71,8 +71,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -88,23 +86,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - pins = "PH4"; - function = "gpio_in"; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - pins = "PH5"; - function = "gpio_in"; - }; - - usb2_vbus_pin_mk802: usb2_vbus_pin@0 { - pins = "PH12"; - function = "gpio_out"; - }; -}; - ®_usb0_vbus { status = "okay"; }; @@ -114,14 +95,13 @@ }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_mk802>; gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; @@ -131,8 +111,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts index e74a881fd9a7..e460da2eb139 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts @@ -67,8 +67,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -82,8 +80,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -105,7 +101,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 462412ee903c..49247fbe6acd 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -58,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -89,6 +100,10 @@ cooling-max-level = <2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -98,8 +113,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -108,9 +121,17 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -124,8 +145,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; eeprom: eeprom@50 { @@ -144,8 +163,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -166,24 +183,19 @@ }; &pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - pins = "PC3"; - function = "gpio_out"; - }; - - led_pins_olinuxinolime: led_pins@0 { + led_pins_olinuxinolime: led-pin { pins = "PH2"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -191,7 +203,6 @@ }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -210,7 +221,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 84f55e76df0c..6e140547b638 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino>; tx { label = "pcduino:green:tx"; @@ -76,26 +74,24 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_pcduino>; #address-cells = <1>; #size-cells = <0>; - button@0 { + back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - button@1 { + home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - button@2 { + menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; @@ -116,8 +112,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -127,8 +121,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -146,8 +138,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -168,17 +158,7 @@ }; &pio { - led_pins_pcduino: led_pins@0 { - pins = "PH15", "PH16"; - function = "gpio_out"; - }; - - key_pins_pcduino: key_pins@0 { - pins = "PH17", "PH18", "PH19"; - function = "gpio_in"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; @@ -214,7 +194,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts index 811d00ee2ade..bc4f128965ed 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts @@ -55,16 +55,7 @@ compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; }; -&pio { - usb2_vbus_pin_pcduino2: usb2_vbus_pin@0 { - pins = "PD2"; - function = "gpio_out"; - }; -}; - ®_usb2_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_pcduino2>; gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index c0f8c88b5a7d..5081303f79e7 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -58,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_protab>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -72,8 +70,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; @@ -87,8 +83,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -100,20 +94,14 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; /* pull-ups and devices require AXP209 LDO3 */ status = "failed"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; - pixcir_ts@5c { - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; + touchscreen@5c { compatible = "pixcir,pixcir_tangoc"; reg = <0x5c>; interrupt-parent = <&pio>; @@ -132,14 +120,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@400 { + button-400 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <400000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; @@ -148,8 +136,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -162,28 +148,13 @@ }; &pio { - bl_en_pin_protab: bl_en_pin@0 { - pins = "PH7"; - function = "gpio_out"; - }; - - codec_pa_pin: codec_pa_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - touchscreen_pins: touchscreen_pins@0 { - pins = "PA5", "PB13"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -192,7 +163,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -231,7 +202,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 41c2579143fd..4f2f2eea0755 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -41,14 +41,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include <dt-bindings/thermal/thermal.h> - -#include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> +#include <dt-bindings/clock/sun4i-a10-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&intc>; aliases { @@ -60,46 +60,48 @@ #size-cells = <1>; ranges; - framebuffer@0 { + framebuffer-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@1 { + framebuffer-fe0-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@2 { + framebuffer-fe0-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@3 { + framebuffer-fe0-lcd0-tve0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 5>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; @@ -111,7 +113,7 @@ device_type = "cpu"; compatible = "arm,cortex-a8"; reg = <0x0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -127,7 +129,7 @@ }; thermal-zones { - cpu_thermal { + cpu-thermal { /* milliseconds */ polling-delay-passive = <250>; polling-delay = <1000>; @@ -141,14 +143,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <850000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; @@ -158,532 +160,46 @@ }; }; - memory { - reg = <0x40000000 0x80000000>; - }; - clocks { #address-cells = <1>; #size-cells = <1>; ranges; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc3M: osc3M_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; }; + }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>; - clock-output-names = "ahb"; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, <6>, - <7>, <8>, <9>, - <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, - <21>, <22>, <23>, - <24>, <25>, <26>, - <32>, <33>, <34>, - <35>, <36>, <37>, - <40>, <41>, <43>, - <44>, <45>, - <46>, <47>, - <50>, <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", - "ahb_ohci1", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", - "ahb_spi1", "ahb_spi2", "ahb_spi3", - "ahb_pata", "ahb_sata", "ahb_gps", - "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", - "ahb_csi0", "ahb_csi1", "ahb_hdmi", - "ahb_de_be0", "ahb_de_be1", - "ahb_de_fe0", "ahb_de_fe1", - "ahb_mp", "ahb_mali400"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, - <5>, <6>, - <7>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis", - "apb0_pio", "apb0_ir0", - "apb0_ir1", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <4>, - <5>, <6>, - <7>, <16>, - <17>, <18>, - <19>, <20>, - <21>, <22>, - <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_can", - "apb1_scr", "apb1_ps20", - "apb1_ps21", "apb1_uart0", - "apb1_uart1", "apb1_uart2", - "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", - "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; + de: display-engine { + compatible = "allwinner,sun4i-a10-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; }; - soc@01c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -697,14 +213,14 @@ }; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -712,19 +228,19 @@ }; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <27>; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <37>; - clocks = <&ahb_gates 13>, <&nand_clk>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; @@ -733,11 +249,11 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -747,30 +263,34 @@ #size-cells = <0>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; - clocks = <&ahb_gates 17>; + clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -778,78 +298,154 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <45>; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; interrupts = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; interrupts = <33>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; interrupts = <34>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; interrupts = <35>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = <38>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -859,51 +455,95 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <39>; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <64>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <86>; - clocks = <&ahb_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun4i-a10-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -913,39 +553,39 @@ #size-cells = <0>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <56>; - clocks = <&pll6 0>, <&ahb_gates 25>; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; status = "disabled"; }; - ehci1: usb@01c1c000 { + ehci1: usb@1c1c000 { compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <40>; - clocks = <&ahb_gates 3>; + clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci1: usb@01c1c400 { + ohci1: usb@1c1c400 { compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <65>; - clocks = <&usb_clk 7>, <&ahb_gates 4>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - spi3: spi@01c1f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <50>; - clocks = <&ahb_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; @@ -955,30 +595,39 @@ #size-cells = <0>; }; - intc: interrupt-controller@01c20400 { + ccu: clock@1c20000 { + compatible = "allwinner,sun4i-a10-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun4i-a10-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; - can0_pins_a: can0@0 { + can0_ph_pins: can0-ph-pins { pins = "PH20", "PH21"; function = "can"; }; - emac_pins_a: emac0@0 { + emac_pins: emac0-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", @@ -987,42 +636,42 @@ function = "emac"; }; - i2c0_pins_a: i2c0@0 { + i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins: i2c1-pins { pins = "PB18", "PB19"; function = "i2c1"; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins: i2c2-pins { pins = "PB20", "PB21"; function = "i2c2"; }; - ir0_rx_pins_a: ir0@0 { + ir0_rx_pins: ir0-rx-pin { pins = "PB4"; function = "ir0"; }; - ir0_tx_pins_a: ir0@1 { + ir0_tx_pins: ir0-tx-pin { pins = "PB3"; function = "ir0"; }; - ir1_rx_pins_a: ir1@0 { + ir1_rx_pins: ir1-rx-pin { pins = "PB23"; function = "ir1"; }; - ir1_tx_pins_a: ir1@1 { + ir1_tx_pins: ir1-tx-pin { pins = "PB22"; function = "ir1"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -1030,107 +679,107 @@ bias-pull-up; }; - ps20_pins_a: ps20@0 { + ps2_ch0_pins: ps2-ch0-pins { pins = "PI20", "PI21"; function = "ps2"; }; - ps21_pins_a: ps21@0 { + ps2_ch1_ph_pins: ps2-ch1-ph-pins { pins = "PH12", "PH13"; function = "ps2"; }; - pwm0_pins_a: pwm0@0 { + pwm0_pin: pwm0-pin { pins = "PB2"; function = "pwm"; }; - pwm1_pins_a: pwm1@0 { + pwm1_pin: pwm1-pin { pins = "PI3"; function = "pwm"; }; - spdif_tx_pins_a: spdif@0 { + spdif_tx_pin: spdif-tx-pin { pins = "PB13"; function = "spdif"; bias-pull-up; }; - spi0_pins_a: spi0@0 { + spi0_pi_pins: spi0-pi-pins { pins = "PI11", "PI12", "PI13"; function = "spi0"; }; - spi0_cs0_pins_a: spi0_cs0@0 { + spi0_cs0_pi_pin: spi0-cs0-pi-pin { pins = "PI10"; function = "spi0"; }; - spi1_pins_a: spi1@0 { + spi1_pins: spi1-pins { pins = "PI17", "PI18", "PI19"; function = "spi1"; }; - spi1_cs0_pins_a: spi1_cs0@0 { + spi1_cs0_pin: spi1-cs0-pin { pins = "PI16"; function = "spi1"; }; - spi2_pins_a: spi2@0 { - pins = "PC20", "PC21", "PC22"; + spi2_pb_pins: spi2-pb-pins { + pins = "PB15", "PB16", "PB17"; function = "spi2"; }; - spi2_pins_b: spi2@1 { - pins = "PB15", "PB16", "PB17"; + spi2_pc_pins: spi2-pc-pins { + pins = "PC20", "PC21", "PC22"; function = "spi2"; }; - spi2_cs0_pins_a: spi2_cs0@0 { - pins = "PC19"; + spi2_cs0_pb_pin: spi2-cs0-pb-pin { + pins = "PB14"; function = "spi2"; }; - spi2_cs0_pins_b: spi2_cs0@1 { - pins = "PB14"; + spi2_cs0_pc_pins: spi2-cs0-pc-pin { + pins = "PC19"; function = "spi2"; }; - uart0_pins_a: uart0@0 { + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; - uart0_pins_b: uart0@1 { + uart0_pf_pins: uart0-pf-pins { pins = "PF2", "PF4"; function = "uart0"; }; - uart1_pins_a: uart1@0 { + uart1_pins: uart1-pins { pins = "PA10", "PA11"; function = "uart1"; }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - rtc: rtc@01c20d00 { + rtc: rtc@1c20d00 { compatible = "allwinner,sun4i-a10-rtc"; reg = <0x01c20d00 0x20>; interrupts = <24>; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun4i-a10-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; @@ -1138,12 +787,12 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <13>; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -1151,37 +800,50 @@ status = "disabled"; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = <5>; reg = <0x01c21800 0x40>; status = "disabled"; }; - ir1: ir@01c21c00 { + ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = <6>; reg = <0x01c21c00 0x40>; status = "disabled"; }; - lradc: lradc@01c22800 { + i2s0: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <31>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-codec"; reg = <0x01c22c00 0x40>; interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -1189,150 +851,316 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun4i-a10-ts"; reg = <0x01c25000 0x100>; interrupts = <29>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; + clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; + clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <17>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; + clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <18>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; + clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; - uart6: serial@01c29800 { + uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <19>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 22>; + clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; - uart7: serial@01c29c00 { + uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <20>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 23>; + clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; - ps20: ps2@01c2a000 { + ps20: ps2@1c2a000 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = <62>; - clocks = <&apb1_gates 6>; + clocks = <&ccu CLK_APB1_PS20>; status = "disabled"; }; - ps21: ps2@01c2a400 { + ps21: ps2@1c2a400 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a400 0x400>; interrupts = <63>; - clocks = <&apb1_gates 7>; + clocks = <&ccu CLK_APB1_PS21>; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - can0: can@01c2bc00 { + can0: can@1c2bc00 { compatible = "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; interrupts = <26>; - clocks = <&apb1_gates 4>; + clocks = <&ccu CLK_APB1_CAN>; status = "disabled"; }; + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be1>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 18f25c5e75ae..316cb8b2945b 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -76,14 +76,14 @@ allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - hdmi: hdmi@01c16000 { + soc@1c00000 { + hdmi: hdmi@1c16000 { compatible = "allwinner,sun5i-a10s-hdmi"; reg = <0x01c16000 0x1000>; interrupts = <58>; clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu 9>, - <&ccu 16>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, @@ -111,7 +111,7 @@ }; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; clocks = <&ccu CLK_HOSC>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 38072c7e10e2..4b9af423c6d5 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -114,6 +114,10 @@ status = "okay"; }; +&codec { + status = "okay"; +}; + &ehci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 6436bad94404..4e830f5cb7f1 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -88,8 +88,8 @@ allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - pwm: pwm@01c20e00 { + soc@1c00000 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a13-pwm"; reg = <0x01c20e00 0xc>; clocks = <&ccu CLK_HOSC>; diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index 3eb56cad0cea..ef0b7446a99d 100644 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -54,8 +54,8 @@ allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - pwm: pwm@01c20e00 { + soc@1c00000 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; clocks = <&ccu CLK_HOSC>; @@ -63,7 +63,7 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; @@ -76,7 +76,7 @@ status = "disabled"; }; - i2s0: i2s@01c22400 { + i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 8a4d2277826f..49229b3d5492 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -110,6 +110,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + &lradc { vref-supply = <®_ldo2>; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 98cc00341b00..07f2248ed5f8 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -93,7 +93,7 @@ #size-cells = <1>; ranges; - osc24M: clk@01c20050 { + osc24M: clk@1c20050 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -108,20 +108,20 @@ }; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -135,14 +135,14 @@ status = "disabled"; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -150,7 +150,7 @@ }; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <27>; @@ -158,7 +158,7 @@ #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <37>; @@ -171,7 +171,7 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; @@ -185,7 +185,7 @@ #size-cells = <0>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <11>; @@ -199,7 +199,7 @@ #size-cells = <0>; }; - tve0: tv-encoder@01c0a000 { + tve0: tv-encoder@1c0a000 { compatible = "allwinner,sun4i-a10-tv-encoder"; reg = <0x01c0a000 0x1000>; clocks = <&ccu CLK_AHB_TVE>; @@ -217,7 +217,7 @@ }; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; @@ -226,7 +226,7 @@ status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -234,7 +234,7 @@ #size-cells = <0>; }; - tcon0: lcd-controller@01c0c000 { + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun5i-a13-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <44>; @@ -278,7 +278,7 @@ }; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; @@ -289,7 +289,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; @@ -300,7 +300,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; @@ -311,7 +311,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; clocks = <&ccu CLK_AHB_OTG>; @@ -324,7 +324,7 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4>; @@ -336,7 +336,7 @@ status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <39>; @@ -346,7 +346,7 @@ status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <40>; @@ -356,7 +356,7 @@ status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun5i-a13-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; @@ -365,7 +365,7 @@ clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <12>; @@ -379,7 +379,7 @@ #size-cells = <0>; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; clock-names = "hosc", "losc"; @@ -387,14 +387,14 @@ #reset-cells = <1>; }; - intc: interrupt-controller@01c20400 { + intc: interrupt-controller@1c20400 { compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { reg = <0x01c20800 0x400>; interrupts = <28>; clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; @@ -538,19 +538,19 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&ccu CLK_HOSC>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; clock-names = "apb", "ir"; @@ -559,14 +559,14 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <31>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-codec"; reg = <0x01c22c00 0x40>; @@ -579,19 +579,19 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <29>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <1>; @@ -601,7 +601,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; @@ -611,7 +611,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <3>; @@ -621,7 +621,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <4>; @@ -631,7 +631,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; @@ -641,7 +641,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; @@ -651,7 +651,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; @@ -661,14 +661,14 @@ #size-cells = <0>; }; - timer@01c60000 { + timer@1c60000 { compatible = "allwinner,sun5i-a13-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <82>, <83>; clocks = <&ccu CLK_AHB_HSTIMER>; }; - fe0: display-frontend@01e00000 { + fe0: display-frontend@1e00000 { compatible = "allwinner,sun5i-a13-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <47>; @@ -696,7 +696,7 @@ }; }; - be0: display-backend@01e60000 { + be0: display-backend@1e60000 { compatible = "allwinner,sun5i-a13-display-backend"; reg = <0x01e60000 0x10000>; interrupts = <47>; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 9ecb5f0b3f83..19e382a11297 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -62,6 +62,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vga-connector { compatible = "vga-connector"; @@ -162,6 +173,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index eef072a21acc..72d3fe44ecaf 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -221,7 +221,7 @@ clock-output-names = "gmac_int_tx"; }; - gmac_tx_clk: clk@01c200d0 { + gmac_tx_clk: clk@1c200d0 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c200d0 0x4>; @@ -236,13 +236,13 @@ status = "disabled"; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -251,7 +251,7 @@ #dma-cells = <1>; }; - tcon0: lcd-controller@01c0c000 { + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun6i-a31-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -278,17 +278,28 @@ reg = <0>; remote-endpoint = <&drc0_out_tcon0>; }; + + tcon0_in_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon0>; + }; }; tcon0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; }; }; }; - tcon1: lcd-controller@01c0d000 { + tcon1: lcd-controller@1c0d000 { compatible = "allwinner,sun6i-a31-tcon"; reg = <0x01c0d000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; @@ -311,6 +322,11 @@ #size-cells = <0>; reg = <0>; + tcon1_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon1>; + }; + tcon1_in_drc1: endpoint@1 { reg = <1>; remote-endpoint = <&drc1_out_tcon1>; @@ -321,11 +337,17 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; }; }; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_AHB1_MMC0>, @@ -344,7 +366,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_AHB1_MMC1>, @@ -363,7 +385,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_AHB1_MMC2>, @@ -382,7 +404,7 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; clocks = <&ccu CLK_AHB1_MMC3>, @@ -401,7 +423,50 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun6i-a31-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, + <&ccu CLK_HDMI_DDC>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; + resets = <&ccu RST_AHB1_HDMI>; + reset-names = "ahb"; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + dmas = <&dma 13>, <&dma 13>, <&dma 14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + usb_otg: usb@1c19000 { compatible = "allwinner,sun6i-a31-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_AHB1_OTG>; @@ -414,7 +479,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun6i-a31-usb-phy"; reg = <0x01c19400 0x10>, <0x01c1a800 0x4>, @@ -438,7 +503,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -449,7 +514,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -460,7 +525,7 @@ status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -471,7 +536,7 @@ status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -482,7 +547,7 @@ status = "disabled"; }; - ohci2: usb@01c1c400 { + ohci2: usb@1c1c400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -491,7 +556,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -500,7 +565,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -633,7 +698,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -644,12 +709,12 @@ clocks = <&osc24M>; }; - wdt1: watchdog@01c20ca0 { + wdt1: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-spdif"; reg = <0x01c21000 0x400>; @@ -662,21 +727,47 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; + resets = <&ccu RST_APB1_DAUDIO0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; + resets = <&ccu RST_APB1_DAUDIO1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun6i-a31-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -689,7 +780,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -702,7 +793,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -715,7 +806,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -728,7 +819,7 @@ status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -741,7 +832,7 @@ status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -754,7 +845,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -765,7 +856,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -776,7 +867,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -787,7 +878,7 @@ #size-cells = <0>; }; - i2c3: i2c@01c2b800 { + i2c3: i2c@1c2b800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -798,7 +889,7 @@ #size-cells = <0>; }; - gmac: ethernet@01c30000 { + gmac: ethernet@1c30000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c30000 0x1054>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -815,7 +906,7 @@ #size-cells = <0>; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun6i-a31-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; @@ -826,7 +917,7 @@ reset-names = "ahb"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-codec"; reg = <0x01c22c00 0x400>; @@ -839,7 +930,7 @@ status = "disabled"; }; - timer@01c60000 { + timer@1c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; @@ -851,7 +942,7 @@ resets = <&ccu RST_AHB1_HSTIMER>; }; - spi0: spi@01c68000 { + spi0: spi@1c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -863,7 +954,7 @@ status = "disabled"; }; - spi1: spi@01c69000 { + spi1: spi@1c69000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; @@ -875,7 +966,7 @@ status = "disabled"; }; - spi2: spi@01c6a000 { + spi2: spi@1c6a000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6a000 0x1000>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; @@ -887,7 +978,7 @@ status = "disabled"; }; - spi3: spi@01c6b000 { + spi3: spi@1c6b000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6b000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; @@ -899,7 +990,7 @@ status = "disabled"; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -910,7 +1001,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - fe0: display-frontend@01e00000 { + fe0: display-frontend@1e00000 { compatible = "allwinner,sun6i-a31-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; @@ -942,7 +1033,7 @@ }; }; - fe1: display-frontend@01e20000 { + fe1: display-frontend@1e20000 { compatible = "allwinner,sun6i-a31-display-frontend"; reg = <0x01e20000 0x20000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; @@ -974,7 +1065,7 @@ }; }; - be1: display-backend@01e40000 { + be1: display-backend@1e40000 { compatible = "allwinner,sun6i-a31-display-backend"; reg = <0x01e40000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -1020,7 +1111,7 @@ }; }; - drc1: drc@01e50000 { + drc1: drc@1e50000 { compatible = "allwinner,sun6i-a31-drc"; reg = <0x01e50000 0x10000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; @@ -1053,6 +1144,11 @@ #size-cells = <0>; reg = <1>; + drc1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc1>; + }; + drc1_out_tcon1: endpoint@1 { reg = <1>; remote-endpoint = <&tcon1_in_drc1>; @@ -1061,7 +1157,7 @@ }; }; - be0: display-backend@01e60000 { + be0: display-backend@1e60000 { compatible = "allwinner,sun6i-a31-display-backend"; reg = <0x01e60000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -1107,7 +1203,7 @@ }; }; - drc0: drc@01e70000 { + drc0: drc@1e70000 { compatible = "allwinner,sun6i-a31-drc"; reg = <0x01e70000 0x10000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; @@ -1144,11 +1240,16 @@ reg = <0>; remote-endpoint = <&tcon0_in_drc0>; }; + + drc0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc0>; + }; }; }; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, @@ -1163,7 +1264,7 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - prcm@01f01400 { + prcm@1f01400 { compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; @@ -1215,12 +1316,12 @@ }; }; - cpucfg@01f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; - ir: ir@01f02000 { + ir: ir@1f02000 { compatible = "allwinner,sun5i-a13-ir"; clocks = <&apb0_gates 1>, <&ir_clk>; clock-names = "apb", "ir"; @@ -1230,7 +1331,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun6i-a31-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, @@ -1255,7 +1356,7 @@ }; }; - p2wi: i2c@01f03400 { + p2wi: i2c@1f03400 { compatible = "allwinner,sun6i-a31-p2wi"; reg = <0x01f03400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 4c10123509c4..0cdb38ab3377 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -52,17 +52,42 @@ / { model = "MSI Primo81 tablet"; compatible = "msi,primo81", "allwinner,sun6i-a31s"; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &cpu0 { cpu-supply = <®_dcdc3>; }; +&de { + status = "okay"; +}; + &ehci0 { /* rtl8188etv wifi is connected here */ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { /* pull-ups and device VDDIO use AXP221 DLDO3 */ pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index b3d98222bd81..298476485bb4 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -53,6 +53,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -90,6 +101,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { /* USB 2.0 4 port hub IC */ status = "okay"; @@ -112,6 +127,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index eb55e74232c9..4ed3162e3e5a 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -109,6 +120,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -130,6 +145,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 2a50207618cb..39f43e4eb742 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -91,6 +102,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -111,6 +126,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 852a0aa24dce..8c9bedc602ec 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -126,6 +137,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -146,6 +161,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 004b6ddac813..442f3c755f36 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -98,6 +109,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -173,6 +188,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -241,6 +266,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_ahci_5v { gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 2ce1a9f13a17..edf9c3c6c0d7 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -62,6 +62,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -80,6 +91,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -100,6 +115,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 097bd755764c..ba250189d07f 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -59,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -85,6 +96,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -105,6 +120,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts new file mode 100644 index 000000000000..d99e7b193efe --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts @@ -0,0 +1,70 @@ + /* + * Copyright 2017 Olimex Ltd. + * Stefan Mavrodiev <stefan@olimex.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun7i-a20-olinuxino-micro.dts" + +/ { + model = "Olimex A20-OLinuXino-MICRO-eMMC"; + compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 0b7403e4d687..dffbaa24b3ee 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -66,6 +66,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -92,6 +103,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -102,7 +117,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_pins_mii_a>, <&gmac_txerr>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -112,6 +127,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -229,6 +254,11 @@ }; &pio { + gmac_txerr: gmac_txerr@0 { + pins = "PA17"; + function = "gmac"; + }; + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { pins = "PH11"; function = "gpio_in"; @@ -256,6 +286,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -330,6 +368,10 @@ status = "okay"; }; +&usb_power_supply { + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index 39bc73db72e5..fb591f32252c 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -58,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -90,6 +101,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -110,6 +125,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 96bee776e145..bd0cd3204273 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -46,9 +46,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> - -#include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> +#include <dt-bindings/clock/sun4i-a10-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> / { interrupt-parent = <&gic>; @@ -66,9 +66,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, + <&ccu CLK_HDMI>; status = "disabled"; }; @@ -76,9 +77,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; @@ -86,10 +87,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 5>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, + <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; @@ -102,7 +103,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -181,23 +182,13 @@ #size-cells = <1>; ranges; - osc24M: clk@01c20050 { + osc24M: clk@1c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; + compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc3M: osc3M_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -205,528 +196,6 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll3>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6", - "pll6_div_4"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll7>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll7-2x"; - }; - - pll8: clk@01c20040 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20040 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll8"; - }; - - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&pll6 3>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 3>; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, <21>, - <22>, <23>, <25>, - <28>, <32>, <33>, <34>, - <35>, <36>, <37>, <40>, - <41>, <42>, <43>, - <44>, <45>, <46>, - <47>, <49>, <50>, - <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", - "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", - "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", - "ahb_spi2", "ahb_spi3", "ahb_sata", - "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", - "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_gmac", "ahb_mp", - "ahb_mali"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <8>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_i2s0", "apb0_i2s1", - "apb0_pio", "apb0_ir0", "apb0_ir1", - "apb0_i2s2", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <15>, <16>, <17>, - <18>, <19>, <20>, - <21>, <22>, <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_i2c3", "apb1_can", - "apb1_scr", "apb1_ps20", "apb1_ps21", - "apb1_i2c4", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - i2s0_clk: clk@01c200b8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200b8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s0"; - }; - - ac97_clk: clk@01c200bc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200bc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "ac97"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - keypad_clk: clk@01c200c4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200c4 0x4>; - clocks = <&osc24M>; - clock-output-names = "keypad"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - i2s1_clk: clk@01c200d8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200d8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s1"; - }; - - i2s2_clk: clk@01c200dc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200dc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s2"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; - clock-output-names = "mbus"; - }; - /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will @@ -736,71 +205,50 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: clk@2 { + mii_phy_tx_clk: clk@1 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: clk@3 { + gmac_int_tx_clk: clk@2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; clock-output-names = "gmac_int_tx"; }; - gmac_tx_clk: clk@01c20164 { + gmac_tx_clk: clk@1c20164 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c20164 0x4>; clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; clock-output-names = "gmac_tx"; }; + }; - /* - * Dummy clock used by output clocks - */ - osc24M_32k: clk@1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <750>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc24M_32k"; - }; - clk_out_a: clk@01c201f0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f0 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_a"; - }; - - clk_out_b: clk@01c201f4 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f4 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_b"; - }; + de: display-engine { + compatible = "allwinner,sun7i-a20-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -814,14 +262,14 @@ }; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -829,7 +277,7 @@ }; }; - nmi_intc: interrupt-controller@01c00030 { + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; #interrupt-cells = <2>; @@ -837,19 +285,19 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 13>, <&nand_clk>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; @@ -858,11 +306,11 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -873,11 +321,11 @@ num-cs = <4>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; @@ -888,16 +336,16 @@ num-cs = <1>; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 17>; + clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -905,13 +353,111 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun7i-a20-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun7i-a20-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_AHB_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -922,13 +468,13 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_AHB_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -939,13 +485,13 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_AHB_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -956,13 +502,13 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; + clocks = <&ccu CLK_AHB_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -973,10 +519,10 @@ #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -986,52 +532,97 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun7i-a20-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun7i-a20-hdmi", + "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -1042,39 +633,39 @@ num-cs = <1>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll6 0>, <&ahb_gates 25>; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; status = "disabled"; }; - ehci1: usb@01c1c000 { + ehci1: usb@1c1c000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 3>; + clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci1: usb@01c1c400 { + ohci1: usb@1c1c400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk 7>, <&ahb_gates 4>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - spi3: spi@01c1f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; @@ -1085,11 +676,20 @@ num-cs = <1>; }; - pio: pinctrl@01c20800 { + ccu: clock@1c20000 { + compatible = "allwinner,sun7i-a20-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1324,7 +924,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, @@ -1336,18 +936,18 @@ clocks = <&osc24M>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - rtc: rtc@01c20d00 { + rtc: rtc@1c20d00 { compatible = "allwinner,sun7i-a20-rtc"; reg = <0x01c20d00 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; @@ -1355,12 +955,12 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -1368,30 +968,30 @@ status = "disabled"; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21800 0x40>; status = "disabled"; }; - ir1: ir@01c21c00 { + ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21c00 0x40>; status = "disabled"; }; - i2s1: i2s@01c22000 { + i2s1: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22000 0x400>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 4>, <&i2s1_clk>; + clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 4>, <&dma SUN4I_DMA_NORMAL 4>; @@ -1399,12 +999,12 @@ status = "disabled"; }; - i2s0: i2s@01c22400 { + i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 3>, <&i2s0_clk>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 3>, <&dma SUN4I_DMA_NORMAL 3>; @@ -1412,19 +1012,19 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun7i-a20-codec"; reg = <0x01c22c00 0x40>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -1432,17 +1032,17 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; }; - i2s2: i2s@01c24400 { + i2s2: i2s@1c24400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c24400 0x400>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 8>, <&i2s2_clk>; + clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 6>, <&dma SUN4I_DMA_NORMAL 6>; @@ -1450,179 +1050,179 @@ status = "disabled"; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; + clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; + clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; + clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; + clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; - uart6: serial@01c29800 { + uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 22>; + clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; - uart7: serial@01c29c00 { + uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 23>; + clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; - ps20: ps2@01c2a000 { + ps20: ps2@1c2a000 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 6>; + clocks = <&ccu CLK_APB1_PS20>; status = "disabled"; }; - ps21: ps2@01c2a400 { + ps21: ps2@1c2a400 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a400 0x400>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 7>; + clocks = <&ccu CLK_APB1_PS21>; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c3: i2c@01c2b800 { + i2c3: i2c@1c2b800 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 3>; + clocks = <&ccu CLK_APB1_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - can0: can@01c2bc00 { + can0: can@1c2bc00 { compatible = "allwinner,sun7i-a20-can", "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 4>; + clocks = <&ccu CLK_APB1_CAN>; status = "disabled"; }; - i2c4: i2c@01c2c000 { + i2c4: i2c@1c2c000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 15>; + clocks = <&ccu CLK_APB1_I2C4>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - gmac: ethernet@01c50000 { + gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx_clk>; + clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; snps,pbl = <2>; snps,fixed-burst; @@ -1632,17 +1232,17 @@ #size-cells = <0>; }; - hstimer@01c60000 { + hstimer@1c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 28>; + clocks = <&ccu CLK_AHB_HSTIMER>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -1653,5 +1253,164 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be1>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index ea50dda75adc..971f9be699a7 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -118,13 +118,13 @@ }; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -133,7 +133,7 @@ #dma-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, @@ -152,7 +152,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, @@ -171,7 +171,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, @@ -190,7 +190,7 @@ #size-cells = <0>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; @@ -203,7 +203,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -216,7 +216,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { /* * compatible and address regions get set in * SoC specific dtsi file @@ -233,7 +233,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -244,7 +244,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -255,7 +255,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; @@ -263,7 +263,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ @@ -344,7 +344,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -352,13 +352,13 @@ clocks = <&osc24M>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; }; - pwm: pwm@01c21400 { + pwm: pwm@1c21400 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c21400 0xc>; clocks = <&osc24M>; @@ -366,14 +366,14 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -386,7 +386,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -399,7 +399,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -412,7 +412,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -425,7 +425,7 @@ status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -438,7 +438,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -449,7 +449,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -460,7 +460,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -498,7 +498,7 @@ assigned-clock-rates = <384000000>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -509,7 +509,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, @@ -527,7 +527,7 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - prcm@01f01400 { + prcm@1f01400 { compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; @@ -575,12 +575,12 @@ }; }; - cpucfg@01f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun8i-a23-cpuconfig"; reg = <0x01f01c00 0x300>; }; - r_uart: serial@01f02800 { + r_uart: serial@1f02800 { compatible = "snps,dw-apb-uart"; reg = <0x01f02800 0x400>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -591,7 +591,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -618,7 +618,7 @@ }; }; - r_rsb: rsb@01f03400 { + r_rsb: rsb@1f03400 { compatible = "allwinner,sun8i-a23-rsb"; reg = <0x01f03400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 4d1f929780a8..58e6585b504b 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -49,8 +49,8 @@ reg = <0x40000000 0x40000000>; }; - soc@01c00000 { - codec: codec@01c22c00 { + soc@1c00000 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a23-codec"; reg = <0x01c22c00 0x400>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 22660919bd08..50eb84fa246a 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -203,8 +203,8 @@ }; }; - soc@01c00000 { - tcon0: lcd-controller@01c0c000 { + soc@1c00000 { + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-a33-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -240,7 +240,7 @@ }; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; @@ -250,7 +250,7 @@ reset-names = "ahb"; }; - dai: dai@01c22c00 { + dai: dai@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-i2s"; reg = <0x01c22c00 0x200>; @@ -263,7 +263,7 @@ status = "disabled"; }; - codec: codec@01c22e00 { + codec: codec@1c22e00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; @@ -273,14 +273,14 @@ status = "disabled"; }; - ths: ths@01c25000 { + ths: ths@1c25000 { compatible = "allwinner,sun8i-a33-ths"; reg = <0x01c25000 0x100>; #thermal-sensor-cells = <0>; #io-channel-cells = <0>; }; - fe0: display-frontend@01e00000 { + fe0: display-frontend@1e00000 { compatible = "allwinner,sun8i-a33-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; @@ -308,7 +308,7 @@ }; }; - be0: display-backend@01e60000 { + be0: display-backend@1e60000 { compatible = "allwinner,sun8i-a33-display-backend"; reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; reg-names = "be", "sat"; @@ -350,7 +350,7 @@ }; }; - drc0: drc@01e70000 { + drc0: drc@1e70000 { compatible = "allwinner,sun8i-a33-drc"; reg = <0x01e70000 0x10000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 1f0d60afb25b..5091cecbcd1e 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -43,7 +43,8 @@ /dts-v1/; #include "sun8i-a83t.dtsi" -#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> / { model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; @@ -56,6 +57,26 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reg_usb0_vbus: reg-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; }; &ehci0 { @@ -65,7 +86,7 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ bus-width = <4>; cd-inverted; @@ -75,7 +96,8 @@ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -86,16 +108,6 @@ status = "okay"; }; -®_usb0_vbus { - gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - status = "okay"; -}; - &r_rsb { status = "okay"; @@ -104,6 +116,8 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; }; ac100: codec@e89 { @@ -131,6 +145,113 @@ }; }; +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ephy"; +}; + +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + regulator-name = "vcc-wifi"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 2bafd7e99ef7..6550bf0e594b 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -44,7 +44,6 @@ /dts-v1/; #include "sun8i-a83t.dtsi" -#include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -53,12 +52,34 @@ compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &ehci0 { @@ -68,20 +89,56 @@ /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_sw>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + allwinner,rx-delay-ps = <700>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ cd-inverted; status = "okay"; }; +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -96,6 +153,10 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + fldoin-supply = <®_dcdc5>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; }; ac100: codec@e89 { @@ -123,17 +184,126 @@ }; }; -®_usb1_vbus { - gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + /* schematics says 3.1V but FEX file says 3.3V */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + /* + * This powers both the WiFi/BT module's main power, I/O supply, + * and external pull-ups on all the data lines. It should be set + * to the same voltage as the I/O supply (DCDC1 in this case) to + * avoid any leakage or mismatch. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pd"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; status = "okay"; }; -®_vcc3v0 { - status = "disabled"; +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; }; -®_vcc5v0 { - status = "disabled"; +®_sw { + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-name = "vcc-ephy"; }; &uart0 { diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 716a205c6dbb..6da08cd0e107 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -44,7 +44,6 @@ /dts-v1/; #include "sun8i-a83t.dtsi" -#include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -53,6 +52,7 @@ compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -95,6 +95,26 @@ refclk-frequency = <19200000>; }; + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ + }; + + reg_usb2_vbus: reg-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "On-board SPDIF"; @@ -112,6 +132,17 @@ #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &ehci0 { @@ -124,20 +155,45 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_dldo4>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ cd-inverted; status = "okay"; }; +&mmc1 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_sw>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -152,6 +208,9 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; }; ac100: codec@e89 { @@ -179,22 +238,143 @@ }; }; -®_usb1_vbus { - gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ - status = "okay"; +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + /* + * The schematics say this should be 3.3V, but the FEX file says + * it should be 3V. The latter makes sense, as the WiFi module's + * I/O is indirectly powered from DCDC1, through SW. It is rated + * at 2.98V maximum. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "dp-pwr"; }; -®_usb2_vbus { - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "ephy-io"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ephy"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; status = "okay"; }; -®_vcc3v0 { - status = "disabled"; +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-1"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-2"; +}; + +®_fldo1 { + /* TODO should be handled by USB PHY */ + regulator-always-on; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; }; -®_vcc5v0 { - status = "disabled"; +®_sw { + regulator-name = "vcc-wifi-io"; }; &spdif { diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts new file mode 100644 index 000000000000..511fca491fe8 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -0,0 +1,411 @@ +/* + * Copyright (C) 2017 Touchless Biometric Systems AG + * Tomas Novotny <tomas@novotny.cz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "TBS A711 Tablet"; + compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>; + + brightness-levels = <0 1 2 4 8 16 32 64 128 255>; + default-brightness-level = <9>; + }; + + panel { + compatible = "tbs,a711-panel", "panel-lvds"; + backlight = <&backlight>; + power-supply = <®_sw>; + + width-mm = <153>; + height-mm = <90>; + data-mapping = "vesa-24"; + + panel-timing { + /* 1024x600 @60Hz */ + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hsync-len = <20>; + hfront-porch = <180>; + hback-porch = <160>; + vfront-porch = <12>; + vback-porch = <23>; + vsync-len = <5>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; + + reg_vbat: reg-vbat { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + reg_vmain: reg-vmain { + compatible = "regulator-fixed"; + regulator-name = "vmain"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vbat>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + + /* + * This is actually Bluetooth's clock, but we have to + * hook it up somewheere + */ + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + }; +}; + +&de { + status = "okay"; +}; + +/* + * An USB-2 hub is connected here, which also means we don't need to + * enable the OHCI controller. + */ +&ehci0 { + status = "okay"; +}; + +/* + * There's a modem connected here that needs to be initialised before + * being able to be enumerated. + */ +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + non-removable; + wakeup-source; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pin>; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; + +}; + +#include "axp81x.dtsi" + +®_aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1.8"; +}; + +®_aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-name = "vdd-drampll"; +}; + +®_aldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-name = "vcc-io"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-A"; +}; + +®_dcdc3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-B"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <4200000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-r"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dsi"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-f"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-hsic"; +}; + +®_fldo2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-ctp"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-vb"; + status = "okay"; +}; + +®_sw { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-lcd"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_lvds_pins>; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +/* There's the BT part of the AP6210 connected to that UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus_supply = <®_vmain>; + usb2_vbus_supply = <®_vmain>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index f996bd343e50..7f4955a5fab7 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -45,8 +45,10 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-a83t-ccu.h> +#include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/reset/sun8i-a83t-ccu.h> +#include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun8i-r-ccu.h> / { @@ -54,12 +56,6 @@ #address-cells = <1>; #size-cells = <1>; - aliases { - }; - - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -157,6 +153,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-a83t-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + memory { reg = <0x40000000 0x80000000>; device_type = "memory"; @@ -168,6 +170,44 @@ #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-a83t-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_PLL_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + syscon: syscon@1c00000 { compatible = "allwinner,sun8i-a83t-system-controller", "syscon"; @@ -183,6 +223,39 @@ #dma-cells = <1>; }; + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-a83t-mmc", "allwinner,sun7i-a20-mmc"; @@ -218,6 +291,8 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -242,7 +317,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a83t-musb", "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; @@ -340,6 +415,45 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + emac_rgmii_pins: emac-rgmii-pins { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD11", "PD12", "PD13", "PD14", "PD18", + "PD19", "PD21", "PD22", "PD23"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + i2c0_pins: i2c0-pins { + pins = "PH0", "PH1"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH2", "PH3"; + function = "i2c1"; + }; + + i2c2_ph_pins: i2c2-ph-pins { + pins = "PH4", "PH5"; + function = "i2c2"; + }; + + i2s1_pins: i2s1-pins { + /* I2S1 does not have external MCLK pin */ + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s1"; + }; + + lcd_lvds_pins: lcd-lvds-pins { + pins = "PD18", "PD19", "PD20", "PD21", "PD22", + "PD23", "PD24", "PD25", "PD26", "PD27"; + function = "lvds0"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -348,6 +462,14 @@ bias-pull-up; }; + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", @@ -357,6 +479,11 @@ bias-pull-up; }; + pwm_pin: pwm-pin { + pins = "PD28"; + function = "pwm"; + }; + spdif_tx_pin: spdif-tx-pin { pins = "PE18"; function = "spdif"; @@ -371,6 +498,16 @@ pins = "PF2", "PF4"; function = "uart0"; }; + + uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; }; timer@1c20c00 { @@ -404,7 +541,57 @@ status = "disabled"; }; - uart0: serial@01c28000 { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + resets = <&ccu RST_BUS_I2S0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_pins>; + status = "disabled"; + }; + + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22800 0x400>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma 27>; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "tx"; + status = "disabled"; + }; + + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-a83t-pwm", + "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -415,6 +602,78 @@ status = "disabled"; }; + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x104>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu 13>; + reset-names = "stmmaceth"; + clocks = <&ccu 27>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts new file mode 100644 index 000000000000..112f09c67d67 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* Orange Pi R1 is based on Orange Pi Zero design */ +#include "sun8i-h2-plus-orangepi-zero.dts" + +/ { + model = "Xunlong Orange Pi R1"; + compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; + + /delete-node/ reg_vcc_wifi; + + /* + * Ths pin of this regulator is the same with the Wi-Fi extra + * regulator on the original Zero. However it's used for USB + * Ethernet rather than the Wi-Fi now. + */ + reg_vcc_usb_eth: reg-vcc-usb-ethernet { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-ethernet"; + enable-active-high; + gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; + }; + + aliases { + ethernet1 = &rtl8189etv; + }; +}; + +&ohci1 { + /* + * RTL8152B USB-Ethernet adapter is connected to USB1, + * and it's a USB 2.0 device. So the OHCI1 controller + * can be left disabled. + */ + status = "disabled"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc_usb_eth>; +}; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index b1502df7b509..6713d0f2b3f4 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -56,6 +56,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &xr819; }; @@ -102,6 +104,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index a337af1de322..f1c3f1cc4d97 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -63,7 +64,6 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_bpi_m2p>; pwr_led { label = "bananapi-m2-plus:red:pwr"; @@ -75,7 +75,6 @@ gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&sw_r_bpi_m2p>; sw4 { label = "power"; @@ -97,7 +96,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; - pinctrl-0 = <&wifi_en_bpi_m2p>; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; }; @@ -114,6 +112,23 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -171,23 +186,6 @@ status = "okay"; }; -&r_pio { - pwr_led_bpi_m2p: led_pins@0 { - pins = "PL10"; - function = "gpio_out"; - }; - - sw_r_bpi_m2p: key_pins@0 { - pins = "PL3"; - function = "gpio_in"; - }; - - wifi_en_bpi_m2p: wifi_en_pin { - pins = "PL7"; - function = "gpio_out"; - }; -}; - ®_usb0_vbus { gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts new file mode 100644 index 000000000000..d406571a0dd6 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Libre Computer Board ALL-H3-CC H3"; + compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "librecomputer:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status_led { + label = "librecomputer:blue:status"; + gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + power { + label = "power"; + linux,code = <KEY_POWER>; + gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; + }; + + reg_vcc1v2: vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v0>; + }; + + /* This represents the board's 5V input */ + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_dram: vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + enable-active-high; + }; + + reg_vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc-io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc3v3>; + gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + }; + + reg_vdd_cpux: vdd-cpux { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpux"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_vcc_io>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + /* VBUS on USB ports are always on */ + usb0_vbus-supply = <®_vcc5v0>; + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + usb3_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 8ddd1b2cc097..a6e61915d648 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -45,6 +45,28 @@ / { model = "FriendlyArm NanoPi M1 Plus"; compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; + + aliases { + serial1 = &uart3; + ethernet0 = &emac; + ethernet1 = &sdio_wifi; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; }; &ehci1 { @@ -55,6 +77,48 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + &ohci1 { status = "okay"; }; @@ -62,3 +126,9 @@ &ohci2 { status = "okay"; }; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts index ec63d104b404..c77fbca4f227 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts @@ -45,6 +45,10 @@ / { model = "FriendlyArm NanoPi M1"; compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; }; &ehci1 { @@ -55,6 +59,19 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + &ohci1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 8d2cc6e9a03f..9f33f6fae595 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -46,3 +46,27 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; + +&ehci0 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index c6decee41a27..7646e331bd29 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -81,7 +81,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sw_r_npi>; - k1@0 { + k1 { label = "k1"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -108,19 +108,19 @@ }; &pio { - leds_npi: led_pins@0 { + leds_npi: led_pins { pins = "PA10"; function = "gpio_out"; }; }; &r_pio { - leds_r_npi: led_pins@0 { + leds_r_npi: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_npi: key_pins@0 { + sw_r_npi: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 8ff71b1bb45b..b20be95b49d5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -152,24 +160,24 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3", "PL4"; function = "gpio_in"; }; - wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 { + wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin { pins = "PL7"; function = "gpio_out"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 9b47a0def740..a70a1daf4e2c 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -141,19 +141,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 5fea430e0eb1..82e5d28cd698 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -97,6 +98,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; @@ -116,19 +124,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 8b93f5c781a7..a10281b455f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,6 +53,11 @@ }; }; +&emac { + /* LEDs changed to active high on the plus */ + /delete-property/ allwinner,leds-active-low; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 1a044b17d6c6..d22546df1b82 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -113,6 +114,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -146,19 +154,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 828ae7a526d9..b403e5d787cb 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,10 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; regulator-name = "gmac-3v3"; @@ -74,6 +78,23 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; @@ -92,7 +113,7 @@ }; &pio { - usb3_vbus_pin_a: usb3_vbus_pin@0 { + usb3_vbus_pin_a: usb3_vbus_pin { pins = "PG11"; function = "gpio_out"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 97920b12a944..6dbf7b2e0c13 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -61,3 +61,19 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ }; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..8495deecedad 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -85,6 +85,10 @@ compatible = "allwinner,sun8i-h3-ccu"; }; +&display_clocks { + compatible = "allwinner,sun8i-h3-de2-clk"; +}; + &mmc0 { compatible = "allwinner,sun7i-a20-mmc"; clocks = <&ccu CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts new file mode 100644 index 000000000000..8c5efe2a9881 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Banana Pi BPI-M2-Ultra"; + compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led-green { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + + user-led-blue { + label = "bananapi:blue:user"; + gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi new file mode 100644 index 000000000000..173dcc1652d2 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -0,0 +1,473 @@ +/* + * Copyright 2017 Chen-Yu Tsai <wens@csie.org> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun8i-r40-ccu.h> +#include <dt-bindings/reset/sun8i-r40-ccu.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nmi_intc: interrupt-controller@1c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-r40-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + pinctrl-0 = <&mmc2_pins>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI2>; + resets = <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-r40-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-r40-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pg_pins: mmc1-pg-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC5", "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC24"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB22", "PB23"; + function = "uart0"; + }; + }; + + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + uart6: serial@1c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART6>; + resets = <&ccu RST_BUS_UART6>; + status = "disabled"; + }; + + uart7: serial@1c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART7>; + resets = <&ccu RST_BUS_UART7>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@1c2b800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@1c2c000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2c000 0x400>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3a06dc5b3746..443b083c6adc 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -178,7 +178,7 @@ }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, @@ -197,7 +197,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, @@ -218,7 +218,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, @@ -237,7 +237,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -250,7 +250,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun8i-v3s-usb-phy"; reg = <0x01c19400 0x2c>, <0x01c1a800 0x4>; @@ -264,7 +264,7 @@ #phy-cells = <1>; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -273,14 +273,14 @@ #reset-cells = <1>; }; - rtc: rtc@01c20400 { + rtc: rtc@1c20400 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01c20400 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-v3s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, @@ -324,7 +324,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -332,7 +332,7 @@ clocks = <&osc24M>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; @@ -345,7 +345,7 @@ status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -356,7 +356,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -367,7 +367,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -378,7 +378,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -391,7 +391,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -416,7 +416,7 @@ #size-cells = <0>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x1000>, diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts new file mode 100644 index 000000000000..fe16fc0eb518 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Banana Pi M2 Berry"; + compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + }; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 3741ac71c3d6..4024639aa005 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard4>; green { label = "cubieboard4:green:usr"; @@ -76,7 +74,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; @@ -87,7 +85,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ @@ -97,7 +95,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_cubieboard4>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_dldo1>; vqmmc-supply = <®_cldo3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -130,30 +128,10 @@ clocks = <&ac100_rtc 0>; }; -&pio { - led_pins_cubieboard4: led-pins@0 { - pins = "PH6", "PH17"; - function = "gpio_out"; - }; - - mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 { - pins = "PH18"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &r_ir { status = "okay"; }; -&r_pio { - wifi_en_pin_cubieboard4: wifi_en_pin@0 { - pins = "PL2"; - function = "gpio_out"; - }; -}; - &r_rsb { status = "okay"; @@ -427,6 +405,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 85f1ad670310..a9b807be99a0 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -62,11 +62,8 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_optimus>, <&led_r_pins_optimus>; /* The LED names match those found on the board */ - led2 { label = "optimus:led2:usr"; gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; @@ -86,8 +83,6 @@ reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_optimus>; - regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; @@ -97,15 +92,13 @@ reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_pin_optimus>; - regulator-name = "usb3-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; @@ -129,7 +122,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */ @@ -139,7 +132,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_optimus>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_dldo1>; vqmmc-supply = <®_cldo3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -180,45 +173,10 @@ clocks = <&ac100_rtc 0>; }; -&pio { - led_pins_optimus: led-pins@0 { - pins = "PH0", "PH1"; - function = "gpio_out"; - }; - - mmc0_cd_pin_optimus: mmc0_cd_pin@0 { - pins = "PH18"; - function = "gpio_in"; - bias-pull-up; - }; - - usb1_vbus_pin_optimus: usb1_vbus_pin@1 { - pins = "PH4"; - function = "gpio_out"; - }; - - usb3_vbus_pin_optimus: usb3_vbus_pin@1 { - pins = "PH5"; - function = "gpio_out"; - }; -}; - &r_ir { status = "okay"; }; -&r_pio { - led_r_pins_optimus: led-pins@1 { - pins = "PM15"; - function = "gpio_out"; - }; - - wifi_en_pin_optimus: wifi_en_pin@0 { - pins = "PL2"; - function = "gpio_out"; - }; -}; - &r_rsb { status = "okay"; @@ -492,7 +450,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 759a72317eb8..90eac0b2a193 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -42,8 +42,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton64.dtsi" - #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun9i-a80-ccu.h> @@ -54,6 +52,8 @@ #include <dt-bindings/reset/sun9i-a80-usb.h> / { + #address-cells = <2>; + #size-cells = <2>; interrupt-parent = <&gic>; cpus { @@ -109,11 +109,6 @@ }; }; - memory { - /* 8GB max. with LPAE */ - reg = <0 0x20000000 0x02 0>; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -144,7 +139,7 @@ * would also throw all the PLL clock rates off, or just the * downstream clocks in the PRCM. */ - osc24M: osc24M_clk { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -156,7 +151,7 @@ * AC100 codec/RTC chip. This serves as a placeholder for * board dts files to specify the source. */ - osc32k: osc32k_clk { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; @@ -164,7 +159,7 @@ clock-output-names = "osc32k"; }; - cpus_clk: clk@08001410 { + cpus_clk: clk@8001410 { compatible = "allwinner,sun9i-a80-cpus-clk"; reg = <0x08001410 0x4>; #clock-cells = <0>; @@ -174,7 +169,7 @@ clock-output-names = "cpus"; }; - ahbs: ahbs_clk { + ahbs: clk-ahbs { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -183,7 +178,7 @@ clock-output-names = "ahbs"; }; - apbs: clk@0800141c { + apbs: clk@800141c { compatible = "allwinner,sun8i-a23-apb0-clk"; reg = <0x0800141c 0x4>; #clock-cells = <0>; @@ -191,7 +186,7 @@ clock-output-names = "apbs"; }; - apbs_gates: clk@08001428 { + apbs_gates: clk@8001428 { compatible = "allwinner,sun9i-a80-apbs-gates-clk"; reg = <0x08001428 0x4>; #clock-cells = <1>; @@ -212,7 +207,7 @@ "apbs_i2s1", "apbs_twd"; }; - r_1wire_clk: clk@08001450 { + r_1wire_clk: clk@8001450 { reg = <0x08001450 0x4>; #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -220,7 +215,7 @@ clock-output-names = "r_1wire"; }; - r_ir_clk: clk@08001454 { + r_ir_clk: clk@8001454 { reg = <0x08001454 0x4>; #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -239,7 +234,7 @@ */ ranges = <0 0 0 0x20000000>; - ehci0: usb@00a00000 { + ehci0: usb@a00000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a00000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -250,7 +245,7 @@ status = "disabled"; }; - ohci0: usb@00a00400 { + ohci0: usb@a00400 { compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; reg = <0x00a00400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -262,7 +257,7 @@ status = "disabled"; }; - usbphy1: phy@00a00800 { + usbphy1: phy@a00800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a00800 0x4>; clocks = <&usb_clocks CLK_USB0_PHY>; @@ -273,7 +268,7 @@ #phy-cells = <0>; }; - ehci1: usb@00a01000 { + ehci1: usb@a01000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a01000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -284,7 +279,7 @@ status = "disabled"; }; - usbphy2: phy@00a01800 { + usbphy2: phy@a01800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a01800 0x4>; clocks = <&usb_clocks CLK_USB1_HSIC>, @@ -303,7 +298,7 @@ phy_type = "hsic"; }; - ehci2: usb@00a02000 { + ehci2: usb@a02000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a02000 0x100>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; @@ -314,7 +309,7 @@ status = "disabled"; }; - ohci2: usb@00a02400 { + ohci2: usb@a02400 { compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; reg = <0x00a02400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -326,7 +321,7 @@ status = "disabled"; }; - usbphy3: phy@00a02800 { + usbphy3: phy@a02800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a02800 0x4>; clocks = <&usb_clocks CLK_USB2_HSIC>, @@ -343,7 +338,7 @@ #phy-cells = <0>; }; - usb_clocks: clock@00a08000 { + usb_clocks: clock@a08000 { compatible = "allwinner,sun9i-a80-usb-clks"; reg = <0x00a08000 0x8>; clocks = <&ccu CLK_BUS_USB>, <&osc24M>; @@ -352,7 +347,7 @@ #reset-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, @@ -367,7 +362,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c10000 0x1000>; clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, @@ -382,7 +377,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c11000 0x1000>; clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, @@ -397,7 +392,7 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c12000 0x1000>; clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, @@ -412,7 +407,7 @@ #size-cells = <0>; }; - mmc_config_clk: clk@01c13000 { + mmc_config_clk: clk@1c13000 { compatible = "allwinner,sun9i-a80-mmc-config-clk"; reg = <0x01c13000 0x10>; clocks = <&ccu CLK_BUS_MMC>; @@ -425,7 +420,7 @@ "mmc2_config", "mmc3_config"; }; - gic: interrupt-controller@01c41000 { + gic: interrupt-controller@1c41000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c41000 0x1000>, <0x01c42000 0x2000>, @@ -436,7 +431,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - de_clocks: clock@03000000 { + de_clocks: clock@3000000 { compatible = "allwinner,sun9i-a80-de-clks"; reg = <0x03000000 0x30>; clocks = <&ccu CLK_DE>, @@ -450,7 +445,7 @@ #reset-cells = <1>; }; - ccu: clock@06000000 { + ccu: clock@6000000 { compatible = "allwinner,sun9i-a80-ccu"; reg = <0x06000000 0x800>; clocks = <&osc24M>, <&osc32k>; @@ -459,7 +454,7 @@ #reset-cells = <1>; }; - timer@06000c00 { + timer@6000c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x06000c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -472,13 +467,13 @@ clocks = <&osc24M>; }; - wdt: watchdog@06000ca0 { + wdt: watchdog@6000ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x06000ca0 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; }; - pio: pinctrl@06000800 { + pio: pinctrl@6000800 { compatible = "allwinner,sun9i-a80-pinctrl"; reg = <0x06000800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -494,12 +489,12 @@ #size-cells = <0>; #gpio-cells = <3>; - i2c3_pins_a: i2c3@0 { + i2c3_pins: i2c3-pins { pins = "PG10", "PG11"; function = "i2c3"; }; - mmc0_pins: mmc0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1" ,"PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -507,7 +502,7 @@ bias-pull-up; }; - mmc1_pins: mmc1 { + mmc1_pins: mmc1-pins { pins = "PG0", "PG1" ,"PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -515,7 +510,7 @@ bias-pull-up; }; - mmc2_8bit_pins: mmc2_8bit { + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", @@ -525,18 +520,18 @@ bias-pull-up; }; - uart0_pins_a: uart0@0 { + uart0_ph_pins: uart0-ph-pins { pins = "PH12", "PH13"; function = "uart0"; }; - uart4_pins_a: uart4@0 { + uart4_pins: uart4-pins { pins = "PG12", "PG13", "PG14", "PG15"; function = "uart4"; }; }; - uart0: serial@07000000 { + uart0: serial@7000000 { compatible = "snps,dw-apb-uart"; reg = <0x07000000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -547,7 +542,7 @@ status = "disabled"; }; - uart1: serial@07000400 { + uart1: serial@7000400 { compatible = "snps,dw-apb-uart"; reg = <0x07000400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -558,7 +553,7 @@ status = "disabled"; }; - uart2: serial@07000800 { + uart2: serial@7000800 { compatible = "snps,dw-apb-uart"; reg = <0x07000800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -569,7 +564,7 @@ status = "disabled"; }; - uart3: serial@07000c00 { + uart3: serial@7000c00 { compatible = "snps,dw-apb-uart"; reg = <0x07000c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -580,7 +575,7 @@ status = "disabled"; }; - uart4: serial@07001000 { + uart4: serial@7001000 { compatible = "snps,dw-apb-uart"; reg = <0x07001000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -591,7 +586,7 @@ status = "disabled"; }; - uart5: serial@07001400 { + uart5: serial@7001400 { compatible = "snps,dw-apb-uart"; reg = <0x07001400 0x400>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -602,7 +597,7 @@ status = "disabled"; }; - i2c0: i2c@07002800 { + i2c0: i2c@7002800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002800 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -613,7 +608,7 @@ #size-cells = <0>; }; - i2c1: i2c@07002c00 { + i2c1: i2c@7002c00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002c00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -624,7 +619,7 @@ #size-cells = <0>; }; - i2c2: i2c@07003000 { + i2c2: i2c@7003000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003000 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -635,7 +630,7 @@ #size-cells = <0>; }; - i2c3: i2c@07003400 { + i2c3: i2c@7003400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003400 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -646,7 +641,7 @@ #size-cells = <0>; }; - i2c4: i2c@07003800 { + i2c4: i2c@7003800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003800 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -657,19 +652,19 @@ #size-cells = <0>; }; - r_wdt: watchdog@08001000 { + r_wdt: watchdog@8001000 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x08001000 0x20>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; }; - apbs_rst: reset@080014b0 { + apbs_rst: reset@80014b0 { reg = <0x080014b0 0x4>; compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; }; - nmi_intc: interrupt-controller@080015a0 { + nmi_intc: interrupt-controller@80015a0 { compatible = "allwinner,sun9i-a80-nmi"; interrupt-controller; #interrupt-cells = <2>; @@ -677,7 +672,7 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - r_ir: ir@08002000 { + r_ir: ir@8002000 { compatible = "allwinner,sun5i-a13-ir"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; @@ -689,7 +684,7 @@ status = "disabled"; }; - r_uart: serial@08002800 { + r_uart: serial@8002800 { compatible = "snps,dw-apb-uart"; reg = <0x08002800 0x400>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -700,7 +695,7 @@ status = "disabled"; }; - r_pio: pinctrl@08002c00 { + r_pio: pinctrl@8002c00 { compatible = "allwinner,sun9i-a80-r-pinctrl"; reg = <0x08002c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, @@ -713,12 +708,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - r_ir_pins: r_ir { + r_ir_pins: r-ir-pins { pins = "PL6"; function = "s_cir_rx"; }; - r_rsb_pins: r_rsb { + r_rsb_pins: r-rsb-pins { pins = "PN0", "PN1"; function = "s_rsb"; drive-strength = <20>; @@ -726,7 +721,7 @@ }; }; - r_rsb: i2c@08003400 { + r_rsb: i2c@8003400 { compatible = "allwinner,sun8i-a23-rsb"; reg = <0x08003400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 11240a8313c2..7a83b15225c7 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -40,9 +40,11 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun8i-h3-ccu.h> #include <dt-bindings/reset/sun8i-r-ccu.h> @@ -51,6 +53,30 @@ #address-cells = <1>; #size-cells = <1>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0-hdmi"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; + status = "disabled"; + }; + + framebuffer-tve { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-tve"; + clocks = <&display_clocks CLK_MIXER1>, + <&ccu CLK_TVE>; + status = "disabled"; + }; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -85,13 +111,25 @@ #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + syscon: syscon@1c00000 { compatible = "allwinner,sun8i-h3-system-controller", "syscon"; reg = <0x01c00000 0x1000>; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-h3-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -100,7 +138,7 @@ #dma-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c0f000 0x1000>; resets = <&ccu RST_BUS_MMC0>; @@ -111,7 +149,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c10000 0x1000>; resets = <&ccu RST_BUS_MMC1>; @@ -122,7 +160,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c11000 0x1000>; resets = <&ccu RST_BUS_MMC2>; @@ -133,7 +171,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x400>; clocks = <&ccu CLK_BUS_OTG>; @@ -146,7 +184,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, <0x01c1a800 0x4>, @@ -178,7 +216,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -187,7 +225,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -197,7 +235,7 @@ status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -208,7 +246,7 @@ status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -220,7 +258,7 @@ status = "disabled"; }; - ehci2: usb@01c1c000 { + ehci2: usb@1c1c000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; @@ -231,7 +269,7 @@ status = "disabled"; }; - ohci2: usb@01c1c400 { + ohci2: usb@1c1c400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -243,7 +281,7 @@ status = "disabled"; }; - ehci3: usb@01c1d000 { + ehci3: usb@1c1d000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1d000 0x100>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; @@ -254,7 +292,7 @@ status = "disabled"; }; - ohci3: usb@01c1d400 { + ohci3: usb@1c1d400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1d400 0x100>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; @@ -266,7 +304,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -275,7 +313,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -310,7 +348,7 @@ function = "i2c2"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins_a: mmc0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -318,13 +356,13 @@ bias-pull-up; }; - mmc0_cd_pin: mmc0_cd_pin@0 { + mmc0_cd_pin: mmc0_cd_pin { pins = "PF6"; function = "gpio_in"; bias-pull-up; }; - mmc1_pins_a: mmc1@0 { + mmc1_pins_a: mmc1 { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -342,7 +380,7 @@ bias-pull-up; }; - spdif_tx_pins_a: spdif@0 { + spdif_tx_pins_a: spdif { pins = "PA17"; function = "spdif"; }; @@ -357,7 +395,7 @@ function = "spi1"; }; - uart0_pins_a: uart0@0 { + uart0_pins_a: uart0 { pins = "PA4", "PA5"; function = "uart0"; }; @@ -381,9 +419,14 @@ pins = "PA13", "PA14"; function = "uart3"; }; + + uart3_rts_cts_pins: uart3_rts_cts { + pins = "PA15", "PA16"; + function = "uart3"; + }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -391,7 +434,56 @@ clocks = <&osc24M>; }; - spi0: spi@01c68000 { + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -407,7 +499,7 @@ #size-cells = <0>; }; - spi1: spi@01c69000 { + spi1: spi@1c69000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; @@ -423,13 +515,13 @@ #size-cells = <0>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-spdif"; reg = <0x01c21000 0x400>; @@ -442,7 +534,7 @@ status = "disabled"; }; - pwm: pwm@01c21400 { + pwm: pwm@1c21400 { compatible = "allwinner,sun8i-h3-pwm"; reg = <0x01c21400 0x8>; clocks = <&osc24M>; @@ -450,7 +542,33 @@ status = "disabled"; }; - codec: codec@01c22c00 { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + resets = <&ccu RST_BUS_I2S0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-codec"; reg = <0x01c22c00 0x400>; @@ -464,7 +582,7 @@ status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -477,7 +595,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -490,7 +608,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -503,7 +621,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -516,7 +634,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -529,7 +647,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -542,9 +660,9 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; + reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; @@ -555,7 +673,7 @@ #size-cells = <0>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -566,7 +684,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, @@ -583,12 +701,12 @@ #reset-cells = <1>; }; - codec_analog: codec-analog@01f015c0 { + codec_analog: codec-analog@1f015c0 { compatible = "allwinner,sun8i-h3-codec-analog"; reg = <0x01f015c0 0x4>; }; - ir: ir@01f02000 { + ir: ir@1f02000 { compatible = "allwinner,sun5i-a13-ir"; clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; @@ -598,7 +716,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -609,7 +727,7 @@ interrupt-controller; #interrupt-cells = <3>; - ir_pins_a: ir@0 { + ir_pins_a: ir { pins = "PL11"; function = "s_cir_rx"; }; diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi index 2565d5137a17..ddf4e722ea93 100644 --- a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi +++ b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi @@ -65,8 +65,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -75,8 +73,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi index 12ab6e0c0331..ff72a8efb73d 100644 --- a/arch/arm/boot/dts/tango4-common.dtsi +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -156,11 +156,10 @@ reg = <0x6e000 0x400>; ranges = <0 0x6e000 0x400>; interrupt-parent = <&gic>; - interrupt-controller; #address-cells = <1>; #size-cells = <1>; - irq0: irq0@000 { + irq0: irq0@0 { reg = <0x000 0x100>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e8e777b8ef1b..d112f85e66ed 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -68,6 +68,10 @@ }; }; + cec@70015000 { + status = "okay"; + }; + gpu@0,57000000 { /* * Node left disabled on purpose - the bootloader will enable diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a7e43dcbf744..174092bfac90 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -125,7 +125,7 @@ nvidia,head = <1>; }; - hdmi@54280000 { + hdmi: hdmi@54280000 { compatible = "nvidia,tegra124-hdmi"; reg = <0x0 0x54280000 0x0 0x00040000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -853,6 +853,16 @@ status = "disabled"; }; + cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x0 0x70015000 0x0 0x00001000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + hdmi-phandle = <&hdmi>; + }; + soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 914f59166a99..864a95872b8d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -10,6 +10,19 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; + iram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: vde { + reg = <0x400 0x3fc00>; + pool; + }; + }; + host1x@50000000 { compatible = "nvidia,tegra20-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; @@ -250,6 +263,28 @@ */ }; + vde@6001a000 { + compatible = "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000 /* Syntax Engine */ + 0x6001b000 0x1000 /* Video Bitstream Engine */ + 0x6001c000 0x100 /* Macroblock Engine */ + 0x6001c200 0x100 /* Post-processing Engine */ + 0x6001c400 0x100 /* Motion Compensation Engine */ + 0x6001c600 0x100 /* Transform Engine */ + 0x6001c800 0x100 /* Pixel prediction block */ + 0x6001ca00 0x100 /* Video DMA */ + 0x6001d800 0x300>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&tegra_car 61>; + }; + apbmisc@70000800 { compatible = "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */ diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi index 5d83df4675a1..8e3cf5109f98 100644 --- a/arch/arm/boot/dts/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/tny_a9260_common.dtsi @@ -27,6 +27,18 @@ ahb { apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + dbgu: serial@fffff200 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index 8cf0a9e08571..7b403db4cd34 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -36,6 +36,18 @@ status = "okay"; }; + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + usb1: gadget@fff78000 { atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts index b3aaab354f3e..a3afd0cda42f 100644 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -38,7 +38,7 @@ }; ðsc { - interrupts = <0 49 4>; + interrupts = <1 8>; }; &serial0 { @@ -53,6 +53,14 @@ status = "okay"; }; +&gpio { + xirq1 { + gpio-hog; + gpios = <UNIPHIER_GPIO_IRQ(1) 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 93586faf950f..0459e84d4d8e 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/gpio/uniphier-gpio.h> + / { compatible = "socionext,uniphier-ld4"; #address-cells = <1>; @@ -37,7 +39,7 @@ clock-frequency = <24576000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -71,6 +73,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -81,6 +84,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -91,6 +95,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -101,6 +106,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <136>; + socionext,interrupt-ranges = <0 48 13>, <14 62 2>; }; i2c0: i2c@58400000 { @@ -113,6 +133,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -126,6 +147,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -139,6 +161,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <400000>; }; @@ -152,6 +175,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -213,6 +237,7 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + has-transaction-translator; }; usb1: usb@5a810100 { @@ -226,6 +251,7 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + has-transaction-translator; }; usb2: usb@5a820100 { @@ -239,6 +265,7 @@ <&mio_clk 14>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>; + has-transaction-translator; }; soc-glue@5f800000 { @@ -251,6 +278,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-ld4-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -305,6 +350,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 2188d114d79b..811b999800ed 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -40,7 +40,7 @@ }; ðsc { - interrupts = <0 52 4>; + interrupts = <4 8>; }; &serial0 { @@ -55,6 +55,14 @@ status = "okay"; }; +&gpio { + xirq4 { + gpio-hog; + gpios = <UNIPHIER_GPIO_IRQ(4) 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index be82cddc4072..de481c372467 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -8,117 +8,117 @@ */ &pinctrl { - pinctrl_aout: aout_grp { + pinctrl_aout: aout { groups = "aout"; function = "aout"; }; - pinctrl_emmc: emmc_grp { + pinctrl_emmc: emmc { groups = "emmc", "emmc_dat8"; function = "emmc"; }; - pinctrl_ether_mii: ether_mii_grp { + pinctrl_ether_mii: ether-mii { groups = "ether_mii"; function = "ether_mii"; }; - pinctrl_ether_rgmii: ether_rgmii_grp { + pinctrl_ether_rgmii: ether-rgmii { groups = "ether_rgmii"; function = "ether_rgmii"; }; - pinctrl_ether_rmii: ether_rmii_grp { + pinctrl_ether_rmii: ether-rmii { groups = "ether_rmii"; function = "ether_rmii"; }; - pinctrl_i2c0: i2c0_grp { + pinctrl_i2c0: i2c0 { groups = "i2c0"; function = "i2c0"; }; - pinctrl_i2c1: i2c1_grp { + pinctrl_i2c1: i2c1 { groups = "i2c1"; function = "i2c1"; }; - pinctrl_i2c2: i2c2_grp { + pinctrl_i2c2: i2c2 { groups = "i2c2"; function = "i2c2"; }; - pinctrl_i2c3: i2c3_grp { + pinctrl_i2c3: i2c3 { groups = "i2c3"; function = "i2c3"; }; - pinctrl_i2c4: i2c4_grp { + pinctrl_i2c4: i2c4 { groups = "i2c4"; function = "i2c4"; }; - pinctrl_nand: nand_grp { + pinctrl_nand: nand { groups = "nand"; function = "nand"; }; - pinctrl_nand2cs: nand2cs_grp { + pinctrl_nand2cs: nand2cs { groups = "nand", "nand_cs1"; function = "nand"; }; - pinctrl_sd: sd_grp { + pinctrl_sd: sd { groups = "sd"; function = "sd"; }; - pinctrl_sd1: sd1_grp { + pinctrl_sd1: sd1 { groups = "sd1"; function = "sd1"; }; - pinctrl_system_bus: system_bus_grp { + pinctrl_system_bus: system-bus { groups = "system_bus", "system_bus_cs1"; function = "system_bus"; }; - pinctrl_uart0: uart0_grp { + pinctrl_uart0: uart0 { groups = "uart0"; function = "uart0"; }; - pinctrl_uart1: uart1_grp { + pinctrl_uart1: uart1 { groups = "uart1"; function = "uart1"; }; - pinctrl_uart2: uart2_grp { + pinctrl_uart2: uart2 { groups = "uart2"; function = "uart2"; }; - pinctrl_uart3: uart3_grp { + pinctrl_uart3: uart3 { groups = "uart3"; function = "uart3"; }; - pinctrl_usb0: usb0_grp { + pinctrl_usb0: usb0 { groups = "usb0"; function = "usb0"; }; - pinctrl_usb1: usb1_grp { + pinctrl_usb1: usb1 { groups = "usb1"; function = "usb1"; }; - pinctrl_usb2: usb2_grp { + pinctrl_usb2: usb2 { groups = "usb2"; function = "usb2"; }; - pinctrl_usb3: usb3_grp { + pinctrl_usb3: usb3 { groups = "usb3"; function = "usb3"; }; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 903df6348e77..6a004e5cf786 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -40,7 +40,7 @@ }; ðsc { - interrupts = <0 50 4>; + interrupts = <2 8>; }; &serial0 { @@ -55,6 +55,14 @@ status = "okay"; }; +&gpio { + xirq2 { + gpio-hog; + gpios = <UNIPHIER_GPIO_IRQ(2) 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 2a9bd7f9f5db..1a29a8619856 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/gpio/uniphier-gpio.h> + / { compatible = "socionext,uniphier-pro4"; #address-cells = <1>; @@ -45,7 +47,7 @@ clock-frequency = <25000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -79,6 +81,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -89,6 +92,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -99,6 +103,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -109,6 +114,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>; }; i2c0: i2c@58780000 { @@ -121,6 +141,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -134,6 +155,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -147,6 +169,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <100000>; }; @@ -160,6 +183,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -173,6 +197,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -184,6 +209,7 @@ #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; clock-frequency = <400000>; }; @@ -245,6 +271,7 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + has-transaction-translator; }; usb3: usb@5a810100 { @@ -258,6 +285,7 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + has-transaction-translator; }; soc-glue@5f800000 { @@ -270,6 +298,29 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-pro4-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x14>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pro4-aidet"; reg = <0x5fc20000 0x200>; @@ -324,6 +375,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index b026bcd42a06..f291dd63de9c 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -37,7 +37,7 @@ }; }; - cpu_opp: opp_table { + cpu_opp: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -119,7 +119,7 @@ clock-frequency = <20000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -166,6 +166,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -176,6 +177,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -186,6 +188,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -196,6 +199,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>; }; i2c0: i2c@58780000 { @@ -208,6 +226,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -221,6 +240,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -234,6 +254,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <100000>; }; @@ -247,6 +268,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -260,6 +282,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -271,6 +294,7 @@ #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; clock-frequency = <400000>; }; @@ -331,6 +355,39 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-pro5-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x28>; + }; + + efuse@300 { + compatible = "socionext,uniphier-efuse"; + reg = <0x300 0x14>; + }; + + efuse@400 { + compatible = "socionext,uniphier-efuse"; + reg = <0x400 0x8>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; @@ -385,6 +442,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 90b020c95083..c083468c17db 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -7,6 +7,9 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/thermal/thermal.h> + / { compatible = "socionext,uniphier-pxs2"; #address-cells = <1>; @@ -16,7 +19,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -24,9 +27,10 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -36,7 +40,7 @@ operating-points-v2 = <&cpu_opp>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; @@ -46,7 +50,7 @@ operating-points-v2 = <&cpu_opp>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; @@ -57,7 +61,7 @@ }; }; - cpu_opp: opp_table { + cpu_opp: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -107,13 +111,42 @@ clock-frequency = <25000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu-crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -141,6 +174,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -151,6 +185,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -161,6 +196,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -171,6 +207,24 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1"; + ngpios = <232>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, + <21 217 3>; }; i2c0: i2c@58780000 { @@ -183,6 +237,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -196,6 +251,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -209,6 +265,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <100000>; }; @@ -222,6 +279,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -233,6 +291,7 @@ #size-cells = <0>; interrupts = <0 45 4>; clocks = <&peri_clk 8>; + resets = <&peri_rst 8>; clock-frequency = <400000>; }; @@ -244,6 +303,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -255,6 +315,7 @@ #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; clock-frequency = <400000>; }; @@ -315,6 +376,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-pxs2-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x58>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pxs2-aidet"; reg = <0x5fc20000 0x200>; @@ -358,6 +437,13 @@ compatible = "socionext,uniphier-pxs2-reset"; #reset-cells = <1>; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-pxs2-thermal"; + interrupts = <0 3 4>; + #thermal-sensor-cells = <0>; + socionext,tmod-calibration = <0x0f86 0x6844>; + }; }; nand: nand@68000000 { @@ -369,6 +455,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts index 5accd3cc76e4..e052ea3b4020 100644 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -38,7 +38,7 @@ }; ðsc { - interrupts = <0 48 4>; + interrupts = <0 8>; }; &serial0 { @@ -53,6 +53,14 @@ status = "okay"; }; +&gpio { + xirq0 { + gpio-hog; + gpios = <UNIPHIER_GPIO_IRQ(0) 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index ebd0c3f63e7f..bc8c24078faa 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/gpio/uniphier-gpio.h> + / { compatible = "socionext,uniphier-sld8"; #address-cells = <1>; @@ -37,7 +39,7 @@ clock-frequency = <25000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -71,6 +73,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -81,6 +84,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -91,6 +95,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -101,6 +106,25 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 104 0 0>, + <&pinctrl 112 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + ngpios = <136>; + socionext,interrupt-ranges = <0 48 13>, <14 62 2>; }; i2c0: i2c@58400000 { @@ -113,6 +137,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -126,6 +151,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -139,6 +165,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <400000>; }; @@ -152,6 +179,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -213,6 +241,7 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + has-transaction-translator; }; usb1: usb@5a810100 { @@ -226,6 +255,7 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + has-transaction-translator; }; usb2: usb@5a820100 { @@ -239,6 +269,7 @@ <&mio_clk 14>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>; + has-transaction-translator; }; soc-glue@5f800000 { @@ -251,6 +282,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-sld8-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x14>; + }; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -305,6 +354,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi index 6c825f192e65..e4e7e1bb9172 100644 --- a/arch/arm/boot/dts/uniphier-support-card.dtsi +++ b/arch/arm/boot/dts/uniphier-support-card.dtsi @@ -11,11 +11,12 @@ status = "okay"; ranges = <1 0x00000000 0x42000000 0x02000000>; - support_card: support_card@1,1f00000 { + support_card: support-card@1,1f00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 1 0x01f00000 0x00100000>; + interrupt-parent = <&gpio>; ethsc: ethernet@0 { compatible = "smsc,lan9118", "smsc,lan9115"; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index 34a49995eda3..de3fa3ab34d6 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -23,6 +23,18 @@ status = "okay"; }; + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + macb0: ethernet@fffc4000 { phy-mode = "rmii"; status = "okay"; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 482381c1c962..0a753b4c74e7 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -36,6 +36,18 @@ status = "okay"; }; + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + macb0: ethernet@fffbc000 { phy-mode = "rmii"; status = "okay"; @@ -128,7 +140,7 @@ }; }; - usb0: ohci@00a00000 { + usb0: ohci@a00000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi index 088c2c3685ab..81c3fe0465d9 100644 --- a/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi @@ -20,8 +20,8 @@ }; i2c-gpio-0 { - rv3029c2@56 { - compatible = "rv3029c2"; + rtc@56 { + compatible = "microcrystal,rv3029"; reg = <0x56>; }; }; diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index 091b738041a0..d8b2972527eb 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -140,7 +140,7 @@ /* M41T0M6 real time clock on carrier board */ rtc: m41t0m6@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index 3d9896171bfc..348bcd30c0f7 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -58,7 +58,7 @@ soc { aips-bus@40000000 { - intc: interrupt-controller@40002000 { + intc: interrupt-controller@40003000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 53e3b8b250c6..6f787e67bd2e 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -198,7 +198,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { #sound-dai-cells = <0>; compatible = "fsl,sgtl5000"; reg = <0x0a>; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index acdf12ad0622..782b69a3acdf 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -255,16 +255,19 @@ port@0 { reg = <0>; label = "lan6"; + phy-handle = <&switch2phy0>; }; port@1 { reg = <1>; label = "lan7"; + phy-handle = <&switch2phy1>; }; port@2 { reg = <2>; label = "lan8"; + phy-handle = <&switch2phy2>; }; port@3 { @@ -304,6 +307,20 @@ }; }; }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch2phy0: phy@0 { + reg = <0>; + }; + switch2phy1: phy@1 { + reg = <1>; + }; + switch2phy2: phy@2 { + reg = <2>; + }; + }; }; }; @@ -371,7 +388,8 @@ reg = <0x22>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&gpio2>; + interrupt-controller; + interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index db3b408ea55a..c6f134c78303 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -73,7 +73,7 @@ #size-cells = <0>; reg = <0>; dsa,member = <0 0>; - eeprom-length = <512>; + eeprom-length = <65536>; interrupt-parent = <&gpio0>; interrupts = <27 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -121,7 +121,7 @@ switch0port10: port@10 { reg = <10>; label = "dsa"; - phy-mode = "xgmii"; + phy-mode = "xaui"; link = <&switch1port10>; }; }; @@ -170,7 +170,7 @@ #size-cells = <0>; reg = <0>; dsa,member = <0 1>; - eeprom-length = <512>; + eeprom-length = <65536>; interrupt-parent = <&gpio0>; interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -208,7 +208,7 @@ switch1port10: port@10 { reg = <10>; label = "dsa"; - phy-mode = "xgmii"; + phy-mode = "xaui"; link = <&switch0port10>; }; }; @@ -359,7 +359,7 @@ }; &i2c1 { - at24mac602@00 { + at24mac602@50 { compatible = "atmel,24c02"; reg = <0x50>; read-only; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 6b58d3a97992..aadd36db0092 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -96,6 +96,10 @@ status = "okay"; }; +&edma1 { + status = "okay"; +}; + &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 5d654b5b4ce6..c3f09b737924 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -84,6 +84,11 @@ mask = <0x1000>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 16>, <&adc1 16>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -762,10 +767,5 @@ status = "disabled"; }; }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 16>, <&adc1 16>; - }; }; }; diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi index 752d28e0f9b0..240e7a23d81f 100644 --- a/arch/arm/boot/dts/zx296702.dtsi +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -38,7 +38,7 @@ reg = <0x00400000 0x1000>; }; - intc: interrupt-controller@00801000 { + intc: interrupt-controller@801000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <1>; @@ -48,7 +48,7 @@ <0x00800100 0x100>; }; - global_timer: timer@008000200 { + global_timer: timer@8000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x00800200 0x20>; interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; @@ -56,7 +56,7 @@ clocks = <&topclk ZX296702_A9_PERIPHCLK>; }; - l2cc: l2-cache-controller@0x00c00000 { + l2cc: l2-cache-controller@c00000 { compatible = "arm,pl310-cache"; reg = <0x00c00000 0x1000>; cache-unified; @@ -67,30 +67,30 @@ arm,double-linefill-incr = <0>; }; - pcu: pcu@0xa0008000 { + pcu: pcu@a0008000 { compatible = "zte,zx296702-pcu"; reg = <0xa0008000 0x1000>; }; - topclk: topclk@0x09800000 { + topclk: topclk@9800000 { compatible = "zte,zx296702-topcrm-clk"; reg = <0x09800000 0x1000>; #clock-cells = <1>; }; - lsp1clk: lsp1clk@0x09400000 { + lsp1clk: lsp1clk@9400000 { compatible = "zte,zx296702-lsp1crpm-clk"; reg = <0x09400000 0x1000>; #clock-cells = <1>; }; - lsp0clk: lsp0clk@0x0b000000 { + lsp0clk: lsp0clk@b000000 { compatible = "zte,zx296702-lsp0crpm-clk"; reg = <0x0b000000 0x1000>; #clock-cells = <1>; }; - uart0: serial@0x09405000 { + uart0: serial@9405000 { compatible = "zte,zx296702-uart"; reg = <0x09405000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -98,7 +98,7 @@ status = "disabled"; }; - uart1: serial@0x09406000 { + uart1: serial@9406000 { compatible = "zte,zx296702-uart"; reg = <0x09406000 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -106,7 +106,7 @@ status = "disabled"; }; - mmc0: mmc@0x09408000 { + mmc0: mmc@9408000 { compatible = "snps,dw-mshc"; #address-cells = <1>; #size-cells = <0>; @@ -119,7 +119,7 @@ status = "disabled"; }; - mmc1: mmc@0x0b003000 { + mmc1: mmc@b003000 { compatible = "snps,dw-mshc"; #address-cells = <1>; #size-cells = <0>; @@ -132,7 +132,7 @@ status = "disabled"; }; - sysctrl: sysctrl@0xa0007000 { + sysctrl: sysctrl@a0007000 { compatible = "zte,sysctrl", "syscon"; reg = <0xa0007000 0x1000>; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 34e8277fce0d..70a5de76b7db 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -152,7 +152,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 7ebc8c5ae39d..cdc326ec3335 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -108,7 +108,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; |