diff options
Diffstat (limited to 'arch/mips/sibyte/bcm1480')
| -rw-r--r-- | arch/mips/sibyte/bcm1480/Makefile | 2 | ||||
| -rw-r--r-- | arch/mips/sibyte/bcm1480/irq.c | 6 | ||||
| -rw-r--r-- | arch/mips/sibyte/bcm1480/setup.c | 10 | ||||
| -rw-r--r-- | arch/mips/sibyte/bcm1480/smp.c | 6 |
4 files changed, 11 insertions, 13 deletions
diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile index 7b36ff3873b7..cdc4c56c3e29 100644 --- a/arch/mips/sibyte/bcm1480/Makefile +++ b/arch/mips/sibyte/bcm1480/Makefile @@ -1,5 +1,3 @@ obj-y := setup.o irq.o time.o obj-$(CONFIG_SMP) += smp.o - -EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 1dc5d05d8962..ba0c4b776c85 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -141,11 +141,11 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask) unsigned long flags; unsigned int irq_dirty; - i = first_cpu(mask); - if (next_cpu(i, mask) <= NR_CPUS) { + if (cpus_weight(mask) != 1) { printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); return; } + i = first_cpu(mask); /* Convert logical CPU to physical CPU */ cpu = cpu_logical_map(i); @@ -420,7 +420,7 @@ void __init arch_init_irq(void) #ifdef CONFIG_GDB_CONSOLE register_gdb_console(); #endif - prom_printf("Waiting for GDB on UART port %d\n", kgdb_port); + printk("Waiting for GDB on UART port %d\n", kgdb_port); set_debug_traps(); breakpoint(); } diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c index 8236d0c48542..bdaac34ae708 100644 --- a/arch/mips/sibyte/bcm1480/setup.c +++ b/arch/mips/sibyte/bcm1480/setup.c @@ -69,7 +69,7 @@ static inline int sys_rev_decode(void) break; default: - prom_printf("Unknown part type %x\n", part_type); + printk("Unknown part type %x\n", part_type); ret = 1; break; } @@ -102,7 +102,7 @@ static inline int setup_bcm1x80_bcm1x55(void) pass_str = "B0 (pass2)"; break; default: - prom_printf("Unknown %s rev %x\n", soc_str, soc_pass); + printk("Unknown %s rev %x\n", soc_str, soc_pass); periph_rev = 1; pass_str = "Unknown Revision"; break; @@ -122,14 +122,14 @@ void bcm1480_setup(void) soc_pass = G_SYS_REVISION(sys_rev); if (sys_rev_decode()) { - prom_printf("Restart after failure to identify SiByte chip\n"); + printk("Restart after failure to identify SiByte chip\n"); machine_restart(NULL); } plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); - prom_printf("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n", + printk("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n", soc_str, pass_str, zbbus_mhz * 2, sb1_pass); - prom_printf("Board type: %s\n", get_system_type()); + printk("Board type: %s\n", get_system_type()); } diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c index bf328277c775..6eac36d1b8c8 100644 --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void); * independent of board/firmware */ -static volatile void *mailbox_0_set_regs[] = { +static void *mailbox_0_set_regs[] = { IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), }; -static volatile void *mailbox_0_clear_regs[] = { +static void *mailbox_0_clear_regs[] = { IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), }; -static volatile void *mailbox_0_regs[] = { +static void *mailbox_0_regs[] = { IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |