diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 48 |
1 files changed, 46 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index f98aba308028..915a20461c77 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -133,6 +133,8 @@ type OTG_DROP_PIXEL[MAX_PIPES]; #define DCCG3_REG_FIELD_LIST(type) \ + type HDMICHARCLK0_EN;\ + type HDMICHARCLK0_SRC_SEL;\ type PHYASYMCLK_FORCE_EN;\ type PHYASYMCLK_FORCE_SRC_SEL;\ type PHYBSYMCLK_FORCE_EN;\ @@ -183,26 +185,65 @@ type SYMCLK32_ROOT_SE1_GATE_DISABLE;\ type SYMCLK32_ROOT_SE2_GATE_DISABLE;\ type SYMCLK32_ROOT_SE3_GATE_DISABLE;\ + type SYMCLK32_SE0_GATE_DISABLE;\ + type SYMCLK32_SE1_GATE_DISABLE;\ + type SYMCLK32_SE2_GATE_DISABLE;\ + type SYMCLK32_SE3_GATE_DISABLE;\ type SYMCLK32_ROOT_LE0_GATE_DISABLE;\ type SYMCLK32_ROOT_LE1_GATE_DISABLE;\ + type SYMCLK32_LE0_GATE_DISABLE;\ + type SYMCLK32_LE1_GATE_DISABLE;\ type DPSTREAMCLK_ROOT_GATE_DISABLE;\ type DPSTREAMCLK_GATE_DISABLE;\ type HDMISTREAMCLK0_DTO_PHASE;\ type HDMISTREAMCLK0_DTO_MODULO;\ type HDMICHARCLK0_GATE_DISABLE;\ - type HDMICHARCLK0_ROOT_GATE_DISABLE; + type HDMICHARCLK0_ROOT_GATE_DISABLE; \ + type PHYASYMCLK_GATE_DISABLE; \ + type PHYBSYMCLK_GATE_DISABLE; \ + type PHYCSYMCLK_GATE_DISABLE; \ + type PHYDSYMCLK_GATE_DISABLE; \ + type PHYESYMCLK_GATE_DISABLE; +#define DCCG32_REG_FIELD_LIST(type) \ + type DPSTREAMCLK0_EN;\ + type DPSTREAMCLK1_EN;\ + type DPSTREAMCLK2_EN;\ + type DPSTREAMCLK3_EN;\ + type DPSTREAMCLK0_SRC_SEL;\ + type DPSTREAMCLK1_SRC_SEL;\ + type DPSTREAMCLK2_SRC_SEL;\ + type DPSTREAMCLK3_SRC_SEL;\ + type HDMISTREAMCLK0_EN;\ + type OTG0_PIXEL_RATE_DIVK1;\ + type OTG0_PIXEL_RATE_DIVK2;\ + type OTG1_PIXEL_RATE_DIVK1;\ + type OTG1_PIXEL_RATE_DIVK2;\ + type OTG2_PIXEL_RATE_DIVK1;\ + type OTG2_PIXEL_RATE_DIVK2;\ + type OTG3_PIXEL_RATE_DIVK1;\ + type OTG3_PIXEL_RATE_DIVK2;\ + type DTBCLK_P0_SRC_SEL;\ + type DTBCLK_P0_EN;\ + type DTBCLK_P1_SRC_SEL;\ + type DTBCLK_P1_EN;\ + type DTBCLK_P2_SRC_SEL;\ + type DTBCLK_P2_EN;\ + type DTBCLK_P3_SRC_SEL;\ + type DTBCLK_P3_EN; struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) DCCG3_REG_FIELD_LIST(uint8_t) DCCG31_REG_FIELD_LIST(uint8_t) + DCCG32_REG_FIELD_LIST(uint8_t) }; struct dccg_mask { DCCG_REG_FIELD_LIST(uint32_t) DCCG3_REG_FIELD_LIST(uint32_t) DCCG31_REG_FIELD_LIST(uint32_t) + DCCG32_REG_FIELD_LIST(uint32_t) }; struct dccg_registers { @@ -233,10 +274,13 @@ struct dccg_registers { uint32_t DSCCLK2_DTO_PARAM; uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; uint32_t DPSTREAMCLK_GATE_DISABLE; + uint32_t DCCG_GATE_DISABLE_CNTL; + uint32_t DCCG_GATE_DISABLE_CNTL2; uint32_t DCCG_GATE_DISABLE_CNTL3; uint32_t HDMISTREAMCLK0_DTO_PARAM; uint32_t DCCG_GATE_DISABLE_CNTL4; - + uint32_t OTG_PIXEL_RATE_DIV; + uint32_t DTBCLK_P_CNTL; }; struct dcn_dccg { |