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path: root/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c21
1 files changed, 18 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
index 368f2a0042ff..bccf7acb7f98 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
@@ -28,8 +28,16 @@
#include <nvfw/flcn.h>
#include <nvfw/sec2.h>
+int
+gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver,
+ const struct nvkm_sec2_fwif *fwif)
+{
+ nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n");
+ return 0;
+}
+
static int
-gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nv_falcon_msg *hdr)
+gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
{
struct nv_sec2_acr_bootstrap_falcon_msg *msg =
container_of(hdr, typeof(*msg), msg.hdr);
@@ -115,6 +123,9 @@ gp102_sec2_acr_0 = {
.bld_write = gp102_sec2_acr_bld_write,
.bld_patch = gp102_sec2_acr_bld_patch,
.boot = gp102_sec2_acr_boot,
+ .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
+ BIT_ULL(NVKM_ACR_LSF_GPCCS) |
+ BIT_ULL(NVKM_ACR_LSF_SEC2),
.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
};
@@ -294,6 +305,9 @@ gp102_sec2_acr_1 = {
.bld_write = gp102_sec2_acr_bld_write_1,
.bld_patch = gp102_sec2_acr_bld_patch_1,
.boot = gp102_sec2_acr_boot,
+ .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
+ BIT_ULL(NVKM_ACR_LSF_GPCCS) |
+ BIT_ULL(NVKM_ACR_LSF_SEC2),
.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
};
@@ -322,8 +336,9 @@ MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin");
static const struct nvkm_sec2_fwif
gp102_sec2_fwif[] = {
- { 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 },
- { 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 },
+ { 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 },
+ { 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 },
+ { -1, gp102_sec2_nofw, &gp102_sec2 },
{}
};