diff options
Diffstat (limited to 'drivers/misc/habanalabs')
125 files changed, 50785 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/Kconfig b/drivers/misc/habanalabs/Kconfig new file mode 100644 index 000000000000..99db2b82ada6 --- /dev/null +++ b/drivers/misc/habanalabs/Kconfig @@ -0,0 +1,25 @@ +# +# HabanaLabs AI accelerators driver +# + +config HABANA_AI + tristate "HabanaAI accelerators (habanalabs)" + depends on PCI && HAS_IOMEM + select FRAME_VECTOR + select DMA_SHARED_BUFFER + select GENERIC_ALLOCATOR + select HWMON + help + Enables PCIe card driver for Habana's AI Processors (AIP) that are + designed to accelerate Deep Learning inference and training workloads. + + The driver manages the PCIe devices and provides IOCTL interface for + the user to submit workloads to the devices. + + The user-space interface is described in + include/uapi/misc/habanalabs.h + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called habanalabs. diff --git a/drivers/misc/habanalabs/Makefile b/drivers/misc/habanalabs/Makefile new file mode 100644 index 000000000000..c6592db59b25 --- /dev/null +++ b/drivers/misc/habanalabs/Makefile @@ -0,0 +1,14 @@ +# +# Makefile for HabanaLabs AI accelerators driver +# + +obj-m := habanalabs.o + +habanalabs-y := habanalabs_drv.o device.o context.o asid.o habanalabs_ioctl.o \ + command_buffer.o hw_queue.o irq.o sysfs.o hwmon.o memory.o \ + command_submission.o mmu.o + +habanalabs-$(CONFIG_DEBUG_FS) += debugfs.o + +include $(src)/goya/Makefile +habanalabs-y += $(HL_GOYA_FILES) diff --git a/drivers/misc/habanalabs/asid.c b/drivers/misc/habanalabs/asid.c new file mode 100644 index 000000000000..f54e7971a762 --- /dev/null +++ b/drivers/misc/habanalabs/asid.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#include <linux/slab.h> + +int hl_asid_init(struct hl_device *hdev) +{ + hdev->asid_bitmap = kcalloc(BITS_TO_LONGS(hdev->asic_prop.max_asid), + sizeof(*hdev->asid_bitmap), GFP_KERNEL); + if (!hdev->asid_bitmap) + return -ENOMEM; + + mutex_init(&hdev->asid_mutex); + + /* ASID 0 is reserved for KMD */ + set_bit(0, hdev->asid_bitmap); + + return 0; +} + +void hl_asid_fini(struct hl_device *hdev) +{ + mutex_destroy(&hdev->asid_mutex); + kfree(hdev->asid_bitmap); +} + +unsigned long hl_asid_alloc(struct hl_device *hdev) +{ + unsigned long found; + + mutex_lock(&hdev->asid_mutex); + + found = find_first_zero_bit(hdev->asid_bitmap, + hdev->asic_prop.max_asid); + if (found == hdev->asic_prop.max_asid) + found = 0; + else + set_bit(found, hdev->asid_bitmap); + + mutex_unlock(&hdev->asid_mutex); + + return found; +} + +void hl_asid_free(struct hl_device *hdev, unsigned long asid) +{ + if (WARN((asid == 0 || asid >= hdev->asic_prop.max_asid), + "Invalid ASID %lu", asid)) + return; + clear_bit(asid, hdev->asid_bitmap); +} diff --git a/drivers/misc/habanalabs/command_buffer.c b/drivers/misc/habanalabs/command_buffer.c new file mode 100644 index 000000000000..85f75806a9a7 --- /dev/null +++ b/drivers/misc/habanalabs/command_buffer.c @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include <uapi/misc/habanalabs.h> +#include "habanalabs.h" + +#include <linux/mm.h> +#include <linux/slab.h> + +static void cb_fini(struct hl_device *hdev, struct hl_cb *cb) +{ + hdev->asic_funcs->dma_free_coherent(hdev, cb->size, + (void *) (uintptr_t) cb->kernel_address, + cb->bus_address); + kfree(cb); +} + +static void cb_do_release(struct hl_device *hdev, struct hl_cb *cb) +{ + if (cb->is_pool) { + spin_lock(&hdev->cb_pool_lock); + list_add(&cb->pool_list, &hdev->cb_pool); + spin_unlock(&hdev->cb_pool_lock); + } else { + cb_fini(hdev, cb); + } +} + +static void cb_release(struct kref *ref) +{ + struct hl_device *hdev; + struct hl_cb *cb; + + cb = container_of(ref, struct hl_cb, refcount); + hdev = cb->hdev; + + hl_debugfs_remove_cb(cb); + + cb_do_release(hdev, cb); +} + +static struct hl_cb *hl_cb_alloc(struct hl_device *hdev, u32 cb_size, + int ctx_id) +{ + struct hl_cb *cb; + void *p; + + /* + * We use of GFP_ATOMIC here because this function can be called from + * the latency-sensitive code path for command submission. Due to H/W + * limitations in some of the ASICs, the kernel must copy the user CB + * that is designated for an external queue and actually enqueue + * the kernel's copy. Hence, we must never sleep in this code section + * and must use GFP_ATOMIC for all memory allocations. + */ + if (ctx_id == HL_KERNEL_ASID_ID) + cb = kzalloc(sizeof(*cb), GFP_ATOMIC); + else + cb = kzalloc(sizeof(*cb), GFP_KERNEL); + + if (!cb) + return NULL; + + if (ctx_id == HL_KERNEL_ASID_ID) + p = hdev->asic_funcs->dma_alloc_coherent(hdev, cb_size, + &cb->bus_address, GFP_ATOMIC); + else + p = hdev->asic_funcs->dma_alloc_coherent(hdev, cb_size, + &cb->bus_address, + GFP_USER | __GFP_ZERO); + if (!p) { + dev_err(hdev->dev, + "failed to allocate %d of dma memory for CB\n", + cb_size); + kfree(cb); + return NULL; + } + + cb->kernel_address = (u64) (uintptr_t) p; + cb->size = cb_size; + + return cb; +} + +int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, + u32 cb_size, u64 *handle, int ctx_id) +{ + struct hl_cb *cb; + bool alloc_new_cb = true; + int rc; + + /* + * Can't use generic function to check this because of special case + * where we create a CB as part of the reset process + */ + if ((hdev->disabled) || ((atomic_read(&hdev->in_reset)) && + (ctx_id != HL_KERNEL_ASID_ID))) { + dev_warn_ratelimited(hdev->dev, + "Device is disabled or in reset. Can't create new CBs\n"); + rc = -EBUSY; + goto out_err; + } + + if (cb_size > HL_MAX_CB_SIZE) { + dev_err(hdev->dev, + "CB size %d must be less then %d\n", + cb_size, HL_MAX_CB_SIZE); + rc = -EINVAL; + goto out_err; + } + + /* Minimum allocation must be PAGE SIZE */ + if (cb_size < PAGE_SIZE) + cb_size = PAGE_SIZE; + + if (ctx_id == HL_KERNEL_ASID_ID && + cb_size <= hdev->asic_prop.cb_pool_cb_size) { + + spin_lock(&hdev->cb_pool_lock); + if (!list_empty(&hdev->cb_pool)) { + cb = list_first_entry(&hdev->cb_pool, typeof(*cb), + pool_list); + list_del(&cb->pool_list); + spin_unlock(&hdev->cb_pool_lock); + alloc_new_cb = false; + } else { + spin_unlock(&hdev->cb_pool_lock); + dev_dbg(hdev->dev, "CB pool is empty\n"); + } + } + + if (alloc_new_cb) { + cb = hl_cb_alloc(hdev, cb_size, ctx_id); + if (!cb) { + rc = -ENOMEM; + goto out_err; + } + } + + cb->hdev = hdev; + cb->ctx_id = ctx_id; + + spin_lock(&mgr->cb_lock); + rc = idr_alloc(&mgr->cb_handles, cb, 1, 0, GFP_ATOMIC); + spin_unlock(&mgr->cb_lock); + + if (rc < 0) { + dev_err(hdev->dev, "Failed to allocate IDR for a new CB\n"); + goto release_cb; + } + + cb->id = rc; + + kref_init(&cb->refcount); + spin_lock_init(&cb->lock); + + /* + * idr is 32-bit so we can safely OR it with a mask that is above + * 32 bit + */ + *handle = cb->id | HL_MMAP_CB_MASK; + *handle <<= PAGE_SHIFT; + + hl_debugfs_add_cb(cb); + + return 0; + +release_cb: + cb_do_release(hdev, cb); +out_err: + *handle = 0; + + return rc; +} + +int hl_cb_destroy(struct hl_device *hdev, struct hl_cb_mgr *mgr, u64 cb_handle) +{ + struct hl_cb *cb; + u32 handle; + int rc = 0; + + /* + * handle was given to user to do mmap, I need to shift it back to + * how the idr module gave it to me + */ + cb_handle >>= PAGE_SHIFT; + handle = (u32) cb_handle; + + spin_lock(&mgr->cb_lock); + + cb = idr_find(&mgr->cb_handles, handle); + if (cb) { + idr_remove(&mgr->cb_handles, handle); + spin_unlock(&mgr->cb_lock); + kref_put(&cb->refcount, cb_release); + } else { + spin_unlock(&mgr->cb_lock); + dev_err(hdev->dev, + "CB destroy failed, no match to handle 0x%x\n", handle); + rc = -EINVAL; + } + + return rc; +} + +int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data) +{ + union hl_cb_args *args = data; + struct hl_device *hdev = hpriv->hdev; + u64 handle; + int rc; + + switch (args->in.op) { + case HL_CB_OP_CREATE: + rc = hl_cb_create(hdev, &hpriv->cb_mgr, args->in.cb_size, + &handle, hpriv->ctx->asid); + memset(args, 0, sizeof(*args)); + args->out.cb_handle = handle; + break; + case HL_CB_OP_DESTROY: + rc = hl_cb_destroy(hdev, &hpriv->cb_mgr, + args->in.cb_handle); + break; + default: + rc = -ENOTTY; + break; + } + + return rc; +} + +static void cb_vm_close(struct vm_area_struct *vma) +{ + struct hl_cb *cb = (struct hl_cb *) vma->vm_private_data; + long new_mmap_size; + + new_mmap_size = cb->mmap_size - (vma->vm_end - vma->vm_start); + + if (new_mmap_size > 0) { + cb->mmap_size = new_mmap_size; + return; + } + + spin_lock(&cb->lock); + cb->mmap = false; + spin_unlock(&cb->lock); + + hl_cb_put(cb); + vma->vm_private_data = NULL; +} + +static const struct vm_operations_struct cb_vm_ops = { + .close = cb_vm_close +}; + +int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_cb *cb; + phys_addr_t address; + u32 handle; + int rc; + + handle = vma->vm_pgoff; + + /* reference was taken here */ + cb = hl_cb_get(hdev, &hpriv->cb_mgr, handle); + if (!cb) { + dev_err(hdev->dev, + "CB mmap failed, no match to handle %d\n", handle); + return -EINVAL; + } + + /* Validation check */ + if ((vma->vm_end - vma->vm_start) != ALIGN(cb->size, PAGE_SIZE)) { + dev_err(hdev->dev, + "CB mmap failed, mmap size 0x%lx != 0x%x cb size\n", + vma->vm_end - vma->vm_start, cb->size); + rc = -EINVAL; + goto put_cb; + } + + spin_lock(&cb->lock); + + if (cb->mmap) { + dev_err(hdev->dev, + "CB mmap failed, CB already mmaped to user\n"); + rc = -EINVAL; + goto release_lock; + } + + cb->mmap = true; + + spin_unlock(&cb->lock); + + vma->vm_ops = &cb_vm_ops; + + /* + * Note: We're transferring the cb reference to + * vma->vm_private_data here. + */ + + vma->vm_private_data = cb; + + /* Calculate address for CB */ + address = virt_to_phys((void *) (uintptr_t) cb->kernel_address); + + rc = hdev->asic_funcs->cb_mmap(hdev, vma, cb->kernel_address, + address, cb->size); + + if (rc) { + spin_lock(&cb->lock); + cb->mmap = false; + goto release_lock; + } + + cb->mmap_size = cb->size; + + return 0; + +release_lock: + spin_unlock(&cb->lock); +put_cb: + hl_cb_put(cb); + return rc; +} + +struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr, + u32 handle) +{ + struct hl_cb *cb; + + spin_lock(&mgr->cb_lock); + cb = idr_find(&mgr->cb_handles, handle); + + if (!cb) { + spin_unlock(&mgr->cb_lock); + dev_warn(hdev->dev, + "CB get failed, no match to handle %d\n", handle); + return NULL; + } + + kref_get(&cb->refcount); + + spin_unlock(&mgr->cb_lock); + + return cb; + +} + +void hl_cb_put(struct hl_cb *cb) +{ + kref_put(&cb->refcount, cb_release); +} + +void hl_cb_mgr_init(struct hl_cb_mgr *mgr) +{ + spin_lock_init(&mgr->cb_lock); + idr_init(&mgr->cb_handles); +} + +void hl_cb_mgr_fini(struct hl_device *hdev, struct hl_cb_mgr *mgr) +{ + struct hl_cb *cb; + struct idr *idp; + u32 id; + + idp = &mgr->cb_handles; + + idr_for_each_entry(idp, cb, id) { + if (kref_put(&cb->refcount, cb_release) != 1) + dev_err(hdev->dev, + "CB %d for CTX ID %d is still alive\n", + id, cb->ctx_id); + } + + idr_destroy(&mgr->cb_handles); +} + +struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size) +{ + u64 cb_handle; + struct hl_cb *cb; + int rc; + + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, cb_size, &cb_handle, + HL_KERNEL_ASID_ID); + if (rc) { + dev_err(hdev->dev, "Failed to allocate CB for KMD %d\n", rc); + return NULL; + } + + cb_handle >>= PAGE_SHIFT; + cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr, (u32) cb_handle); + /* hl_cb_get should never fail here so use kernel WARN */ + WARN(!cb, "Kernel CB handle invalid 0x%x\n", (u32) cb_handle); + if (!cb) + goto destroy_cb; + + return cb; + +destroy_cb: + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb_handle << PAGE_SHIFT); + + return NULL; +} + +int hl_cb_pool_init(struct hl_device *hdev) +{ + struct hl_cb *cb; + int i; + + INIT_LIST_HEAD(&hdev->cb_pool); + spin_lock_init(&hdev->cb_pool_lock); + + for (i = 0 ; i < hdev->asic_prop.cb_pool_cb_cnt ; i++) { + cb = hl_cb_alloc(hdev, hdev->asic_prop.cb_pool_cb_size, + HL_KERNEL_ASID_ID); + if (cb) { + cb->is_pool = true; + list_add(&cb->pool_list, &hdev->cb_pool); + } else { + hl_cb_pool_fini(hdev); + return -ENOMEM; + } + } + + return 0; +} + +int hl_cb_pool_fini(struct hl_device *hdev) +{ + struct hl_cb *cb, *tmp; + + list_for_each_entry_safe(cb, tmp, &hdev->cb_pool, pool_list) { + list_del(&cb->pool_list); + cb_fini(hdev, cb); + } + + return 0; +} diff --git a/drivers/misc/habanalabs/command_submission.c b/drivers/misc/habanalabs/command_submission.c new file mode 100644 index 000000000000..3525236ed8d9 --- /dev/null +++ b/drivers/misc/habanalabs/command_submission.c @@ -0,0 +1,780 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include <uapi/misc/habanalabs.h> +#include "habanalabs.h" + +#include <linux/uaccess.h> +#include <linux/slab.h> + +static void job_wq_completion(struct work_struct *work); +static long _hl_cs_wait_ioctl(struct hl_device *hdev, + struct hl_ctx *ctx, u64 timeout_us, u64 seq); +static void cs_do_release(struct kref *ref); + +static const char *hl_fence_get_driver_name(struct dma_fence *fence) +{ + return "HabanaLabs"; +} + +static const char *hl_fence_get_timeline_name(struct dma_fence *fence) +{ + struct hl_dma_fence *hl_fence = + container_of(fence, struct hl_dma_fence, base_fence); + + return dev_name(hl_fence->hdev->dev); +} + +static bool hl_fence_enable_signaling(struct dma_fence *fence) +{ + return true; +} + +static void hl_fence_release(struct dma_fence *fence) +{ + struct hl_dma_fence *hl_fence = + container_of(fence, struct hl_dma_fence, base_fence); + + kfree_rcu(hl_fence, base_fence.rcu); +} + +static const struct dma_fence_ops hl_fence_ops = { + .get_driver_name = hl_fence_get_driver_name, + .get_timeline_name = hl_fence_get_timeline_name, + .enable_signaling = hl_fence_enable_signaling, + .wait = dma_fence_default_wait, + .release = hl_fence_release +}; + +static void cs_get(struct hl_cs *cs) +{ + kref_get(&cs->refcount); +} + +static int cs_get_unless_zero(struct hl_cs *cs) +{ + return kref_get_unless_zero(&cs->refcount); +} + +static void cs_put(struct hl_cs *cs) +{ + kref_put(&cs->refcount, cs_do_release); +} + +/* + * cs_parser - parse the user command submission + * + * @hpriv : pointer to the private data of the fd + * @job : pointer to the job that holds the command submission info + * + * The function parses the command submission of the user. It calls the + * ASIC specific parser, which returns a list of memory blocks to send + * to the device as different command buffers + * + */ +static int cs_parser(struct hl_fpriv *hpriv, struct hl_cs_job *job) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_cs_parser parser; + int rc; + + parser.ctx_id = job->cs->ctx->asid; + parser.cs_sequence = job->cs->sequence; + parser.job_id = job->id; + + parser.hw_queue_id = job->hw_queue_id; + parser.job_userptr_list = &job->userptr_list; + parser.patched_cb = NULL; + parser.user_cb = job->user_cb; + parser.user_cb_size = job->user_cb_size; + parser.ext_queue = job->ext_queue; + job->patched_cb = NULL; + parser.use_virt_addr = hdev->mmu_enable; + + rc = hdev->asic_funcs->cs_parser(hdev, &parser); + if (job->ext_queue) { + if (!rc) { + job->patched_cb = parser.patched_cb; + job->job_cb_size = parser.patched_cb_size; + + spin_lock(&job->patched_cb->lock); + job->patched_cb->cs_cnt++; + spin_unlock(&job->patched_cb->lock); + } + + /* + * Whether the parsing worked or not, we don't need the + * original CB anymore because it was already parsed and + * won't be accessed again for this CS + */ + spin_lock(&job->user_cb->lock); + job->user_cb->cs_cnt--; + spin_unlock(&job->user_cb->lock); + hl_cb_put(job->user_cb); + job->user_cb = NULL; + } + + return rc; +} + +static void free_job(struct hl_device *hdev, struct hl_cs_job *job) +{ + struct hl_cs *cs = job->cs; + + if (job->ext_queue) { + hl_userptr_delete_list(hdev, &job->userptr_list); + + /* + * We might arrive here from rollback and patched CB wasn't + * created, so we need to check it's not NULL + */ + if (job->patched_cb) { + spin_lock(&job->patched_cb->lock); + job->patched_cb->cs_cnt--; + spin_unlock(&job->patched_cb->lock); + + hl_cb_put(job->patched_cb); + } + } + + /* + * This is the only place where there can be multiple threads + * modifying the list at the same time + */ + spin_lock(&cs->job_lock); + list_del(&job->cs_node); + spin_unlock(&cs->job_lock); + + hl_debugfs_remove_job(hdev, job); + + if (job->ext_queue) + cs_put(cs); + + kfree(job); +} + +static void cs_do_release(struct kref *ref) +{ + struct hl_cs *cs = container_of(ref, struct hl_cs, + refcount); + struct hl_device *hdev = cs->ctx->hdev; + struct hl_cs_job *job, *tmp; + + cs->completed = true; + + /* + * Although if we reached here it means that all external jobs have + * finished, because each one of them took refcnt to CS, we still + * need to go over the internal jobs and free them. Otherwise, we + * will have leaked memory and what's worse, the CS object (and + * potentially the CTX object) could be released, while the JOB + * still holds a pointer to them (but no reference). + */ + list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node) + free_job(hdev, job); + + /* We also need to update CI for internal queues */ + if (cs->submitted) { + hl_int_hw_queue_update_ci(cs); + + spin_lock(&hdev->hw_queues_mirror_lock); + /* remove CS from hw_queues mirror list */ + list_del_init(&cs->mirror_node); + spin_unlock(&hdev->hw_queues_mirror_lock); + + /* + * Don't cancel TDR in case this CS was timedout because we + * might be running from the TDR context + */ + if ((!cs->timedout) && + (hdev->timeout_jiffies != MAX_SCHEDULE_TIMEOUT)) { + struct hl_cs *next; + + if (cs->tdr_active) + cancel_delayed_work_sync(&cs->work_tdr); + + spin_lock(&hdev->hw_queues_mirror_lock); + + /* queue TDR for next CS */ + next = list_first_entry_or_null( + &hdev->hw_queues_mirror_list, + struct hl_cs, mirror_node); + + if ((next) && (!next->tdr_active)) { + next->tdr_active = true; + schedule_delayed_work(&next->work_tdr, + hdev->timeout_jiffies); + } + + spin_unlock(&hdev->hw_queues_mirror_lock); + } + } + + /* + * Must be called before hl_ctx_put because inside we use ctx to get + * the device + */ + hl_debugfs_remove_cs(cs); + + hl_ctx_put(cs->ctx); + + if (cs->timedout) + dma_fence_set_error(cs->fence, -ETIMEDOUT); + else if (cs->aborted) + dma_fence_set_error(cs->fence, -EIO); + + dma_fence_signal(cs->fence); + dma_fence_put(cs->fence); + + kfree(cs); +} + +static void cs_timedout(struct work_struct *work) +{ + struct hl_device *hdev; + int ctx_asid, rc; + struct hl_cs *cs = container_of(work, struct hl_cs, + work_tdr.work); + rc = cs_get_unless_zero(cs); + if (!rc) + return; + + if ((!cs->submitted) || (cs->completed)) { + cs_put(cs); + return; + } + + /* Mark the CS is timed out so we won't try to cancel its TDR */ + cs->timedout = true; + + hdev = cs->ctx->hdev; + ctx_asid = cs->ctx->asid; + + /* TODO: add information about last signaled seq and last emitted seq */ + dev_err(hdev->dev, "CS %d.%llu got stuck!\n", ctx_asid, cs->sequence); + + cs_put(cs); + + if (hdev->reset_on_lockup) + hl_device_reset(hdev, false, false); +} + +static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, + struct hl_cs **cs_new) +{ + struct hl_dma_fence *fence; + struct dma_fence *other = NULL; + struct hl_cs *cs; + int rc; + + cs = kzalloc(sizeof(*cs), GFP_ATOMIC); + if (!cs) + return -ENOMEM; + + cs->ctx = ctx; + cs->submitted = false; + cs->completed = false; + INIT_LIST_HEAD(&cs->job_list); + INIT_DELAYED_WORK(&cs->work_tdr, cs_timedout); + kref_init(&cs->refcount); + spin_lock_init(&cs->job_lock); + + fence = kmalloc(sizeof(*fence), GFP_ATOMIC); + if (!fence) { + rc = -ENOMEM; + goto free_cs; + } + + fence->hdev = hdev; + spin_lock_init(&fence->lock); + cs->fence = &fence->base_fence; + + spin_lock(&ctx->cs_lock); + + fence->cs_seq = ctx->cs_sequence; + other = ctx->cs_pending[fence->cs_seq & (HL_MAX_PENDING_CS - 1)]; + if ((other) && (!dma_fence_is_signaled(other))) { + spin_unlock(&ctx->cs_lock); + rc = -EAGAIN; + goto free_fence; + } + + dma_fence_init(&fence->base_fence, &hl_fence_ops, &fence->lock, + ctx->asid, ctx->cs_sequence); + + cs->sequence = fence->cs_seq; + + ctx->cs_pending[fence->cs_seq & (HL_MAX_PENDING_CS - 1)] = + &fence->base_fence; + ctx->cs_sequence++; + + dma_fence_get(&fence->base_fence); + + dma_fence_put(other); + + spin_unlock(&ctx->cs_lock); + + *cs_new = cs; + + return 0; + +free_fence: + kfree(fence); +free_cs: + kfree(cs); + return rc; +} + +static void cs_rollback(struct hl_device *hdev, struct hl_cs *cs) +{ + struct hl_cs_job *job, *tmp; + + list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node) + free_job(hdev, job); +} + +void hl_cs_rollback_all(struct hl_device *hdev) +{ + struct hl_cs *cs, *tmp; + + /* flush all completions */ + flush_workqueue(hdev->cq_wq); + + /* Make sure we don't have leftovers in the H/W queues mirror list */ + list_for_each_entry_safe(cs, tmp, &hdev->hw_queues_mirror_list, + mirror_node) { + cs_get(cs); + cs->aborted = true; + dev_warn_ratelimited(hdev->dev, "Killing CS %d.%llu\n", + cs->ctx->asid, cs->sequence); + cs_rollback(hdev, cs); + cs_put(cs); + } +} + +static void job_wq_completion(struct work_struct *work) +{ + struct hl_cs_job *job = container_of(work, struct hl_cs_job, + finish_work); + struct hl_cs *cs = job->cs; + struct hl_device *hdev = cs->ctx->hdev; + + /* job is no longer needed */ + free_job(hdev, job); +} + +static struct hl_cb *validate_queue_index(struct hl_device *hdev, + struct hl_cb_mgr *cb_mgr, + struct hl_cs_chunk *chunk, + bool *ext_queue) +{ + struct asic_fixed_properties *asic = &hdev->asic_prop; + struct hw_queue_properties *hw_queue_prop; + u32 cb_handle; + struct hl_cb *cb; + + /* Assume external queue */ + *ext_queue = true; + + hw_queue_prop = &asic->hw_queues_props[chunk->queue_index]; + + if ((chunk->queue_index >= HL_MAX_QUEUES) || + (hw_queue_prop->type == QUEUE_TYPE_NA)) { + dev_err(hdev->dev, "Queue index %d is invalid\n", + chunk->queue_index); + return NULL; + } + + if (hw_queue_prop->kmd_only) { + dev_err(hdev->dev, "Queue index %d is restricted for KMD\n", + chunk->queue_index); + return NULL; + } else if (hw_queue_prop->type == QUEUE_TYPE_INT) { + *ext_queue = false; + return (struct hl_cb *) (uintptr_t) chunk->cb_handle; + } + + /* Retrieve CB object */ + cb_handle = (u32) (chunk->cb_handle >> PAGE_SHIFT); + + cb = hl_cb_get(hdev, cb_mgr, cb_handle); + if (!cb) { + dev_err(hdev->dev, "CB handle 0x%x invalid\n", cb_handle); + return NULL; + } + + if ((chunk->cb_size < 8) || (chunk->cb_size > cb->size)) { + dev_err(hdev->dev, "CB size %u invalid\n", chunk->cb_size); + goto release_cb; + } + + spin_lock(&cb->lock); + cb->cs_cnt++; + spin_unlock(&cb->lock); + + return cb; + +release_cb: + hl_cb_put(cb); + return NULL; +} + +struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, bool ext_queue) +{ + struct hl_cs_job *job; + + job = kzalloc(sizeof(*job), GFP_ATOMIC); + if (!job) + return NULL; + + job->ext_queue = ext_queue; + + if (job->ext_queue) { + INIT_LIST_HEAD(&job->userptr_list); + INIT_WORK(&job->finish_work, job_wq_completion); + } + + return job; +} + +static int _hl_cs_ioctl(struct hl_fpriv *hpriv, void __user *chunks, + u32 num_chunks, u64 *cs_seq) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_cs_chunk *cs_chunk_array; + struct hl_cs_job *job; + struct hl_cs *cs; + struct hl_cb *cb; + bool ext_queue_present = false; + u32 size_to_copy; + int rc, i, parse_cnt; + + *cs_seq = ULLONG_MAX; + + if (num_chunks > HL_MAX_JOBS_PER_CS) { + dev_err(hdev->dev, + "Number of chunks can NOT be larger than %d\n", + HL_MAX_JOBS_PER_CS); + rc = -EINVAL; + goto out; + } + + cs_chunk_array = kmalloc_array(num_chunks, sizeof(*cs_chunk_array), + GFP_ATOMIC); + if (!cs_chunk_array) { + rc = -ENOMEM; + goto out; + } + + size_to_copy = num_chunks * sizeof(struct hl_cs_chunk); + if (copy_from_user(cs_chunk_array, chunks, size_to_copy)) { + dev_err(hdev->dev, "Failed to copy cs chunk array from user\n"); + rc = -EFAULT; + goto free_cs_chunk_array; + } + + /* increment refcnt for context */ + hl_ctx_get(hdev, hpriv->ctx); + + rc = allocate_cs(hdev, hpriv->ctx, &cs); + if (rc) { + hl_ctx_put(hpriv->ctx); + goto free_cs_chunk_array; + } + + *cs_seq = cs->sequence; + + hl_debugfs_add_cs(cs); + + /* Validate ALL the CS chunks before submitting the CS */ + for (i = 0, parse_cnt = 0 ; i < num_chunks ; i++, parse_cnt++) { + struct hl_cs_chunk *chunk = &cs_chunk_array[i]; + bool ext_queue; + + cb = validate_queue_index(hdev, &hpriv->cb_mgr, chunk, + &ext_queue); + if (ext_queue) { + ext_queue_present = true; + if (!cb) { + rc = -EINVAL; + goto free_cs_object; + } + } + + job = hl_cs_allocate_job(hdev, ext_queue); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + if (ext_queue) + goto release_cb; + else + goto free_cs_object; + } + + job->id = i + 1; + job->cs = cs; + job->user_cb = cb; + job->user_cb_size = chunk->cb_size; + if (job->ext_queue) + job->job_cb_size = cb->size; + else + job->job_cb_size = chunk->cb_size; + job->hw_queue_id = chunk->queue_index; + + cs->jobs_in_queue_cnt[job->hw_queue_id]++; + + list_add_tail(&job->cs_node, &cs->job_list); + + /* + * Increment CS reference. When CS reference is 0, CS is + * done and can be signaled to user and free all its resources + * Only increment for JOB on external queues, because only + * for those JOBs we get completion + */ + if (job->ext_queue) + cs_get(cs); + + hl_debugfs_add_job(hdev, job); + + rc = cs_parser(hpriv, job); + if (rc) { + dev_err(hdev->dev, + "Failed to parse JOB %d.%llu.%d, err %d, rejecting the CS\n", + cs->ctx->asid, cs->sequence, job->id, rc); + goto free_cs_object; + } + } + + if (!ext_queue_present) { + dev_err(hdev->dev, + "Reject CS %d.%llu because no external queues jobs\n", + cs->ctx->asid, cs->sequence); + rc = -EINVAL; + goto free_cs_object; + } + + rc = hl_hw_queue_schedule_cs(cs); + if (rc) { + dev_err(hdev->dev, + "Failed to submit CS %d.%llu to H/W queues, error %d\n", + cs->ctx->asid, cs->sequence, rc); + goto free_cs_object; + } + + rc = HL_CS_STATUS_SUCCESS; + goto put_cs; + +release_cb: + spin_lock(&cb->lock); + cb->cs_cnt--; + spin_unlock(&cb->lock); + hl_cb_put(cb); +free_cs_object: + cs_rollback(hdev, cs); + *cs_seq = ULLONG_MAX; + /* The path below is both for good and erroneous exits */ +put_cs: + /* We finished with the CS in this function, so put the ref */ + cs_put(cs); +free_cs_chunk_array: + kfree(cs_chunk_array); +out: + return rc; +} + +int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) +{ + struct hl_device *hdev = hpriv->hdev; + union hl_cs_args *args = data; + struct hl_ctx *ctx = hpriv->ctx; + void __user *chunks; + u32 num_chunks; + u64 cs_seq = ULONG_MAX; + int rc, do_restore; + bool need_soft_reset = false; + + if (hl_device_disabled_or_in_reset(hdev)) { + dev_warn(hdev->dev, + "Device is %s. Can't submit new CS\n", + atomic_read(&hdev->in_reset) ? "in_reset" : "disabled"); + rc = -EBUSY; + goto out; + } + + do_restore = atomic_cmpxchg(&ctx->thread_restore_token, 1, 0); + + if (do_restore || (args->in.cs_flags & HL_CS_FLAGS_FORCE_RESTORE)) { + long ret; + + chunks = (void __user *)(uintptr_t)args->in.chunks_restore; + num_chunks = args->in.num_chunks_restore; + + mutex_lock(&hpriv->restore_phase_mutex); + + if (do_restore) { + rc = hdev->asic_funcs->context_switch(hdev, ctx->asid); + if (rc) { + dev_err_ratelimited(hdev->dev, + "Failed to switch to context %d, rejecting CS! %d\n", + ctx->asid, rc); + /* + * If we timedout, or if the device is not IDLE + * while we want to do context-switch (-EBUSY), + * we need to soft-reset because QMAN is + * probably stuck. However, we can't call to + * reset here directly because of deadlock, so + * need to do it at the very end of this + * function + */ + if ((rc == -ETIMEDOUT) || (rc == -EBUSY)) + need_soft_reset = true; + mutex_unlock(&hpriv->restore_phase_mutex); + goto out; + } + } + + hdev->asic_funcs->restore_phase_topology(hdev); + + if (num_chunks == 0) { + dev_dbg(hdev->dev, + "Need to run restore phase but restore CS is empty\n"); + rc = 0; + } else { + rc = _hl_cs_ioctl(hpriv, chunks, num_chunks, + &cs_seq); + } + + mutex_unlock(&hpriv->restore_phase_mutex); + + if (rc) { + dev_err(hdev->dev, + "Failed to submit restore CS for context %d (%d)\n", + ctx->asid, rc); + goto out; + } + + /* Need to wait for restore completion before execution phase */ + if (num_chunks > 0) { + ret = _hl_cs_wait_ioctl(hdev, ctx, + jiffies_to_usecs(hdev->timeout_jiffies), + cs_seq); + if (ret <= 0) { + dev_err(hdev->dev, + "Restore CS for context %d failed to complete %ld\n", + ctx->asid, ret); + rc = -ENOEXEC; + goto out; + } + } + + ctx->thread_restore_wait_token = 1; + } else if (!ctx->thread_restore_wait_token) { + u32 tmp; + + rc = hl_poll_timeout_memory(hdev, + (u64) (uintptr_t) &ctx->thread_restore_wait_token, + jiffies_to_usecs(hdev->timeout_jiffies), + &tmp); + + if (rc || !tmp) { + dev_err(hdev->dev, + "restore phase hasn't finished in time\n"); + rc = -ETIMEDOUT; + goto out; + } + } + + chunks = (void __user *)(uintptr_t)args->in.chunks_execute; + num_chunks = args->in.num_chunks_execute; + + if (num_chunks == 0) { + dev_err(hdev->dev, + "Got execute CS with 0 chunks, context %d\n", + ctx->asid); + rc = -EINVAL; + goto out; + } + + rc = _hl_cs_ioctl(hpriv, chunks, num_chunks, &cs_seq); + +out: + if (rc != -EAGAIN) { + memset(args, 0, sizeof(*args)); + args->out.status = rc; + args->out.seq = cs_seq; + } + + if (((rc == -ETIMEDOUT) || (rc == -EBUSY)) && (need_soft_reset)) + hl_device_reset(hdev, false, false); + + return rc; +} + +static long _hl_cs_wait_ioctl(struct hl_device *hdev, + struct hl_ctx *ctx, u64 timeout_us, u64 seq) +{ + struct dma_fence *fence; + unsigned long timeout; + long rc; + + if (timeout_us == MAX_SCHEDULE_TIMEOUT) + timeout = timeout_us; + else + timeout = usecs_to_jiffies(timeout_us); + + hl_ctx_get(hdev, ctx); + + fence = hl_ctx_get_fence(ctx, seq); + if (IS_ERR(fence)) { + rc = PTR_ERR(fence); + } else if (fence) { + rc = dma_fence_wait_timeout(fence, true, timeout); + if (fence->error == -ETIMEDOUT) + rc = -ETIMEDOUT; + else if (fence->error == -EIO) + rc = -EIO; + dma_fence_put(fence); + } else + rc = 1; + + hl_ctx_put(ctx); + + return rc; +} + +int hl_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data) +{ + struct hl_device *hdev = hpriv->hdev; + union hl_wait_cs_args *args = data; + u64 seq = args->in.seq; + long rc; + + rc = _hl_cs_wait_ioctl(hdev, hpriv->ctx, args->in.timeout_us, seq); + + memset(args, 0, sizeof(*args)); + + if (rc < 0) { + dev_err(hdev->dev, "Error %ld on waiting for CS handle %llu\n", + rc, seq); + if (rc == -ERESTARTSYS) { + args->out.status = HL_WAIT_CS_STATUS_INTERRUPTED; + rc = -EINTR; + } else if (rc == -ETIMEDOUT) { + args->out.status = HL_WAIT_CS_STATUS_TIMEDOUT; + } else if (rc == -EIO) { + args->out.status = HL_WAIT_CS_STATUS_ABORTED; + } + return rc; + } + + if (rc == 0) + args->out.status = HL_WAIT_CS_STATUS_BUSY; + else + args->out.status = HL_WAIT_CS_STATUS_COMPLETED; + + return 0; +} diff --git a/drivers/misc/habanalabs/context.c b/drivers/misc/habanalabs/context.c new file mode 100644 index 000000000000..619ace1c4ef7 --- /dev/null +++ b/drivers/misc/habanalabs/context.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#include <linux/slab.h> + +static void hl_ctx_fini(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + int i; + + /* + * If we arrived here, there are no jobs waiting for this context + * on its queues so we can safely remove it. + * This is because for each CS, we increment the ref count and for + * every CS that was finished we decrement it and we won't arrive + * to this function unless the ref count is 0 + */ + + for (i = 0 ; i < HL_MAX_PENDING_CS ; i++) + dma_fence_put(ctx->cs_pending[i]); + + if (ctx->asid != HL_KERNEL_ASID_ID) { + hl_vm_ctx_fini(ctx); + hl_asid_free(hdev, ctx->asid); + } +} + +void hl_ctx_do_release(struct kref *ref) +{ + struct hl_ctx *ctx; + + ctx = container_of(ref, struct hl_ctx, refcount); + + hl_ctx_fini(ctx); + + if (ctx->hpriv) + hl_hpriv_put(ctx->hpriv); + + kfree(ctx); +} + +int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv) +{ + struct hl_ctx_mgr *mgr = &hpriv->ctx_mgr; + struct hl_ctx *ctx; + int rc; + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + rc = -ENOMEM; + goto out_err; + } + + rc = hl_ctx_init(hdev, ctx, false); + if (rc) + goto free_ctx; + + hl_hpriv_get(hpriv); + ctx->hpriv = hpriv; + + /* TODO: remove for multiple contexts */ + hpriv->ctx = ctx; + hdev->user_ctx = ctx; + + mutex_lock(&mgr->ctx_lock); + rc = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL); + mutex_unlock(&mgr->ctx_lock); + + if (rc < 0) { + dev_err(hdev->dev, "Failed to allocate IDR for a new CTX\n"); + hl_ctx_free(hdev, ctx); + goto out_err; + } + + return 0; + +free_ctx: + kfree(ctx); +out_err: + return rc; +} + +void hl_ctx_free(struct hl_device *hdev, struct hl_ctx *ctx) +{ + if (kref_put(&ctx->refcount, hl_ctx_do_release) == 1) + return; + + dev_warn(hdev->dev, + "Context %d closed or terminated but its CS are executing\n", + ctx->asid); +} + +int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx) +{ + int rc = 0; + + ctx->hdev = hdev; + + kref_init(&ctx->refcount); + + ctx->cs_sequence = 1; + spin_lock_init(&ctx->cs_lock); + atomic_set(&ctx->thread_restore_token, 1); + ctx->thread_restore_wait_token = 0; + + if (is_kernel_ctx) { + ctx->asid = HL_KERNEL_ASID_ID; /* KMD gets ASID 0 */ + } else { + ctx->asid = hl_asid_alloc(hdev); + if (!ctx->asid) { + dev_err(hdev->dev, "No free ASID, failed to create context\n"); + return -ENOMEM; + } + + rc = hl_vm_ctx_init(ctx); + if (rc) { + dev_err(hdev->dev, "Failed to init mem ctx module\n"); + rc = -ENOMEM; + goto mem_ctx_err; + } + } + + return 0; + +mem_ctx_err: + if (ctx->asid != HL_KERNEL_ASID_ID) + hl_asid_free(hdev, ctx->asid); + + return rc; +} + +void hl_ctx_get(struct hl_device *hdev, struct hl_ctx *ctx) +{ + kref_get(&ctx->refcount); +} + +int hl_ctx_put(struct hl_ctx *ctx) +{ + return kref_put(&ctx->refcount, hl_ctx_do_release); +} + +struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq) +{ + struct hl_device *hdev = ctx->hdev; + struct dma_fence *fence; + + spin_lock(&ctx->cs_lock); + + if (seq >= ctx->cs_sequence) { + dev_notice(hdev->dev, + "Can't wait on seq %llu because current CS is at seq %llu\n", + seq, ctx->cs_sequence); + spin_unlock(&ctx->cs_lock); + return ERR_PTR(-EINVAL); + } + + + if (seq + HL_MAX_PENDING_CS < ctx->cs_sequence) { + dev_dbg(hdev->dev, + "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", + seq, ctx->cs_sequence); + spin_unlock(&ctx->cs_lock); + return NULL; + } + + fence = dma_fence_get( + ctx->cs_pending[seq & (HL_MAX_PENDING_CS - 1)]); + spin_unlock(&ctx->cs_lock); + + return fence; +} + +/* + * hl_ctx_mgr_init - initialize the context manager + * + * @mgr: pointer to context manager structure + * + * This manager is an object inside the hpriv object of the user process. + * The function is called when a user process opens the FD. + */ +void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr) +{ + mutex_init(&mgr->ctx_lock); + idr_init(&mgr->ctx_handles); +} + +/* + * hl_ctx_mgr_fini - finalize the context manager + * + * @hdev: pointer to device structure + * @mgr: pointer to context manager structure + * + * This function goes over all the contexts in the manager and frees them. + * It is called when a process closes the FD. + */ +void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr) +{ + struct hl_ctx *ctx; + struct idr *idp; + u32 id; + + idp = &mgr->ctx_handles; + + idr_for_each_entry(idp, ctx, id) + hl_ctx_free(hdev, ctx); + + idr_destroy(&mgr->ctx_handles); + mutex_destroy(&mgr->ctx_lock); +} diff --git a/drivers/misc/habanalabs/debugfs.c b/drivers/misc/habanalabs/debugfs.c new file mode 100644 index 000000000000..a53c12aff6ad --- /dev/null +++ b/drivers/misc/habanalabs/debugfs.c @@ -0,0 +1,1077 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" +#include "include/hw_ip/mmu/mmu_general.h" + +#include <linux/pci.h> +#include <linux/debugfs.h> +#include <linux/uaccess.h> + +#define MMU_ADDR_BUF_SIZE 40 +#define MMU_ASID_BUF_SIZE 10 +#define MMU_KBUF_SIZE (MMU_ADDR_BUF_SIZE + MMU_ASID_BUF_SIZE) + +static struct dentry *hl_debug_root; + +static int hl_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, + u8 i2c_reg, u32 *val) +{ + struct armcp_packet pkt; + int rc; + + if (hl_device_disabled_or_in_reset(hdev)) + return -EBUSY; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_I2C_RD << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.i2c_bus = i2c_bus; + pkt.i2c_addr = i2c_addr; + pkt.i2c_reg = i2c_reg; + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_DEVICE_TIMEOUT_USEC, (long *) val); + + if (rc) + dev_err(hdev->dev, "Failed to read from I2C, error %d\n", rc); + + return rc; +} + +static int hl_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, + u8 i2c_reg, u32 val) +{ + struct armcp_packet pkt; + int rc; + + if (hl_device_disabled_or_in_reset(hdev)) + return -EBUSY; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_I2C_WR << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.i2c_bus = i2c_bus; + pkt.i2c_addr = i2c_addr; + pkt.i2c_reg = i2c_reg; + pkt.value = __cpu_to_le64(val); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_DEVICE_TIMEOUT_USEC, NULL); + + if (rc) + dev_err(hdev->dev, "Failed to write to I2C, error %d\n", rc); + + return rc; +} + +static void hl_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state) +{ + struct armcp_packet pkt; + int rc; + + if (hl_device_disabled_or_in_reset(hdev)) + return; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_LED_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.led_index = __cpu_to_le32(led); + pkt.value = __cpu_to_le64(state); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_DEVICE_TIMEOUT_USEC, NULL); + + if (rc) + dev_err(hdev->dev, "Failed to set LED %d, error %d\n", led, rc); +} + +static int command_buffers_show(struct seq_file *s, void *data) +{ + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_cb *cb; + bool first = true; + + spin_lock(&dev_entry->cb_spinlock); + + list_for_each_entry(cb, &dev_entry->cb_list, debugfs_list) { + if (first) { + first = false; + seq_puts(s, "\n"); + seq_puts(s, " CB ID CTX ID CB size CB RefCnt mmap? CS counter\n"); + seq_puts(s, "---------------------------------------------------------------\n"); + } + seq_printf(s, + " %03d %d 0x%08x %d %d %d\n", + cb->id, cb->ctx_id, cb->size, + kref_read(&cb->refcount), + cb->mmap, cb->cs_cnt); + } + + spin_unlock(&dev_entry->cb_spinlock); + + if (!first) + seq_puts(s, "\n"); + + return 0; +} + +static int command_submission_show(struct seq_file *s, void *data) +{ + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_cs *cs; + bool first = true; + + spin_lock(&dev_entry->cs_spinlock); + + list_for_each_entry(cs, &dev_entry->cs_list, debugfs_list) { + if (first) { + first = false; + seq_puts(s, "\n"); + seq_puts(s, " CS ID CTX ASID CS RefCnt Submitted Completed\n"); + seq_puts(s, "------------------------------------------------------\n"); + } + seq_printf(s, + " %llu %d %d %d %d\n", + cs->sequence, cs->ctx->asid, + kref_read(&cs->refcount), + cs->submitted, cs->completed); + } + + spin_unlock(&dev_entry->cs_spinlock); + + if (!first) + seq_puts(s, "\n"); + + return 0; +} + +static int command_submission_jobs_show(struct seq_file *s, void *data) +{ + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_cs_job *job; + bool first = true; + + spin_lock(&dev_entry->cs_job_spinlock); + + list_for_each_entry(job, &dev_entry->cs_job_list, debugfs_list) { + if (first) { + first = false; + seq_puts(s, "\n"); + seq_puts(s, " JOB ID CS ID CTX ASID H/W Queue\n"); + seq_puts(s, "---------------------------------------\n"); + } + if (job->cs) + seq_printf(s, + " %02d %llu %d %d\n", + job->id, job->cs->sequence, job->cs->ctx->asid, + job->hw_queue_id); + else + seq_printf(s, + " %02d 0 %d %d\n", + job->id, HL_KERNEL_ASID_ID, job->hw_queue_id); + } + + spin_unlock(&dev_entry->cs_job_spinlock); + + if (!first) + seq_puts(s, "\n"); + + return 0; +} + +static int userptr_show(struct seq_file *s, void *data) +{ + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_userptr *userptr; + char dma_dir[4][30] = {"DMA_BIDIRECTIONAL", "DMA_TO_DEVICE", + "DMA_FROM_DEVICE", "DMA_NONE"}; + bool first = true; + + spin_lock(&dev_entry->userptr_spinlock); + + list_for_each_entry(userptr, &dev_entry->userptr_list, debugfs_list) { + if (first) { + first = false; + seq_puts(s, "\n"); + seq_puts(s, " user virtual address size dma dir\n"); + seq_puts(s, "----------------------------------------------------------\n"); + } + seq_printf(s, + " 0x%-14llx %-10u %-30s\n", + userptr->addr, userptr->size, dma_dir[userptr->dir]); + } + + spin_unlock(&dev_entry->userptr_spinlock); + + if (!first) + seq_puts(s, "\n"); + + return 0; +} + +static int vm_show(struct seq_file *s, void *data) +{ + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_ctx *ctx; + struct hl_vm *vm; + struct hl_vm_hash_node *hnode; + struct hl_userptr *userptr; + struct hl_vm_phys_pg_pack *phys_pg_pack = NULL; + enum vm_type_t *vm_type; + bool once = true; + int i; + + if (!dev_entry->hdev->mmu_enable) + return 0; + + spin_lock(&dev_entry->ctx_mem_hash_spinlock); + + list_for_each_entry(ctx, &dev_entry->ctx_mem_hash_list, debugfs_list) { + once = false; + seq_puts(s, "\n\n----------------------------------------------------"); + seq_puts(s, "\n----------------------------------------------------\n\n"); + seq_printf(s, "ctx asid: %u\n", ctx->asid); + + seq_puts(s, "\nmappings:\n\n"); + seq_puts(s, " virtual address size handle\n"); + seq_puts(s, "----------------------------------------------------\n"); + mutex_lock(&ctx->mem_hash_lock); + hash_for_each(ctx->mem_hash, i, hnode, node) { + vm_type = hnode->ptr; + + if (*vm_type == VM_TYPE_USERPTR) { + userptr = hnode->ptr; + seq_printf(s, + " 0x%-14llx %-10u\n", + hnode->vaddr, userptr->size); + } else { + phys_pg_pack = hnode->ptr; + seq_printf(s, + " 0x%-14llx %-10u %-4u\n", + hnode->vaddr, phys_pg_pack->total_size, + phys_pg_pack->handle); + } + } + mutex_unlock(&ctx->mem_hash_lock); + + vm = &ctx->hdev->vm; + spin_lock(&vm->idr_lock); + + if (!idr_is_empty(&vm->phys_pg_pack_handles)) + seq_puts(s, "\n\nallocations:\n"); + + idr_for_each_entry(&vm->phys_pg_pack_handles, phys_pg_pack, i) { + if (phys_pg_pack->asid != ctx->asid) + continue; + + seq_printf(s, "\nhandle: %u\n", phys_pg_pack->handle); + seq_printf(s, "page size: %u\n\n", + phys_pg_pack->page_size); + seq_puts(s, " physical address\n"); + seq_puts(s, "---------------------\n"); + for (i = 0 ; i < phys_pg_pack->npages ; i++) { + seq_printf(s, " 0x%-14llx\n", + phys_pg_pack->pages[i]); + } + } + spin_unlock(&vm->idr_lock); + + } + + spin_unlock(&dev_entry->ctx_mem_hash_spinlock); + + if (!once) + seq_puts(s, "\n"); + + return 0; +} + +/* these inline functions are copied from mmu.c */ +static inline u64 get_hop0_addr(struct hl_ctx *ctx) +{ + return ctx->hdev->asic_prop.mmu_pgt_addr + + (ctx->asid * ctx->hdev->asic_prop.mmu_hop_table_size); +} + +static inline u64 get_hop0_pte_addr(struct hl_ctx *ctx, u64 hop_addr, + u64 virt_addr) +{ + return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * + ((virt_addr & HOP0_MASK) >> HOP0_SHIFT); +} + +static inline u64 get_hop1_pte_addr(struct hl_ctx *ctx, u64 hop_addr, + u64 virt_addr) +{ + return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * + ((virt_addr & HOP1_MASK) >> HOP1_SHIFT); +} + +static inline u64 get_hop2_pte_addr(struct hl_ctx *ctx, u64 hop_addr, + u64 virt_addr) +{ + return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * + ((virt_addr & HOP2_MASK) >> HOP2_SHIFT); +} + +static inline u64 get_hop3_pte_addr(struct hl_ctx *ctx, u64 hop_addr, + u64 virt_addr) +{ + return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * + ((virt_addr & HOP3_MASK) >> HOP3_SHIFT); +} + +static inline u64 get_hop4_pte_addr(struct hl_ctx *ctx, u64 hop_addr, + u64 virt_addr) +{ + return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * + ((virt_addr & HOP4_MASK) >> HOP4_SHIFT); +} + +static inline u64 get_next_hop_addr(u64 curr_pte) +{ + if (curr_pte & PAGE_PRESENT_MASK) + return curr_pte & PHYS_ADDR_MASK; + else + return ULLONG_MAX; +} + +static int mmu_show(struct seq_file *s, void *data) +{ + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_device *hdev = dev_entry->hdev; + struct hl_ctx *ctx = hdev->user_ctx; + + u64 hop0_addr = 0, hop0_pte_addr = 0, hop0_pte = 0, + hop1_addr = 0, hop1_pte_addr = 0, hop1_pte = 0, + hop2_addr = 0, hop2_pte_addr = 0, hop2_pte = 0, + hop3_addr = 0, hop3_pte_addr = 0, hop3_pte = 0, + hop4_addr = 0, hop4_pte_addr = 0, hop4_pte = 0, + virt_addr = dev_entry->mmu_addr; + + if (!hdev->mmu_enable) + return 0; + + if (!ctx) { + dev_err(hdev->dev, "no ctx available\n"); + return 0; + } + + mutex_lock(&ctx->mmu_lock); + + /* the following lookup is copied from unmap() in mmu.c */ + + hop0_addr = get_hop0_addr(ctx); + hop0_pte_addr = get_hop0_pte_addr(ctx, hop0_addr, virt_addr); + hop0_pte = hdev->asic_funcs->read_pte(hdev, hop0_pte_addr); + hop1_addr = get_next_hop_addr(hop0_pte); + + if (hop1_addr == ULLONG_MAX) + goto not_mapped; + + hop1_pte_addr = get_hop1_pte_addr(ctx, hop1_addr, virt_addr); + hop1_pte = hdev->asic_funcs->read_pte(hdev, hop1_pte_addr); + hop2_addr = get_next_hop_addr(hop1_pte); + + if (hop2_addr == ULLONG_MAX) + goto not_mapped; + + hop2_pte_addr = get_hop2_pte_addr(ctx, hop2_addr, virt_addr); + hop2_pte = hdev->asic_funcs->read_pte(hdev, hop2_pte_addr); + hop3_addr = get_next_hop_addr(hop2_pte); + + if (hop3_addr == ULLONG_MAX) + goto not_mapped; + + hop3_pte_addr = get_hop3_pte_addr(ctx, hop3_addr, virt_addr); + hop3_pte = hdev->asic_funcs->read_pte(hdev, hop3_pte_addr); + + if (!(hop3_pte & LAST_MASK)) { + hop4_addr = get_next_hop_addr(hop3_pte); + + if (hop4_addr == ULLONG_MAX) + goto not_mapped; + + hop4_pte_addr = get_hop4_pte_addr(ctx, hop4_addr, virt_addr); + hop4_pte = hdev->asic_funcs->read_pte(hdev, hop4_pte_addr); + if (!(hop4_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + } else { + if (!(hop3_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + } + + seq_printf(s, "asid: %u, virt_addr: 0x%llx\n", + dev_entry->mmu_asid, dev_entry->mmu_addr); + + seq_printf(s, "hop0_addr: 0x%llx\n", hop0_addr); + seq_printf(s, "hop0_pte_addr: 0x%llx\n", hop0_pte_addr); + seq_printf(s, "hop0_pte: 0x%llx\n", hop0_pte); + + seq_printf(s, "hop1_addr: 0x%llx\n", hop1_addr); + seq_printf(s, "hop1_pte_addr: 0x%llx\n", hop1_pte_addr); + seq_printf(s, "hop1_pte: 0x%llx\n", hop1_pte); + + seq_printf(s, "hop2_addr: 0x%llx\n", hop2_addr); + seq_printf(s, "hop2_pte_addr: 0x%llx\n", hop2_pte_addr); + seq_printf(s, "hop2_pte: 0x%llx\n", hop2_pte); + + seq_printf(s, "hop3_addr: 0x%llx\n", hop3_addr); + seq_printf(s, "hop3_pte_addr: 0x%llx\n", hop3_pte_addr); + seq_printf(s, "hop3_pte: 0x%llx\n", hop3_pte); + + if (!(hop3_pte & LAST_MASK)) { + seq_printf(s, "hop4_addr: 0x%llx\n", hop4_addr); + seq_printf(s, "hop4_pte_addr: 0x%llx\n", hop4_pte_addr); + seq_printf(s, "hop4_pte: 0x%llx\n", hop4_pte); + } + + goto out; + +not_mapped: + dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n", + virt_addr); +out: + mutex_unlock(&ctx->mmu_lock); + + return 0; +} + +static ssize_t mmu_write(struct file *file, const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct seq_file *s = file->private_data; + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_device *hdev = dev_entry->hdev; + char kbuf[MMU_KBUF_SIZE], asid_kbuf[MMU_ASID_BUF_SIZE], + addr_kbuf[MMU_ADDR_BUF_SIZE]; + char *c; + ssize_t rc; + + if (!hdev->mmu_enable) + return count; + + memset(kbuf, 0, sizeof(kbuf)); + memset(asid_kbuf, 0, sizeof(asid_kbuf)); + memset(addr_kbuf, 0, sizeof(addr_kbuf)); + + if (copy_from_user(kbuf, buf, count)) + goto err; + + kbuf[MMU_KBUF_SIZE - 1] = 0; + + c = strchr(kbuf, ' '); + if (!c) + goto err; + + memcpy(asid_kbuf, kbuf, c - kbuf); + + rc = kstrtouint(asid_kbuf, 10, &dev_entry->mmu_asid); + if (rc) + goto err; + + c = strstr(kbuf, " 0x"); + if (!c) + goto err; + + c += 3; + memcpy(addr_kbuf, c, (kbuf + count) - c); + + rc = kstrtoull(addr_kbuf, 16, &dev_entry->mmu_addr); + if (rc) + goto err; + + return count; + +err: + dev_err(hdev->dev, "usage: echo <asid> <0xaddr> > mmu\n"); + + return -EINVAL; +} + +static ssize_t hl_data_read32(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char tmp_buf[32]; + u32 val; + ssize_t rc; + + if (*ppos) + return 0; + + rc = hdev->asic_funcs->debugfs_read32(hdev, entry->addr, &val); + if (rc) { + dev_err(hdev->dev, "Failed to read from 0x%010llx\n", + entry->addr); + return rc; + } + + sprintf(tmp_buf, "0x%08x\n", val); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_data_write32(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + rc = kstrtouint_from_user(buf, count, 16, &value); + if (rc) + return rc; + + rc = hdev->asic_funcs->debugfs_write32(hdev, entry->addr, value); + if (rc) { + dev_err(hdev->dev, "Failed to write 0x%08x to 0x%010llx\n", + value, entry->addr); + return rc; + } + + return count; +} + +static ssize_t hl_get_power_state(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char tmp_buf[200]; + ssize_t rc; + int i; + + if (*ppos) + return 0; + + if (hdev->pdev->current_state == PCI_D0) + i = 1; + else if (hdev->pdev->current_state == PCI_D3hot) + i = 2; + else + i = 3; + + sprintf(tmp_buf, + "current power state: %d\n1 - D0\n2 - D3hot\n3 - Unknown\n", i); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_set_power_state(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + if (value == 1) { + pci_set_power_state(hdev->pdev, PCI_D0); + pci_restore_state(hdev->pdev); + rc = pci_enable_device(hdev->pdev); + } else if (value == 2) { + pci_save_state(hdev->pdev); + pci_disable_device(hdev->pdev); + pci_set_power_state(hdev->pdev, PCI_D3hot); + } else { + dev_dbg(hdev->dev, "invalid power state value %u\n", value); + return -EINVAL; + } + + return count; +} + +static ssize_t hl_i2c_data_read(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char tmp_buf[32]; + u32 val; + ssize_t rc; + + if (*ppos) + return 0; + + rc = hl_debugfs_i2c_read(hdev, entry->i2c_bus, entry->i2c_addr, + entry->i2c_reg, &val); + if (rc) { + dev_err(hdev->dev, + "Failed to read from I2C bus %d, addr %d, reg %d\n", + entry->i2c_bus, entry->i2c_addr, entry->i2c_reg); + return rc; + } + + sprintf(tmp_buf, "0x%02x\n", val); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_i2c_data_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + rc = kstrtouint_from_user(buf, count, 16, &value); + if (rc) + return rc; + + rc = hl_debugfs_i2c_write(hdev, entry->i2c_bus, entry->i2c_addr, + entry->i2c_reg, value); + if (rc) { + dev_err(hdev->dev, + "Failed to write 0x%02x to I2C bus %d, addr %d, reg %d\n", + value, entry->i2c_bus, entry->i2c_addr, entry->i2c_reg); + return rc; + } + + return count; +} + +static ssize_t hl_led0_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + value = value ? 1 : 0; + + hl_debugfs_led_set(hdev, 0, value); + + return count; +} + +static ssize_t hl_led1_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + value = value ? 1 : 0; + + hl_debugfs_led_set(hdev, 1, value); + + return count; +} + +static ssize_t hl_led2_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + value = value ? 1 : 0; + + hl_debugfs_led_set(hdev, 2, value); + + return count; +} + +static ssize_t hl_device_read(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + char tmp_buf[200]; + ssize_t rc; + + if (*ppos) + return 0; + + sprintf(tmp_buf, + "Valid values: disable, enable, suspend, resume, cpu_timeout\n"); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_device_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char data[30]; + + /* don't allow partial writes */ + if (*ppos != 0) + return 0; + + simple_write_to_buffer(data, 29, ppos, buf, count); + + if (strncmp("disable", data, strlen("disable")) == 0) { + hdev->disabled = true; + } else if (strncmp("enable", data, strlen("enable")) == 0) { + hdev->disabled = false; + } else if (strncmp("suspend", data, strlen("suspend")) == 0) { + hdev->asic_funcs->suspend(hdev); + } else if (strncmp("resume", data, strlen("resume")) == 0) { + hdev->asic_funcs->resume(hdev); + } else if (strncmp("cpu_timeout", data, strlen("cpu_timeout")) == 0) { + hdev->device_cpu_disabled = true; + } else { + dev_err(hdev->dev, + "Valid values: disable, enable, suspend, resume, cpu_timeout\n"); + count = -EINVAL; + } + + return count; +} + +static const struct file_operations hl_data32b_fops = { + .owner = THIS_MODULE, + .read = hl_data_read32, + .write = hl_data_write32 +}; + +static const struct file_operations hl_i2c_data_fops = { + .owner = THIS_MODULE, + .read = hl_i2c_data_read, + .write = hl_i2c_data_write +}; + +static const struct file_operations hl_power_fops = { + .owner = THIS_MODULE, + .read = hl_get_power_state, + .write = hl_set_power_state +}; + +static const struct file_operations hl_led0_fops = { + .owner = THIS_MODULE, + .write = hl_led0_write +}; + +static const struct file_operations hl_led1_fops = { + .owner = THIS_MODULE, + .write = hl_led1_write +}; + +static const struct file_operations hl_led2_fops = { + .owner = THIS_MODULE, + .write = hl_led2_write +}; + +static const struct file_operations hl_device_fops = { + .owner = THIS_MODULE, + .read = hl_device_read, + .write = hl_device_write +}; + +static const struct hl_info_list hl_debugfs_list[] = { + {"command_buffers", command_buffers_show, NULL}, + {"command_submission", command_submission_show, NULL}, + {"command_submission_jobs", command_submission_jobs_show, NULL}, + {"userptr", userptr_show, NULL}, + {"vm", vm_show, NULL}, + {"mmu", mmu_show, mmu_write}, +}; + +static int hl_debugfs_open(struct inode *inode, struct file *file) +{ + struct hl_debugfs_entry *node = inode->i_private; + + return single_open(file, node->info_ent->show, node); +} + +static ssize_t hl_debugfs_write(struct file *file, const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct hl_debugfs_entry *node = file->f_inode->i_private; + + if (node->info_ent->write) + return node->info_ent->write(file, buf, count, f_pos); + else + return -EINVAL; + +} + +static const struct file_operations hl_debugfs_fops = { + .owner = THIS_MODULE, + .open = hl_debugfs_open, + .read = seq_read, + .write = hl_debugfs_write, + .llseek = seq_lseek, + .release = single_release, +}; + +void hl_debugfs_add_device(struct hl_device *hdev) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + int count = ARRAY_SIZE(hl_debugfs_list); + struct hl_debugfs_entry *entry; + struct dentry *ent; + int i; + + dev_entry->hdev = hdev; + dev_entry->entry_arr = kmalloc_array(count, + sizeof(struct hl_debugfs_entry), + GFP_KERNEL); + if (!dev_entry->entry_arr) + return; + + INIT_LIST_HEAD(&dev_entry->file_list); + INIT_LIST_HEAD(&dev_entry->cb_list); + INIT_LIST_HEAD(&dev_entry->cs_list); + INIT_LIST_HEAD(&dev_entry->cs_job_list); + INIT_LIST_HEAD(&dev_entry->userptr_list); + INIT_LIST_HEAD(&dev_entry->ctx_mem_hash_list); + mutex_init(&dev_entry->file_mutex); + spin_lock_init(&dev_entry->cb_spinlock); + spin_lock_init(&dev_entry->cs_spinlock); + spin_lock_init(&dev_entry->cs_job_spinlock); + spin_lock_init(&dev_entry->userptr_spinlock); + spin_lock_init(&dev_entry->ctx_mem_hash_spinlock); + + dev_entry->root = debugfs_create_dir(dev_name(hdev->dev), + hl_debug_root); + + debugfs_create_x64("addr", + 0644, + dev_entry->root, + &dev_entry->addr); + + debugfs_create_file("data32", + 0644, + dev_entry->root, + dev_entry, + &hl_data32b_fops); + + debugfs_create_file("set_power_state", + 0200, + dev_entry->root, + dev_entry, + &hl_power_fops); + + debugfs_create_u8("i2c_bus", + 0644, + dev_entry->root, + &dev_entry->i2c_bus); + + debugfs_create_u8("i2c_addr", + 0644, + dev_entry->root, + &dev_entry->i2c_addr); + + debugfs_create_u8("i2c_reg", + 0644, + dev_entry->root, + &dev_entry->i2c_reg); + + debugfs_create_file("i2c_data", + 0644, + dev_entry->root, + dev_entry, + &hl_i2c_data_fops); + + debugfs_create_file("led0", + 0200, + dev_entry->root, + dev_entry, + &hl_led0_fops); + + debugfs_create_file("led1", + 0200, + dev_entry->root, + dev_entry, + &hl_led1_fops); + + debugfs_create_file("led2", + 0200, + dev_entry->root, + dev_entry, + &hl_led2_fops); + + debugfs_create_file("device", + 0200, + dev_entry->root, + dev_entry, + &hl_device_fops); + + for (i = 0, entry = dev_entry->entry_arr ; i < count ; i++, entry++) { + + ent = debugfs_create_file(hl_debugfs_list[i].name, + 0444, + dev_entry->root, + entry, + &hl_debugfs_fops); + entry->dent = ent; + entry->info_ent = &hl_debugfs_list[i]; + entry->dev_entry = dev_entry; + } +} + +void hl_debugfs_remove_device(struct hl_device *hdev) +{ + struct hl_dbg_device_entry *entry = &hdev->hl_debugfs; + + debugfs_remove_recursive(entry->root); + + mutex_destroy(&entry->file_mutex); + kfree(entry->entry_arr); +} + +void hl_debugfs_add_file(struct hl_fpriv *hpriv) +{ + struct hl_dbg_device_entry *dev_entry = &hpriv->hdev->hl_debugfs; + + mutex_lock(&dev_entry->file_mutex); + list_add(&hpriv->debugfs_list, &dev_entry->file_list); + mutex_unlock(&dev_entry->file_mutex); +} + +void hl_debugfs_remove_file(struct hl_fpriv *hpriv) +{ + struct hl_dbg_device_entry *dev_entry = &hpriv->hdev->hl_debugfs; + + mutex_lock(&dev_entry->file_mutex); + list_del(&hpriv->debugfs_list); + mutex_unlock(&dev_entry->file_mutex); +} + +void hl_debugfs_add_cb(struct hl_cb *cb) +{ + struct hl_dbg_device_entry *dev_entry = &cb->hdev->hl_debugfs; + + spin_lock(&dev_entry->cb_spinlock); + list_add(&cb->debugfs_list, &dev_entry->cb_list); + spin_unlock(&dev_entry->cb_spinlock); +} + +void hl_debugfs_remove_cb(struct hl_cb *cb) +{ + struct hl_dbg_device_entry *dev_entry = &cb->hdev->hl_debugfs; + + spin_lock(&dev_entry->cb_spinlock); + list_del(&cb->debugfs_list); + spin_unlock(&dev_entry->cb_spinlock); +} + +void hl_debugfs_add_cs(struct hl_cs *cs) +{ + struct hl_dbg_device_entry *dev_entry = &cs->ctx->hdev->hl_debugfs; + + spin_lock(&dev_entry->cs_spinlock); + list_add(&cs->debugfs_list, &dev_entry->cs_list); + spin_unlock(&dev_entry->cs_spinlock); +} + +void hl_debugfs_remove_cs(struct hl_cs *cs) +{ + struct hl_dbg_device_entry *dev_entry = &cs->ctx->hdev->hl_debugfs; + + spin_lock(&dev_entry->cs_spinlock); + list_del(&cs->debugfs_list); + spin_unlock(&dev_entry->cs_spinlock); +} + +void hl_debugfs_add_job(struct hl_device *hdev, struct hl_cs_job *job) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + + spin_lock(&dev_entry->cs_job_spinlock); + list_add(&job->debugfs_list, &dev_entry->cs_job_list); + spin_unlock(&dev_entry->cs_job_spinlock); +} + +void hl_debugfs_remove_job(struct hl_device *hdev, struct hl_cs_job *job) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + + spin_lock(&dev_entry->cs_job_spinlock); + list_del(&job->debugfs_list); + spin_unlock(&dev_entry->cs_job_spinlock); +} + +void hl_debugfs_add_userptr(struct hl_device *hdev, struct hl_userptr *userptr) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + + spin_lock(&dev_entry->userptr_spinlock); + list_add(&userptr->debugfs_list, &dev_entry->userptr_list); + spin_unlock(&dev_entry->userptr_spinlock); +} + +void hl_debugfs_remove_userptr(struct hl_device *hdev, + struct hl_userptr *userptr) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + + spin_lock(&dev_entry->userptr_spinlock); + list_del(&userptr->debugfs_list); + spin_unlock(&dev_entry->userptr_spinlock); +} + +void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + + spin_lock(&dev_entry->ctx_mem_hash_spinlock); + list_add(&ctx->debugfs_list, &dev_entry->ctx_mem_hash_list); + spin_unlock(&dev_entry->ctx_mem_hash_spinlock); +} + +void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + + spin_lock(&dev_entry->ctx_mem_hash_spinlock); + list_del(&ctx->debugfs_list); + spin_unlock(&dev_entry->ctx_mem_hash_spinlock); +} + +void __init hl_debugfs_init(void) +{ + hl_debug_root = debugfs_create_dir("habanalabs", NULL); +} + +void hl_debugfs_fini(void) +{ + debugfs_remove_recursive(hl_debug_root); +} diff --git a/drivers/misc/habanalabs/device.c b/drivers/misc/habanalabs/device.c new file mode 100644 index 000000000000..de46aa6ed154 --- /dev/null +++ b/drivers/misc/habanalabs/device.c @@ -0,0 +1,1140 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#include <linux/pci.h> +#include <linux/sched/signal.h> +#include <linux/hwmon.h> + +bool hl_device_disabled_or_in_reset(struct hl_device *hdev) +{ + if ((hdev->disabled) || (atomic_read(&hdev->in_reset))) + return true; + else + return false; +} + +static void hpriv_release(struct kref *ref) +{ + struct hl_fpriv *hpriv; + struct hl_device *hdev; + + hpriv = container_of(ref, struct hl_fpriv, refcount); + + hdev = hpriv->hdev; + + put_pid(hpriv->taskpid); + + hl_debugfs_remove_file(hpriv); + + mutex_destroy(&hpriv->restore_phase_mutex); + + kfree(hpriv); + + /* Now the FD is really closed */ + atomic_dec(&hdev->fd_open_cnt); + + /* This allows a new user context to open the device */ + hdev->user_ctx = NULL; +} + +void hl_hpriv_get(struct hl_fpriv *hpriv) +{ + kref_get(&hpriv->refcount); +} + +void hl_hpriv_put(struct hl_fpriv *hpriv) +{ + kref_put(&hpriv->refcount, hpriv_release); +} + +/* + * hl_device_release - release function for habanalabs device + * + * @inode: pointer to inode structure + * @filp: pointer to file structure + * + * Called when process closes an habanalabs device + */ +static int hl_device_release(struct inode *inode, struct file *filp) +{ + struct hl_fpriv *hpriv = filp->private_data; + + hl_cb_mgr_fini(hpriv->hdev, &hpriv->cb_mgr); + hl_ctx_mgr_fini(hpriv->hdev, &hpriv->ctx_mgr); + + filp->private_data = NULL; + + hl_hpriv_put(hpriv); + + return 0; +} + +/* + * hl_mmap - mmap function for habanalabs device + * + * @*filp: pointer to file structure + * @*vma: pointer to vm_area_struct of the process + * + * Called when process does an mmap on habanalabs device. Call the device's mmap + * function at the end of the common code. + */ +static int hl_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct hl_fpriv *hpriv = filp->private_data; + + if ((vma->vm_pgoff & HL_MMAP_CB_MASK) == HL_MMAP_CB_MASK) { + vma->vm_pgoff ^= HL_MMAP_CB_MASK; + return hl_cb_mmap(hpriv, vma); + } + + return -EINVAL; +} + +static const struct file_operations hl_ops = { + .owner = THIS_MODULE, + .open = hl_device_open, + .release = hl_device_release, + .mmap = hl_mmap, + .unlocked_ioctl = hl_ioctl, + .compat_ioctl = hl_ioctl +}; + +/* + * device_setup_cdev - setup cdev and device for habanalabs device + * + * @hdev: pointer to habanalabs device structure + * @hclass: pointer to the class object of the device + * @minor: minor number of the specific device + * @fpos : file operations to install for this device + * + * Create a cdev and a Linux device for habanalabs's device. Need to be + * called at the end of the habanalabs device initialization process, + * because this function exposes the device to the user + */ +static int device_setup_cdev(struct hl_device *hdev, struct class *hclass, + int minor, const struct file_operations *fops) +{ + int err, devno = MKDEV(hdev->major, minor); + struct cdev *hdev_cdev = &hdev->cdev; + char *name; + + name = kasprintf(GFP_KERNEL, "hl%d", hdev->id); + if (!name) + return -ENOMEM; + + cdev_init(hdev_cdev, fops); + hdev_cdev->owner = THIS_MODULE; + err = cdev_add(hdev_cdev, devno, 1); + if (err) { + pr_err("Failed to add char device %s\n", name); + goto err_cdev_add; + } + + hdev->dev = device_create(hclass, NULL, devno, NULL, "%s", name); + if (IS_ERR(hdev->dev)) { + pr_err("Failed to create device %s\n", name); + err = PTR_ERR(hdev->dev); + goto err_device_create; + } + + dev_set_drvdata(hdev->dev, hdev); + + kfree(name); + + return 0; + +err_device_create: + cdev_del(hdev_cdev); +err_cdev_add: + kfree(name); + return err; +} + +/* + * device_early_init - do some early initialization for the habanalabs device + * + * @hdev: pointer to habanalabs device structure + * + * Install the relevant function pointers and call the early_init function, + * if such a function exists + */ +static int device_early_init(struct hl_device *hdev) +{ + int rc; + + switch (hdev->asic_type) { + case ASIC_GOYA: + goya_set_asic_funcs(hdev); + strlcpy(hdev->asic_name, "GOYA", sizeof(hdev->asic_name)); + break; + default: + dev_err(hdev->dev, "Unrecognized ASIC type %d\n", + hdev->asic_type); + return -EINVAL; + } + + rc = hdev->asic_funcs->early_init(hdev); + if (rc) + return rc; + + rc = hl_asid_init(hdev); + if (rc) + goto early_fini; + + hdev->cq_wq = alloc_workqueue("hl-free-jobs", WQ_UNBOUND, 0); + if (hdev->cq_wq == NULL) { + dev_err(hdev->dev, "Failed to allocate CQ workqueue\n"); + rc = -ENOMEM; + goto asid_fini; + } + + hdev->eq_wq = alloc_workqueue("hl-events", WQ_UNBOUND, 0); + if (hdev->eq_wq == NULL) { + dev_err(hdev->dev, "Failed to allocate EQ workqueue\n"); + rc = -ENOMEM; + goto free_cq_wq; + } + + hdev->hl_chip_info = kzalloc(sizeof(struct hwmon_chip_info), + GFP_KERNEL); + if (!hdev->hl_chip_info) { + rc = -ENOMEM; + goto free_eq_wq; + } + + hl_cb_mgr_init(&hdev->kernel_cb_mgr); + + mutex_init(&hdev->fd_open_cnt_lock); + mutex_init(&hdev->send_cpu_message_lock); + INIT_LIST_HEAD(&hdev->hw_queues_mirror_list); + spin_lock_init(&hdev->hw_queues_mirror_lock); + atomic_set(&hdev->in_reset, 0); + atomic_set(&hdev->fd_open_cnt, 0); + + return 0; + +free_eq_wq: + destroy_workqueue(hdev->eq_wq); +free_cq_wq: + destroy_workqueue(hdev->cq_wq); +asid_fini: + hl_asid_fini(hdev); +early_fini: + if (hdev->asic_funcs->early_fini) + hdev->asic_funcs->early_fini(hdev); + + return rc; +} + +/* + * device_early_fini - finalize all that was done in device_early_init + * + * @hdev: pointer to habanalabs device structure + * + */ +static void device_early_fini(struct hl_device *hdev) +{ + mutex_destroy(&hdev->send_cpu_message_lock); + + hl_cb_mgr_fini(hdev, &hdev->kernel_cb_mgr); + + kfree(hdev->hl_chip_info); + + destroy_workqueue(hdev->eq_wq); + destroy_workqueue(hdev->cq_wq); + + hl_asid_fini(hdev); + + if (hdev->asic_funcs->early_fini) + hdev->asic_funcs->early_fini(hdev); + + mutex_destroy(&hdev->fd_open_cnt_lock); +} + +static void set_freq_to_low_job(struct work_struct *work) +{ + struct hl_device *hdev = container_of(work, struct hl_device, + work_freq.work); + + if (atomic_read(&hdev->fd_open_cnt) == 0) + hl_device_set_frequency(hdev, PLL_LOW); + + schedule_delayed_work(&hdev->work_freq, + usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC)); +} + +static void hl_device_heartbeat(struct work_struct *work) +{ + struct hl_device *hdev = container_of(work, struct hl_device, + work_heartbeat.work); + + if (hl_device_disabled_or_in_reset(hdev)) + goto reschedule; + + if (!hdev->asic_funcs->send_heartbeat(hdev)) + goto reschedule; + + dev_err(hdev->dev, "Device heartbeat failed!\n"); + hl_device_reset(hdev, true, false); + + return; + +reschedule: + schedule_delayed_work(&hdev->work_heartbeat, + usecs_to_jiffies(HL_HEARTBEAT_PER_USEC)); +} + +/* + * device_late_init - do late stuff initialization for the habanalabs device + * + * @hdev: pointer to habanalabs device structure + * + * Do stuff that either needs the device H/W queues to be active or needs + * to happen after all the rest of the initialization is finished + */ +static int device_late_init(struct hl_device *hdev) +{ + int rc; + + INIT_DELAYED_WORK(&hdev->work_freq, set_freq_to_low_job); + hdev->high_pll = hdev->asic_prop.high_pll; + + /* force setting to low frequency */ + atomic_set(&hdev->curr_pll_profile, PLL_LOW); + + if (hdev->pm_mng_profile == PM_AUTO) + hdev->asic_funcs->set_pll_profile(hdev, PLL_LOW); + else + hdev->asic_funcs->set_pll_profile(hdev, PLL_LAST); + + if (hdev->asic_funcs->late_init) { + rc = hdev->asic_funcs->late_init(hdev); + if (rc) { + dev_err(hdev->dev, + "failed late initialization for the H/W\n"); + return rc; + } + } + + schedule_delayed_work(&hdev->work_freq, + usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC)); + + if (hdev->heartbeat) { + INIT_DELAYED_WORK(&hdev->work_heartbeat, hl_device_heartbeat); + schedule_delayed_work(&hdev->work_heartbeat, + usecs_to_jiffies(HL_HEARTBEAT_PER_USEC)); + } + + hdev->late_init_done = true; + + return 0; +} + +/* + * device_late_fini - finalize all that was done in device_late_init + * + * @hdev: pointer to habanalabs device structure + * + */ +static void device_late_fini(struct hl_device *hdev) +{ + if (!hdev->late_init_done) + return; + + cancel_delayed_work_sync(&hdev->work_freq); + if (hdev->heartbeat) + cancel_delayed_work_sync(&hdev->work_heartbeat); + + if (hdev->asic_funcs->late_fini) + hdev->asic_funcs->late_fini(hdev); + + hdev->late_init_done = false; +} + +/* + * hl_device_set_frequency - set the frequency of the device + * + * @hdev: pointer to habanalabs device structure + * @freq: the new frequency value + * + * Change the frequency if needed. + * We allose to set PLL to low only if there is no user process + * Returns 0 if no change was done, otherwise returns 1; + */ +int hl_device_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq) +{ + enum hl_pll_frequency old_freq = + (freq == PLL_HIGH) ? PLL_LOW : PLL_HIGH; + int ret; + + if (hdev->pm_mng_profile == PM_MANUAL) + return 0; + + ret = atomic_cmpxchg(&hdev->curr_pll_profile, old_freq, freq); + if (ret == freq) + return 0; + + /* + * in case we want to lower frequency, check if device is not + * opened. We must have a check here to workaround race condition with + * hl_device_open + */ + if ((freq == PLL_LOW) && (atomic_read(&hdev->fd_open_cnt) > 0)) { + atomic_set(&hdev->curr_pll_profile, PLL_HIGH); + return 0; + } + + dev_dbg(hdev->dev, "Changing device frequency to %s\n", + freq == PLL_HIGH ? "high" : "low"); + + hdev->asic_funcs->set_pll_profile(hdev, freq); + + return 1; +} + +/* + * hl_device_suspend - initiate device suspend + * + * @hdev: pointer to habanalabs device structure + * + * Puts the hw in the suspend state (all asics). + * Returns 0 for success or an error on failure. + * Called at driver suspend. + */ +int hl_device_suspend(struct hl_device *hdev) +{ + int rc; + + pci_save_state(hdev->pdev); + + rc = hdev->asic_funcs->suspend(hdev); + if (rc) + dev_err(hdev->dev, + "Failed to disable PCI access of device CPU\n"); + + /* Shut down the device */ + pci_disable_device(hdev->pdev); + pci_set_power_state(hdev->pdev, PCI_D3hot); + + return 0; +} + +/* + * hl_device_resume - initiate device resume + * + * @hdev: pointer to habanalabs device structure + * + * Bring the hw back to operating state (all asics). + * Returns 0 for success or an error on failure. + * Called at driver resume. + */ +int hl_device_resume(struct hl_device *hdev) +{ + int rc; + + pci_set_power_state(hdev->pdev, PCI_D0); + pci_restore_state(hdev->pdev); + rc = pci_enable_device(hdev->pdev); + if (rc) { + dev_err(hdev->dev, + "Failed to enable PCI device in resume\n"); + return rc; + } + + rc = hdev->asic_funcs->resume(hdev); + if (rc) { + dev_err(hdev->dev, + "Failed to enable PCI access from device CPU\n"); + return rc; + } + + return 0; +} + +static void hl_device_hard_reset_pending(struct work_struct *work) +{ + struct hl_device_reset_work *device_reset_work = + container_of(work, struct hl_device_reset_work, reset_work); + struct hl_device *hdev = device_reset_work->hdev; + u16 pending_cnt = HL_PENDING_RESET_PER_SEC; + struct task_struct *task = NULL; + + /* Flush all processes that are inside hl_open */ + mutex_lock(&hdev->fd_open_cnt_lock); + + while ((atomic_read(&hdev->fd_open_cnt)) && (pending_cnt)) { + + pending_cnt--; + + dev_info(hdev->dev, + "Can't HARD reset, waiting for user to close FD\n"); + ssleep(1); + } + + if (atomic_read(&hdev->fd_open_cnt)) { + task = get_pid_task(hdev->user_ctx->hpriv->taskpid, + PIDTYPE_PID); + if (task) { + dev_info(hdev->dev, "Killing user processes\n"); + send_sig(SIGKILL, task, 1); + msleep(100); + + put_task_struct(task); + } + } + + mutex_unlock(&hdev->fd_open_cnt_lock); + + hl_device_reset(hdev, true, true); + + kfree(device_reset_work); +} + +/* + * hl_device_reset - reset the device + * + * @hdev: pointer to habanalabs device structure + * @hard_reset: should we do hard reset to all engines or just reset the + * compute/dma engines + * + * Block future CS and wait for pending CS to be enqueued + * Call ASIC H/W fini + * Flush all completions + * Re-initialize all internal data structures + * Call ASIC H/W init, late_init + * Test queues + * Enable device + * + * Returns 0 for success or an error on failure. + */ +int hl_device_reset(struct hl_device *hdev, bool hard_reset, + bool from_hard_reset_thread) +{ + int i, rc; + + if (!hdev->init_done) { + dev_err(hdev->dev, + "Can't reset before initialization is done\n"); + return 0; + } + + /* + * Prevent concurrency in this function - only one reset should be + * done at any given time. Only need to perform this if we didn't + * get from the dedicated hard reset thread + */ + if (!from_hard_reset_thread) { + /* Block future CS/VM/JOB completion operations */ + rc = atomic_cmpxchg(&hdev->in_reset, 0, 1); + if (rc) + return 0; + + /* This also blocks future CS/VM/JOB completion operations */ + hdev->disabled = true; + + /* + * Flush anyone that is inside the critical section of enqueue + * jobs to the H/W + */ + hdev->asic_funcs->hw_queues_lock(hdev); + hdev->asic_funcs->hw_queues_unlock(hdev); + + dev_err(hdev->dev, "Going to RESET device!\n"); + } + +again: + if ((hard_reset) && (!from_hard_reset_thread)) { + struct hl_device_reset_work *device_reset_work; + + if (!hdev->pdev) { + dev_err(hdev->dev, + "Reset action is NOT supported in simulator\n"); + rc = -EINVAL; + goto out_err; + } + + hdev->hard_reset_pending = true; + + device_reset_work = kzalloc(sizeof(*device_reset_work), + GFP_ATOMIC); + if (!device_reset_work) { + rc = -ENOMEM; + goto out_err; + } + + /* + * Because the reset function can't run from interrupt or + * from heartbeat work, we need to call the reset function + * from a dedicated work + */ + INIT_WORK(&device_reset_work->reset_work, + hl_device_hard_reset_pending); + device_reset_work->hdev = hdev; + schedule_work(&device_reset_work->reset_work); + + return 0; + } + + if (hard_reset) { + device_late_fini(hdev); + + /* + * Now that the heartbeat thread is closed, flush processes + * which are sending messages to CPU + */ + mutex_lock(&hdev->send_cpu_message_lock); + mutex_unlock(&hdev->send_cpu_message_lock); + } + + /* + * Halt the engines and disable interrupts so we won't get any more + * completions from H/W and we won't have any accesses from the + * H/W to the host machine + */ + hdev->asic_funcs->halt_engines(hdev, hard_reset); + + /* Go over all the queues, release all CS and their jobs */ + hl_cs_rollback_all(hdev); + + if (hard_reset) { + /* Release kernel context */ + if (hl_ctx_put(hdev->kernel_ctx) != 1) { + dev_err(hdev->dev, + "kernel ctx is alive during hard reset\n"); + rc = -EBUSY; + goto out_err; + } + + hdev->kernel_ctx = NULL; + } + + /* Reset the H/W. It will be in idle state after this returns */ + hdev->asic_funcs->hw_fini(hdev, hard_reset); + + if (hard_reset) { + hl_vm_fini(hdev); + hl_eq_reset(hdev, &hdev->event_queue); + } + + /* Re-initialize PI,CI to 0 in all queues (hw queue, cq) */ + hl_hw_queue_reset(hdev, hard_reset); + for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) + hl_cq_reset(hdev, &hdev->completion_queue[i]); + + /* Make sure the setup phase for the user context will run again */ + if (hdev->user_ctx) { + atomic_set(&hdev->user_ctx->thread_restore_token, 1); + hdev->user_ctx->thread_restore_wait_token = 0; + } + + /* Finished tear-down, starting to re-initialize */ + + if (hard_reset) { + hdev->device_cpu_disabled = false; + + /* Allocate the kernel context */ + hdev->kernel_ctx = kzalloc(sizeof(*hdev->kernel_ctx), + GFP_KERNEL); + if (!hdev->kernel_ctx) { + rc = -ENOMEM; + goto out_err; + } + + hdev->user_ctx = NULL; + + rc = hl_ctx_init(hdev, hdev->kernel_ctx, true); + if (rc) { + dev_err(hdev->dev, + "failed to init kernel ctx in hard reset\n"); + kfree(hdev->kernel_ctx); + hdev->kernel_ctx = NULL; + goto out_err; + } + } + + rc = hdev->asic_funcs->hw_init(hdev); + if (rc) { + dev_err(hdev->dev, + "failed to initialize the H/W after reset\n"); + goto out_err; + } + + hdev->disabled = false; + + /* Check that the communication with the device is working */ + rc = hdev->asic_funcs->test_queues(hdev); + if (rc) { + dev_err(hdev->dev, + "Failed to detect if device is alive after reset\n"); + goto out_err; + } + + if (hard_reset) { + rc = device_late_init(hdev); + if (rc) { + dev_err(hdev->dev, + "Failed late init after hard reset\n"); + goto out_err; + } + + rc = hl_vm_init(hdev); + if (rc) { + dev_err(hdev->dev, + "Failed to init memory module after hard reset\n"); + goto out_err; + } + + hl_set_max_power(hdev, hdev->max_power); + + hdev->hard_reset_pending = false; + } else { + rc = hdev->asic_funcs->soft_reset_late_init(hdev); + if (rc) { + dev_err(hdev->dev, + "Failed late init after soft reset\n"); + goto out_err; + } + } + + atomic_set(&hdev->in_reset, 0); + + if (hard_reset) + hdev->hard_reset_cnt++; + else + hdev->soft_reset_cnt++; + + return 0; + +out_err: + hdev->disabled = true; + + if (hard_reset) { + dev_err(hdev->dev, + "Failed to reset! Device is NOT usable\n"); + hdev->hard_reset_cnt++; + } else { + dev_err(hdev->dev, + "Failed to do soft-reset, trying hard reset\n"); + hdev->soft_reset_cnt++; + hard_reset = true; + goto again; + } + + atomic_set(&hdev->in_reset, 0); + + return rc; +} + +/* + * hl_device_init - main initialization function for habanalabs device + * + * @hdev: pointer to habanalabs device structure + * + * Allocate an id for the device, do early initialization and then call the + * ASIC specific initialization functions. Finally, create the cdev and the + * Linux device to expose it to the user + */ +int hl_device_init(struct hl_device *hdev, struct class *hclass) +{ + int i, rc, cq_ready_cnt; + + /* Create device */ + rc = device_setup_cdev(hdev, hclass, hdev->id, &hl_ops); + + if (rc) + goto out_disabled; + + /* Initialize ASIC function pointers and perform early init */ + rc = device_early_init(hdev); + if (rc) + goto release_device; + + /* + * Start calling ASIC initialization. First S/W then H/W and finally + * late init + */ + rc = hdev->asic_funcs->sw_init(hdev); + if (rc) + goto early_fini; + + /* + * Initialize the H/W queues. Must be done before hw_init, because + * there the addresses of the kernel queue are being written to the + * registers of the device + */ + rc = hl_hw_queues_create(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize kernel queues\n"); + goto sw_fini; + } + + /* + * Initialize the completion queues. Must be done before hw_init, + * because there the addresses of the completion queues are being + * passed as arguments to request_irq + */ + hdev->completion_queue = + kcalloc(hdev->asic_prop.completion_queues_count, + sizeof(*hdev->completion_queue), GFP_KERNEL); + + if (!hdev->completion_queue) { + dev_err(hdev->dev, "failed to allocate completion queues\n"); + rc = -ENOMEM; + goto hw_queues_destroy; + } + + for (i = 0, cq_ready_cnt = 0; + i < hdev->asic_prop.completion_queues_count; + i++, cq_ready_cnt++) { + rc = hl_cq_init(hdev, &hdev->completion_queue[i], i); + if (rc) { + dev_err(hdev->dev, + "failed to initialize completion queue\n"); + goto cq_fini; + } + } + + /* + * Initialize the event queue. Must be done before hw_init, + * because there the address of the event queue is being + * passed as argument to request_irq + */ + rc = hl_eq_init(hdev, &hdev->event_queue); + if (rc) { + dev_err(hdev->dev, "failed to initialize event queue\n"); + goto cq_fini; + } + + /* Allocate the kernel context */ + hdev->kernel_ctx = kzalloc(sizeof(*hdev->kernel_ctx), GFP_KERNEL); + if (!hdev->kernel_ctx) { + rc = -ENOMEM; + goto eq_fini; + } + + hdev->user_ctx = NULL; + + rc = hl_ctx_init(hdev, hdev->kernel_ctx, true); + if (rc) { + dev_err(hdev->dev, "failed to initialize kernel context\n"); + goto free_ctx; + } + + rc = hl_cb_pool_init(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize CB pool\n"); + goto release_ctx; + } + + rc = hl_sysfs_init(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize sysfs\n"); + goto free_cb_pool; + } + + hl_debugfs_add_device(hdev); + + if (hdev->asic_funcs->get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { + dev_info(hdev->dev, + "H/W state is dirty, must reset before initializing\n"); + hdev->asic_funcs->hw_fini(hdev, true); + } + + rc = hdev->asic_funcs->hw_init(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize the H/W\n"); + rc = 0; + goto out_disabled; + } + + hdev->disabled = false; + + /* Check that the communication with the device is working */ + rc = hdev->asic_funcs->test_queues(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to detect if device is alive\n"); + rc = 0; + goto out_disabled; + } + + /* After test_queues, KMD can start sending messages to device CPU */ + + rc = device_late_init(hdev); + if (rc) { + dev_err(hdev->dev, "Failed late initialization\n"); + rc = 0; + goto out_disabled; + } + + dev_info(hdev->dev, "Found %s device with %lluGB DRAM\n", + hdev->asic_name, + hdev->asic_prop.dram_size / 1024 / 1024 / 1024); + + rc = hl_vm_init(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize memory module\n"); + rc = 0; + goto out_disabled; + } + + /* + * hl_hwmon_init must be called after device_late_init, because only + * there we get the information from the device about which + * hwmon-related sensors the device supports + */ + rc = hl_hwmon_init(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize hwmon\n"); + rc = 0; + goto out_disabled; + } + + dev_notice(hdev->dev, + "Successfully added device to habanalabs driver\n"); + + hdev->init_done = true; + + return 0; + +free_cb_pool: + hl_cb_pool_fini(hdev); +release_ctx: + if (hl_ctx_put(hdev->kernel_ctx) != 1) + dev_err(hdev->dev, + "kernel ctx is still alive on initialization failure\n"); +free_ctx: + kfree(hdev->kernel_ctx); +eq_fini: + hl_eq_fini(hdev, &hdev->event_queue); +cq_fini: + for (i = 0 ; i < cq_ready_cnt ; i++) + hl_cq_fini(hdev, &hdev->completion_queue[i]); + kfree(hdev->completion_queue); +hw_queues_destroy: + hl_hw_queues_destroy(hdev); +sw_fini: + hdev->asic_funcs->sw_fini(hdev); +early_fini: + device_early_fini(hdev); +release_device: + device_destroy(hclass, hdev->dev->devt); + cdev_del(&hdev->cdev); +out_disabled: + hdev->disabled = true; + if (hdev->pdev) + dev_err(&hdev->pdev->dev, + "Failed to initialize hl%d. Device is NOT usable !\n", + hdev->id); + else + pr_err("Failed to initialize hl%d. Device is NOT usable !\n", + hdev->id); + + return rc; +} + +/* + * hl_device_fini - main tear-down function for habanalabs device + * + * @hdev: pointer to habanalabs device structure + * + * Destroy the device, call ASIC fini functions and release the id + */ +void hl_device_fini(struct hl_device *hdev) +{ + int i, rc; + ktime_t timeout; + + dev_info(hdev->dev, "Removing device\n"); + + /* + * This function is competing with the reset function, so try to + * take the reset atomic and if we are already in middle of reset, + * wait until reset function is finished. Reset function is designed + * to always finish (could take up to a few seconds in worst case). + */ + + timeout = ktime_add_us(ktime_get(), + HL_PENDING_RESET_PER_SEC * 1000 * 1000 * 4); + rc = atomic_cmpxchg(&hdev->in_reset, 0, 1); + while (rc) { + usleep_range(50, 200); + rc = atomic_cmpxchg(&hdev->in_reset, 0, 1); + if (ktime_compare(ktime_get(), timeout) > 0) { + WARN(1, "Failed to remove device because reset function did not finish\n"); + return; + } + }; + + /* Mark device as disabled */ + hdev->disabled = true; + + hl_hwmon_fini(hdev); + + device_late_fini(hdev); + + hl_debugfs_remove_device(hdev); + + hl_sysfs_fini(hdev); + + /* + * Halt the engines and disable interrupts so we won't get any more + * completions from H/W and we won't have any accesses from the + * H/W to the host machine + */ + hdev->asic_funcs->halt_engines(hdev, true); + + /* Go over all the queues, release all CS and their jobs */ + hl_cs_rollback_all(hdev); + + hl_cb_pool_fini(hdev); + + /* Release kernel context */ + if ((hdev->kernel_ctx) && (hl_ctx_put(hdev->kernel_ctx) != 1)) + dev_err(hdev->dev, "kernel ctx is still alive\n"); + + /* Reset the H/W. It will be in idle state after this returns */ + hdev->asic_funcs->hw_fini(hdev, true); + + hl_vm_fini(hdev); + + hl_eq_fini(hdev, &hdev->event_queue); + + for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) + hl_cq_fini(hdev, &hdev->completion_queue[i]); + kfree(hdev->completion_queue); + + hl_hw_queues_destroy(hdev); + + /* Call ASIC S/W finalize function */ + hdev->asic_funcs->sw_fini(hdev); + + device_early_fini(hdev); + + /* Hide device from user */ + device_destroy(hdev->dev->class, hdev->dev->devt); + cdev_del(&hdev->cdev); + + pr_info("removed device successfully\n"); +} + +/* + * hl_poll_timeout_memory - Periodically poll a host memory address + * until it is not zero or a timeout occurs + * @hdev: pointer to habanalabs device structure + * @addr: Address to poll + * @timeout_us: timeout in us + * @val: Variable to read the value into + * + * Returns 0 on success and -ETIMEDOUT upon a timeout. In either + * case, the last read value at @addr is stored in @val. Must not + * be called from atomic context if sleep_us or timeout_us are used. + * + * The function sleeps for 100us with timeout value of + * timeout_us + */ +int hl_poll_timeout_memory(struct hl_device *hdev, u64 addr, + u32 timeout_us, u32 *val) +{ + /* + * address in this function points always to a memory location in the + * host's (server's) memory. That location is updated asynchronously + * either by the direct access of the device or by another core + */ + u32 *paddr = (u32 *) (uintptr_t) addr; + ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); + + might_sleep(); + + for (;;) { + /* + * Flush CPU read/write buffers to make sure we read updates + * done by other cores or by the device + */ + mb(); + *val = *paddr; + if (*val) + break; + if (ktime_compare(ktime_get(), timeout) > 0) { + *val = *paddr; + break; + } + usleep_range((100 >> 2) + 1, 100); + } + + return *val ? 0 : -ETIMEDOUT; +} + +/* + * hl_poll_timeout_devicememory - Periodically poll a device memory address + * until it is not zero or a timeout occurs + * @hdev: pointer to habanalabs device structure + * @addr: Device address to poll + * @timeout_us: timeout in us + * @val: Variable to read the value into + * + * Returns 0 on success and -ETIMEDOUT upon a timeout. In either + * case, the last read value at @addr is stored in @val. Must not + * be called from atomic context if sleep_us or timeout_us are used. + * + * The function sleeps for 100us with timeout value of + * timeout_us + */ +int hl_poll_timeout_device_memory(struct hl_device *hdev, void __iomem *addr, + u32 timeout_us, u32 *val) +{ + ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); + + might_sleep(); + + for (;;) { + *val = readl(addr); + if (*val) + break; + if (ktime_compare(ktime_get(), timeout) > 0) { + *val = readl(addr); + break; + } + usleep_range((100 >> 2) + 1, 100); + } + + return *val ? 0 : -ETIMEDOUT; +} + +/* + * MMIO register access helper functions. + */ + +/* + * hl_rreg - Read an MMIO register + * + * @hdev: pointer to habanalabs device structure + * @reg: MMIO register offset (in bytes) + * + * Returns the value of the MMIO register we are asked to read + * + */ +inline u32 hl_rreg(struct hl_device *hdev, u32 reg) +{ + return readl(hdev->rmmio + reg); +} + +/* + * hl_wreg - Write to an MMIO register + * + * @hdev: pointer to habanalabs device structure + * @reg: MMIO register offset (in bytes) + * @val: 32-bit value + * + * Writes the 32-bit value into the MMIO register + * + */ +inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val) +{ + writel(val, hdev->rmmio + reg); +} diff --git a/drivers/misc/habanalabs/goya/Makefile b/drivers/misc/habanalabs/goya/Makefile new file mode 100644 index 000000000000..e458e5ba500b --- /dev/null +++ b/drivers/misc/habanalabs/goya/Makefile @@ -0,0 +1,3 @@ +subdir-ccflags-y += -I$(src) + +HL_GOYA_FILES := goya/goya.o goya/goya_security.o goya/goya_hwmgr.o diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c new file mode 100644 index 000000000000..238dd57c541b --- /dev/null +++ b/drivers/misc/habanalabs/goya/goya.c @@ -0,0 +1,5391 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "goyaP.h" +#include "include/hw_ip/mmu/mmu_general.h" +#include "include/hw_ip/mmu/mmu_v1_0.h" +#include "include/goya/asic_reg/goya_masks.h" + +#include <linux/pci.h> +#include <linux/genalloc.h> +#include <linux/firmware.h> +#include <linux/hwmon.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/io-64-nonatomic-hi-lo.h> + +/* + * GOYA security scheme: + * + * 1. Host is protected by: + * - Range registers (When MMU is enabled, DMA RR does NOT protect host) + * - MMU + * + * 2. DRAM is protected by: + * - Range registers (protect the first 512MB) + * - MMU (isolation between users) + * + * 3. Configuration is protected by: + * - Range registers + * - Protection bits + * + * When MMU is disabled: + * + * QMAN DMA: PQ, CQ, CP, DMA are secured. + * PQ, CB and the data are on the host. + * + * QMAN TPC/MME: + * PQ, CQ and CP are not secured. + * PQ, CB and the data are on the SRAM/DRAM. + * + * Since QMAN DMA is secured, KMD is parsing the DMA CB: + * - KMD checks DMA pointer + * - WREG, MSG_PROT are not allowed. + * - MSG_LONG/SHORT are allowed. + * + * A read/write transaction by the QMAN to a protected area will succeed if + * and only if the QMAN's CP is secured and MSG_PROT is used + * + * + * When MMU is enabled: + * + * QMAN DMA: PQ, CQ and CP are secured. + * MMU is set to bypass on the Secure props register of the QMAN. + * The reasons we don't enable MMU for PQ, CQ and CP are: + * - PQ entry is in kernel address space and KMD doesn't map it. + * - CP writes to MSIX register and to kernel address space (completion + * queue). + * + * DMA is not secured but because CP is secured, KMD still needs to parse the + * CB, but doesn't need to check the DMA addresses. + * + * For QMAN DMA 0, DMA is also secured because only KMD uses this DMA and KMD + * doesn't map memory in MMU. + * + * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode) + * + * DMA RR does NOT protect host because DMA is not secured + * + */ + +#define GOYA_MMU_REGS_NUM 61 + +#define GOYA_DMA_POOL_BLK_SIZE 0x100 /* 256 bytes */ + +#define GOYA_RESET_TIMEOUT_MSEC 500 /* 500ms */ +#define GOYA_PLDM_RESET_TIMEOUT_MSEC 20000 /* 20s */ +#define GOYA_RESET_WAIT_MSEC 1 /* 1ms */ +#define GOYA_CPU_RESET_WAIT_MSEC 100 /* 100ms */ +#define GOYA_PLDM_RESET_WAIT_MSEC 1000 /* 1s */ +#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */ +#define GOYA_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ +#define GOYA_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100) +#define GOYA_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) + +#define GOYA_QMAN0_FENCE_VAL 0xD169B243 + +#define GOYA_MAX_INITIATORS 20 + +#define GOYA_MAX_STRING_LEN 20 + +#define GOYA_CB_POOL_CB_CNT 512 +#define GOYA_CB_POOL_CB_SIZE 0x20000 /* 128KB */ + +static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = { + "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3", + "goya cq 4", "goya cpu eq" +}; + +static u16 goya_packet_sizes[MAX_PACKET_ID] = { + [PACKET_WREG_32] = sizeof(struct packet_wreg32), + [PACKET_WREG_BULK] = sizeof(struct packet_wreg_bulk), + [PACKET_MSG_LONG] = sizeof(struct packet_msg_long), + [PACKET_MSG_SHORT] = sizeof(struct packet_msg_short), + [PACKET_CP_DMA] = sizeof(struct packet_cp_dma), + [PACKET_MSG_PROT] = sizeof(struct packet_msg_prot), + [PACKET_FENCE] = sizeof(struct packet_fence), + [PACKET_LIN_DMA] = sizeof(struct packet_lin_dma), + [PACKET_NOP] = sizeof(struct packet_nop), + [PACKET_STOP] = sizeof(struct packet_stop) +}; + +static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = { + mmDMA_QM_0_GLBL_NON_SECURE_PROPS, + mmDMA_QM_1_GLBL_NON_SECURE_PROPS, + mmDMA_QM_2_GLBL_NON_SECURE_PROPS, + mmDMA_QM_3_GLBL_NON_SECURE_PROPS, + mmDMA_QM_4_GLBL_NON_SECURE_PROPS, + mmTPC0_QM_GLBL_SECURE_PROPS, + mmTPC0_QM_GLBL_NON_SECURE_PROPS, + mmTPC0_CMDQ_GLBL_SECURE_PROPS, + mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC0_CFG_ARUSER, + mmTPC0_CFG_AWUSER, + mmTPC1_QM_GLBL_SECURE_PROPS, + mmTPC1_QM_GLBL_NON_SECURE_PROPS, + mmTPC1_CMDQ_GLBL_SECURE_PROPS, + mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC1_CFG_ARUSER, + mmTPC1_CFG_AWUSER, + mmTPC2_QM_GLBL_SECURE_PROPS, + mmTPC2_QM_GLBL_NON_SECURE_PROPS, + mmTPC2_CMDQ_GLBL_SECURE_PROPS, + mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC2_CFG_ARUSER, + mmTPC2_CFG_AWUSER, + mmTPC3_QM_GLBL_SECURE_PROPS, + mmTPC3_QM_GLBL_NON_SECURE_PROPS, + mmTPC3_CMDQ_GLBL_SECURE_PROPS, + mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC3_CFG_ARUSER, + mmTPC3_CFG_AWUSER, + mmTPC4_QM_GLBL_SECURE_PROPS, + mmTPC4_QM_GLBL_NON_SECURE_PROPS, + mmTPC4_CMDQ_GLBL_SECURE_PROPS, + mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC4_CFG_ARUSER, + mmTPC4_CFG_AWUSER, + mmTPC5_QM_GLBL_SECURE_PROPS, + mmTPC5_QM_GLBL_NON_SECURE_PROPS, + mmTPC5_CMDQ_GLBL_SECURE_PROPS, + mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC5_CFG_ARUSER, + mmTPC5_CFG_AWUSER, + mmTPC6_QM_GLBL_SECURE_PROPS, + mmTPC6_QM_GLBL_NON_SECURE_PROPS, + mmTPC6_CMDQ_GLBL_SECURE_PROPS, + mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC6_CFG_ARUSER, + mmTPC6_CFG_AWUSER, + mmTPC7_QM_GLBL_SECURE_PROPS, + mmTPC7_QM_GLBL_NON_SECURE_PROPS, + mmTPC7_CMDQ_GLBL_SECURE_PROPS, + mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS, + mmTPC7_CFG_ARUSER, + mmTPC7_CFG_AWUSER, + mmMME_QM_GLBL_SECURE_PROPS, + mmMME_QM_GLBL_NON_SECURE_PROPS, + mmMME_CMDQ_GLBL_SECURE_PROPS, + mmMME_CMDQ_GLBL_NON_SECURE_PROPS, + mmMME_SBA_CONTROL_DATA, + mmMME_SBB_CONTROL_DATA, + mmMME_SBC_CONTROL_DATA, + mmMME_WBC_CONTROL_DATA +}; + +#define GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE 121 + +static u32 goya_non_fatal_events[GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE] = { + GOYA_ASYNC_EVENT_ID_PCIE_IF, + GOYA_ASYNC_EVENT_ID_TPC0_ECC, + GOYA_ASYNC_EVENT_ID_TPC1_ECC, + GOYA_ASYNC_EVENT_ID_TPC2_ECC, + GOYA_ASYNC_EVENT_ID_TPC3_ECC, + GOYA_ASYNC_EVENT_ID_TPC4_ECC, + GOYA_ASYNC_EVENT_ID_TPC5_ECC, + GOYA_ASYNC_EVENT_ID_TPC6_ECC, + GOYA_ASYNC_EVENT_ID_TPC7_ECC, + GOYA_ASYNC_EVENT_ID_MME_ECC, + GOYA_ASYNC_EVENT_ID_MME_ECC_EXT, + GOYA_ASYNC_EVENT_ID_MMU_ECC, + GOYA_ASYNC_EVENT_ID_DMA_MACRO, + GOYA_ASYNC_EVENT_ID_DMA_ECC, + GOYA_ASYNC_EVENT_ID_CPU_IF_ECC, + GOYA_ASYNC_EVENT_ID_PSOC_MEM, + GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT, + GOYA_ASYNC_EVENT_ID_SRAM0, + GOYA_ASYNC_EVENT_ID_SRAM1, + GOYA_ASYNC_EVENT_ID_SRAM2, + GOYA_ASYNC_EVENT_ID_SRAM3, + GOYA_ASYNC_EVENT_ID_SRAM4, + GOYA_ASYNC_EVENT_ID_SRAM5, + GOYA_ASYNC_EVENT_ID_SRAM6, + GOYA_ASYNC_EVENT_ID_SRAM7, + GOYA_ASYNC_EVENT_ID_SRAM8, + GOYA_ASYNC_EVENT_ID_SRAM9, + GOYA_ASYNC_EVENT_ID_SRAM10, + GOYA_ASYNC_EVENT_ID_SRAM11, + GOYA_ASYNC_EVENT_ID_SRAM12, + GOYA_ASYNC_EVENT_ID_SRAM13, + GOYA_ASYNC_EVENT_ID_SRAM14, + GOYA_ASYNC_EVENT_ID_SRAM15, + GOYA_ASYNC_EVENT_ID_SRAM16, + GOYA_ASYNC_EVENT_ID_SRAM17, + GOYA_ASYNC_EVENT_ID_SRAM18, + GOYA_ASYNC_EVENT_ID_SRAM19, + GOYA_ASYNC_EVENT_ID_SRAM20, + GOYA_ASYNC_EVENT_ID_SRAM21, + GOYA_ASYNC_EVENT_ID_SRAM22, + GOYA_ASYNC_EVENT_ID_SRAM23, + GOYA_ASYNC_EVENT_ID_SRAM24, + GOYA_ASYNC_EVENT_ID_SRAM25, + GOYA_ASYNC_EVENT_ID_SRAM26, + GOYA_ASYNC_EVENT_ID_SRAM27, + GOYA_ASYNC_EVENT_ID_SRAM28, + GOYA_ASYNC_EVENT_ID_SRAM29, + GOYA_ASYNC_EVENT_ID_GIC500, + GOYA_ASYNC_EVENT_ID_PLL0, + GOYA_ASYNC_EVENT_ID_PLL1, + GOYA_ASYNC_EVENT_ID_PLL3, + GOYA_ASYNC_EVENT_ID_PLL4, + GOYA_ASYNC_EVENT_ID_PLL5, + GOYA_ASYNC_EVENT_ID_PLL6, + GOYA_ASYNC_EVENT_ID_AXI_ECC, + GOYA_ASYNC_EVENT_ID_L2_RAM_ECC, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT, + GOYA_ASYNC_EVENT_ID_PCIE_DEC, + GOYA_ASYNC_EVENT_ID_TPC0_DEC, + GOYA_ASYNC_EVENT_ID_TPC1_DEC, + GOYA_ASYNC_EVENT_ID_TPC2_DEC, + GOYA_ASYNC_EVENT_ID_TPC3_DEC, + GOYA_ASYNC_EVENT_ID_TPC4_DEC, + GOYA_ASYNC_EVENT_ID_TPC5_DEC, + GOYA_ASYNC_EVENT_ID_TPC6_DEC, + GOYA_ASYNC_EVENT_ID_TPC7_DEC, + GOYA_ASYNC_EVENT_ID_MME_WACS, + GOYA_ASYNC_EVENT_ID_MME_WACSD, + GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER, + GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC, + GOYA_ASYNC_EVENT_ID_PSOC, + GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR, + GOYA_ASYNC_EVENT_ID_TPC0_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC1_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC2_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC3_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC4_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC5_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC6_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC7_CMDQ, + GOYA_ASYNC_EVENT_ID_TPC0_QM, + GOYA_ASYNC_EVENT_ID_TPC1_QM, + GOYA_ASYNC_EVENT_ID_TPC2_QM, + GOYA_ASYNC_EVENT_ID_TPC3_QM, + GOYA_ASYNC_EVENT_ID_TPC4_QM, + GOYA_ASYNC_EVENT_ID_TPC5_QM, + GOYA_ASYNC_EVENT_ID_TPC6_QM, + GOYA_ASYNC_EVENT_ID_TPC7_QM, + GOYA_ASYNC_EVENT_ID_MME_QM, + GOYA_ASYNC_EVENT_ID_MME_CMDQ, + GOYA_ASYNC_EVENT_ID_DMA0_QM, + GOYA_ASYNC_EVENT_ID_DMA1_QM, + GOYA_ASYNC_EVENT_ID_DMA2_QM, + GOYA_ASYNC_EVENT_ID_DMA3_QM, + GOYA_ASYNC_EVENT_ID_DMA4_QM, + GOYA_ASYNC_EVENT_ID_DMA0_CH, + GOYA_ASYNC_EVENT_ID_DMA1_CH, + GOYA_ASYNC_EVENT_ID_DMA2_CH, + GOYA_ASYNC_EVENT_ID_DMA3_CH, + GOYA_ASYNC_EVENT_ID_DMA4_CH, + GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH0, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH1, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH2, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH3, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH4 +}; + +static int goya_armcp_info_get(struct hl_device *hdev); +static void goya_mmu_prepare(struct hl_device *hdev, u32 asid); +static int goya_mmu_clear_pgt_range(struct hl_device *hdev); +static int goya_mmu_set_dram_default_page(struct hl_device *hdev); +static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid, + u64 phys_addr); + +static void goya_get_fixed_properties(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int i; + + for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) { + prop->hw_queues_props[i].type = QUEUE_TYPE_EXT; + prop->hw_queues_props[i].kmd_only = 0; + } + + for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) { + prop->hw_queues_props[i].type = QUEUE_TYPE_CPU; + prop->hw_queues_props[i].kmd_only = 1; + } + + for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES + + NUMBER_OF_INT_HW_QUEUES; i++) { + prop->hw_queues_props[i].type = QUEUE_TYPE_INT; + prop->hw_queues_props[i].kmd_only = 0; + } + + for (; i < HL_MAX_QUEUES; i++) + prop->hw_queues_props[i].type = QUEUE_TYPE_NA; + + prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; + + prop->dram_base_address = DRAM_PHYS_BASE; + prop->dram_size = DRAM_PHYS_DEFAULT_SIZE; + prop->dram_end_address = prop->dram_base_address + prop->dram_size; + prop->dram_user_base_address = DRAM_BASE_ADDR_USER; + + prop->sram_base_address = SRAM_BASE_ADDR; + prop->sram_size = SRAM_SIZE; + prop->sram_end_address = prop->sram_base_address + prop->sram_size; + prop->sram_user_base_address = prop->sram_base_address + + SRAM_USER_BASE_OFFSET; + + prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR; + prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR; + if (hdev->pldm) + prop->mmu_pgt_size = 0x800000; /* 8MB */ + else + prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE; + prop->mmu_pte_size = HL_PTE_SIZE; + prop->mmu_hop_table_size = HOP_TABLE_SIZE; + prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE; + prop->dram_page_size = PAGE_SIZE_2MB; + + prop->host_phys_base_address = HOST_PHYS_BASE; + prop->va_space_host_start_address = VA_HOST_SPACE_START; + prop->va_space_host_end_address = VA_HOST_SPACE_END; + prop->va_space_dram_start_address = VA_DDR_SPACE_START; + prop->va_space_dram_end_address = VA_DDR_SPACE_END; + prop->dram_size_for_default_page_mapping = + prop->va_space_dram_end_address; + prop->cfg_size = CFG_SIZE; + prop->max_asid = MAX_ASID; + prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE; + prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT; + prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE; + prop->max_power_default = MAX_POWER_DEFAULT; + prop->tpc_enabled_mask = TPC_ENABLED_MASK; + + prop->high_pll = PLL_HIGH_DEFAULT; +} + +int goya_send_pci_access_msg(struct hl_device *hdev, u32 opcode) +{ + struct armcp_packet pkt; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(opcode << ARMCP_PKT_CTL_OPCODE_SHIFT); + + return hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, + sizeof(pkt), HL_DEVICE_TIMEOUT_USEC, NULL); +} + +/* + * goya_pci_bars_map - Map PCI BARS of Goya device + * + * @hdev: pointer to hl_device structure + * + * Request PCI regions and map them to kernel virtual addresses. + * Returns 0 on success + * + */ +static int goya_pci_bars_map(struct hl_device *hdev) +{ + struct pci_dev *pdev = hdev->pdev; + int rc; + + rc = pci_request_regions(pdev, HL_NAME); + if (rc) { + dev_err(hdev->dev, "Cannot obtain PCI resources\n"); + return rc; + } + + hdev->pcie_bar[SRAM_CFG_BAR_ID] = + pci_ioremap_bar(pdev, SRAM_CFG_BAR_ID); + if (!hdev->pcie_bar[SRAM_CFG_BAR_ID]) { + dev_err(hdev->dev, "pci_ioremap_bar failed for CFG\n"); + rc = -ENODEV; + goto err_release_regions; + } + + hdev->pcie_bar[MSIX_BAR_ID] = pci_ioremap_bar(pdev, MSIX_BAR_ID); + if (!hdev->pcie_bar[MSIX_BAR_ID]) { + dev_err(hdev->dev, "pci_ioremap_bar failed for MSIX\n"); + rc = -ENODEV; + goto err_unmap_sram_cfg; + } + + hdev->pcie_bar[DDR_BAR_ID] = pci_ioremap_wc_bar(pdev, DDR_BAR_ID); + if (!hdev->pcie_bar[DDR_BAR_ID]) { + dev_err(hdev->dev, "pci_ioremap_bar failed for DDR\n"); + rc = -ENODEV; + goto err_unmap_msix; + } + + hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + + (CFG_BASE - SRAM_BASE_ADDR); + + return 0; + +err_unmap_msix: + iounmap(hdev->pcie_bar[MSIX_BAR_ID]); +err_unmap_sram_cfg: + iounmap(hdev->pcie_bar[SRAM_CFG_BAR_ID]); +err_release_regions: + pci_release_regions(pdev); + + return rc; +} + +/* + * goya_pci_bars_unmap - Unmap PCI BARS of Goya device + * + * @hdev: pointer to hl_device structure + * + * Release all PCI BARS and unmap their virtual addresses + * + */ +static void goya_pci_bars_unmap(struct hl_device *hdev) +{ + struct pci_dev *pdev = hdev->pdev; + + iounmap(hdev->pcie_bar[DDR_BAR_ID]); + iounmap(hdev->pcie_bar[MSIX_BAR_ID]); + iounmap(hdev->pcie_bar[SRAM_CFG_BAR_ID]); + pci_release_regions(pdev); +} + +/* + * goya_elbi_write - Write through the ELBI interface + * + * @hdev: pointer to hl_device structure + * + * return 0 on success, -1 on failure + * + */ +static int goya_elbi_write(struct hl_device *hdev, u64 addr, u32 data) +{ + struct pci_dev *pdev = hdev->pdev; + ktime_t timeout; + u32 val; + + /* Clear previous status */ + pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0); + + pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr); + pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data); + pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL, + PCI_CONFIG_ELBI_CTRL_WRITE); + + timeout = ktime_add_ms(ktime_get(), 10); + for (;;) { + pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val); + if (val & PCI_CONFIG_ELBI_STS_MASK) + break; + if (ktime_compare(ktime_get(), timeout) > 0) { + pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, + &val); + break; + } + usleep_range(300, 500); + } + + if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE) + return 0; + + if (val & PCI_CONFIG_ELBI_STS_ERR) { + dev_err(hdev->dev, "Error writing to ELBI\n"); + return -EIO; + } + + if (!(val & PCI_CONFIG_ELBI_STS_MASK)) { + dev_err(hdev->dev, "ELBI write didn't finish in time\n"); + return -EIO; + } + + dev_err(hdev->dev, "ELBI write has undefined bits in status\n"); + return -EIO; +} + +/* + * goya_iatu_write - iatu write routine + * + * @hdev: pointer to hl_device structure + * + */ +static int goya_iatu_write(struct hl_device *hdev, u32 addr, u32 data) +{ + u32 dbi_offset; + int rc; + + dbi_offset = addr & 0xFFF; + + rc = goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0x00300000); + rc |= goya_elbi_write(hdev, mmPCIE_DBI_BASE + dbi_offset, data); + + if (rc) + return -EIO; + + return 0; +} + +static void goya_reset_link_through_bridge(struct hl_device *hdev) +{ + struct pci_dev *pdev = hdev->pdev; + struct pci_dev *parent_port; + u16 val; + + parent_port = pdev->bus->self; + pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val); + val |= PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val); + ssleep(1); + + val &= ~(PCI_BRIDGE_CTL_BUS_RESET); + pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val); + ssleep(3); +} + +/* + * goya_set_ddr_bar_base - set DDR bar to map specific device address + * + * @hdev: pointer to hl_device structure + * @addr: address in DDR. Must be aligned to DDR bar size + * + * This function configures the iATU so that the DDR bar will start at the + * specified addr. + * + */ +static int goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr) +{ + struct goya_device *goya = hdev->asic_specific; + int rc; + + if ((goya) && (goya->ddr_bar_cur_addr == addr)) + return 0; + + /* Inbound Region 1 - Bar 4 - Point to DDR */ + rc = goya_iatu_write(hdev, 0x314, lower_32_bits(addr)); + rc |= goya_iatu_write(hdev, 0x318, upper_32_bits(addr)); + rc |= goya_iatu_write(hdev, 0x300, 0); + /* Enable + Bar match + match enable + Bar 4 */ + rc |= goya_iatu_write(hdev, 0x304, 0xC0080400); + + /* Return the DBI window to the default location */ + rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0); + rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI_32, 0); + + if (rc) { + dev_err(hdev->dev, "failed to map DDR bar to 0x%08llx\n", addr); + return -EIO; + } + + if (goya) + goya->ddr_bar_cur_addr = addr; + + return 0; +} + +/* + * goya_init_iatu - Initialize the iATU unit inside the PCI controller + * + * @hdev: pointer to hl_device structure + * + * This is needed in case the firmware doesn't initialize the iATU + * + */ +static int goya_init_iatu(struct hl_device *hdev) +{ + int rc; + + /* Inbound Region 0 - Bar 0 - Point to SRAM_BASE_ADDR */ + rc = goya_iatu_write(hdev, 0x114, lower_32_bits(SRAM_BASE_ADDR)); + rc |= goya_iatu_write(hdev, 0x118, upper_32_bits(SRAM_BASE_ADDR)); + rc |= goya_iatu_write(hdev, 0x100, 0); + /* Enable + Bar match + match enable */ + rc |= goya_iatu_write(hdev, 0x104, 0xC0080000); + + /* Inbound Region 1 - Bar 4 - Point to DDR */ + rc |= goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE); + + /* Outbound Region 0 - Point to Host */ + rc |= goya_iatu_write(hdev, 0x008, lower_32_bits(HOST_PHYS_BASE)); + rc |= goya_iatu_write(hdev, 0x00C, upper_32_bits(HOST_PHYS_BASE)); + rc |= goya_iatu_write(hdev, 0x010, + lower_32_bits(HOST_PHYS_BASE + HOST_PHYS_SIZE - 1)); + rc |= goya_iatu_write(hdev, 0x014, 0); + rc |= goya_iatu_write(hdev, 0x018, 0); + rc |= goya_iatu_write(hdev, 0x020, + upper_32_bits(HOST_PHYS_BASE + HOST_PHYS_SIZE - 1)); + /* Increase region size */ + rc |= goya_iatu_write(hdev, 0x000, 0x00002000); + /* Enable */ + rc |= goya_iatu_write(hdev, 0x004, 0x80000000); + + /* Return the DBI window to the default location */ + rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0); + rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI_32, 0); + + if (rc) + return -EIO; + + return 0; +} + +/* + * goya_early_init - GOYA early initialization code + * + * @hdev: pointer to hl_device structure + * + * Verify PCI bars + * Set DMA masks + * PCI controller initialization + * Map PCI bars + * + */ +static int goya_early_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct pci_dev *pdev = hdev->pdev; + u32 val; + int rc; + + goya_get_fixed_properties(hdev); + + /* Check BAR sizes */ + if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) { + dev_err(hdev->dev, + "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", + SRAM_CFG_BAR_ID, + (unsigned long long) pci_resource_len(pdev, + SRAM_CFG_BAR_ID), + CFG_BAR_SIZE); + return -ENODEV; + } + + if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) { + dev_err(hdev->dev, + "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", + MSIX_BAR_ID, + (unsigned long long) pci_resource_len(pdev, + MSIX_BAR_ID), + MSIX_BAR_SIZE); + return -ENODEV; + } + + prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID); + + /* set DMA mask for GOYA */ + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(39)); + if (rc) { + dev_warn(hdev->dev, "Unable to set pci dma mask to 39 bits\n"); + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (rc) { + dev_err(hdev->dev, + "Unable to set pci dma mask to 32 bits\n"); + return rc; + } + } + + rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); + if (rc) { + dev_warn(hdev->dev, + "Unable to set pci consistent dma mask to 39 bits\n"); + rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + if (rc) { + dev_err(hdev->dev, + "Unable to set pci consistent dma mask to 32 bits\n"); + return rc; + } + } + + if (hdev->reset_pcilink) + goya_reset_link_through_bridge(hdev); + + rc = pci_enable_device_mem(pdev); + if (rc) { + dev_err(hdev->dev, "can't enable PCI device\n"); + return rc; + } + + pci_set_master(pdev); + + rc = goya_init_iatu(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize iATU\n"); + goto disable_device; + } + + rc = goya_pci_bars_map(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize PCI BARS\n"); + goto disable_device; + } + + if (!hdev->pldm) { + val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); + if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK) + dev_warn(hdev->dev, + "PCI strap is not configured correctly, PCI bus errors may occur\n"); + } + + return 0; + +disable_device: + pci_clear_master(pdev); + pci_disable_device(pdev); + + return rc; +} + +/* + * goya_early_fini - GOYA early finalization code + * + * @hdev: pointer to hl_device structure + * + * Unmap PCI bars + * + */ +static int goya_early_fini(struct hl_device *hdev) +{ + goya_pci_bars_unmap(hdev); + + pci_clear_master(hdev->pdev); + pci_disable_device(hdev->pdev); + + return 0; +} + +/* + * goya_fetch_psoc_frequency - Fetch PSOC frequency values + * + * @hdev: pointer to hl_device structure + * + */ +static void goya_fetch_psoc_frequency(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR); + prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF); + prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD); + prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1); +} + +/* + * goya_late_init - GOYA late initialization code + * + * @hdev: pointer to hl_device structure + * + * Get ArmCP info and send message to CPU to enable PCI access + */ +static int goya_late_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct goya_device *goya = hdev->asic_specific; + int rc; + + rc = goya->armcp_info_get(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to get armcp info\n"); + return rc; + } + + /* Now that we have the DRAM size in ASIC prop, we need to check + * its size and configure the DMA_IF DDR wrap protection (which is in + * the MMU block) accordingly. The value is the log2 of the DRAM size + */ + WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); + + rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS); + if (rc) { + dev_err(hdev->dev, "Failed to enable PCI access from CPU\n"); + return rc; + } + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GOYA_ASYNC_EVENT_ID_INTS_REGISTER); + + goya_fetch_psoc_frequency(hdev); + + rc = goya_mmu_clear_pgt_range(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to clear MMU page tables range\n"); + goto disable_pci_access; + } + + rc = goya_mmu_set_dram_default_page(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to set DRAM default page\n"); + goto disable_pci_access; + } + + return 0; + +disable_pci_access: + goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + + return rc; +} + +/* + * goya_late_fini - GOYA late tear-down code + * + * @hdev: pointer to hl_device structure + * + * Free sensors allocated structures + */ +void goya_late_fini(struct hl_device *hdev) +{ + const struct hwmon_channel_info **channel_info_arr; + int i = 0; + + if (!hdev->hl_chip_info->info) + return; + + channel_info_arr = hdev->hl_chip_info->info; + + while (channel_info_arr[i]) { + kfree(channel_info_arr[i]->config); + kfree(channel_info_arr[i]); + i++; + } + + kfree(channel_info_arr); + + hdev->hl_chip_info->info = NULL; +} + +/* + * goya_sw_init - Goya software initialization code + * + * @hdev: pointer to hl_device structure + * + */ +static int goya_sw_init(struct hl_device *hdev) +{ + struct goya_device *goya; + int rc; + + /* Allocate device structure */ + goya = kzalloc(sizeof(*goya), GFP_KERNEL); + if (!goya) + return -ENOMEM; + + goya->test_cpu_queue = goya_test_cpu_queue; + goya->armcp_info_get = goya_armcp_info_get; + + /* according to goya_init_iatu */ + goya->ddr_bar_cur_addr = DRAM_PHYS_BASE; + + goya->mme_clk = GOYA_PLL_FREQ_LOW; + goya->tpc_clk = GOYA_PLL_FREQ_LOW; + goya->ic_clk = GOYA_PLL_FREQ_LOW; + + hdev->asic_specific = goya; + + /* Create DMA pool for small allocations */ + hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), + &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0); + if (!hdev->dma_pool) { + dev_err(hdev->dev, "failed to create DMA pool\n"); + rc = -ENOMEM; + goto free_goya_device; + } + + hdev->cpu_accessible_dma_mem = + hdev->asic_funcs->dma_alloc_coherent(hdev, + CPU_ACCESSIBLE_MEM_SIZE, + &hdev->cpu_accessible_dma_address, + GFP_KERNEL | __GFP_ZERO); + + if (!hdev->cpu_accessible_dma_mem) { + dev_err(hdev->dev, + "failed to allocate %d of dma memory for CPU accessible memory space\n", + CPU_ACCESSIBLE_MEM_SIZE); + rc = -ENOMEM; + goto free_dma_pool; + } + + hdev->cpu_accessible_dma_pool = gen_pool_create(CPU_PKT_SHIFT, -1); + if (!hdev->cpu_accessible_dma_pool) { + dev_err(hdev->dev, + "Failed to create CPU accessible DMA pool\n"); + rc = -ENOMEM; + goto free_cpu_pq_dma_mem; + } + + rc = gen_pool_add(hdev->cpu_accessible_dma_pool, + (uintptr_t) hdev->cpu_accessible_dma_mem, + CPU_ACCESSIBLE_MEM_SIZE, -1); + if (rc) { + dev_err(hdev->dev, + "Failed to add memory to CPU accessible DMA pool\n"); + rc = -EFAULT; + goto free_cpu_pq_pool; + } + + spin_lock_init(&goya->hw_queues_lock); + + return 0; + +free_cpu_pq_pool: + gen_pool_destroy(hdev->cpu_accessible_dma_pool); +free_cpu_pq_dma_mem: + hdev->asic_funcs->dma_free_coherent(hdev, CPU_ACCESSIBLE_MEM_SIZE, + hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); +free_dma_pool: + dma_pool_destroy(hdev->dma_pool); +free_goya_device: + kfree(goya); + + return rc; +} + +/* + * goya_sw_fini - Goya software tear-down code + * + * @hdev: pointer to hl_device structure + * + */ +static int goya_sw_fini(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + + gen_pool_destroy(hdev->cpu_accessible_dma_pool); + + hdev->asic_funcs->dma_free_coherent(hdev, CPU_ACCESSIBLE_MEM_SIZE, + hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); + + dma_pool_destroy(hdev->dma_pool); + + kfree(goya); + + return 0; +} + +static void goya_init_dma_qman(struct hl_device *hdev, int dma_id, + dma_addr_t bus_address) +{ + struct goya_device *goya = hdev->asic_specific; + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 gic_base_lo, gic_base_hi; + u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); + + mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + + gic_base_lo = + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + gic_base_hi = + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + + WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); + WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); + + WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); + WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); + WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); + + WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); + WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); + WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); + WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); + WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); + WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); + WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off, + GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id); + + /* PQ has buffer of 2 cache lines, while CQ has 8 lines */ + WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002); + WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008); + + if (goya->hw_cap_initialized & HW_CAP_MMU) + WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED); + else + WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED); + + WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN); + WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE); +} + +static void goya_init_dma_ch(struct hl_device *hdev, int dma_id) +{ + u32 gic_base_lo, gic_base_hi; + u64 sob_addr; + u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1); + + gic_base_lo = + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + gic_base_hi = + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + + WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo); + WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi); + WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off, + GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id); + + if (dma_id) + sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 + + (dma_id - 1) * 4; + else + sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007; + + WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + reg_off, lower_32_bits(sob_addr)); + WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr)); + WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001); +} + +/* + * goya_init_dma_qmans - Initialize QMAN DMA registers + * + * @hdev: pointer to hl_device structure + * + * Initialize the H/W registers of the QMAN DMA channels + * + */ +static void goya_init_dma_qmans(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + struct hl_hw_queue *q; + dma_addr_t bus_address; + int i; + + if (goya->hw_cap_initialized & HW_CAP_DMA) + return; + + q = &hdev->kernel_queues[0]; + + for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) { + bus_address = q->bus_address + + hdev->asic_prop.host_phys_base_address; + + goya_init_dma_qman(hdev, i, bus_address); + goya_init_dma_ch(hdev, i); + } + + goya->hw_cap_initialized |= HW_CAP_DMA; +} + +/* + * goya_disable_external_queues - Disable external queues + * + * @hdev: pointer to hl_device structure + * + */ +static void goya_disable_external_queues(struct hl_device *hdev) +{ + WREG32(mmDMA_QM_0_GLBL_CFG0, 0); + WREG32(mmDMA_QM_1_GLBL_CFG0, 0); + WREG32(mmDMA_QM_2_GLBL_CFG0, 0); + WREG32(mmDMA_QM_3_GLBL_CFG0, 0); + WREG32(mmDMA_QM_4_GLBL_CFG0, 0); +} + +static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg, + u32 cp_sts_reg, u32 glbl_sts0_reg) +{ + int rc; + u32 status; + + /* use the values of TPC0 as they are all the same*/ + + WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + + status = RREG32(cp_sts_reg); + if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) { + rc = hl_poll_timeout( + hdev, + cp_sts_reg, + status, + !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK), + 1000, + QMAN_FENCE_TIMEOUT_USEC); + + /* if QMAN is stuck in fence no need to check for stop */ + if (rc) + return 0; + } + + rc = hl_poll_timeout( + hdev, + glbl_sts0_reg, + status, + (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK), + 1000, + QMAN_STOP_TIMEOUT_USEC); + + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for QMAN to stop\n"); + return -EINVAL; + } + + return 0; +} + +/* + * goya_stop_external_queues - Stop external queues + * + * @hdev: pointer to hl_device structure + * + * Returns 0 on success + * + */ +static int goya_stop_external_queues(struct hl_device *hdev) +{ + int rc, retval = 0; + + rc = goya_stop_queue(hdev, + mmDMA_QM_0_GLBL_CFG1, + mmDMA_QM_0_CP_STS, + mmDMA_QM_0_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop DMA QMAN 0\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmDMA_QM_1_GLBL_CFG1, + mmDMA_QM_1_CP_STS, + mmDMA_QM_1_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop DMA QMAN 1\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmDMA_QM_2_GLBL_CFG1, + mmDMA_QM_2_CP_STS, + mmDMA_QM_2_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop DMA QMAN 2\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmDMA_QM_3_GLBL_CFG1, + mmDMA_QM_3_CP_STS, + mmDMA_QM_3_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop DMA QMAN 3\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmDMA_QM_4_GLBL_CFG1, + mmDMA_QM_4_CP_STS, + mmDMA_QM_4_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop DMA QMAN 4\n"); + retval = -EIO; + } + + return retval; +} + +static void goya_resume_external_queues(struct hl_device *hdev) +{ + WREG32(mmDMA_QM_0_GLBL_CFG1, 0); + WREG32(mmDMA_QM_1_GLBL_CFG1, 0); + WREG32(mmDMA_QM_2_GLBL_CFG1, 0); + WREG32(mmDMA_QM_3_GLBL_CFG1, 0); + WREG32(mmDMA_QM_4_GLBL_CFG1, 0); +} + +/* + * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU + * + * @hdev: pointer to hl_device structure + * + * Returns 0 on success + * + */ +static int goya_init_cpu_queues(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + struct hl_eq *eq; + dma_addr_t bus_address; + u32 status; + struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ]; + int err; + + if (!hdev->cpu_queues_enable) + return 0; + + if (goya->hw_cap_initialized & HW_CAP_CPU_Q) + return 0; + + eq = &hdev->event_queue; + + bus_address = cpu_pq->bus_address + + hdev->asic_prop.host_phys_base_address; + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_0, lower_32_bits(bus_address)); + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_1, upper_32_bits(bus_address)); + + bus_address = eq->bus_address + hdev->asic_prop.host_phys_base_address; + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_2, lower_32_bits(bus_address)); + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_3, upper_32_bits(bus_address)); + + bus_address = hdev->cpu_accessible_dma_address + + hdev->asic_prop.host_phys_base_address; + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_8, lower_32_bits(bus_address)); + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_9, upper_32_bits(bus_address)); + + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_5, HL_QUEUE_SIZE_IN_BYTES); + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_4, HL_EQ_SIZE_IN_BYTES); + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_10, CPU_ACCESSIBLE_MEM_SIZE); + + /* Used for EQ CI */ + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, 0); + + WREG32(mmCPU_IF_PF_PQ_PI, 0); + + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_7, PQ_INIT_STATUS_READY_FOR_CP); + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GOYA_ASYNC_EVENT_ID_PI_UPDATE); + + err = hl_poll_timeout( + hdev, + mmPSOC_GLOBAL_CONF_SCRATCHPAD_7, + status, + (status == PQ_INIT_STATUS_READY_FOR_HOST), + 1000, + GOYA_CPU_TIMEOUT_USEC); + + if (err) { + dev_err(hdev->dev, + "Failed to communicate with ARM CPU (ArmCP timeout)\n"); + return -EIO; + } + + goya->hw_cap_initialized |= HW_CAP_CPU_Q; + return 0; +} + +static void goya_set_pll_refclk(struct hl_device *hdev) +{ + WREG32(mmCPU_PLL_DIV_SEL_0, 0x0); + WREG32(mmCPU_PLL_DIV_SEL_1, 0x0); + WREG32(mmCPU_PLL_DIV_SEL_2, 0x0); + WREG32(mmCPU_PLL_DIV_SEL_3, 0x0); + + WREG32(mmIC_PLL_DIV_SEL_0, 0x0); + WREG32(mmIC_PLL_DIV_SEL_1, 0x0); + WREG32(mmIC_PLL_DIV_SEL_2, 0x0); + WREG32(mmIC_PLL_DIV_SEL_3, 0x0); + + WREG32(mmMC_PLL_DIV_SEL_0, 0x0); + WREG32(mmMC_PLL_DIV_SEL_1, 0x0); + WREG32(mmMC_PLL_DIV_SEL_2, 0x0); + WREG32(mmMC_PLL_DIV_SEL_3, 0x0); + + WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0); + WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0); + WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0); + WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0); + + WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0); + WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0); + WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0); + WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0); + + WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0); + WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0); + WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0); + WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0); + + WREG32(mmTPC_PLL_DIV_SEL_0, 0x0); + WREG32(mmTPC_PLL_DIV_SEL_1, 0x0); + WREG32(mmTPC_PLL_DIV_SEL_2, 0x0); + WREG32(mmTPC_PLL_DIV_SEL_3, 0x0); +} + +static void goya_disable_clk_rlx(struct hl_device *hdev) +{ + WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010); + WREG32(mmIC_PLL_CLK_RLX_0, 0x100010); +} + +static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id) +{ + u64 tpc_eml_address; + u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset; + int err, slm_index; + + tpc_offset = tpc_id * 0x40000; + tpc_eml_offset = tpc_id * 0x200000; + tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE); + tpc_slm_offset = tpc_eml_address + 0x100000; + + /* + * Workaround for Bug H2 #2443 : + * "TPC SB is not initialized on chip reset" + */ + + val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset); + if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK) + dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n", + tpc_id); + + WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000); + + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF); + WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF); + + WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset, + 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT); + + err = hl_poll_timeout( + hdev, + mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset, + val, + (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK), + 1000, + HL_DEVICE_TIMEOUT_USEC); + + if (err) + dev_err(hdev->dev, + "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id); + + WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset, + 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT); + + msleep(GOYA_RESET_WAIT_MSEC); + + WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset, + ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT)); + + msleep(GOYA_RESET_WAIT_MSEC); + + for (slm_index = 0 ; slm_index < 256 ; slm_index++) + WREG32(tpc_slm_offset + (slm_index << 2), 0); + + val = RREG32(tpc_slm_offset); +} + +static void goya_tpc_mbist_workaround(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + int i; + + if (hdev->pldm) + return; + + if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST) + return; + + /* Workaround for H2 #2443 */ + + for (i = 0 ; i < TPC_MAX_NUM ; i++) + _goya_tpc_mbist_workaround(hdev, i); + + goya->hw_cap_initialized |= HW_CAP_TPC_MBIST; +} + +/* + * goya_init_golden_registers - Initialize golden registers + * + * @hdev: pointer to hl_device structure + * + * Initialize the H/W registers of the device + * + */ +static void goya_init_golden_registers(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + u32 polynom[10], tpc_intr_mask, offset; + int i; + + if (goya->hw_cap_initialized & HW_CAP_GOLDEN) + return; + + polynom[0] = 0x00020080; + polynom[1] = 0x00401000; + polynom[2] = 0x00200800; + polynom[3] = 0x00002000; + polynom[4] = 0x00080200; + polynom[5] = 0x00040100; + polynom[6] = 0x00100400; + polynom[7] = 0x00004000; + polynom[8] = 0x00010000; + polynom[9] = 0x00008000; + + /* Mask all arithmetic interrupts from TPC */ + tpc_intr_mask = 0x7FFF; + + for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) { + WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); + WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); + WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); + WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); + WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); + + WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204); + WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204); + WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204); + WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204); + WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204); + + + WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206); + WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206); + WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206); + WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207); + WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207); + + WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207); + WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207); + WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206); + WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206); + WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206); + + WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101); + WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102); + WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103); + WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104); + WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105); + + WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105); + WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104); + WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103); + WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102); + WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101); + } + + WREG32(mmMME_STORE_MAX_CREDIT, 0x21); + WREG32(mmMME_AGU, 0x0f0f0f10); + WREG32(mmMME_SEI_MASK, ~0x0); + + WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101); + WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101); + WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101); + WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101); + WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101); + WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701); + WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401); + WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401); + WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301); + WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101); + WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101); + WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105); + WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501); + WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501); + WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301); + WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401); + WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101); + WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101); + WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202); + WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101); + WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201); + WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701); + WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101); + WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101); + WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101); + WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101); + WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701); + WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201); + WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101); + WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102); + WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701); + WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701); + WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707); + WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201); + WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201); + WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201); + WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102); + WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102); + WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102); + WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102); + WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102); + WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107); + WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106); + WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102); + WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102); + WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102); + WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102); + WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102); + WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702); + WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702); + WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602); + WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402); + WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202); + WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102); + WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401); + WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401); + WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401); + WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401); + WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401); + WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401); + WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101); + WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101); + WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101); + WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101); + WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101); + WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107); + WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107); + WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101); + WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101); + WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101); + WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101); + WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101); + WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501); + WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501); + WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301); + WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401); + WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101); + WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101); + WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101); + WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101); + WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101); + WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101); + WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101); + WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101); + + WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101); + WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101); + WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101); + WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102); + WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101); + WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202); + WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201); + WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201); + WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202); + WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101); + WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101); + WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101); + + WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101); + WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101); + WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201); + WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102); + WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101); + WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202); + WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201); + WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201); + WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202); + WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101); + WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101); + WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101); + + WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101); + WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101); + WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301); + WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102); + WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101); + WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301); + WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201); + WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201); + WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402); + WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101); + WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101); + WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401); + + WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101); + WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101); + WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401); + WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102); + WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101); + WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702); + WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201); + WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201); + WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602); + WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101); + WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101); + WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301); + + WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101); + WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101); + WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501); + WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102); + WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101); + WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602); + WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201); + WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201); + WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702); + WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101); + WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101); + WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501); + + WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101); + WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101); + WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601); + WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101); + WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101); + WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702); + WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101); + WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101); + WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702); + WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101); + WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101); + WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501); + + for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) { + WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + + WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + + WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); + } + + for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) { + WREG32(mmMME1_RTR_SCRAMB_EN + offset, + 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT); + WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset, + 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT); + } + + for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) { + /* + * Workaround for Bug H2 #2441 : + * "ST.NOP set trace event illegal opcode" + */ + WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask); + + WREG32(mmTPC0_NRTR_SCRAMB_EN + offset, + 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT); + WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset, + 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT); + } + + WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT); + WREG32(mmDMA_NRTR_NON_LIN_SCRAMB, + 1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT); + + WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT); + WREG32(mmPCI_NRTR_NON_LIN_SCRAMB, + 1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT); + + /* + * Workaround for H2 #HW-23 bug + * Set DMA max outstanding read requests to 240 on DMA CH 1. Set it + * to 16 on KMD DMA + * We need to limit only these DMAs because the user can only read + * from Host using DMA CH 1 + */ + WREG32(mmDMA_CH_0_CFG0, 0x0fff0010); + WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0); + + goya->hw_cap_initialized |= HW_CAP_GOLDEN; +} + +static void goya_init_mme_qman(struct hl_device *hdev) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 gic_base_lo, gic_base_hi; + u64 qman_base_addr; + + mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + + gic_base_lo = + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + gic_base_hi = + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + + qman_base_addr = hdev->asic_prop.sram_base_address + + MME_QMAN_BASE_OFFSET; + + WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr)); + WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr)); + WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH)); + WREG32(mmMME_QM_PQ_PI, 0); + WREG32(mmMME_QM_PQ_CI, 0); + WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0); + WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4); + WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8); + WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC); + + WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo); + WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi); + WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo); + WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi); + + /* QMAN CQ has 8 cache lines */ + WREG32(mmMME_QM_CQ_CFG1, 0x00080008); + + WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo); + WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi); + + WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM); + + WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN); + + WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT); + + WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE); +} + +static void goya_init_mme_cmdq(struct hl_device *hdev) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 gic_base_lo, gic_base_hi; + u64 qman_base_addr; + + mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + + gic_base_lo = + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + gic_base_hi = + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + + qman_base_addr = hdev->asic_prop.sram_base_address + + MME_QMAN_BASE_OFFSET; + + WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo); + WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi); + WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo); + WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi); + + /* CMDQ CQ has 20 cache lines */ + WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014); + + WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo); + WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi); + + WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ); + + WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN); + + WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT); + + WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE); +} + +static void goya_init_mme_qmans(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + u32 so_base_lo, so_base_hi; + + if (goya->hw_cap_initialized & HW_CAP_MME) + return; + + so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + + WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo); + WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi); + + goya_init_mme_qman(hdev); + goya_init_mme_cmdq(hdev); + + goya->hw_cap_initialized |= HW_CAP_MME; +} + +static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 gic_base_lo, gic_base_hi; + u64 qman_base_addr; + u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI); + + mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + + gic_base_lo = + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + gic_base_hi = + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + + qman_base_addr = hdev->asic_prop.sram_base_address + base_off; + + WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr)); + WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr)); + WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH)); + WREG32(mmTPC0_QM_PQ_PI + reg_off, 0); + WREG32(mmTPC0_QM_PQ_CI + reg_off, 0); + WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0); + WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4); + WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8); + WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC); + + WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); + WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); + WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); + WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); + + WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008); + + WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); + WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); + + WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off, + GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id); + + WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN); + + WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT); + + WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE); +} + +static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 gic_base_lo, gic_base_hi; + u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1); + + mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + + gic_base_lo = + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + gic_base_hi = + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); + + WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); + WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); + WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); + WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); + + WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014); + + WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); + WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); + + WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off, + GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id); + + WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN); + + WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT); + + WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE); +} + +static void goya_init_tpc_qmans(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + u32 so_base_lo, so_base_hi; + u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW - + mmTPC0_CFG_SM_BASE_ADDRESS_LOW; + int i; + + if (goya->hw_cap_initialized & HW_CAP_TPC) + return; + + so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + + for (i = 0 ; i < TPC_MAX_NUM ; i++) { + WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off, + so_base_lo); + WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off, + so_base_hi); + } + + goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0); + goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1); + goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2); + goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3); + goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4); + goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5); + goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6); + goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7); + + for (i = 0 ; i < TPC_MAX_NUM ; i++) + goya_init_tpc_cmdq(hdev, i); + + goya->hw_cap_initialized |= HW_CAP_TPC; +} + +/* + * goya_disable_internal_queues - Disable internal queues + * + * @hdev: pointer to hl_device structure + * + */ +static void goya_disable_internal_queues(struct hl_device *hdev) +{ + WREG32(mmMME_QM_GLBL_CFG0, 0); + WREG32(mmMME_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC0_QM_GLBL_CFG0, 0); + WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC1_QM_GLBL_CFG0, 0); + WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC2_QM_GLBL_CFG0, 0); + WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC3_QM_GLBL_CFG0, 0); + WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC4_QM_GLBL_CFG0, 0); + WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC5_QM_GLBL_CFG0, 0); + WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC6_QM_GLBL_CFG0, 0); + WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0); + + WREG32(mmTPC7_QM_GLBL_CFG0, 0); + WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0); +} + +/* + * goya_stop_internal_queues - Stop internal queues + * + * @hdev: pointer to hl_device structure + * + * Returns 0 on success + * + */ +static int goya_stop_internal_queues(struct hl_device *hdev) +{ + int rc, retval = 0; + + /* + * Each queue (QMAN) is a separate H/W logic. That means that each + * QMAN can be stopped independently and failure to stop one does NOT + * mandate we should not try to stop other QMANs + */ + + rc = goya_stop_queue(hdev, + mmMME_QM_GLBL_CFG1, + mmMME_QM_CP_STS, + mmMME_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop MME QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmMME_CMDQ_GLBL_CFG1, + mmMME_CMDQ_CP_STS, + mmMME_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop MME CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC0_QM_GLBL_CFG1, + mmTPC0_QM_CP_STS, + mmTPC0_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC0_CMDQ_GLBL_CFG1, + mmTPC0_CMDQ_CP_STS, + mmTPC0_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC1_QM_GLBL_CFG1, + mmTPC1_QM_CP_STS, + mmTPC1_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC1_CMDQ_GLBL_CFG1, + mmTPC1_CMDQ_CP_STS, + mmTPC1_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC2_QM_GLBL_CFG1, + mmTPC2_QM_CP_STS, + mmTPC2_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC2_CMDQ_GLBL_CFG1, + mmTPC2_CMDQ_CP_STS, + mmTPC2_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC3_QM_GLBL_CFG1, + mmTPC3_QM_CP_STS, + mmTPC3_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC3_CMDQ_GLBL_CFG1, + mmTPC3_CMDQ_CP_STS, + mmTPC3_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC4_QM_GLBL_CFG1, + mmTPC4_QM_CP_STS, + mmTPC4_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC4_CMDQ_GLBL_CFG1, + mmTPC4_CMDQ_CP_STS, + mmTPC4_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC5_QM_GLBL_CFG1, + mmTPC5_QM_CP_STS, + mmTPC5_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC5_CMDQ_GLBL_CFG1, + mmTPC5_CMDQ_CP_STS, + mmTPC5_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC6_QM_GLBL_CFG1, + mmTPC6_QM_CP_STS, + mmTPC6_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC6_CMDQ_GLBL_CFG1, + mmTPC6_CMDQ_CP_STS, + mmTPC6_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC7_QM_GLBL_CFG1, + mmTPC7_QM_CP_STS, + mmTPC7_QM_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n"); + retval = -EIO; + } + + rc = goya_stop_queue(hdev, + mmTPC7_CMDQ_GLBL_CFG1, + mmTPC7_CMDQ_CP_STS, + mmTPC7_CMDQ_GLBL_STS0); + + if (rc) { + dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n"); + retval = -EIO; + } + + return retval; +} + +static void goya_resume_internal_queues(struct hl_device *hdev) +{ + WREG32(mmMME_QM_GLBL_CFG1, 0); + WREG32(mmMME_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC0_QM_GLBL_CFG1, 0); + WREG32(mmTPC0_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC1_QM_GLBL_CFG1, 0); + WREG32(mmTPC1_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC2_QM_GLBL_CFG1, 0); + WREG32(mmTPC2_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC3_QM_GLBL_CFG1, 0); + WREG32(mmTPC3_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC4_QM_GLBL_CFG1, 0); + WREG32(mmTPC4_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC5_QM_GLBL_CFG1, 0); + WREG32(mmTPC5_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC6_QM_GLBL_CFG1, 0); + WREG32(mmTPC6_CMDQ_GLBL_CFG1, 0); + + WREG32(mmTPC7_QM_GLBL_CFG1, 0); + WREG32(mmTPC7_CMDQ_GLBL_CFG1, 0); +} + +static void goya_dma_stall(struct hl_device *hdev) +{ + WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT); + WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT); + WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT); + WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT); + WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT); +} + +static void goya_tpc_stall(struct hl_device *hdev) +{ + WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT); +} + +static void goya_mme_stall(struct hl_device *hdev) +{ + WREG32(mmMME_STALL, 0xFFFFFFFF); +} + +static int goya_enable_msix(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + int cq_cnt = hdev->asic_prop.completion_queues_count; + int rc, i, irq_cnt_init, irq; + + if (goya->hw_cap_initialized & HW_CAP_MSIX) + return 0; + + rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES, + GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX); + if (rc < 0) { + dev_err(hdev->dev, + "MSI-X: Failed to enable support -- %d/%d\n", + GOYA_MSIX_ENTRIES, rc); + return rc; + } + + for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) { + irq = pci_irq_vector(hdev->pdev, i); + rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i], + &hdev->completion_queue[i]); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_irqs; + } + } + + irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX); + + rc = request_irq(irq, hl_irq_handler_eq, 0, + goya_irq_name[EVENT_QUEUE_MSIX_IDX], + &hdev->event_queue); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_irqs; + } + + goya->hw_cap_initialized |= HW_CAP_MSIX; + return 0; + +free_irqs: + for (i = 0 ; i < irq_cnt_init ; i++) + free_irq(pci_irq_vector(hdev->pdev, i), + &hdev->completion_queue[i]); + + pci_free_irq_vectors(hdev->pdev); + return rc; +} + +static void goya_sync_irqs(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + int i; + + if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) + return; + + /* Wait for all pending IRQs to be finished */ + for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) + synchronize_irq(pci_irq_vector(hdev->pdev, i)); + + synchronize_irq(pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX)); +} + +static void goya_disable_msix(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + int i, irq; + + if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) + return; + + goya_sync_irqs(hdev); + + irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX); + free_irq(irq, &hdev->event_queue); + + for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) { + irq = pci_irq_vector(hdev->pdev, i); + free_irq(irq, &hdev->completion_queue[i]); + } + + pci_free_irq_vectors(hdev->pdev); + + goya->hw_cap_initialized &= ~HW_CAP_MSIX; +} + +static void goya_halt_engines(struct hl_device *hdev, bool hard_reset) +{ + u32 wait_timeout_ms, cpu_timeout_ms; + + dev_info(hdev->dev, + "Halting compute engines and disabling interrupts\n"); + + if (hdev->pldm) { + wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC; + cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC; + } else { + wait_timeout_ms = GOYA_RESET_WAIT_MSEC; + cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC; + } + + if (hard_reset) { + /* + * I don't know what is the state of the CPU so make sure it is + * stopped in any means necessary + */ + WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE); + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GOYA_ASYNC_EVENT_ID_HALT_MACHINE); + msleep(cpu_timeout_ms); + } + + goya_stop_external_queues(hdev); + goya_stop_internal_queues(hdev); + + msleep(wait_timeout_ms); + + goya_dma_stall(hdev); + goya_tpc_stall(hdev); + goya_mme_stall(hdev); + + msleep(wait_timeout_ms); + + goya_disable_external_queues(hdev); + goya_disable_internal_queues(hdev); + + if (hard_reset) + goya_disable_msix(hdev); + else + goya_sync_irqs(hdev); +} + +/* + * goya_push_fw_to_device - Push FW code to device + * + * @hdev: pointer to hl_device structure + * + * Copy fw code from firmware file to device memory. + * Returns 0 on success + * + */ +static int goya_push_fw_to_device(struct hl_device *hdev, const char *fw_name, + void __iomem *dst) +{ + const struct firmware *fw; + const u64 *fw_data; + size_t fw_size, i; + int rc; + + rc = request_firmware(&fw, fw_name, hdev->dev); + + if (rc) { + dev_err(hdev->dev, "Failed to request %s\n", fw_name); + goto out; + } + + fw_size = fw->size; + if ((fw_size % 4) != 0) { + dev_err(hdev->dev, "illegal %s firmware size %zu\n", + fw_name, fw_size); + rc = -EINVAL; + goto out; + } + + dev_dbg(hdev->dev, "%s firmware size == %zu\n", fw_name, fw_size); + + fw_data = (const u64 *) fw->data; + + if ((fw->size % 8) != 0) + fw_size -= 8; + + for (i = 0 ; i < fw_size ; i += 8, fw_data++, dst += 8) { + if (!(i & (0x80000 - 1))) { + dev_dbg(hdev->dev, + "copied so far %zu out of %zu for %s firmware", + i, fw_size, fw_name); + usleep_range(20, 100); + } + + writeq(*fw_data, dst); + } + + if ((fw->size % 8) != 0) + writel(*(const u32 *) fw_data, dst); + +out: + release_firmware(fw); + return rc; +} + +static int goya_pldm_init_cpu(struct hl_device *hdev) +{ + char fw_name[200]; + void __iomem *dst; + u32 val, unit_rst_val; + int rc; + + /* Must initialize SRAM scrambler before pushing u-boot to SRAM */ + goya_init_golden_registers(hdev); + + /* Put ARM cores into reset */ + WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT); + val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); + + /* Reset the CA53 MACRO */ + unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); + WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET); + val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); + WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val); + val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); + + snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-u-boot.bin"); + dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET; + rc = goya_push_fw_to_device(hdev, fw_name, dst); + if (rc) + return rc; + + snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb"); + dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; + rc = goya_push_fw_to_device(hdev, fw_name, dst); + if (rc) + return rc; + + WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); + WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA); + + WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0, + lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET)); + WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0, + upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET)); + + /* Release ARM core 0 from reset */ + WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, + CPU_RESET_CORE0_DEASSERT); + val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); + + return 0; +} + +/* + * FW component passes an offset from SRAM_BASE_ADDR in SCRATCHPAD_xx. + * The version string should be located by that offset. + */ +static void goya_read_device_fw_version(struct hl_device *hdev, + enum goya_fw_component fwc) +{ + const char *name; + u32 ver_off; + char *dest; + + switch (fwc) { + case FW_COMP_UBOOT: + ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_29); + dest = hdev->asic_prop.uboot_ver; + name = "U-Boot"; + break; + case FW_COMP_PREBOOT: + ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_28); + dest = hdev->asic_prop.preboot_ver; + name = "Preboot"; + break; + default: + dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc); + return; + } + + ver_off &= ~((u32)SRAM_BASE_ADDR); + + if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) { + memcpy_fromio(dest, hdev->pcie_bar[SRAM_CFG_BAR_ID] + ver_off, + VERSION_MAX_LEN); + } else { + dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n", + name, ver_off); + strcpy(dest, "unavailable"); + } +} + +static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout) +{ + struct goya_device *goya = hdev->asic_specific; + char fw_name[200]; + void __iomem *dst; + u32 status; + int rc; + + if (!hdev->cpu_enable) + return 0; + + if (goya->hw_cap_initialized & HW_CAP_CPU) + return 0; + + /* + * Before pushing u-boot/linux to device, need to set the ddr bar to + * base address of dram + */ + rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE); + if (rc) { + dev_err(hdev->dev, + "failed to map DDR bar to DRAM base address\n"); + return rc; + } + + if (hdev->pldm) { + rc = goya_pldm_init_cpu(hdev); + if (rc) + return rc; + + goto out; + } + + /* Make sure CPU boot-loader is running */ + rc = hl_poll_timeout( + hdev, + mmPSOC_GLOBAL_CONF_WARM_REBOOT, + status, + (status == CPU_BOOT_STATUS_DRAM_RDY) || + (status == CPU_BOOT_STATUS_SRAM_AVAIL), + 10000, + cpu_timeout); + + if (rc) { + dev_err(hdev->dev, "Error in ARM u-boot!"); + switch (status) { + case CPU_BOOT_STATUS_NA: + dev_err(hdev->dev, + "ARM status %d - BTL did NOT run\n", status); + break; + case CPU_BOOT_STATUS_IN_WFE: + dev_err(hdev->dev, + "ARM status %d - Inside WFE loop\n", status); + break; + case CPU_BOOT_STATUS_IN_BTL: + dev_err(hdev->dev, + "ARM status %d - Stuck in BTL\n", status); + break; + case CPU_BOOT_STATUS_IN_PREBOOT: + dev_err(hdev->dev, + "ARM status %d - Stuck in Preboot\n", status); + break; + case CPU_BOOT_STATUS_IN_SPL: + dev_err(hdev->dev, + "ARM status %d - Stuck in SPL\n", status); + break; + case CPU_BOOT_STATUS_IN_UBOOT: + dev_err(hdev->dev, + "ARM status %d - Stuck in u-boot\n", status); + break; + case CPU_BOOT_STATUS_DRAM_INIT_FAIL: + dev_err(hdev->dev, + "ARM status %d - DDR initialization failed\n", + status); + break; + default: + dev_err(hdev->dev, + "ARM status %d - Invalid status code\n", + status); + break; + } + return -EIO; + } + + /* Read U-Boot version now in case we will later fail */ + goya_read_device_fw_version(hdev, FW_COMP_UBOOT); + goya_read_device_fw_version(hdev, FW_COMP_PREBOOT); + + if (status == CPU_BOOT_STATUS_SRAM_AVAIL) + goto out; + + if (!hdev->fw_loading) { + dev_info(hdev->dev, "Skip loading FW\n"); + goto out; + } + + snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb"); + dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; + rc = goya_push_fw_to_device(hdev, fw_name, dst); + if (rc) + return rc; + + WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); + + rc = hl_poll_timeout( + hdev, + mmPSOC_GLOBAL_CONF_WARM_REBOOT, + status, + (status == CPU_BOOT_STATUS_SRAM_AVAIL), + 10000, + cpu_timeout); + + if (rc) { + if (status == CPU_BOOT_STATUS_FIT_CORRUPTED) + dev_err(hdev->dev, + "ARM u-boot reports FIT image is corrupted\n"); + else + dev_err(hdev->dev, + "ARM Linux failed to load, %d\n", status); + WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA); + return -EIO; + } + + dev_info(hdev->dev, "Successfully loaded firmware to device\n"); + +out: + goya->hw_cap_initialized |= HW_CAP_CPU; + + return 0; +} + +static int goya_mmu_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct goya_device *goya = hdev->asic_specific; + u64 hop0_addr; + int rc, i; + + if (!hdev->mmu_enable) + return 0; + + if (goya->hw_cap_initialized & HW_CAP_MMU) + return 0; + + hdev->dram_supports_virtual_memory = true; + hdev->dram_default_page_mapping = true; + + for (i = 0 ; i < prop->max_asid ; i++) { + hop0_addr = prop->mmu_pgt_addr + + (i * prop->mmu_hop_table_size); + + rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr); + if (rc) { + dev_err(hdev->dev, + "failed to set hop0 addr for asid %d\n", i); + goto err; + } + } + + goya->hw_cap_initialized |= HW_CAP_MMU; + + /* init MMU cache manage page */ + WREG32(mmSTLB_CACHE_INV_BASE_39_8, + lower_32_bits(MMU_CACHE_MNG_ADDR >> 8)); + WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40); + + /* Remove follower feature due to performance bug */ + WREG32_AND(mmSTLB_STLB_FEATURE_EN, + (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK)); + + hdev->asic_funcs->mmu_invalidate_cache(hdev, true); + + WREG32(mmMMU_MMU_ENABLE, 1); + WREG32(mmMMU_SPI_MASK, 0xF); + + return 0; + +err: + return rc; +} + +/* + * goya_hw_init - Goya hardware initialization code + * + * @hdev: pointer to hl_device structure + * + * Returns 0 on success + * + */ +static int goya_hw_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 val; + int rc; + + dev_info(hdev->dev, "Starting initialization of H/W\n"); + + /* Perform read from the device to make sure device is up */ + val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + /* + * Let's mark in the H/W that we have reached this point. We check + * this value in the reset_before_init function to understand whether + * we need to reset the chip before doing H/W init. This register is + * cleared by the H/W upon H/W reset + */ + WREG32(mmPSOC_GLOBAL_CONF_APP_STATUS, HL_DEVICE_HW_STATE_DIRTY); + + rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU\n"); + return rc; + } + + goya_tpc_mbist_workaround(hdev); + + goya_init_golden_registers(hdev); + + /* + * After CPU initialization is finished, change DDR bar mapping inside + * iATU to point to the start address of the MMU page tables + */ + rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE + + (MMU_PAGE_TABLES_ADDR & ~(prop->dram_pci_bar_size - 0x1ull))); + if (rc) { + dev_err(hdev->dev, + "failed to map DDR bar to MMU page tables\n"); + return rc; + } + + rc = goya_mmu_init(hdev); + if (rc) + return rc; + + goya_init_security(hdev); + + goya_init_dma_qmans(hdev); + + goya_init_mme_qmans(hdev); + + goya_init_tpc_qmans(hdev); + + /* MSI-X must be enabled before CPU queues are initialized */ + rc = goya_enable_msix(hdev); + if (rc) + goto disable_queues; + + rc = goya_init_cpu_queues(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n", + rc); + goto disable_msix; + } + + /* CPU initialization is finished, we can now move to 48 bit DMA mask */ + rc = pci_set_dma_mask(hdev->pdev, DMA_BIT_MASK(48)); + if (rc) { + dev_warn(hdev->dev, "Unable to set pci dma mask to 48 bits\n"); + rc = pci_set_dma_mask(hdev->pdev, DMA_BIT_MASK(32)); + if (rc) { + dev_err(hdev->dev, + "Unable to set pci dma mask to 32 bits\n"); + goto disable_pci_access; + } + } + + rc = pci_set_consistent_dma_mask(hdev->pdev, DMA_BIT_MASK(48)); + if (rc) { + dev_warn(hdev->dev, + "Unable to set pci consistent dma mask to 48 bits\n"); + rc = pci_set_consistent_dma_mask(hdev->pdev, DMA_BIT_MASK(32)); + if (rc) { + dev_err(hdev->dev, + "Unable to set pci consistent dma mask to 32 bits\n"); + goto disable_pci_access; + } + } + + /* Perform read from the device to flush all MSI-X configuration */ + val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + return 0; + +disable_pci_access: + goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); +disable_msix: + goya_disable_msix(hdev); +disable_queues: + goya_disable_internal_queues(hdev); + goya_disable_external_queues(hdev); + + return rc; +} + +/* + * goya_hw_fini - Goya hardware tear-down code + * + * @hdev: pointer to hl_device structure + * @hard_reset: should we do hard reset to all engines or just reset the + * compute/dma engines + */ +static void goya_hw_fini(struct hl_device *hdev, bool hard_reset) +{ + struct goya_device *goya = hdev->asic_specific; + u32 reset_timeout_ms, status; + + if (hdev->pldm) + reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC; + else + reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC; + + if (hard_reset) { + goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE); + goya_disable_clk_rlx(hdev); + goya_set_pll_refclk(hdev); + + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL); + dev_info(hdev->dev, + "Issued HARD reset command, going to wait %dms\n", + reset_timeout_ms); + } else { + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET); + dev_info(hdev->dev, + "Issued SOFT reset command, going to wait %dms\n", + reset_timeout_ms); + } + + /* + * After hard reset, we can't poll the BTM_FSM register because the PSOC + * itself is in reset. In either reset we need to wait until the reset + * is deasserted + */ + msleep(reset_timeout_ms); + + status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM); + if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) + dev_err(hdev->dev, + "Timeout while waiting for device to reset 0x%x\n", + status); + + if (!hard_reset) { + goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME | + HW_CAP_GOLDEN | HW_CAP_TPC); + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GOYA_ASYNC_EVENT_ID_SOFT_RESET); + return; + } + + /* Chicken bit to re-initiate boot sequencer flow */ + WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, + 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT); + /* Move boot manager FSM to pre boot sequencer init state */ + WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM, + 0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT); + + goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | + HW_CAP_DDR_0 | HW_CAP_DDR_1 | + HW_CAP_DMA | HW_CAP_MME | + HW_CAP_MMU | HW_CAP_TPC_MBIST | + HW_CAP_GOLDEN | HW_CAP_TPC); + memset(goya->events_stat, 0, sizeof(goya->events_stat)); + + if (!hdev->pldm) { + int rc; + /* In case we are running inside VM and the VM is + * shutting down, we need to make sure CPU boot-loader + * is running before we can continue the VM shutdown. + * That is because the VM will send an FLR signal that + * we must answer + */ + dev_info(hdev->dev, + "Going to wait up to %ds for CPU boot loader\n", + GOYA_CPU_TIMEOUT_USEC / 1000 / 1000); + + rc = hl_poll_timeout( + hdev, + mmPSOC_GLOBAL_CONF_WARM_REBOOT, + status, + (status == CPU_BOOT_STATUS_DRAM_RDY), + 10000, + GOYA_CPU_TIMEOUT_USEC); + if (rc) + dev_err(hdev->dev, + "failed to wait for CPU boot loader\n"); + } +} + +int goya_suspend(struct hl_device *hdev) +{ + int rc; + + rc = goya_stop_internal_queues(hdev); + + if (rc) { + dev_err(hdev->dev, "failed to stop internal queues\n"); + return rc; + } + + rc = goya_stop_external_queues(hdev); + + if (rc) { + dev_err(hdev->dev, "failed to stop external queues\n"); + return rc; + } + + rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + if (rc) + dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); + + return rc; +} + +int goya_resume(struct hl_device *hdev) +{ + int rc; + + goya_resume_external_queues(hdev); + goya_resume_internal_queues(hdev); + + rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS); + if (rc) + dev_err(hdev->dev, "Failed to enable PCI access from CPU\n"); + return rc; +} + +static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma, + u64 kaddress, phys_addr_t paddress, u32 size) +{ + int rc; + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | + VM_DONTCOPY | VM_NORESERVE; + + rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT, + size, vma->vm_page_prot); + if (rc) + dev_err(hdev->dev, "remap_pfn_range error %d", rc); + + return rc; +} + +static void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi) +{ + u32 db_reg_offset, db_value; + bool invalid_queue = false; + + switch (hw_queue_id) { + case GOYA_QUEUE_ID_DMA_0: + db_reg_offset = mmDMA_QM_0_PQ_PI; + break; + + case GOYA_QUEUE_ID_DMA_1: + db_reg_offset = mmDMA_QM_1_PQ_PI; + break; + + case GOYA_QUEUE_ID_DMA_2: + db_reg_offset = mmDMA_QM_2_PQ_PI; + break; + + case GOYA_QUEUE_ID_DMA_3: + db_reg_offset = mmDMA_QM_3_PQ_PI; + break; + + case GOYA_QUEUE_ID_DMA_4: + db_reg_offset = mmDMA_QM_4_PQ_PI; + break; + + case GOYA_QUEUE_ID_CPU_PQ: + if (hdev->cpu_queues_enable) + db_reg_offset = mmCPU_IF_PF_PQ_PI; + else + invalid_queue = true; + break; + + case GOYA_QUEUE_ID_MME: + db_reg_offset = mmMME_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC0: + db_reg_offset = mmTPC0_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC1: + db_reg_offset = mmTPC1_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC2: + db_reg_offset = mmTPC2_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC3: + db_reg_offset = mmTPC3_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC4: + db_reg_offset = mmTPC4_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC5: + db_reg_offset = mmTPC5_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC6: + db_reg_offset = mmTPC6_QM_PQ_PI; + break; + + case GOYA_QUEUE_ID_TPC7: + db_reg_offset = mmTPC7_QM_PQ_PI; + break; + + default: + invalid_queue = true; + } + + if (invalid_queue) { + /* Should never get here */ + dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n", + hw_queue_id); + return; + } + + db_value = pi; + + /* ring the doorbell */ + WREG32(db_reg_offset, db_value); + + if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GOYA_ASYNC_EVENT_ID_PI_UPDATE); +} + +void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val) +{ + /* Not needed in Goya */ +} + +static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size, + dma_addr_t *dma_handle, gfp_t flags) +{ + return dma_alloc_coherent(&hdev->pdev->dev, size, dma_handle, flags); +} + +static void goya_dma_free_coherent(struct hl_device *hdev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) +{ + dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, dma_handle); +} + +void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id, + dma_addr_t *dma_handle, u16 *queue_len) +{ + void *base; + u32 offset; + + *dma_handle = hdev->asic_prop.sram_base_address; + + base = hdev->pcie_bar[SRAM_CFG_BAR_ID]; + + switch (queue_id) { + case GOYA_QUEUE_ID_MME: + offset = MME_QMAN_BASE_OFFSET; + *queue_len = MME_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC0: + offset = TPC0_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC1: + offset = TPC1_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC2: + offset = TPC2_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC3: + offset = TPC3_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC4: + offset = TPC4_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC5: + offset = TPC5_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC6: + offset = TPC6_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + case GOYA_QUEUE_ID_TPC7: + offset = TPC7_QMAN_BASE_OFFSET; + *queue_len = TPC_QMAN_LENGTH; + break; + default: + dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id); + return NULL; + } + + base += offset; + *dma_handle += offset; + + return base; +} + +static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job) +{ + struct goya_device *goya = hdev->asic_specific; + struct packet_msg_prot *fence_pkt; + u32 *fence_ptr; + dma_addr_t fence_dma_addr; + struct hl_cb *cb; + u32 tmp, timeout; + int rc; + + if (hdev->pldm) + timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC; + else + timeout = HL_DEVICE_TIMEOUT_USEC; + + if (!hdev->asic_funcs->is_device_idle(hdev)) { + dev_err_ratelimited(hdev->dev, + "Can't send KMD job on QMAN0 if device is not idle\n"); + return -EBUSY; + } + + fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL, + &fence_dma_addr); + if (!fence_ptr) { + dev_err(hdev->dev, + "Failed to allocate fence memory for QMAN0\n"); + return -ENOMEM; + } + + *fence_ptr = 0; + + if (goya->hw_cap_initialized & HW_CAP_MMU) { + WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED); + RREG32(mmDMA_QM_0_GLBL_PROT); + } + + /* + * goya cs parser saves space for 2xpacket_msg_prot at end of CB. For + * synchronized kernel jobs we only need space for 1 packet_msg_prot + */ + job->job_cb_size -= sizeof(struct packet_msg_prot); + + cb = job->patched_cb; + + fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address + + job->job_cb_size - sizeof(struct packet_msg_prot)); + + tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | + (1 << GOYA_PKT_CTL_EB_SHIFT) | + (1 << GOYA_PKT_CTL_MB_SHIFT); + fence_pkt->ctl = cpu_to_le32(tmp); + fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL); + fence_pkt->addr = cpu_to_le64(fence_dma_addr + + hdev->asic_prop.host_phys_base_address); + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0, + job->job_cb_size, cb->bus_address); + if (rc) { + dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc); + goto free_fence_ptr; + } + + rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr, timeout, + &tmp); + + hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0); + + if ((rc) || (tmp != GOYA_QMAN0_FENCE_VAL)) { + dev_err(hdev->dev, "QMAN0 Job hasn't finished in time\n"); + rc = -ETIMEDOUT; + } + +free_fence_ptr: + hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr, + fence_dma_addr); + + if (goya->hw_cap_initialized & HW_CAP_MMU) { + WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED); + RREG32(mmDMA_QM_0_GLBL_PROT); + } + + return rc; +} + +int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len, + u32 timeout, long *result) +{ + struct goya_device *goya = hdev->asic_specific; + struct armcp_packet *pkt; + dma_addr_t pkt_dma_addr; + u32 tmp; + int rc = 0; + + if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) { + if (result) + *result = 0; + return 0; + } + + if (len > CPU_CB_SIZE) { + dev_err(hdev->dev, "Invalid CPU message size of %d bytes\n", + len); + return -ENOMEM; + } + + pkt = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, len, + &pkt_dma_addr); + if (!pkt) { + dev_err(hdev->dev, + "Failed to allocate DMA memory for packet to CPU\n"); + return -ENOMEM; + } + + memcpy(pkt, msg, len); + + mutex_lock(&hdev->send_cpu_message_lock); + + if (hdev->disabled) + goto out; + + if (hdev->device_cpu_disabled) { + rc = -EIO; + goto out; + } + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_CPU_PQ, len, + pkt_dma_addr); + if (rc) { + dev_err(hdev->dev, "Failed to send CB on CPU PQ (%d)\n", rc); + goto out; + } + + rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) &pkt->fence, + timeout, &tmp); + + hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_CPU_PQ); + + if (rc == -ETIMEDOUT) { + dev_err(hdev->dev, "Timeout while waiting for device CPU\n"); + hdev->device_cpu_disabled = true; + goto out; + } + + if (tmp == ARMCP_PACKET_FENCE_VAL) { + u32 ctl = le32_to_cpu(pkt->ctl); + + rc = (ctl & ARMCP_PKT_CTL_RC_MASK) >> ARMCP_PKT_CTL_RC_SHIFT; + if (rc) { + dev_err(hdev->dev, + "F/W ERROR %d for CPU packet %d\n", + rc, (ctl & ARMCP_PKT_CTL_OPCODE_MASK) + >> ARMCP_PKT_CTL_OPCODE_SHIFT); + rc = -EINVAL; + } else if (result) { + *result = (long) le64_to_cpu(pkt->result); + } + } else { + dev_err(hdev->dev, "CPU packet wrong fence value\n"); + rc = -EINVAL; + } + +out: + mutex_unlock(&hdev->send_cpu_message_lock); + + hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, len, pkt); + + return rc; +} + +int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) +{ + struct packet_msg_prot *fence_pkt; + dma_addr_t pkt_dma_addr; + u32 fence_val, tmp; + dma_addr_t fence_dma_addr; + u32 *fence_ptr; + int rc; + + fence_val = GOYA_QMAN0_FENCE_VAL; + + fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL, + &fence_dma_addr); + if (!fence_ptr) { + dev_err(hdev->dev, + "Failed to allocate memory for queue testing\n"); + return -ENOMEM; + } + + *fence_ptr = 0; + + fence_pkt = hdev->asic_funcs->dma_pool_zalloc(hdev, + sizeof(struct packet_msg_prot), + GFP_KERNEL, &pkt_dma_addr); + if (!fence_pkt) { + dev_err(hdev->dev, + "Failed to allocate packet for queue testing\n"); + rc = -ENOMEM; + goto free_fence_ptr; + } + + tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | + (1 << GOYA_PKT_CTL_EB_SHIFT) | + (1 << GOYA_PKT_CTL_MB_SHIFT); + fence_pkt->ctl = cpu_to_le32(tmp); + fence_pkt->value = cpu_to_le32(fence_val); + fence_pkt->addr = cpu_to_le64(fence_dma_addr + + hdev->asic_prop.host_phys_base_address); + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, + sizeof(struct packet_msg_prot), + pkt_dma_addr); + if (rc) { + dev_err(hdev->dev, + "Failed to send fence packet\n"); + goto free_pkt; + } + + rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr, + GOYA_TEST_QUEUE_WAIT_USEC, &tmp); + + hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id); + + if ((!rc) && (tmp == fence_val)) { + dev_info(hdev->dev, + "queue test on H/W queue %d succeeded\n", + hw_queue_id); + } else { + dev_err(hdev->dev, + "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n", + hw_queue_id, (unsigned long long) fence_dma_addr, tmp); + rc = -EINVAL; + } + +free_pkt: + hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_pkt, + pkt_dma_addr); +free_fence_ptr: + hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr, + fence_dma_addr); + return rc; +} + +int goya_test_cpu_queue(struct hl_device *hdev) +{ + struct armcp_packet test_pkt; + long result; + int rc; + + /* cpu_queues_enable flag is always checked in send cpu message */ + + memset(&test_pkt, 0, sizeof(test_pkt)); + + test_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST << + ARMCP_PKT_CTL_OPCODE_SHIFT); + test_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &test_pkt, + sizeof(test_pkt), HL_DEVICE_TIMEOUT_USEC, &result); + + if (!rc) { + if (result == ARMCP_PACKET_FENCE_VAL) + dev_info(hdev->dev, + "queue test on CPU queue succeeded\n"); + else + dev_err(hdev->dev, + "CPU queue test failed (0x%08lX)\n", result); + } else { + dev_err(hdev->dev, "CPU queue test failed, error %d\n", rc); + } + + return rc; +} + +static int goya_test_queues(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + int i, rc, ret_val = 0; + + for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) { + rc = goya_test_queue(hdev, i); + if (rc) + ret_val = -EINVAL; + } + + if (hdev->cpu_queues_enable) { + rc = goya->test_cpu_queue(hdev); + if (rc) + ret_val = -EINVAL; + } + + return ret_val; +} + +static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size, + gfp_t mem_flags, dma_addr_t *dma_handle) +{ + if (size > GOYA_DMA_POOL_BLK_SIZE) + return NULL; + + return dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle); +} + +static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr, + dma_addr_t dma_addr) +{ + dma_pool_free(hdev->dma_pool, vaddr, dma_addr); +} + +static void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, + size_t size, dma_addr_t *dma_handle) +{ + u64 kernel_addr; + + /* roundup to CPU_PKT_SIZE */ + size = (size + (CPU_PKT_SIZE - 1)) & CPU_PKT_MASK; + + kernel_addr = gen_pool_alloc(hdev->cpu_accessible_dma_pool, size); + + *dma_handle = hdev->cpu_accessible_dma_address + + (kernel_addr - (u64) (uintptr_t) hdev->cpu_accessible_dma_mem); + + return (void *) (uintptr_t) kernel_addr; +} + +static void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, + size_t size, void *vaddr) +{ + /* roundup to CPU_PKT_SIZE */ + size = (size + (CPU_PKT_SIZE - 1)) & CPU_PKT_MASK; + + gen_pool_free(hdev->cpu_accessible_dma_pool, (u64) (uintptr_t) vaddr, + size); +} + +static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ + if (!dma_map_sg(&hdev->pdev->dev, sg, nents, dir)) + return -ENOMEM; + + return 0; +} + +static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ + dma_unmap_sg(&hdev->pdev->dev, sg, nents, dir); +} + +u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt) +{ + struct scatterlist *sg, *sg_next_iter; + u32 count, dma_desc_cnt; + u64 len, len_next; + dma_addr_t addr, addr_next; + + dma_desc_cnt = 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, count) { + + len = sg_dma_len(sg); + addr = sg_dma_address(sg); + + if (len == 0) + break; + + while ((count + 1) < sgt->nents) { + sg_next_iter = sg_next(sg); + len_next = sg_dma_len(sg_next_iter); + addr_next = sg_dma_address(sg_next_iter); + + if (len_next == 0) + break; + + if ((addr + len == addr_next) && + (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { + len += len_next; + count++; + sg = sg_next_iter; + } else { + break; + } + } + + dma_desc_cnt++; + } + + return dma_desc_cnt * sizeof(struct packet_lin_dma); +} + +static int goya_pin_memory_before_cs(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + u64 addr, enum dma_data_direction dir) +{ + struct hl_userptr *userptr; + int rc; + + if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), + parser->job_userptr_list, &userptr)) + goto already_pinned; + + userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC); + if (!userptr) + return -ENOMEM; + + rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), + userptr); + if (rc) + goto free_userptr; + + list_add_tail(&userptr->job_node, parser->job_userptr_list); + + rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl, + userptr->sgt->nents, dir); + if (rc) { + dev_err(hdev->dev, "failed to map sgt with DMA region\n"); + goto unpin_memory; + } + + userptr->dma_mapped = true; + userptr->dir = dir; + +already_pinned: + parser->patched_cb_size += + goya_get_dma_desc_list_size(hdev, userptr->sgt); + + return 0; + +unpin_memory: + hl_unpin_host_memory(hdev, userptr); +free_userptr: + kfree(userptr); + return rc; +} + +static int goya_validate_dma_pkt_host(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt) +{ + u64 device_memory_addr, addr; + enum dma_data_direction dir; + enum goya_dma_direction user_dir; + bool sram_addr = true; + bool skip_host_mem_pin = false; + bool user_memset; + u32 ctl; + int rc = 0; + + ctl = le32_to_cpu(user_dma_pkt->ctl); + + user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> + GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; + + user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >> + GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; + + switch (user_dir) { + case DMA_HOST_TO_DRAM: + dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n"); + dir = DMA_TO_DEVICE; + sram_addr = false; + addr = le64_to_cpu(user_dma_pkt->src_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); + if (user_memset) + skip_host_mem_pin = true; + break; + + case DMA_DRAM_TO_HOST: + dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n"); + dir = DMA_FROM_DEVICE; + sram_addr = false; + addr = le64_to_cpu(user_dma_pkt->dst_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); + break; + + case DMA_HOST_TO_SRAM: + dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n"); + dir = DMA_TO_DEVICE; + addr = le64_to_cpu(user_dma_pkt->src_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); + if (user_memset) + skip_host_mem_pin = true; + break; + + case DMA_SRAM_TO_HOST: + dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n"); + dir = DMA_FROM_DEVICE; + addr = le64_to_cpu(user_dma_pkt->dst_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); + break; + default: + dev_err(hdev->dev, "DMA direction is undefined\n"); + return -EFAULT; + } + + if (parser->ctx_id != HL_KERNEL_ASID_ID) { + if (sram_addr) { + if (!hl_mem_area_inside_range(device_memory_addr, + le32_to_cpu(user_dma_pkt->tsize), + hdev->asic_prop.sram_user_base_address, + hdev->asic_prop.sram_end_address)) { + + dev_err(hdev->dev, + "SRAM address 0x%llx + 0x%x is invalid\n", + device_memory_addr, + user_dma_pkt->tsize); + return -EFAULT; + } + } else { + if (!hl_mem_area_inside_range(device_memory_addr, + le32_to_cpu(user_dma_pkt->tsize), + hdev->asic_prop.dram_user_base_address, + hdev->asic_prop.dram_end_address)) { + + dev_err(hdev->dev, + "DRAM address 0x%llx + 0x%x is invalid\n", + device_memory_addr, + user_dma_pkt->tsize); + return -EFAULT; + } + } + } + + if (skip_host_mem_pin) + parser->patched_cb_size += sizeof(*user_dma_pkt); + else { + if ((dir == DMA_TO_DEVICE) && + (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) { + dev_err(hdev->dev, + "Can't DMA from host on queue other then 1\n"); + return -EFAULT; + } + + rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt, + addr, dir); + } + + return rc; +} + +static int goya_validate_dma_pkt_no_host(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt) +{ + u64 sram_memory_addr, dram_memory_addr; + enum goya_dma_direction user_dir; + u32 ctl; + + ctl = le32_to_cpu(user_dma_pkt->ctl); + user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> + GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; + + if (user_dir == DMA_DRAM_TO_SRAM) { + dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n"); + dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); + sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); + } else { + dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n"); + sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); + dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); + } + + if (!hl_mem_area_inside_range(sram_memory_addr, + le32_to_cpu(user_dma_pkt->tsize), + hdev->asic_prop.sram_user_base_address, + hdev->asic_prop.sram_end_address)) { + dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n", + sram_memory_addr, user_dma_pkt->tsize); + return -EFAULT; + } + + if (!hl_mem_area_inside_range(dram_memory_addr, + le32_to_cpu(user_dma_pkt->tsize), + hdev->asic_prop.dram_user_base_address, + hdev->asic_prop.dram_end_address)) { + dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n", + dram_memory_addr, user_dma_pkt->tsize); + return -EFAULT; + } + + parser->patched_cb_size += sizeof(*user_dma_pkt); + + return 0; +} + +static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt) +{ + enum goya_dma_direction user_dir; + u32 ctl; + int rc; + + dev_dbg(hdev->dev, "DMA packet details:\n"); + dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr); + dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr); + dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize); + + ctl = le32_to_cpu(user_dma_pkt->ctl); + user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> + GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; + + /* + * Special handling for DMA with size 0. The H/W has a bug where + * this can cause the QMAN DMA to get stuck, so block it here. + */ + if (user_dma_pkt->tsize == 0) { + dev_err(hdev->dev, + "Got DMA with size 0, might reset the device\n"); + return -EINVAL; + } + + if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM)) + rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt); + else + rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt); + + return rc; +} + +static int goya_validate_dma_pkt_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt) +{ + dev_dbg(hdev->dev, "DMA packet details:\n"); + dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr); + dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr); + dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize); + + /* + * WA for HW-23. + * We can't allow user to read from Host using QMANs other than 1. + */ + if (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1 && + hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr), + le32_to_cpu(user_dma_pkt->tsize), + hdev->asic_prop.va_space_host_start_address, + hdev->asic_prop.va_space_host_end_address)) { + dev_err(hdev->dev, + "Can't DMA from host on queue other then 1\n"); + return -EFAULT; + } + + if (user_dma_pkt->tsize == 0) { + dev_err(hdev->dev, + "Got DMA with size 0, might reset the device\n"); + return -EINVAL; + } + + parser->patched_cb_size += sizeof(*user_dma_pkt); + + return 0; +} + +static int goya_validate_wreg32(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_wreg32 *wreg_pkt) +{ + struct goya_device *goya = hdev->asic_specific; + u32 sob_start_addr, sob_end_addr; + u16 reg_offset; + + reg_offset = le32_to_cpu(wreg_pkt->ctl) & + GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK; + + dev_dbg(hdev->dev, "WREG32 packet details:\n"); + dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset); + dev_dbg(hdev->dev, "value == 0x%x\n", wreg_pkt->value); + + if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) { + dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n", + reg_offset); + return -EPERM; + } + + /* + * With MMU, DMA channels are not secured, so it doesn't matter where + * the WR COMP will be written to because it will go out with + * non-secured property + */ + if (goya->hw_cap_initialized & HW_CAP_MMU) + return 0; + + sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); + sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023); + + if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) || + (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) { + + dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n", + wreg_pkt->value); + return -EPERM; + } + + return 0; +} + +static int goya_validate_cb(struct hl_device *hdev, + struct hl_cs_parser *parser, bool is_mmu) +{ + u32 cb_parsed_length = 0; + int rc = 0; + + parser->patched_cb_size = 0; + + /* cb_user_size is more than 0 so loop will always be executed */ + while (cb_parsed_length < parser->user_cb_size) { + enum packet_id pkt_id; + u16 pkt_size; + void *user_pkt; + + user_pkt = (void *) (uintptr_t) + (parser->user_cb->kernel_address + cb_parsed_length); + + pkt_id = (enum packet_id) (((*(u64 *) user_pkt) & + PACKET_HEADER_PACKET_ID_MASK) >> + PACKET_HEADER_PACKET_ID_SHIFT); + + pkt_size = goya_packet_sizes[pkt_id]; + cb_parsed_length += pkt_size; + if (cb_parsed_length > parser->user_cb_size) { + dev_err(hdev->dev, + "packet 0x%x is out of CB boundary\n", pkt_id); + rc = -EINVAL; + break; + } + + switch (pkt_id) { + case PACKET_WREG_32: + /* + * Although it is validated after copy in patch_cb(), + * need to validate here as well because patch_cb() is + * not called in MMU path while this function is called + */ + rc = goya_validate_wreg32(hdev, parser, user_pkt); + break; + + case PACKET_WREG_BULK: + dev_err(hdev->dev, + "User not allowed to use WREG_BULK\n"); + rc = -EPERM; + break; + + case PACKET_MSG_PROT: + dev_err(hdev->dev, + "User not allowed to use MSG_PROT\n"); + rc = -EPERM; + break; + + case PACKET_CP_DMA: + dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); + rc = -EPERM; + break; + + case PACKET_STOP: + dev_err(hdev->dev, "User not allowed to use STOP\n"); + rc = -EPERM; + break; + + case PACKET_LIN_DMA: + if (is_mmu) + rc = goya_validate_dma_pkt_mmu(hdev, parser, + user_pkt); + else + rc = goya_validate_dma_pkt_no_mmu(hdev, parser, + user_pkt); + break; + + case PACKET_MSG_LONG: + case PACKET_MSG_SHORT: + case PACKET_FENCE: + case PACKET_NOP: + parser->patched_cb_size += pkt_size; + break; + + default: + dev_err(hdev->dev, "Invalid packet header 0x%x\n", + pkt_id); + rc = -EINVAL; + break; + } + + if (rc) + break; + } + + /* + * The new CB should have space at the end for two MSG_PROT packets: + * 1. A packet that will act as a completion packet + * 2. A packet that will generate MSI-X interrupt + */ + parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2; + + return rc; +} + +static int goya_patch_dma_packet(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + struct packet_lin_dma *new_dma_pkt, + u32 *new_dma_pkt_size) +{ + struct hl_userptr *userptr; + struct scatterlist *sg, *sg_next_iter; + u32 count, dma_desc_cnt; + u64 len, len_next; + dma_addr_t dma_addr, dma_addr_next; + enum goya_dma_direction user_dir; + u64 device_memory_addr, addr; + enum dma_data_direction dir; + struct sg_table *sgt; + bool skip_host_mem_pin = false; + bool user_memset; + u32 user_rdcomp_mask, user_wrcomp_mask, ctl; + + ctl = le32_to_cpu(user_dma_pkt->ctl); + + user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> + GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; + + user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >> + GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; + + if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) || + (user_dma_pkt->tsize == 0)) { + memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt)); + *new_dma_pkt_size = sizeof(*new_dma_pkt); + return 0; + } + + if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) { + addr = le64_to_cpu(user_dma_pkt->src_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); + dir = DMA_TO_DEVICE; + if (user_memset) + skip_host_mem_pin = true; + } else { + addr = le64_to_cpu(user_dma_pkt->dst_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); + dir = DMA_FROM_DEVICE; + } + + if ((!skip_host_mem_pin) && + (hl_userptr_is_pinned(hdev, addr, + le32_to_cpu(user_dma_pkt->tsize), + parser->job_userptr_list, &userptr) == false)) { + dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n", + addr, user_dma_pkt->tsize); + return -EFAULT; + } + + if ((user_memset) && (dir == DMA_TO_DEVICE)) { + memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt)); + *new_dma_pkt_size = sizeof(*user_dma_pkt); + return 0; + } + + user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK; + + user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK; + + sgt = userptr->sgt; + dma_desc_cnt = 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, count) { + len = sg_dma_len(sg); + dma_addr = sg_dma_address(sg); + + if (len == 0) + break; + + while ((count + 1) < sgt->nents) { + sg_next_iter = sg_next(sg); + len_next = sg_dma_len(sg_next_iter); + dma_addr_next = sg_dma_address(sg_next_iter); + + if (len_next == 0) + break; + + if ((dma_addr + len == dma_addr_next) && + (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { + len += len_next; + count++; + sg = sg_next_iter; + } else { + break; + } + } + + ctl = le32_to_cpu(user_dma_pkt->ctl); + if (likely(dma_desc_cnt)) + ctl &= ~GOYA_PKT_CTL_EB_MASK; + ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK | + GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK); + new_dma_pkt->ctl = cpu_to_le32(ctl); + new_dma_pkt->tsize = cpu_to_le32((u32) len); + + dma_addr += hdev->asic_prop.host_phys_base_address; + + if (dir == DMA_TO_DEVICE) { + new_dma_pkt->src_addr = cpu_to_le64(dma_addr); + new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr); + } else { + new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr); + new_dma_pkt->dst_addr = cpu_to_le64(dma_addr); + } + + if (!user_memset) + device_memory_addr += len; + dma_desc_cnt++; + new_dma_pkt++; + } + + if (!dma_desc_cnt) { + dev_err(hdev->dev, + "Error of 0 SG entries when patching DMA packet\n"); + return -EFAULT; + } + + /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */ + new_dma_pkt--; + new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask); + + *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma); + + return 0; +} + +static int goya_patch_cb(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u32 cb_parsed_length = 0; + u32 cb_patched_cur_length = 0; + int rc = 0; + + /* cb_user_size is more than 0 so loop will always be executed */ + while (cb_parsed_length < parser->user_cb_size) { + enum packet_id pkt_id; + u16 pkt_size; + u32 new_pkt_size = 0; + void *user_pkt, *kernel_pkt; + + user_pkt = (void *) (uintptr_t) + (parser->user_cb->kernel_address + cb_parsed_length); + kernel_pkt = (void *) (uintptr_t) + (parser->patched_cb->kernel_address + + cb_patched_cur_length); + + pkt_id = (enum packet_id) (((*(u64 *) user_pkt) & + PACKET_HEADER_PACKET_ID_MASK) >> + PACKET_HEADER_PACKET_ID_SHIFT); + + pkt_size = goya_packet_sizes[pkt_id]; + cb_parsed_length += pkt_size; + if (cb_parsed_length > parser->user_cb_size) { + dev_err(hdev->dev, + "packet 0x%x is out of CB boundary\n", pkt_id); + rc = -EINVAL; + break; + } + + switch (pkt_id) { + case PACKET_LIN_DMA: + rc = goya_patch_dma_packet(hdev, parser, user_pkt, + kernel_pkt, &new_pkt_size); + cb_patched_cur_length += new_pkt_size; + break; + + case PACKET_WREG_32: + memcpy(kernel_pkt, user_pkt, pkt_size); + cb_patched_cur_length += pkt_size; + rc = goya_validate_wreg32(hdev, parser, kernel_pkt); + break; + + case PACKET_WREG_BULK: + dev_err(hdev->dev, + "User not allowed to use WREG_BULK\n"); + rc = -EPERM; + break; + + case PACKET_MSG_PROT: + dev_err(hdev->dev, + "User not allowed to use MSG_PROT\n"); + rc = -EPERM; + break; + + case PACKET_CP_DMA: + dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); + rc = -EPERM; + break; + + case PACKET_STOP: + dev_err(hdev->dev, "User not allowed to use STOP\n"); + rc = -EPERM; + break; + + case PACKET_MSG_LONG: + case PACKET_MSG_SHORT: + case PACKET_FENCE: + case PACKET_NOP: + memcpy(kernel_pkt, user_pkt, pkt_size); + cb_patched_cur_length += pkt_size; + break; + + default: + dev_err(hdev->dev, "Invalid packet header 0x%x\n", + pkt_id); + rc = -EINVAL; + break; + } + + if (rc) + break; + } + + return rc; +} + +static int goya_parse_cb_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u64 patched_cb_handle; + u32 patched_cb_size; + struct hl_cb *user_cb; + int rc; + + /* + * The new CB should have space at the end for two MSG_PROT pkt: + * 1. A packet that will act as a completion packet + * 2. A packet that will generate MSI-X interrupt + */ + parser->patched_cb_size = parser->user_cb_size + + sizeof(struct packet_msg_prot) * 2; + + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, + parser->patched_cb_size, + &patched_cb_handle, HL_KERNEL_ASID_ID); + + if (rc) { + dev_err(hdev->dev, + "Failed to allocate patched CB for DMA CS %d\n", + rc); + return rc; + } + + patched_cb_handle >>= PAGE_SHIFT; + parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr, + (u32) patched_cb_handle); + /* hl_cb_get should never fail here so use kernel WARN */ + WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n", + (u32) patched_cb_handle); + if (!parser->patched_cb) { + rc = -EFAULT; + goto out; + } + + /* + * The check that parser->user_cb_size <= parser->user_cb->size was done + * in validate_queue_index(). + */ + memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address, + (void *) (uintptr_t) parser->user_cb->kernel_address, + parser->user_cb_size); + + patched_cb_size = parser->patched_cb_size; + + /* validate patched CB instead of user CB */ + user_cb = parser->user_cb; + parser->user_cb = parser->patched_cb; + rc = goya_validate_cb(hdev, parser, true); + parser->user_cb = user_cb; + + if (rc) { + hl_cb_put(parser->patched_cb); + goto out; + } + + if (patched_cb_size != parser->patched_cb_size) { + dev_err(hdev->dev, "user CB size mismatch\n"); + hl_cb_put(parser->patched_cb); + rc = -EINVAL; + goto out; + } + +out: + /* + * Always call cb destroy here because we still have 1 reference + * to it by calling cb_get earlier. After the job will be completed, + * cb_put will release it, but here we want to remove it from the + * idr + */ + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, + patched_cb_handle << PAGE_SHIFT); + + return rc; +} + +static int goya_parse_cb_no_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u64 patched_cb_handle; + int rc; + + rc = goya_validate_cb(hdev, parser, false); + + if (rc) + goto free_userptr; + + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, + parser->patched_cb_size, + &patched_cb_handle, HL_KERNEL_ASID_ID); + if (rc) { + dev_err(hdev->dev, + "Failed to allocate patched CB for DMA CS %d\n", rc); + goto free_userptr; + } + + patched_cb_handle >>= PAGE_SHIFT; + parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr, + (u32) patched_cb_handle); + /* hl_cb_get should never fail here so use kernel WARN */ + WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n", + (u32) patched_cb_handle); + if (!parser->patched_cb) { + rc = -EFAULT; + goto out; + } + + rc = goya_patch_cb(hdev, parser); + + if (rc) + hl_cb_put(parser->patched_cb); + +out: + /* + * Always call cb destroy here because we still have 1 reference + * to it by calling cb_get earlier. After the job will be completed, + * cb_put will release it, but here we want to remove it from the + * idr + */ + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, + patched_cb_handle << PAGE_SHIFT); + +free_userptr: + if (rc) + hl_userptr_delete_list(hdev, parser->job_userptr_list); + return rc; +} + +static int goya_parse_cb_no_ext_quque(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + struct asic_fixed_properties *asic_prop = &hdev->asic_prop; + struct goya_device *goya = hdev->asic_specific; + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) { + /* For internal queue jobs, just check if cb address is valid */ + if (hl_mem_area_inside_range( + (u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->sram_user_base_address, + asic_prop->sram_end_address)) + return 0; + + if (hl_mem_area_inside_range( + (u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->dram_user_base_address, + asic_prop->dram_end_address)) + return 0; + + dev_err(hdev->dev, + "Internal CB address %px + 0x%x is not in SRAM nor in DRAM\n", + parser->user_cb, parser->user_cb_size); + + return -EFAULT; + } + + return 0; +} + +int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) +{ + struct goya_device *goya = hdev->asic_specific; + + if (!parser->ext_queue) + return goya_parse_cb_no_ext_quque(hdev, parser); + + if ((goya->hw_cap_initialized & HW_CAP_MMU) && parser->use_virt_addr) + return goya_parse_cb_mmu(hdev, parser); + else + return goya_parse_cb_no_mmu(hdev, parser); +} + +void goya_add_end_of_cb_packets(u64 kernel_address, u32 len, u64 cq_addr, + u32 cq_val, u32 msix_vec) +{ + struct packet_msg_prot *cq_pkt; + u32 tmp; + + cq_pkt = (struct packet_msg_prot *) (uintptr_t) + (kernel_address + len - (sizeof(struct packet_msg_prot) * 2)); + + tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | + (1 << GOYA_PKT_CTL_EB_SHIFT) | + (1 << GOYA_PKT_CTL_MB_SHIFT); + cq_pkt->ctl = cpu_to_le32(tmp); + cq_pkt->value = cpu_to_le32(cq_val); + cq_pkt->addr = cpu_to_le64(cq_addr); + + cq_pkt++; + + tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | + (1 << GOYA_PKT_CTL_MB_SHIFT); + cq_pkt->ctl = cpu_to_le32(tmp); + cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF); + cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF); +} + +static void goya_update_eq_ci(struct hl_device *hdev, u32 val) +{ + WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, val); +} + +static void goya_restore_phase_topology(struct hl_device *hdev) +{ + int i, num_of_sob_in_longs, num_of_mon_in_longs; + + num_of_sob_in_longs = + ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4); + + num_of_mon_in_longs = + ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4); + + for (i = 0 ; i < num_of_sob_in_longs ; i += 4) + WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0); + + for (i = 0 ; i < num_of_mon_in_longs ; i += 4) + WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0); + + /* Flush all WREG to prevent race */ + i = RREG32(mmSYNC_MNGR_SOB_OBJ_0); +} + +/* + * goya_debugfs_read32 - read a 32bit value from a given device address + * + * @hdev: pointer to hl_device structure + * @addr: address in device + * @val: returned value + * + * In case of DDR address that is not mapped into the default aperture that + * the DDR bar exposes, the function will configure the iATU so that the DDR + * bar will be positioned at a base address that allows reading from the + * required address. Configuring the iATU during normal operation can + * lead to undefined behavior and therefore, should be done with extreme care + * + */ +static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { + *val = RREG32(addr - CFG_BASE); + + } else if ((addr >= SRAM_BASE_ADDR) && + (addr < SRAM_BASE_ADDR + SRAM_SIZE)) { + + *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + + } else if ((addr >= DRAM_PHYS_BASE) && + (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) { + + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + rc = goya_set_ddr_bar_base(hdev, bar_base_addr); + if (!rc) { + *val = readl(hdev->pcie_bar[DDR_BAR_ID] + + (addr - bar_base_addr)); + + rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE + + (MMU_PAGE_TABLES_ADDR & + ~(prop->dram_pci_bar_size - 0x1ull))); + } + } else { + rc = -EFAULT; + } + + return rc; +} + +/* + * goya_debugfs_write32 - write a 32bit value to a given device address + * + * @hdev: pointer to hl_device structure + * @addr: address in device + * @val: returned value + * + * In case of DDR address that is not mapped into the default aperture that + * the DDR bar exposes, the function will configure the iATU so that the DDR + * bar will be positioned at a base address that allows writing to the + * required address. Configuring the iATU during normal operation can + * lead to undefined behavior and therefore, should be done with extreme care + * + */ +static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { + WREG32(addr - CFG_BASE, val); + + } else if ((addr >= SRAM_BASE_ADDR) && + (addr < SRAM_BASE_ADDR + SRAM_SIZE)) { + + writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + + } else if ((addr >= DRAM_PHYS_BASE) && + (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) { + + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + rc = goya_set_ddr_bar_base(hdev, bar_base_addr); + if (!rc) { + writel(val, hdev->pcie_bar[DDR_BAR_ID] + + (addr - bar_base_addr)); + + rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE + + (MMU_PAGE_TABLES_ADDR & + ~(prop->dram_pci_bar_size - 0x1ull))); + } + } else { + rc = -EFAULT; + } + + return rc; +} + +static u64 goya_read_pte(struct hl_device *hdev, u64 addr) +{ + struct goya_device *goya = hdev->asic_specific; + + return readq(hdev->pcie_bar[DDR_BAR_ID] + + (addr - goya->ddr_bar_cur_addr)); +} + +static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val) +{ + struct goya_device *goya = hdev->asic_specific; + + writeq(val, hdev->pcie_bar[DDR_BAR_ID] + + (addr - goya->ddr_bar_cur_addr)); +} + +static const char *_goya_get_event_desc(u16 event_type) +{ + switch (event_type) { + case GOYA_ASYNC_EVENT_ID_PCIE_DEC: + return "PCIe_dec"; + case GOYA_ASYNC_EVENT_ID_TPC0_DEC: + case GOYA_ASYNC_EVENT_ID_TPC1_DEC: + case GOYA_ASYNC_EVENT_ID_TPC2_DEC: + case GOYA_ASYNC_EVENT_ID_TPC3_DEC: + case GOYA_ASYNC_EVENT_ID_TPC4_DEC: + case GOYA_ASYNC_EVENT_ID_TPC5_DEC: + case GOYA_ASYNC_EVENT_ID_TPC6_DEC: + case GOYA_ASYNC_EVENT_ID_TPC7_DEC: + return "TPC%d_dec"; + case GOYA_ASYNC_EVENT_ID_MME_WACS: + return "MME_wacs"; + case GOYA_ASYNC_EVENT_ID_MME_WACSD: + return "MME_wacsd"; + case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER: + return "CPU_axi_splitter"; + case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC: + return "PSOC_axi_dec"; + case GOYA_ASYNC_EVENT_ID_PSOC: + return "PSOC"; + case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR: + return "TPC%d_krn_err"; + case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ: + return "TPC%d_cq"; + case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM: + return "TPC%d_qm"; + case GOYA_ASYNC_EVENT_ID_MME_QM: + return "MME_qm"; + case GOYA_ASYNC_EVENT_ID_MME_CMDQ: + return "MME_cq"; + case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM: + return "DMA%d_qm"; + case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH: + return "DMA%d_ch"; + default: + return "N/A"; + } +} + +static void goya_get_event_desc(u16 event_type, char *desc, size_t size) +{ + u8 index; + + switch (event_type) { + case GOYA_ASYNC_EVENT_ID_TPC0_DEC: + case GOYA_ASYNC_EVENT_ID_TPC1_DEC: + case GOYA_ASYNC_EVENT_ID_TPC2_DEC: + case GOYA_ASYNC_EVENT_ID_TPC3_DEC: + case GOYA_ASYNC_EVENT_ID_TPC4_DEC: + case GOYA_ASYNC_EVENT_ID_TPC5_DEC: + case GOYA_ASYNC_EVENT_ID_TPC6_DEC: + case GOYA_ASYNC_EVENT_ID_TPC7_DEC: + index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3; + snprintf(desc, size, _goya_get_event_desc(event_type), index); + break; + case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR: + index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10; + snprintf(desc, size, _goya_get_event_desc(event_type), index); + break; + case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ: + index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ; + snprintf(desc, size, _goya_get_event_desc(event_type), index); + break; + case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM: + index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM; + snprintf(desc, size, _goya_get_event_desc(event_type), index); + break; + case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM: + index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM; + snprintf(desc, size, _goya_get_event_desc(event_type), index); + break; + case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH: + index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH; + snprintf(desc, size, _goya_get_event_desc(event_type), index); + break; + default: + snprintf(desc, size, _goya_get_event_desc(event_type)); + break; + } +} + +static void goya_print_razwi_info(struct hl_device *hdev) +{ + if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) { + dev_err(hdev->dev, "Illegal write to LBW\n"); + WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0); + } + + if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) { + dev_err(hdev->dev, "Illegal read from LBW\n"); + WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0); + } + + if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) { + dev_err(hdev->dev, "Illegal write to HBW\n"); + WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0); + } + + if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) { + dev_err(hdev->dev, "Illegal read from HBW\n"); + WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0); + } +} + +static void goya_print_mmu_error_info(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + u64 addr; + u32 val; + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) + return; + + val = RREG32(mmMMU_PAGE_ERROR_CAPTURE); + if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) { + addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK; + addr <<= 32; + addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA); + + dev_err(hdev->dev, "MMU page fault on va 0x%llx\n", addr); + + WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0); + } +} + +static void goya_print_irq_info(struct hl_device *hdev, u16 event_type) +{ + char desc[20] = ""; + + goya_get_event_desc(event_type, desc, sizeof(desc)); + dev_err(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", + event_type, desc); + + goya_print_razwi_info(hdev); + goya_print_mmu_error_info(hdev); +} + +static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr, + size_t irq_arr_size) +{ + struct armcp_unmask_irq_arr_packet *pkt; + size_t total_pkt_size; + long result; + int rc; + + total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) + + irq_arr_size; + + /* data should be aligned to 8 bytes in order to ArmCP to copy it */ + total_pkt_size = (total_pkt_size + 0x7) & ~0x7; + + /* total_pkt_size is casted to u16 later on */ + if (total_pkt_size > USHRT_MAX) { + dev_err(hdev->dev, "too many elements in IRQ array\n"); + return -EINVAL; + } + + pkt = kzalloc(total_pkt_size, GFP_KERNEL); + if (!pkt) + return -ENOMEM; + + pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0])); + memcpy(&pkt->irqs, irq_arr, irq_arr_size); + + pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << + ARMCP_PKT_CTL_OPCODE_SHIFT); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, + total_pkt_size, HL_DEVICE_TIMEOUT_USEC, &result); + + if (rc) + dev_err(hdev->dev, "failed to unmask IRQ array\n"); + + kfree(pkt); + + return rc; +} + +static int goya_soft_reset_late_init(struct hl_device *hdev) +{ + /* + * Unmask all IRQs since some could have been received + * during the soft reset + */ + return goya_unmask_irq_arr(hdev, goya_non_fatal_events, + sizeof(goya_non_fatal_events)); +} + +static int goya_unmask_irq(struct hl_device *hdev, u16 event_type) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.value = cpu_to_le64(event_type); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_DEVICE_TIMEOUT_USEC, &result); + + if (rc) + dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type); + + return rc; +} + +void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry) +{ + u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); + u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) + >> EQ_CTL_EVENT_TYPE_SHIFT); + struct goya_device *goya = hdev->asic_specific; + + goya->events_stat[event_type]++; + + switch (event_type) { + case GOYA_ASYNC_EVENT_ID_PCIE_IF: + case GOYA_ASYNC_EVENT_ID_TPC0_ECC: + case GOYA_ASYNC_EVENT_ID_TPC1_ECC: + case GOYA_ASYNC_EVENT_ID_TPC2_ECC: + case GOYA_ASYNC_EVENT_ID_TPC3_ECC: + case GOYA_ASYNC_EVENT_ID_TPC4_ECC: + case GOYA_ASYNC_EVENT_ID_TPC5_ECC: + case GOYA_ASYNC_EVENT_ID_TPC6_ECC: + case GOYA_ASYNC_EVENT_ID_TPC7_ECC: + case GOYA_ASYNC_EVENT_ID_MME_ECC: + case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT: + case GOYA_ASYNC_EVENT_ID_MMU_ECC: + case GOYA_ASYNC_EVENT_ID_DMA_MACRO: + case GOYA_ASYNC_EVENT_ID_DMA_ECC: + case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC: + case GOYA_ASYNC_EVENT_ID_PSOC_MEM: + case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT: + case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29: + case GOYA_ASYNC_EVENT_ID_GIC500: + case GOYA_ASYNC_EVENT_ID_PLL0: + case GOYA_ASYNC_EVENT_ID_PLL1: + case GOYA_ASYNC_EVENT_ID_PLL3: + case GOYA_ASYNC_EVENT_ID_PLL4: + case GOYA_ASYNC_EVENT_ID_PLL5: + case GOYA_ASYNC_EVENT_ID_PLL6: + case GOYA_ASYNC_EVENT_ID_AXI_ECC: + case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC: + case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET: + case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT: + dev_err(hdev->dev, + "Received H/W interrupt %d, reset the chip\n", + event_type); + hl_device_reset(hdev, true, false); + break; + + case GOYA_ASYNC_EVENT_ID_PCIE_DEC: + case GOYA_ASYNC_EVENT_ID_TPC0_DEC: + case GOYA_ASYNC_EVENT_ID_TPC1_DEC: + case GOYA_ASYNC_EVENT_ID_TPC2_DEC: + case GOYA_ASYNC_EVENT_ID_TPC3_DEC: + case GOYA_ASYNC_EVENT_ID_TPC4_DEC: + case GOYA_ASYNC_EVENT_ID_TPC5_DEC: + case GOYA_ASYNC_EVENT_ID_TPC6_DEC: + case GOYA_ASYNC_EVENT_ID_TPC7_DEC: + case GOYA_ASYNC_EVENT_ID_MME_WACS: + case GOYA_ASYNC_EVENT_ID_MME_WACSD: + case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER: + case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC: + case GOYA_ASYNC_EVENT_ID_PSOC: + case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR: + case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM: + case GOYA_ASYNC_EVENT_ID_MME_QM: + case GOYA_ASYNC_EVENT_ID_MME_CMDQ: + case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM: + case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH: + goya_print_irq_info(hdev, event_type); + goya_unmask_irq(hdev, event_type); + break; + + case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU: + case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0: + case GOYA_ASYNC_EVENT_ID_DMA_BM_CH1: + case GOYA_ASYNC_EVENT_ID_DMA_BM_CH2: + case GOYA_ASYNC_EVENT_ID_DMA_BM_CH3: + case GOYA_ASYNC_EVENT_ID_DMA_BM_CH4: + dev_info(hdev->dev, "Received H/W interrupt %d\n", event_type); + break; + + default: + dev_err(hdev->dev, "Received invalid H/W interrupt %d\n", + event_type); + break; + } +} + +void *goya_get_events_stat(struct hl_device *hdev, u32 *size) +{ + struct goya_device *goya = hdev->asic_specific; + + *size = (u32) sizeof(goya->events_stat); + + return goya->events_stat; +} + +static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u32 size, + u64 val, bool is_dram) +{ + struct packet_lin_dma *lin_dma_pkt; + struct hl_cs_parser parser; + struct hl_cs_job *job; + u32 cb_size, ctl; + struct hl_cb *cb; + int rc; + + cb = hl_cb_kernel_create(hdev, PAGE_SIZE); + if (!cb) + return -EFAULT; + + lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address; + + memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt)); + cb_size = sizeof(*lin_dma_pkt); + + ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) | + (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) | + (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) | + (1 << GOYA_PKT_CTL_RB_SHIFT) | + (1 << GOYA_PKT_CTL_MB_SHIFT)); + ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) << + GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; + lin_dma_pkt->ctl = cpu_to_le32(ctl); + + lin_dma_pkt->src_addr = cpu_to_le64(val); + lin_dma_pkt->dst_addr = cpu_to_le64(addr); + lin_dma_pkt->tsize = cpu_to_le32(size); + + job = hl_cs_allocate_job(hdev, true); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + goto release_cb; + } + + job->id = 0; + job->user_cb = cb; + job->user_cb->cs_cnt++; + job->user_cb_size = cb_size; + job->hw_queue_id = GOYA_QUEUE_ID_DMA_0; + + hl_debugfs_add_job(hdev, job); + + parser.ctx_id = HL_KERNEL_ASID_ID; + parser.cs_sequence = 0; + parser.job_id = job->id; + parser.hw_queue_id = job->hw_queue_id; + parser.job_userptr_list = &job->userptr_list; + parser.user_cb = job->user_cb; + parser.user_cb_size = job->user_cb_size; + parser.ext_queue = job->ext_queue; + parser.use_virt_addr = hdev->mmu_enable; + + rc = hdev->asic_funcs->cs_parser(hdev, &parser); + if (rc) { + dev_err(hdev->dev, "Failed to parse kernel CB\n"); + goto free_job; + } + + job->patched_cb = parser.patched_cb; + job->job_cb_size = parser.patched_cb_size; + job->patched_cb->cs_cnt++; + + rc = goya_send_job_on_qman0(hdev, job); + + job->patched_cb->cs_cnt--; + hl_cb_put(job->patched_cb); + +free_job: + hl_userptr_delete_list(hdev, &job->userptr_list); + hl_debugfs_remove_job(hdev, job); + kfree(job); + cb->cs_cnt--; + +release_cb: + hl_cb_put(cb); + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT); + + return rc; +} + +static int goya_context_switch(struct hl_device *hdev, u32 asid) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 addr = prop->sram_base_address; + u32 size = hdev->pldm ? 0x10000 : prop->sram_size; + u64 val = 0x7777777777777777ull; + int rc; + + rc = goya_memset_device_memory(hdev, addr, size, val, false); + if (rc) { + dev_err(hdev->dev, "Failed to clear SRAM in context switch\n"); + return rc; + } + + goya_mmu_prepare(hdev, asid); + + return 0; +} + +static int goya_mmu_clear_pgt_range(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct goya_device *goya = hdev->asic_specific; + u64 addr = prop->mmu_pgt_addr; + u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE + + MMU_CACHE_MNG_SIZE; + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) + return 0; + + return goya_memset_device_memory(hdev, addr, size, 0, true); +} + +static int goya_mmu_set_dram_default_page(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + u64 addr = hdev->asic_prop.mmu_dram_default_page_addr; + u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE; + u64 val = 0x9999999999999999ull; + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) + return 0; + + return goya_memset_device_memory(hdev, addr, size, val, true); +} + +static void goya_mmu_prepare(struct hl_device *hdev, u32 asid) +{ + struct goya_device *goya = hdev->asic_specific; + int i; + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) + return; + + if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) { + WARN(1, "asid %u is too big\n", asid); + return; + } + + /* zero the MMBP and ASID bits and then set the ASID */ + for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++) { + WREG32_AND(goya_mmu_regs[i], ~0x7FF); + WREG32_OR(goya_mmu_regs[i], asid); + } +} + +static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard) +{ + struct goya_device *goya = hdev->asic_specific; + u32 status, timeout_usec; + int rc; + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) + return; + + /* no need in L1 only invalidation in Goya */ + if (!is_hard) + return; + + if (hdev->pldm) + timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + mutex_lock(&hdev->mmu_cache_lock); + + /* L0 & L1 invalidation */ + WREG32(mmSTLB_INV_ALL_START, 1); + + rc = hl_poll_timeout( + hdev, + mmSTLB_INV_ALL_START, + status, + !status, + 1000, + timeout_usec); + + mutex_unlock(&hdev->mmu_cache_lock); + + if (rc) + dev_notice_ratelimited(hdev->dev, + "Timeout when waiting for MMU cache invalidation\n"); +} + +static void goya_mmu_invalidate_cache_range(struct hl_device *hdev, + bool is_hard, u32 asid, u64 va, u64 size) +{ + struct goya_device *goya = hdev->asic_specific; + u32 status, timeout_usec, inv_data, pi; + int rc; + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) + return; + + /* no need in L1 only invalidation in Goya */ + if (!is_hard) + return; + + if (hdev->pldm) + timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + mutex_lock(&hdev->mmu_cache_lock); + + /* + * TODO: currently invalidate entire L0 & L1 as in regular hard + * invalidation. Need to apply invalidation of specific cache lines with + * mask of ASID & VA & size. + * Note that L1 with be flushed entirely in any case. + */ + + /* L0 & L1 invalidation */ + inv_data = RREG32(mmSTLB_CACHE_INV); + /* PI is 8 bit */ + pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF; + WREG32(mmSTLB_CACHE_INV, + (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi); + + rc = hl_poll_timeout( + hdev, + mmSTLB_INV_CONSUMER_INDEX, + status, + status == pi, + 1000, + timeout_usec); + + mutex_unlock(&hdev->mmu_cache_lock); + + if (rc) + dev_notice_ratelimited(hdev->dev, + "Timeout when waiting for MMU cache invalidation\n"); +} + +static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid, + u64 phys_addr) +{ + u32 status, timeout_usec; + int rc; + + if (hdev->pldm) + timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT); + WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT); + WREG32(MMU_ASID_BUSY, 0x80000000 | asid); + + rc = hl_poll_timeout( + hdev, + MMU_ASID_BUSY, + status, + !(status & 0x80000000), + 1000, + timeout_usec); + + if (rc) { + dev_err(hdev->dev, + "Timeout during MMU hop0 config of asid %d\n", asid); + return rc; + } + + return 0; +} + +int goya_send_heartbeat(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + struct armcp_packet hb_pkt; + long result; + int rc; + + if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + memset(&hb_pkt, 0, sizeof(hb_pkt)); + + hb_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST << + ARMCP_PKT_CTL_OPCODE_SHIFT); + hb_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &hb_pkt, + sizeof(hb_pkt), HL_DEVICE_TIMEOUT_USEC, &result); + + if ((rc) || (result != ARMCP_PACKET_FENCE_VAL)) + rc = -EIO; + + return rc; +} + +static int goya_armcp_info_get(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct armcp_packet pkt; + void *armcp_info_cpu_addr; + dma_addr_t armcp_info_dma_addr; + u64 dram_size; + long result; + int rc; + + if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + armcp_info_cpu_addr = + hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, + sizeof(struct armcp_info), &armcp_info_dma_addr); + if (!armcp_info_cpu_addr) { + dev_err(hdev->dev, + "Failed to allocate DMA memory for ArmCP info packet\n"); + return -ENOMEM; + } + + memset(armcp_info_cpu_addr, 0, sizeof(struct armcp_info)); + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_INFO_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.addr = cpu_to_le64(armcp_info_dma_addr + + prop->host_phys_base_address); + pkt.data_max_size = cpu_to_le32(sizeof(struct armcp_info)); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + GOYA_ARMCP_INFO_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to send armcp info pkt, error %d\n", rc); + goto out; + } + + memcpy(&prop->armcp_info, armcp_info_cpu_addr, + sizeof(prop->armcp_info)); + + dram_size = le64_to_cpu(prop->armcp_info.dram_size); + if (dram_size) { + if ((!is_power_of_2(dram_size)) || + (dram_size < DRAM_PHYS_DEFAULT_SIZE)) { + dev_err(hdev->dev, + "F/W reported invalid DRAM size %llu. Trying to use default size\n", + dram_size); + dram_size = DRAM_PHYS_DEFAULT_SIZE; + } + + prop->dram_size = dram_size; + prop->dram_end_address = prop->dram_base_address + dram_size; + } + + rc = hl_build_hwmon_channel_info(hdev, prop->armcp_info.sensors); + if (rc) { + dev_err(hdev->dev, + "Failed to build hwmon channel info, error %d\n", rc); + rc = -EFAULT; + goto out; + } + +out: + hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, + sizeof(struct armcp_info), armcp_info_cpu_addr); + + return rc; +} + +static void goya_init_clock_gating(struct hl_device *hdev) +{ + +} + +static void goya_disable_clock_gating(struct hl_device *hdev) +{ + +} + +static bool goya_is_device_idle(struct hl_device *hdev) +{ + u64 offset, dma_qm_reg, tpc_qm_reg, tpc_cmdq_reg, tpc_cfg_reg; + int i; + + offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0; + + for (i = 0 ; i < DMA_MAX_NUM ; i++) { + dma_qm_reg = mmDMA_QM_0_GLBL_STS0 + i * offset; + + if ((RREG32(dma_qm_reg) & DMA_QM_IDLE_MASK) != + DMA_QM_IDLE_MASK) + return false; + } + + offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0; + + for (i = 0 ; i < TPC_MAX_NUM ; i++) { + tpc_qm_reg = mmTPC0_QM_GLBL_STS0 + i * offset; + tpc_cmdq_reg = mmTPC0_CMDQ_GLBL_STS0 + i * offset; + tpc_cfg_reg = mmTPC0_CFG_STATUS + i * offset; + + if ((RREG32(tpc_qm_reg) & TPC_QM_IDLE_MASK) != + TPC_QM_IDLE_MASK) + return false; + + if ((RREG32(tpc_cmdq_reg) & TPC_CMDQ_IDLE_MASK) != + TPC_CMDQ_IDLE_MASK) + return false; + + if ((RREG32(tpc_cfg_reg) & TPC_CFG_IDLE_MASK) != + TPC_CFG_IDLE_MASK) + return false; + } + + if ((RREG32(mmMME_QM_GLBL_STS0) & MME_QM_IDLE_MASK) != + MME_QM_IDLE_MASK) + return false; + + if ((RREG32(mmMME_CMDQ_GLBL_STS0) & MME_CMDQ_IDLE_MASK) != + MME_CMDQ_IDLE_MASK) + return false; + + if ((RREG32(mmMME_ARCH_STATUS) & MME_ARCH_IDLE_MASK) != + MME_ARCH_IDLE_MASK) + return false; + + if (RREG32(mmMME_SHADOW_0_STATUS) & MME_SHADOW_IDLE_MASK) + return false; + + return true; +} + +static void goya_hw_queues_lock(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + + spin_lock(&goya->hw_queues_lock); +} + +static void goya_hw_queues_unlock(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + + spin_unlock(&goya->hw_queues_lock); +} + +static u32 goya_get_pci_id(struct hl_device *hdev) +{ + return hdev->pdev->device; +} + +static int goya_get_eeprom_data(struct hl_device *hdev, void *data, + size_t max_size) +{ + struct goya_device *goya = hdev->asic_specific; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct armcp_packet pkt; + void *eeprom_info_cpu_addr; + dma_addr_t eeprom_info_dma_addr; + long result; + int rc; + + if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + eeprom_info_cpu_addr = + hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, + max_size, &eeprom_info_dma_addr); + if (!eeprom_info_cpu_addr) { + dev_err(hdev->dev, + "Failed to allocate DMA memory for EEPROM info packet\n"); + return -ENOMEM; + } + + memset(eeprom_info_cpu_addr, 0, max_size); + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_EEPROM_DATA_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.addr = cpu_to_le64(eeprom_info_dma_addr + + prop->host_phys_base_address); + pkt.data_max_size = cpu_to_le32(max_size); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + GOYA_ARMCP_EEPROM_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to send armcp EEPROM pkt, error %d\n", rc); + goto out; + } + + /* result contains the actual size */ + memcpy(data, eeprom_info_cpu_addr, min((size_t)result, max_size)); + +out: + hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, max_size, + eeprom_info_cpu_addr); + + return rc; +} + +static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev) +{ + return RREG32(mmPSOC_GLOBAL_CONF_APP_STATUS); +} + +static const struct hl_asic_funcs goya_funcs = { + .early_init = goya_early_init, + .early_fini = goya_early_fini, + .late_init = goya_late_init, + .late_fini = goya_late_fini, + .sw_init = goya_sw_init, + .sw_fini = goya_sw_fini, + .hw_init = goya_hw_init, + .hw_fini = goya_hw_fini, + .halt_engines = goya_halt_engines, + .suspend = goya_suspend, + .resume = goya_resume, + .cb_mmap = goya_cb_mmap, + .ring_doorbell = goya_ring_doorbell, + .flush_pq_write = goya_flush_pq_write, + .dma_alloc_coherent = goya_dma_alloc_coherent, + .dma_free_coherent = goya_dma_free_coherent, + .get_int_queue_base = goya_get_int_queue_base, + .test_queues = goya_test_queues, + .dma_pool_zalloc = goya_dma_pool_zalloc, + .dma_pool_free = goya_dma_pool_free, + .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc, + .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free, + .hl_dma_unmap_sg = goya_dma_unmap_sg, + .cs_parser = goya_cs_parser, + .asic_dma_map_sg = goya_dma_map_sg, + .get_dma_desc_list_size = goya_get_dma_desc_list_size, + .add_end_of_cb_packets = goya_add_end_of_cb_packets, + .update_eq_ci = goya_update_eq_ci, + .context_switch = goya_context_switch, + .restore_phase_topology = goya_restore_phase_topology, + .debugfs_read32 = goya_debugfs_read32, + .debugfs_write32 = goya_debugfs_write32, + .add_device_attr = goya_add_device_attr, + .handle_eqe = goya_handle_eqe, + .set_pll_profile = goya_set_pll_profile, + .get_events_stat = goya_get_events_stat, + .read_pte = goya_read_pte, + .write_pte = goya_write_pte, + .mmu_invalidate_cache = goya_mmu_invalidate_cache, + .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range, + .send_heartbeat = goya_send_heartbeat, + .enable_clock_gating = goya_init_clock_gating, + .disable_clock_gating = goya_disable_clock_gating, + .is_device_idle = goya_is_device_idle, + .soft_reset_late_init = goya_soft_reset_late_init, + .hw_queues_lock = goya_hw_queues_lock, + .hw_queues_unlock = goya_hw_queues_unlock, + .get_pci_id = goya_get_pci_id, + .get_eeprom_data = goya_get_eeprom_data, + .send_cpu_message = goya_send_cpu_message, + .get_hw_state = goya_get_hw_state +}; + +/* + * goya_set_asic_funcs - set Goya function pointers + * + * @*hdev: pointer to hl_device structure + * + */ +void goya_set_asic_funcs(struct hl_device *hdev) +{ + hdev->asic_funcs = &goya_funcs; +} diff --git a/drivers/misc/habanalabs/goya/goyaP.h b/drivers/misc/habanalabs/goya/goyaP.h new file mode 100644 index 000000000000..830551b6b062 --- /dev/null +++ b/drivers/misc/habanalabs/goya/goyaP.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYAP_H_ +#define GOYAP_H_ + +#include <uapi/misc/habanalabs.h> +#include "habanalabs.h" +#include "include/hl_boot_if.h" +#include "include/goya/goya_packets.h" +#include "include/goya/goya.h" +#include "include/goya/goya_async_events.h" +#include "include/goya/goya_fw_if.h" + +#define NUMBER_OF_CMPLT_QUEUES 5 +#define NUMBER_OF_EXT_HW_QUEUES 5 +#define NUMBER_OF_CPU_HW_QUEUES 1 +#define NUMBER_OF_INT_HW_QUEUES 9 +#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \ + NUMBER_OF_CPU_HW_QUEUES + \ + NUMBER_OF_INT_HW_QUEUES) + +/* + * Number of MSIX interrupts IDS: + * Each completion queue has 1 ID + * The event queue has 1 ID + */ +#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + 1) + +#if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES) +#error "Number of H/W queues must be smaller than HL_MAX_QUEUES" +#endif + +#if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES) +#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES" +#endif + +#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */ + +#define QMAN_STOP_TIMEOUT_USEC 100000 /* 100 ms */ + +#define TPC_ENABLED_MASK 0xFF + +#define PLL_HIGH_DEFAULT 1575000000 /* 1.575 GHz */ + +#define MAX_POWER_DEFAULT 200000 /* 200W */ + +#define GOYA_ARMCP_INFO_TIMEOUT 10000000 /* 10s */ +#define GOYA_ARMCP_EEPROM_TIMEOUT 10000000 /* 10s */ + +#define DRAM_PHYS_DEFAULT_SIZE 0x100000000ull /* 4GB */ + +/* DRAM Memory Map */ + +#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */ +#define MMU_PAGE_TABLES_SIZE 0x0DE00000 /* 222MB */ +#define MMU_DRAM_DEFAULT_PAGE_SIZE 0x00200000 /* 2MB */ +#define MMU_CACHE_MNG_SIZE 0x00001000 /* 4KB */ +#define CPU_PQ_PKT_SIZE 0x00001000 /* 4KB */ +#define CPU_PQ_DATA_SIZE 0x01FFE000 /* 32MB - 8KB */ + +#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE +#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE) +#define MMU_DRAM_DEFAULT_PAGE_ADDR (MMU_PAGE_TABLES_ADDR + \ + MMU_PAGE_TABLES_SIZE) +#define MMU_CACHE_MNG_ADDR (MMU_DRAM_DEFAULT_PAGE_ADDR + \ + MMU_DRAM_DEFAULT_PAGE_SIZE) +#define CPU_PQ_PKT_ADDR (MMU_CACHE_MNG_ADDR + \ + MMU_CACHE_MNG_SIZE) +#define CPU_PQ_DATA_ADDR (CPU_PQ_PKT_ADDR + CPU_PQ_PKT_SIZE) +#define DRAM_BASE_ADDR_USER (CPU_PQ_DATA_ADDR + CPU_PQ_DATA_SIZE) + +#if (DRAM_BASE_ADDR_USER != 0x20000000) +#error "KMD must reserve 512MB" +#endif + +/* + * SRAM Memory Map for KMD + * + * KMD occupies KMD_SRAM_SIZE bytes from the start of SRAM. It is used for + * MME/TPC QMANs + * + */ + +#define MME_QMAN_BASE_OFFSET 0x000000 /* Must be 0 */ +#define MME_QMAN_LENGTH 64 +#define TPC_QMAN_LENGTH 64 + +#define TPC0_QMAN_BASE_OFFSET (MME_QMAN_BASE_OFFSET + \ + (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) +#define TPC1_QMAN_BASE_OFFSET (TPC0_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) +#define TPC2_QMAN_BASE_OFFSET (TPC1_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) +#define TPC3_QMAN_BASE_OFFSET (TPC2_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) +#define TPC4_QMAN_BASE_OFFSET (TPC3_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) +#define TPC5_QMAN_BASE_OFFSET (TPC4_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) +#define TPC6_QMAN_BASE_OFFSET (TPC5_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) +#define TPC7_QMAN_BASE_OFFSET (TPC6_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) + +#define SRAM_KMD_RES_OFFSET (TPC7_QMAN_BASE_OFFSET + \ + (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)) + +#if (SRAM_KMD_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START) +#error "MME/TPC QMANs SRAM space exceeds limit" +#endif + +#define SRAM_USER_BASE_OFFSET GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START + +/* Virtual address space */ +#define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */ +#define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */ +#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \ + VA_HOST_SPACE_START) /* 767TB */ + +#define VA_DDR_SPACE_START 0x800000000ull /* 32GB */ +#define VA_DDR_SPACE_END 0x2000000000ull /* 128GB */ +#define VA_DDR_SPACE_SIZE (VA_DDR_SPACE_END - \ + VA_DDR_SPACE_START) /* 128GB */ + +#define DMA_MAX_TRANSFER_SIZE U32_MAX + +#define HW_CAP_PLL 0x00000001 +#define HW_CAP_DDR_0 0x00000002 +#define HW_CAP_DDR_1 0x00000004 +#define HW_CAP_MME 0x00000008 +#define HW_CAP_CPU 0x00000010 +#define HW_CAP_DMA 0x00000020 +#define HW_CAP_MSIX 0x00000040 +#define HW_CAP_CPU_Q 0x00000080 +#define HW_CAP_MMU 0x00000100 +#define HW_CAP_TPC_MBIST 0x00000200 +#define HW_CAP_GOLDEN 0x00000400 +#define HW_CAP_TPC 0x00000800 + +#define CPU_PKT_SHIFT 5 +#define CPU_PKT_SIZE (1 << CPU_PKT_SHIFT) +#define CPU_PKT_MASK (~((1 << CPU_PKT_SHIFT) - 1)) +#define CPU_MAX_PKTS_IN_CB 32 +#define CPU_CB_SIZE (CPU_PKT_SIZE * CPU_MAX_PKTS_IN_CB) +#define CPU_ACCESSIBLE_MEM_SIZE (HL_QUEUE_LENGTH * CPU_CB_SIZE) + +enum goya_fw_component { + FW_COMP_UBOOT, + FW_COMP_PREBOOT +}; + +struct goya_device { + int (*test_cpu_queue)(struct hl_device *hdev); + int (*armcp_info_get)(struct hl_device *hdev); + + /* TODO: remove hw_queues_lock after moving to scheduler code */ + spinlock_t hw_queues_lock; + + u64 mme_clk; + u64 tpc_clk; + u64 ic_clk; + + u64 ddr_bar_cur_addr; + u32 events_stat[GOYA_ASYNC_EVENT_ID_SIZE]; + u32 hw_cap_initialized; +}; + +int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus, + u8 i2c_addr, u8 i2c_reg, u32 *val); +int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus, + u8 i2c_addr, u8 i2c_reg, u32 val); +int goya_test_cpu_queue(struct hl_device *hdev); +int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len, + u32 timeout, long *result); +long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr); +long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr); +long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr); +long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr); +long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr); +void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, + long value); +void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state); +void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq); +void goya_add_device_attr(struct hl_device *hdev, + struct attribute_group *dev_attr_grp); +void goya_init_security(struct hl_device *hdev); +u64 goya_get_max_power(struct hl_device *hdev); +void goya_set_max_power(struct hl_device *hdev, u64 value); + +int goya_send_pci_access_msg(struct hl_device *hdev, u32 opcode); +void goya_late_fini(struct hl_device *hdev); +int goya_suspend(struct hl_device *hdev); +int goya_resume(struct hl_device *hdev); +void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val); +void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry); +void *goya_get_events_stat(struct hl_device *hdev, u32 *size); +void goya_add_end_of_cb_packets(u64 kernel_address, u32 len, u64 cq_addr, + u32 cq_val, u32 msix_vec); +int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser); +void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id, + dma_addr_t *dma_handle, u16 *queue_len); +u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt); +int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id); +int goya_send_heartbeat(struct hl_device *hdev); + +#endif /* GOYAP_H_ */ diff --git a/drivers/misc/habanalabs/goya/goya_hwmgr.c b/drivers/misc/habanalabs/goya/goya_hwmgr.c new file mode 100644 index 000000000000..088692c852b6 --- /dev/null +++ b/drivers/misc/habanalabs/goya/goya_hwmgr.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "goyaP.h" + +void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq) +{ + struct goya_device *goya = hdev->asic_specific; + + switch (freq) { + case PLL_HIGH: + hl_set_frequency(hdev, MME_PLL, hdev->high_pll); + hl_set_frequency(hdev, TPC_PLL, hdev->high_pll); + hl_set_frequency(hdev, IC_PLL, hdev->high_pll); + break; + case PLL_LOW: + hl_set_frequency(hdev, MME_PLL, GOYA_PLL_FREQ_LOW); + hl_set_frequency(hdev, TPC_PLL, GOYA_PLL_FREQ_LOW); + hl_set_frequency(hdev, IC_PLL, GOYA_PLL_FREQ_LOW); + break; + case PLL_LAST: + hl_set_frequency(hdev, MME_PLL, goya->mme_clk); + hl_set_frequency(hdev, TPC_PLL, goya->tpc_clk); + hl_set_frequency(hdev, IC_PLL, goya->ic_clk); + break; + default: + dev_err(hdev->dev, "unknown frequency setting\n"); + } +} + +static ssize_t mme_clk_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, false); + + if (value < 0) + return value; + + return sprintf(buf, "%lu\n", value); +} + +static ssize_t mme_clk_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + struct goya_device *goya = hdev->asic_specific; + int rc; + long value; + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto fail; + } + + if (hdev->pm_mng_profile == PM_AUTO) { + count = -EPERM; + goto fail; + } + + rc = kstrtoul(buf, 0, &value); + + if (rc) { + count = -EINVAL; + goto fail; + } + + hl_set_frequency(hdev, MME_PLL, value); + goya->mme_clk = value; + +fail: + return count; +} + +static ssize_t tpc_clk_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, TPC_PLL, false); + + if (value < 0) + return value; + + return sprintf(buf, "%lu\n", value); +} + +static ssize_t tpc_clk_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + struct goya_device *goya = hdev->asic_specific; + int rc; + long value; + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto fail; + } + + if (hdev->pm_mng_profile == PM_AUTO) { + count = -EPERM; + goto fail; + } + + rc = kstrtoul(buf, 0, &value); + + if (rc) { + count = -EINVAL; + goto fail; + } + + hl_set_frequency(hdev, TPC_PLL, value); + goya->tpc_clk = value; + +fail: + return count; +} + +static ssize_t ic_clk_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, IC_PLL, false); + + if (value < 0) + return value; + + return sprintf(buf, "%lu\n", value); +} + +static ssize_t ic_clk_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + struct goya_device *goya = hdev->asic_specific; + int rc; + long value; + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto fail; + } + + if (hdev->pm_mng_profile == PM_AUTO) { + count = -EPERM; + goto fail; + } + + rc = kstrtoul(buf, 0, &value); + + if (rc) { + count = -EINVAL; + goto fail; + } + + hl_set_frequency(hdev, IC_PLL, value); + goya->ic_clk = value; + +fail: + return count; +} + +static ssize_t mme_clk_curr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, true); + + if (value < 0) + return value; + + return sprintf(buf, "%lu\n", value); +} + +static ssize_t tpc_clk_curr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, TPC_PLL, true); + + if (value < 0) + return value; + + return sprintf(buf, "%lu\n", value); +} + +static ssize_t ic_clk_curr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, IC_PLL, true); + + if (value < 0) + return value; + + return sprintf(buf, "%lu\n", value); +} + +static DEVICE_ATTR_RW(ic_clk); +static DEVICE_ATTR_RO(ic_clk_curr); +static DEVICE_ATTR_RW(mme_clk); +static DEVICE_ATTR_RO(mme_clk_curr); +static DEVICE_ATTR_RW(tpc_clk); +static DEVICE_ATTR_RO(tpc_clk_curr); + +static struct attribute *goya_dev_attrs[] = { + &dev_attr_ic_clk.attr, + &dev_attr_ic_clk_curr.attr, + &dev_attr_mme_clk.attr, + &dev_attr_mme_clk_curr.attr, + &dev_attr_tpc_clk.attr, + &dev_attr_tpc_clk_curr.attr, + NULL, +}; + +void goya_add_device_attr(struct hl_device *hdev, + struct attribute_group *dev_attr_grp) +{ + dev_attr_grp->attrs = goya_dev_attrs; +} diff --git a/drivers/misc/habanalabs/goya/goya_security.c b/drivers/misc/habanalabs/goya/goya_security.c new file mode 100644 index 000000000000..575003238401 --- /dev/null +++ b/drivers/misc/habanalabs/goya/goya_security.c @@ -0,0 +1,2999 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "goyaP.h" + +/* + * goya_set_block_as_protected - set the given block as protected + * + * @hdev: pointer to hl_device structure + * @block: block base address + * + */ +static void goya_pb_set_block(struct hl_device *hdev, u64 base) +{ + u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; + + while (pb_addr & 0xFFF) { + WREG32(pb_addr, 0); + pb_addr += 4; + } +} + +static void goya_init_mme_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + /* TODO: change to real reg name when Soc Online is updated */ + u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, + mmMME_SBB_POWER_ECO2 = 0xDFF64; + + goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_0_BASE); + goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_1_BASE); + goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_2_BASE); + goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_3_BASE); + + goya_pb_set_block(hdev, mmSBA_ECC_MEM_BASE); + goya_pb_set_block(hdev, mmSBB_ECC_MEM_BASE); + + goya_pb_set_block(hdev, mmMME1_RTR_BASE); + goya_pb_set_block(hdev, mmMME1_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME1_WR_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME2_RTR_BASE); + goya_pb_set_block(hdev, mmMME2_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME2_WR_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME3_RTR_BASE); + goya_pb_set_block(hdev, mmMME3_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME3_WR_REGULATOR_BASE); + + goya_pb_set_block(hdev, mmMME4_RTR_BASE); + goya_pb_set_block(hdev, mmMME4_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME4_WR_REGULATOR_BASE); + + goya_pb_set_block(hdev, mmMME5_RTR_BASE); + goya_pb_set_block(hdev, mmMME5_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME5_WR_REGULATOR_BASE); + + goya_pb_set_block(hdev, mmMME6_RTR_BASE); + goya_pb_set_block(hdev, mmMME6_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmMME6_WR_REGULATOR_BASE); + + pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); + mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmMME_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmMME_LOG_SHADOW & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_STORE_MAX_CREDIT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_STORE_MAX_CREDIT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_STORE_MAX_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME_AGU & 0x7F) >> 2); + mask |= 1 << ((mmMME_SBA & 0x7F) >> 2); + mask |= 1 << ((mmMME_SBB & 0x7F) >> 2); + mask |= 1 << ((mmMME_SBC & 0x7F) >> 2); + mask |= 1 << ((mmMME_WBC & 0x7F) >> 2); + mask |= 1 << ((mmMME_SBA_CONTROL_DATA & 0x7F) >> 2); + mask |= 1 << ((mmMME_SBB_CONTROL_DATA & 0x7F) >> 2); + mask |= 1 << ((mmMME_SBC_CONTROL_DATA & 0x7F) >> 2); + mask |= 1 << ((mmMME_WBC_CONTROL_DATA & 0x7F) >> 2); + mask |= 1 << ((mmMME_TE & 0x7F) >> 2); + mask |= 1 << ((mmMME_TE2DEC & 0x7F) >> 2); + mask |= 1 << ((mmMME_REI_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmMME_REI_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME_SEI_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmMME_SEI_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME_SPI_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmMME_SPI_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_QM_CP_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_QM_CP_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_QM_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_PQ_BUF_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmMME_QM_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_CMDQ_CQ_IFIFO_CNT & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmMME_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME_SBB_POWER_ECO1 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME_SBB_POWER_ECO1 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME_SBB_POWER_ECO1 & 0x7F) >> 2); + mask |= 1 << ((mmMME_SBB_POWER_ECO2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); +} + +static void goya_init_dma_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + goya_pb_set_block(hdev, mmDMA_NRTR_BASE); + goya_pb_set_block(hdev, mmDMA_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmDMA_WR_REGULATOR_BASE); + + pb_addr = (mmDMA_QM_0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_0_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_0_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_0_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_0_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_0_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_0_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_0_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmDMA_CH_0_BASE); + + pb_addr = (mmDMA_QM_1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_1_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_1_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_1_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_1_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_1_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_1_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_1_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmDMA_CH_1_BASE); + + pb_addr = (mmDMA_QM_2_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_2_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_2_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_2_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_2_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_2_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_2_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_2_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_2_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmDMA_CH_2_BASE); + + pb_addr = (mmDMA_QM_3_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_3_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_3_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_3_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_3_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_3_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_3_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_3_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_3_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmDMA_CH_3_BASE); + + pb_addr = (mmDMA_QM_4_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_4_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_4_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_4_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_4_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_4_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA_QM_4_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA_QM_4_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA_QM_4_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmDMA_CH_4_BASE); +} + +static void goya_init_tpc_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + goya_pb_set_block(hdev, mmTPC0_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC0_WR_REGULATOR_BASE); + + pb_addr = (mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_FUNC_MBIST_CNTRL & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmTPC1_RTR_BASE); + goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE); + + pb_addr = (mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_FUNC_MBIST_CNTRL & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmTPC2_RTR_BASE); + goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE); + + pb_addr = (mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_FUNC_MBIST_CNTRL & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmTPC3_RTR_BASE); + goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE); + + pb_addr = (mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH + & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_FUNC_MBIST_CNTRL + & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmTPC4_RTR_BASE); + goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE); + + pb_addr = (mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_FUNC_MBIST_CNTRL & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmTPC5_RTR_BASE); + goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE); + + pb_addr = (mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_FUNC_MBIST_CNTRL & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmTPC6_RTR_BASE); + goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE); + + pb_addr = (mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_FUNC_MBIST_CNTRL & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + goya_pb_set_block(hdev, mmTPC7_NRTR_BASE); + goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE); + + pb_addr = (mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CFG_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_AWUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_FUNC_MBIST_CNTRL & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_PQ_PUSH0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PUSH1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PUSH2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PUSH3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CMDQ_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CMDQ_CQ_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_ARUSER & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_CTL_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_STS1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CP_DBG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); +} + +/* + * goya_init_protection_bits - Initialize protection bits for specific registers + * + * @hdev: pointer to hl_device structure + * + * All protection bits are 1 by default, means not protected. Need to set to 0 + * each bit that belongs to a protected register. + * + */ +static void goya_init_protection_bits(struct hl_device *hdev) +{ + /* + * In each 4K block of registers, the last 128 bytes are protection + * bits - total of 1024 bits, one for each register. Each bit is related + * to a specific register, by the order of the registers. + * So in order to calculate the bit that is related to a given register, + * we need to calculate its word offset and then the exact bit inside + * the word (which is 4 bytes). + * + * Register address: + * + * 31 12 11 7 6 2 1 0 + * ----------------------------------------------------------------- + * | Don't | word | bit location | 0 | + * | care | offset | inside word | | + * ----------------------------------------------------------------- + * + * Bits 7-11 represents the word offset inside the 128 bytes. + * Bits 2-6 represents the bit location inside the word. + */ + + goya_pb_set_block(hdev, mmPCI_NRTR_BASE); + goya_pb_set_block(hdev, mmPCI_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmPCI_WR_REGULATOR_BASE); + + goya_pb_set_block(hdev, mmSRAM_Y0_X0_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X0_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X1_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X1_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X2_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X2_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X3_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X3_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X4_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y0_X4_RTR_BASE); + + goya_pb_set_block(hdev, mmSRAM_Y1_X0_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X0_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X1_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X1_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X2_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X2_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X3_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X3_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X4_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y1_X4_RTR_BASE); + + goya_pb_set_block(hdev, mmSRAM_Y2_X0_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X0_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X1_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X1_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X2_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X2_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X3_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X3_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X4_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y2_X4_RTR_BASE); + + goya_pb_set_block(hdev, mmSRAM_Y3_X0_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X0_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X1_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X1_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X2_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X2_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X3_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X3_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X4_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y3_X4_RTR_BASE); + + goya_pb_set_block(hdev, mmSRAM_Y4_X0_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X0_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X1_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X1_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X2_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X2_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X3_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X3_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X4_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y4_X4_RTR_BASE); + + goya_pb_set_block(hdev, mmSRAM_Y5_X0_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X0_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X1_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X1_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X2_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X2_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X3_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X3_RTR_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X4_BANK_BASE); + goya_pb_set_block(hdev, mmSRAM_Y5_X4_RTR_BASE); + + goya_pb_set_block(hdev, mmPCIE_WRAP_BASE); + goya_pb_set_block(hdev, mmPCIE_CORE_BASE); + goya_pb_set_block(hdev, mmPCIE_DB_CFG_BASE); + goya_pb_set_block(hdev, mmPCIE_DB_CMD_BASE); + goya_pb_set_block(hdev, mmPCIE_AUX_BASE); + goya_pb_set_block(hdev, mmPCIE_DB_RSV_BASE); + goya_pb_set_block(hdev, mmPCIE_PHY_BASE); + + goya_init_mme_protection_bits(hdev); + + goya_init_dma_protection_bits(hdev); + + goya_init_tpc_protection_bits(hdev); +} + +/* + * goya_init_security - Initialize security model + * + * @hdev: pointer to hl_device structure + * + * Initialize the security model of the device + * That includes range registers and protection bit per register + * + */ +void goya_init_security(struct hl_device *hdev) +{ + struct goya_device *goya = hdev->asic_specific; + + u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE); + u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); + + u32 lbw_rng0_base = 0xFC440000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng0_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng1_base = 0xFC480000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng1_mask = 0xFFF80000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng2_base = 0xFC600000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng2_mask = 0xFFE00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng3_base = 0xFC800000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng3_mask = 0xFFF00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng4_base = 0xFCC02000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng4_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng5_base = 0xFCC40000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng5_mask = 0xFFFF8000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng6_base = 0xFCC48000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng6_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng7_base = 0xFCC4A000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng7_mask = 0xFFFFE000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng8_base = 0xFCC4C000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng8_mask = 0xFFFFC000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng9_base = 0xFCC50000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng9_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng10_base = 0xFCC60000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng10_mask = 0xFFFE0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng11_base = 0xFCE00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng11_mask = 0xFFFFC000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng12_base = 0xFE484000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng12_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + u32 lbw_rng13_base = 0xFEC43000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + u32 lbw_rng13_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; + + WREG32(mmDMA_MACRO_LBW_RANGE_HIT_BLOCK, 0xFFFF); + WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFF); + + if (!(goya->hw_cap_initialized & HW_CAP_MMU)) { + WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFE); + + /* Protect HOST */ + WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_0, 0); + WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_0, 0); + WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_0, 0); + WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_0, 0xFFF80); + } + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_1, dram_addr_lo); + WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_1, dram_addr_hi); + WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_1, 0xE0000000); + WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_1, 0x3FFFF); + + /* Protect registers */ + + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmDMA_MACRO_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmDMA_MACRO_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmMME1_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmMME2_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmMME3_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmMME4_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmMME5_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmMME6_RTR_LBW_RANGE_HIT, 0xFFFF); + + WREG32(mmMME1_RTR_HBW_RANGE_HIT, 0xFE); + WREG32(mmMME2_RTR_HBW_RANGE_HIT, 0xFE); + WREG32(mmMME3_RTR_HBW_RANGE_HIT, 0xFE); + WREG32(mmMME4_RTR_HBW_RANGE_HIT, 0xFE); + WREG32(mmMME5_RTR_HBW_RANGE_HIT, 0xFE); + WREG32(mmMME6_RTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmMME1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmMME1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmMME1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmMME2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmMME2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmMME2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmMME3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmMME3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmMME3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmMME4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmMME4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmMME4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmMME5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmMME5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmMME5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmMME6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmMME6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmMME6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC0_NRTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC0_NRTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC1_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC1_RTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC2_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC2_RTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC3_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC3_RTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC4_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC4_RTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC5_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC5_RTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC6_RTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC6_RTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + WREG32(mmTPC7_NRTR_LBW_RANGE_HIT, 0xFFFF); + WREG32(mmTPC7_NRTR_HBW_RANGE_HIT, 0xFE); + + /* Protect HOST */ + WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_0, 0); + WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_0, 0); + WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_0, 0); + WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80); + + /* + * Protect DDR @ + * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END + * The mask protects the first 512MB + */ + WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo); + WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi); + WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000); + WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF); + + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask); + WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base); + WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask); + + goya_init_protection_bits(hdev); +} diff --git a/drivers/misc/habanalabs/habanalabs.h b/drivers/misc/habanalabs/habanalabs.h new file mode 100644 index 000000000000..a7c95e9f9b9a --- /dev/null +++ b/drivers/misc/habanalabs/habanalabs.h @@ -0,0 +1,1464 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef HABANALABSP_H_ +#define HABANALABSP_H_ + +#include "include/armcp_if.h" +#include "include/qman_if.h" + +#define pr_fmt(fmt) "habanalabs: " fmt + +#include <linux/cdev.h> +#include <linux/iopoll.h> +#include <linux/irqreturn.h> +#include <linux/dma-fence.h> +#include <linux/dma-direction.h> +#include <linux/scatterlist.h> +#include <linux/hashtable.h> + +#define HL_NAME "habanalabs" + +#define HL_MMAP_CB_MASK (0x8000000000000000ull >> PAGE_SHIFT) + +#define HL_PENDING_RESET_PER_SEC 5 + +#define HL_DEVICE_TIMEOUT_USEC 1000000 /* 1 s */ + +#define HL_HEARTBEAT_PER_USEC 5000000 /* 5 s */ + +#define HL_PLL_LOW_JOB_FREQ_USEC 5000000 /* 5 s */ + +#define HL_MAX_QUEUES 128 + +#define HL_MAX_JOBS_PER_CS 64 + +/* MUST BE POWER OF 2 and larger than 1 */ +#define HL_MAX_PENDING_CS 64 + +/* Memory */ +#define MEM_HASH_TABLE_BITS 7 /* 1 << 7 buckets */ + +/* MMU */ +#define MMU_HASH_TABLE_BITS 7 /* 1 << 7 buckets */ + +/** + * struct pgt_info - MMU hop page info. + * @node: hash linked-list node for the pgts hash of pgts. + * @addr: physical address of the pgt. + * @ctx: pointer to the owner ctx. + * @num_of_ptes: indicates how many ptes are used in the pgt. + * + * The MMU page tables hierarchy is placed on the DRAM. When a new level (hop) + * is needed during mapping, a new page is allocated and this structure holds + * its essential information. During unmapping, if no valid PTEs remained in the + * page, it is freed with its pgt_info structure. + */ +struct pgt_info { + struct hlist_node node; + u64 addr; + struct hl_ctx *ctx; + int num_of_ptes; +}; + +struct hl_device; +struct hl_fpriv; + +/** + * enum hl_queue_type - Supported QUEUE types. + * @QUEUE_TYPE_NA: queue is not available. + * @QUEUE_TYPE_EXT: external queue which is a DMA channel that may access the + * host. + * @QUEUE_TYPE_INT: internal queue that performs DMA inside the device's + * memories and/or operates the compute engines. + * @QUEUE_TYPE_CPU: S/W queue for communication with the device's CPU. + */ +enum hl_queue_type { + QUEUE_TYPE_NA, + QUEUE_TYPE_EXT, + QUEUE_TYPE_INT, + QUEUE_TYPE_CPU +}; + +/** + * struct hw_queue_properties - queue information. + * @type: queue type. + * @kmd_only: true if only KMD is allowed to send a job to this queue, false + * otherwise. + */ +struct hw_queue_properties { + enum hl_queue_type type; + u8 kmd_only; +}; + +/** + * enum vm_type_t - virtual memory mapping request information. + * @VM_TYPE_USERPTR: mapping of user memory to device virtual address. + * @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address. + */ +enum vm_type_t { + VM_TYPE_USERPTR, + VM_TYPE_PHYS_PACK +}; + +/** + * enum hl_device_hw_state - H/W device state. use this to understand whether + * to do reset before hw_init or not + * @HL_DEVICE_HW_STATE_CLEAN: H/W state is clean. i.e. after hard reset + * @HL_DEVICE_HW_STATE_DIRTY: H/W state is dirty. i.e. we started to execute + * hw_init + */ +enum hl_device_hw_state { + HL_DEVICE_HW_STATE_CLEAN = 0, + HL_DEVICE_HW_STATE_DIRTY +}; + +/** + * struct asic_fixed_properties - ASIC specific immutable properties. + * @hw_queues_props: H/W queues properties. + * @armcp_info: received various information from ArmCP regarding the H/W. e.g. + * available sensors. + * @uboot_ver: F/W U-boot version. + * @preboot_ver: F/W Preboot version. + * @sram_base_address: SRAM physical start address. + * @sram_end_address: SRAM physical end address. + * @sram_user_base_address - SRAM physical start address for user access. + * @dram_base_address: DRAM physical start address. + * @dram_end_address: DRAM physical end address. + * @dram_user_base_address: DRAM physical start address for user access. + * @dram_size: DRAM total size. + * @dram_pci_bar_size: size of PCI bar towards DRAM. + * @host_phys_base_address: base physical address of host memory for + * transactions that the device generates. + * @max_power_default: max power of the device after reset + * @va_space_host_start_address: base address of virtual memory range for + * mapping host memory. + * @va_space_host_end_address: end address of virtual memory range for + * mapping host memory. + * @va_space_dram_start_address: base address of virtual memory range for + * mapping DRAM memory. + * @va_space_dram_end_address: end address of virtual memory range for + * mapping DRAM memory. + * @dram_size_for_default_page_mapping: DRAM size needed to map to avoid page + * fault. + * @mmu_pgt_addr: base physical address in DRAM of MMU page tables. + * @mmu_dram_default_page_addr: DRAM default page physical address. + * @mmu_pgt_size: MMU page tables total size. + * @mmu_pte_size: PTE size in MMU page tables. + * @mmu_hop_table_size: MMU hop table size. + * @mmu_hop0_tables_total_size: total size of MMU hop0 tables. + * @dram_page_size: page size for MMU DRAM allocation. + * @cfg_size: configuration space size on SRAM. + * @sram_size: total size of SRAM. + * @max_asid: maximum number of open contexts (ASIDs). + * @num_of_events: number of possible internal H/W IRQs. + * @psoc_pci_pll_nr: PCI PLL NR value. + * @psoc_pci_pll_nf: PCI PLL NF value. + * @psoc_pci_pll_od: PCI PLL OD value. + * @psoc_pci_pll_div_factor: PCI PLL DIV FACTOR 1 value. + * @completion_queues_count: number of completion queues. + * @high_pll: high PLL frequency used by the device. + * @cb_pool_cb_cnt: number of CBs in the CB pool. + * @cb_pool_cb_size: size of each CB in the CB pool. + * @tpc_enabled_mask: which TPCs are enabled. + */ +struct asic_fixed_properties { + struct hw_queue_properties hw_queues_props[HL_MAX_QUEUES]; + struct armcp_info armcp_info; + char uboot_ver[VERSION_MAX_LEN]; + char preboot_ver[VERSION_MAX_LEN]; + u64 sram_base_address; + u64 sram_end_address; + u64 sram_user_base_address; + u64 dram_base_address; + u64 dram_end_address; + u64 dram_user_base_address; + u64 dram_size; + u64 dram_pci_bar_size; + u64 host_phys_base_address; + u64 max_power_default; + u64 va_space_host_start_address; + u64 va_space_host_end_address; + u64 va_space_dram_start_address; + u64 va_space_dram_end_address; + u64 dram_size_for_default_page_mapping; + u64 mmu_pgt_addr; + u64 mmu_dram_default_page_addr; + u32 mmu_pgt_size; + u32 mmu_pte_size; + u32 mmu_hop_table_size; + u32 mmu_hop0_tables_total_size; + u32 dram_page_size; + u32 cfg_size; + u32 sram_size; + u32 max_asid; + u32 num_of_events; + u32 psoc_pci_pll_nr; + u32 psoc_pci_pll_nf; + u32 psoc_pci_pll_od; + u32 psoc_pci_pll_div_factor; + u32 high_pll; + u32 cb_pool_cb_cnt; + u32 cb_pool_cb_size; + u8 completion_queues_count; + u8 tpc_enabled_mask; +}; + +/** + * struct hl_dma_fence - wrapper for fence object used by command submissions. + * @base_fence: kernel fence object. + * @lock: spinlock to protect fence. + * @hdev: habanalabs device structure. + * @cs_seq: command submission sequence number. + */ +struct hl_dma_fence { + struct dma_fence base_fence; + spinlock_t lock; + struct hl_device *hdev; + u64 cs_seq; +}; + +/* + * Command Buffers + */ + +#define HL_MAX_CB_SIZE 0x200000 /* 2MB */ + +/** + * struct hl_cb_mgr - describes a Command Buffer Manager. + * @cb_lock: protects cb_handles. + * @cb_handles: an idr to hold all command buffer handles. + */ +struct hl_cb_mgr { + spinlock_t cb_lock; + struct idr cb_handles; /* protected by cb_lock */ +}; + +/** + * struct hl_cb - describes a Command Buffer. + * @refcount: reference counter for usage of the CB. + * @hdev: pointer to device this CB belongs to. + * @lock: spinlock to protect mmap/cs flows. + * @debugfs_list: node in debugfs list of command buffers. + * @pool_list: node in pool list of command buffers. + * @kernel_address: Holds the CB's kernel virtual address. + * @bus_address: Holds the CB's DMA address. + * @mmap_size: Holds the CB's size that was mmaped. + * @size: holds the CB's size. + * @id: the CB's ID. + * @cs_cnt: holds number of CS that this CB participates in. + * @ctx_id: holds the ID of the owner's context. + * @mmap: true if the CB is currently mmaped to user. + * @is_pool: true if CB was acquired from the pool, false otherwise. + */ +struct hl_cb { + struct kref refcount; + struct hl_device *hdev; + spinlock_t lock; + struct list_head debugfs_list; + struct list_head pool_list; + u64 kernel_address; + dma_addr_t bus_address; + u32 mmap_size; + u32 size; + u32 id; + u32 cs_cnt; + u32 ctx_id; + u8 mmap; + u8 is_pool; +}; + + +/* + * QUEUES + */ + +struct hl_cs_job; + +/* + * Currently, there are two limitations on the maximum length of a queue: + * + * 1. The memory footprint of the queue. The current allocated space for the + * queue is PAGE_SIZE. Because each entry in the queue is HL_BD_SIZE, + * the maximum length of the queue can be PAGE_SIZE / HL_BD_SIZE, + * which currently is 4096/16 = 256 entries. + * + * To increase that, we need either to decrease the size of the + * BD (difficult), or allocate more than a single page (easier). + * + * 2. Because the size of the JOB handle field in the BD CTL / completion queue + * is 10-bit, we can have up to 1024 open jobs per hardware queue. + * Therefore, each queue can hold up to 1024 entries. + * + * HL_QUEUE_LENGTH is in units of struct hl_bd. + * HL_QUEUE_LENGTH * sizeof(struct hl_bd) should be <= HL_PAGE_SIZE + */ + +#define HL_PAGE_SIZE 4096 /* minimum page size */ +/* Must be power of 2 (HL_PAGE_SIZE / HL_BD_SIZE) */ +#define HL_QUEUE_LENGTH 256 +#define HL_QUEUE_SIZE_IN_BYTES (HL_QUEUE_LENGTH * HL_BD_SIZE) + +/* + * HL_CQ_LENGTH is in units of struct hl_cq_entry. + * HL_CQ_LENGTH should be <= HL_PAGE_SIZE + */ +#define HL_CQ_LENGTH HL_QUEUE_LENGTH +#define HL_CQ_SIZE_IN_BYTES (HL_CQ_LENGTH * HL_CQ_ENTRY_SIZE) + +/* Must be power of 2 (HL_PAGE_SIZE / HL_EQ_ENTRY_SIZE) */ +#define HL_EQ_LENGTH 64 +#define HL_EQ_SIZE_IN_BYTES (HL_EQ_LENGTH * HL_EQ_ENTRY_SIZE) + + +/** + * struct hl_hw_queue - describes a H/W transport queue. + * @shadow_queue: pointer to a shadow queue that holds pointers to jobs. + * @queue_type: type of queue. + * @kernel_address: holds the queue's kernel virtual address. + * @bus_address: holds the queue's DMA address. + * @pi: holds the queue's pi value. + * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci). + * @hw_queue_id: the id of the H/W queue. + * @int_queue_len: length of internal queue (number of entries). + * @valid: is the queue valid (we have array of 32 queues, not all of them + * exists). + */ +struct hl_hw_queue { + struct hl_cs_job **shadow_queue; + enum hl_queue_type queue_type; + u64 kernel_address; + dma_addr_t bus_address; + u32 pi; + u32 ci; + u32 hw_queue_id; + u16 int_queue_len; + u8 valid; +}; + +/** + * struct hl_cq - describes a completion queue + * @hdev: pointer to the device structure + * @kernel_address: holds the queue's kernel virtual address + * @bus_address: holds the queue's DMA address + * @hw_queue_id: the id of the matching H/W queue + * @ci: ci inside the queue + * @pi: pi inside the queue + * @free_slots_cnt: counter of free slots in queue + */ +struct hl_cq { + struct hl_device *hdev; + u64 kernel_address; + dma_addr_t bus_address; + u32 hw_queue_id; + u32 ci; + u32 pi; + atomic_t free_slots_cnt; +}; + +/** + * struct hl_eq - describes the event queue (single one per device) + * @hdev: pointer to the device structure + * @kernel_address: holds the queue's kernel virtual address + * @bus_address: holds the queue's DMA address + * @ci: ci inside the queue + */ +struct hl_eq { + struct hl_device *hdev; + u64 kernel_address; + dma_addr_t bus_address; + u32 ci; +}; + + +/* + * ASICs + */ + +/** + * enum hl_asic_type - supported ASIC types. + * @ASIC_AUTO_DETECT: ASIC type will be automatically set. + * @ASIC_GOYA: Goya device. + * @ASIC_INVALID: Invalid ASIC type. + */ +enum hl_asic_type { + ASIC_AUTO_DETECT, + ASIC_GOYA, + ASIC_INVALID +}; + +struct hl_cs_parser; + +/** + * enum hl_pm_mng_profile - power management profile. + * @PM_AUTO: internal clock is set by KMD. + * @PM_MANUAL: internal clock is set by the user. + * @PM_LAST: last power management type. + */ +enum hl_pm_mng_profile { + PM_AUTO = 1, + PM_MANUAL, + PM_LAST +}; + +/** + * enum hl_pll_frequency - PLL frequency. + * @PLL_HIGH: high frequency. + * @PLL_LOW: low frequency. + * @PLL_LAST: last frequency values that were configured by the user. + */ +enum hl_pll_frequency { + PLL_HIGH = 1, + PLL_LOW, + PLL_LAST +}; + +/** + * struct hl_asic_funcs - ASIC specific functions that are can be called from + * common code. + * @early_init: sets up early driver state (pre sw_init), doesn't configure H/W. + * @early_fini: tears down what was done in early_init. + * @late_init: sets up late driver/hw state (post hw_init) - Optional. + * @late_fini: tears down what was done in late_init (pre hw_fini) - Optional. + * @sw_init: sets up driver state, does not configure H/W. + * @sw_fini: tears down driver state, does not configure H/W. + * @hw_init: sets up the H/W state. + * @hw_fini: tears down the H/W state. + * @halt_engines: halt engines, needed for reset sequence. This also disables + * interrupts from the device. Should be called before + * hw_fini and before CS rollback. + * @suspend: handles IP specific H/W or SW changes for suspend. + * @resume: handles IP specific H/W or SW changes for resume. + * @cb_mmap: maps a CB. + * @ring_doorbell: increment PI on a given QMAN. + * @flush_pq_write: flush PQ entry write if necessary, WARN if flushing failed. + * @dma_alloc_coherent: Allocate coherent DMA memory by calling + * dma_alloc_coherent(). This is ASIC function because its + * implementation is not trivial when the driver is loaded + * in simulation mode (not upstreamed). + * @dma_free_coherent: Free coherent DMA memory by calling dma_free_coherent(). + * This is ASIC function because its implementation is not + * trivial when the driver is loaded in simulation mode + * (not upstreamed). + * @get_int_queue_base: get the internal queue base address. + * @test_queues: run simple test on all queues for sanity check. + * @dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool. + * size of allocation is HL_DMA_POOL_BLK_SIZE. + * @dma_pool_free: free small DMA allocation from pool. + * @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool. + * @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool. + * @hl_dma_unmap_sg: DMA unmap scatter-gather list. + * @cs_parser: parse Command Submission. + * @asic_dma_map_sg: DMA map scatter-gather list. + * @get_dma_desc_list_size: get number of LIN_DMA packets required for CB. + * @add_end_of_cb_packets: Add packets to the end of CB, if device requires it. + * @update_eq_ci: update event queue CI. + * @context_switch: called upon ASID context switch. + * @restore_phase_topology: clear all SOBs amd MONs. + * @debugfs_read32: debug interface for reading u32 from DRAM/SRAM. + * @debugfs_write32: debug interface for writing u32 to DRAM/SRAM. + * @add_device_attr: add ASIC specific device attributes. + * @handle_eqe: handle event queue entry (IRQ) from ArmCP. + * @set_pll_profile: change PLL profile (manual/automatic). + * @get_events_stat: retrieve event queue entries histogram. + * @read_pte: read MMU page table entry from DRAM. + * @write_pte: write MMU page table entry to DRAM. + * @mmu_invalidate_cache: flush MMU STLB cache, either with soft (L1 only) or + * hard (L0 & L1) flush. + * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with + * ASID-VA-size mask. + * @send_heartbeat: send is-alive packet to ArmCP and verify response. + * @enable_clock_gating: enable clock gating for reducing power consumption. + * @disable_clock_gating: disable clock for accessing registers on HBW. + * @is_device_idle: return true if device is idle, false otherwise. + * @soft_reset_late_init: perform certain actions needed after soft reset. + * @hw_queues_lock: acquire H/W queues lock. + * @hw_queues_unlock: release H/W queues lock. + * @get_pci_id: retrieve PCI ID. + * @get_eeprom_data: retrieve EEPROM data from F/W. + * @send_cpu_message: send buffer to ArmCP. + * @get_hw_state: retrieve the H/W state + */ +struct hl_asic_funcs { + int (*early_init)(struct hl_device *hdev); + int (*early_fini)(struct hl_device *hdev); + int (*late_init)(struct hl_device *hdev); + void (*late_fini)(struct hl_device *hdev); + int (*sw_init)(struct hl_device *hdev); + int (*sw_fini)(struct hl_device *hdev); + int (*hw_init)(struct hl_device *hdev); + void (*hw_fini)(struct hl_device *hdev, bool hard_reset); + void (*halt_engines)(struct hl_device *hdev, bool hard_reset); + int (*suspend)(struct hl_device *hdev); + int (*resume)(struct hl_device *hdev); + int (*cb_mmap)(struct hl_device *hdev, struct vm_area_struct *vma, + u64 kaddress, phys_addr_t paddress, u32 size); + void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi); + void (*flush_pq_write)(struct hl_device *hdev, u64 *pq, u64 exp_val); + void* (*dma_alloc_coherent)(struct hl_device *hdev, size_t size, + dma_addr_t *dma_handle, gfp_t flag); + void (*dma_free_coherent)(struct hl_device *hdev, size_t size, + void *cpu_addr, dma_addr_t dma_handle); + void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id, + dma_addr_t *dma_handle, u16 *queue_len); + int (*test_queues)(struct hl_device *hdev); + void* (*dma_pool_zalloc)(struct hl_device *hdev, size_t size, + gfp_t mem_flags, dma_addr_t *dma_handle); + void (*dma_pool_free)(struct hl_device *hdev, void *vaddr, + dma_addr_t dma_addr); + void* (*cpu_accessible_dma_pool_alloc)(struct hl_device *hdev, + size_t size, dma_addr_t *dma_handle); + void (*cpu_accessible_dma_pool_free)(struct hl_device *hdev, + size_t size, void *vaddr); + void (*hl_dma_unmap_sg)(struct hl_device *hdev, + struct scatterlist *sg, int nents, + enum dma_data_direction dir); + int (*cs_parser)(struct hl_device *hdev, struct hl_cs_parser *parser); + int (*asic_dma_map_sg)(struct hl_device *hdev, + struct scatterlist *sg, int nents, + enum dma_data_direction dir); + u32 (*get_dma_desc_list_size)(struct hl_device *hdev, + struct sg_table *sgt); + void (*add_end_of_cb_packets)(u64 kernel_address, u32 len, u64 cq_addr, + u32 cq_val, u32 msix_num); + void (*update_eq_ci)(struct hl_device *hdev, u32 val); + int (*context_switch)(struct hl_device *hdev, u32 asid); + void (*restore_phase_topology)(struct hl_device *hdev); + int (*debugfs_read32)(struct hl_device *hdev, u64 addr, u32 *val); + int (*debugfs_write32)(struct hl_device *hdev, u64 addr, u32 val); + void (*add_device_attr)(struct hl_device *hdev, + struct attribute_group *dev_attr_grp); + void (*handle_eqe)(struct hl_device *hdev, + struct hl_eq_entry *eq_entry); + void (*set_pll_profile)(struct hl_device *hdev, + enum hl_pll_frequency freq); + void* (*get_events_stat)(struct hl_device *hdev, u32 *size); + u64 (*read_pte)(struct hl_device *hdev, u64 addr); + void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val); + void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard); + void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard, + u32 asid, u64 va, u64 size); + int (*send_heartbeat)(struct hl_device *hdev); + void (*enable_clock_gating)(struct hl_device *hdev); + void (*disable_clock_gating)(struct hl_device *hdev); + bool (*is_device_idle)(struct hl_device *hdev); + int (*soft_reset_late_init)(struct hl_device *hdev); + void (*hw_queues_lock)(struct hl_device *hdev); + void (*hw_queues_unlock)(struct hl_device *hdev); + u32 (*get_pci_id)(struct hl_device *hdev); + int (*get_eeprom_data)(struct hl_device *hdev, void *data, + size_t max_size); + int (*send_cpu_message)(struct hl_device *hdev, u32 *msg, + u16 len, u32 timeout, long *result); + enum hl_device_hw_state (*get_hw_state)(struct hl_device *hdev); +}; + + +/* + * CONTEXTS + */ + +#define HL_KERNEL_ASID_ID 0 + +/** + * struct hl_va_range - virtual addresses range. + * @lock: protects the virtual addresses list. + * @list: list of virtual addresses blocks available for mappings. + * @start_addr: range start address. + * @end_addr: range end address. + */ +struct hl_va_range { + struct mutex lock; + struct list_head list; + u64 start_addr; + u64 end_addr; +}; + +/** + * struct hl_ctx - user/kernel context. + * @mem_hash: holds mapping from virtual address to virtual memory area + * descriptor (hl_vm_phys_pg_list or hl_userptr). + * @mmu_hash: holds a mapping from virtual address to pgt_info structure. + * @hpriv: pointer to the private (KMD) data of the process (fd). + * @hdev: pointer to the device structure. + * @refcount: reference counter for the context. Context is released only when + * this hits 0l. It is incremented on CS and CS_WAIT. + * @cs_pending: array of DMA fence objects representing pending CS. + * @host_va_range: holds available virtual addresses for host mappings. + * @dram_va_range: holds available virtual addresses for DRAM mappings. + * @mem_hash_lock: protects the mem_hash. + * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifing the + * MMU hash or walking the PGT requires talking this lock + * @debugfs_list: node in debugfs list of contexts. + * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed + * to user so user could inquire about CS. It is used as + * index to cs_pending array. + * @dram_default_hops: array that holds all hops addresses needed for default + * DRAM mapping. + * @cs_lock: spinlock to protect cs_sequence. + * @dram_phys_mem: amount of used physical DRAM memory by this context. + * @thread_restore_token: token to prevent multiple threads of the same context + * from running the restore phase. Only one thread + * should run it. + * @thread_restore_wait_token: token to prevent the threads that didn't run + * the restore phase from moving to their execution + * phase before the restore phase has finished. + * @asid: context's unique address space ID in the device's MMU. + */ +struct hl_ctx { + DECLARE_HASHTABLE(mem_hash, MEM_HASH_TABLE_BITS); + DECLARE_HASHTABLE(mmu_hash, MMU_HASH_TABLE_BITS); + struct hl_fpriv *hpriv; + struct hl_device *hdev; + struct kref refcount; + struct dma_fence *cs_pending[HL_MAX_PENDING_CS]; + struct hl_va_range host_va_range; + struct hl_va_range dram_va_range; + struct mutex mem_hash_lock; + struct mutex mmu_lock; + struct list_head debugfs_list; + u64 cs_sequence; + u64 *dram_default_hops; + spinlock_t cs_lock; + atomic64_t dram_phys_mem; + atomic_t thread_restore_token; + u32 thread_restore_wait_token; + u32 asid; +}; + +/** + * struct hl_ctx_mgr - for handling multiple contexts. + * @ctx_lock: protects ctx_handles. + * @ctx_handles: idr to hold all ctx handles. + */ +struct hl_ctx_mgr { + struct mutex ctx_lock; + struct idr ctx_handles; +}; + + + +/* + * COMMAND SUBMISSIONS + */ + +/** + * struct hl_userptr - memory mapping chunk information + * @vm_type: type of the VM. + * @job_node: linked-list node for hanging the object on the Job's list. + * @vec: pointer to the frame vector. + * @sgt: pointer to the scatter-gather table that holds the pages. + * @dir: for DMA unmapping, the direction must be supplied, so save it. + * @debugfs_list: node in debugfs list of command submissions. + * @addr: user-space virtual pointer to the start of the memory area. + * @size: size of the memory area to pin & map. + * @dma_mapped: true if the SG was mapped to DMA addresses, false otherwise. + */ +struct hl_userptr { + enum vm_type_t vm_type; /* must be first */ + struct list_head job_node; + struct frame_vector *vec; + struct sg_table *sgt; + enum dma_data_direction dir; + struct list_head debugfs_list; + u64 addr; + u32 size; + u8 dma_mapped; +}; + +/** + * struct hl_cs - command submission. + * @jobs_in_queue_cnt: per each queue, maintain counter of submitted jobs. + * @ctx: the context this CS belongs to. + * @job_list: list of the CS's jobs in the various queues. + * @job_lock: spinlock for the CS's jobs list. Needed for free_job. + * @refcount: reference counter for usage of the CS. + * @fence: pointer to the fence object of this CS. + * @work_tdr: delayed work node for TDR. + * @mirror_node : node in device mirror list of command submissions. + * @debugfs_list: node in debugfs list of command submissions. + * @sequence: the sequence number of this CS. + * @submitted: true if CS was submitted to H/W. + * @completed: true if CS was completed by device. + * @timedout : true if CS was timedout. + * @tdr_active: true if TDR was activated for this CS (to prevent + * double TDR activation). + * @aborted: true if CS was aborted due to some device error. + */ +struct hl_cs { + u8 jobs_in_queue_cnt[HL_MAX_QUEUES]; + struct hl_ctx *ctx; + struct list_head job_list; + spinlock_t job_lock; + struct kref refcount; + struct dma_fence *fence; + struct delayed_work work_tdr; + struct list_head mirror_node; + struct list_head debugfs_list; + u64 sequence; + u8 submitted; + u8 completed; + u8 timedout; + u8 tdr_active; + u8 aborted; +}; + +/** + * struct hl_cs_job - command submission job. + * @cs_node: the node to hang on the CS jobs list. + * @cs: the CS this job belongs to. + * @user_cb: the CB we got from the user. + * @patched_cb: in case of patching, this is internal CB which is submitted on + * the queue instead of the CB we got from the IOCTL. + * @finish_work: workqueue object to run when job is completed. + * @userptr_list: linked-list of userptr mappings that belong to this job and + * wait for completion. + * @debugfs_list: node in debugfs list of command submission jobs. + * @id: the id of this job inside a CS. + * @hw_queue_id: the id of the H/W queue this job is submitted to. + * @user_cb_size: the actual size of the CB we got from the user. + * @job_cb_size: the actual size of the CB that we put on the queue. + * @ext_queue: whether the job is for external queue or internal queue. + */ +struct hl_cs_job { + struct list_head cs_node; + struct hl_cs *cs; + struct hl_cb *user_cb; + struct hl_cb *patched_cb; + struct work_struct finish_work; + struct list_head userptr_list; + struct list_head debugfs_list; + u32 id; + u32 hw_queue_id; + u32 user_cb_size; + u32 job_cb_size; + u8 ext_queue; +}; + +/** + * struct hl_cs_parser - command submission paerser properties. + * @user_cb: the CB we got from the user. + * @patched_cb: in case of patching, this is internal CB which is submitted on + * the queue instead of the CB we got from the IOCTL. + * @job_userptr_list: linked-list of userptr mappings that belong to the related + * job and wait for completion. + * @cs_sequence: the sequence number of the related CS. + * @ctx_id: the ID of the context the related CS belongs to. + * @hw_queue_id: the id of the H/W queue this job is submitted to. + * @user_cb_size: the actual size of the CB we got from the user. + * @patched_cb_size: the size of the CB after parsing. + * @ext_queue: whether the job is for external queue or internal queue. + * @job_id: the id of the related job inside the related CS. + * @use_virt_addr: whether to treat the addresses in the CB as virtual during + * parsing. + */ +struct hl_cs_parser { + struct hl_cb *user_cb; + struct hl_cb *patched_cb; + struct list_head *job_userptr_list; + u64 cs_sequence; + u32 ctx_id; + u32 hw_queue_id; + u32 user_cb_size; + u32 patched_cb_size; + u8 ext_queue; + u8 job_id; + u8 use_virt_addr; +}; + + +/* + * MEMORY STRUCTURE + */ + +/** + * struct hl_vm_hash_node - hash element from virtual address to virtual + * memory area descriptor (hl_vm_phys_pg_list or + * hl_userptr). + * @node: node to hang on the hash table in context object. + * @vaddr: key virtual address. + * @ptr: value pointer (hl_vm_phys_pg_list or hl_userptr). + */ +struct hl_vm_hash_node { + struct hlist_node node; + u64 vaddr; + void *ptr; +}; + +/** + * struct hl_vm_phys_pg_pack - physical page pack. + * @vm_type: describes the type of the virtual area descriptor. + * @pages: the physical page array. + * @mapping_cnt: number of shared mappings. + * @asid: the context related to this list. + * @npages: num physical pages in the pack. + * @page_size: size of each page in the pack. + * @total_size: total size of all the pages in this list. + * @flags: HL_MEM_* flags related to this list. + * @handle: the provided handle related to this list. + * @offset: offset from the first page. + * @contiguous: is contiguous physical memory. + * @created_from_userptr: is product of host virtual address. + */ +struct hl_vm_phys_pg_pack { + enum vm_type_t vm_type; /* must be first */ + u64 *pages; + atomic_t mapping_cnt; + u32 asid; + u32 npages; + u32 page_size; + u32 total_size; + u32 flags; + u32 handle; + u32 offset; + u8 contiguous; + u8 created_from_userptr; +}; + +/** + * struct hl_vm_va_block - virtual range block information. + * @node: node to hang on the virtual range list in context object. + * @start: virtual range start address. + * @end: virtual range end address. + * @size: virtual range size. + */ +struct hl_vm_va_block { + struct list_head node; + u64 start; + u64 end; + u64 size; +}; + +/** + * struct hl_vm - virtual memory manager for MMU. + * @dram_pg_pool: pool for DRAM physical pages of 2MB. + * @dram_pg_pool_refcount: reference counter for the pool usage. + * @idr_lock: protects the phys_pg_list_handles. + * @phys_pg_pack_handles: idr to hold all device allocations handles. + * @init_done: whether initialization was done. We need this because VM + * initialization might be skipped during device initialization. + */ +struct hl_vm { + struct gen_pool *dram_pg_pool; + struct kref dram_pg_pool_refcount; + spinlock_t idr_lock; + struct idr phys_pg_pack_handles; + u8 init_done; +}; + +/* + * FILE PRIVATE STRUCTURE + */ + +/** + * struct hl_fpriv - process information stored in FD private data. + * @hdev: habanalabs device structure. + * @filp: pointer to the given file structure. + * @taskpid: current process ID. + * @ctx: current executing context. + * @ctx_mgr: context manager to handle multiple context for this FD. + * @cb_mgr: command buffer manager to handle multiple buffers for this FD. + * @debugfs_list: list of relevant ASIC debugfs. + * @refcount: number of related contexts. + * @restore_phase_mutex: lock for context switch and restore phase. + */ +struct hl_fpriv { + struct hl_device *hdev; + struct file *filp; + struct pid *taskpid; + struct hl_ctx *ctx; /* TODO: remove for multiple ctx */ + struct hl_ctx_mgr ctx_mgr; + struct hl_cb_mgr cb_mgr; + struct list_head debugfs_list; + struct kref refcount; + struct mutex restore_phase_mutex; +}; + + +/* + * DebugFS + */ + +/** + * struct hl_info_list - debugfs file ops. + * @name: file name. + * @show: function to output information. + * @write: function to write to the file. + */ +struct hl_info_list { + const char *name; + int (*show)(struct seq_file *s, void *data); + ssize_t (*write)(struct file *file, const char __user *buf, + size_t count, loff_t *f_pos); +}; + +/** + * struct hl_debugfs_entry - debugfs dentry wrapper. + * @dent: base debugfs entry structure. + * @info_ent: dentry realted ops. + * @dev_entry: ASIC specific debugfs manager. + */ +struct hl_debugfs_entry { + struct dentry *dent; + const struct hl_info_list *info_ent; + struct hl_dbg_device_entry *dev_entry; +}; + +/** + * struct hl_dbg_device_entry - ASIC specific debugfs manager. + * @root: root dentry. + * @hdev: habanalabs device structure. + * @entry_arr: array of available hl_debugfs_entry. + * @file_list: list of available debugfs files. + * @file_mutex: protects file_list. + * @cb_list: list of available CBs. + * @cb_spinlock: protects cb_list. + * @cs_list: list of available CSs. + * @cs_spinlock: protects cs_list. + * @cs_job_list: list of available CB jobs. + * @cs_job_spinlock: protects cs_job_list. + * @userptr_list: list of available userptrs (virtual memory chunk descriptor). + * @userptr_spinlock: protects userptr_list. + * @ctx_mem_hash_list: list of available contexts with MMU mappings. + * @ctx_mem_hash_spinlock: protects cb_list. + * @addr: next address to read/write from/to in read/write32. + * @mmu_addr: next virtual address to translate to physical address in mmu_show. + * @mmu_asid: ASID to use while translating in mmu_show. + * @i2c_bus: generic u8 debugfs file for bus value to use in i2c_data_read. + * @i2c_bus: generic u8 debugfs file for address value to use in i2c_data_read. + * @i2c_bus: generic u8 debugfs file for register value to use in i2c_data_read. + */ +struct hl_dbg_device_entry { + struct dentry *root; + struct hl_device *hdev; + struct hl_debugfs_entry *entry_arr; + struct list_head file_list; + struct mutex file_mutex; + struct list_head cb_list; + spinlock_t cb_spinlock; + struct list_head cs_list; + spinlock_t cs_spinlock; + struct list_head cs_job_list; + spinlock_t cs_job_spinlock; + struct list_head userptr_list; + spinlock_t userptr_spinlock; + struct list_head ctx_mem_hash_list; + spinlock_t ctx_mem_hash_spinlock; + u64 addr; + u64 mmu_addr; + u32 mmu_asid; + u8 i2c_bus; + u8 i2c_addr; + u8 i2c_reg; +}; + + +/* + * DEVICES + */ + +/* Theoretical limit only. A single host can only contain up to 4 or 8 PCIe + * x16 cards. In extereme cases, there are hosts that can accommodate 16 cards + */ +#define HL_MAX_MINORS 256 + +/* + * Registers read & write functions. + */ + +u32 hl_rreg(struct hl_device *hdev, u32 reg); +void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); + +#define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \ + readl_poll_timeout(hdev->rmmio + addr, val, cond, sleep_us, timeout_us) + +#define RREG32(reg) hl_rreg(hdev, (reg)) +#define WREG32(reg, v) hl_wreg(hdev, (reg), (v)) +#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ + hl_rreg(hdev, (reg))) + +#define WREG32_P(reg, val, mask) \ + do { \ + u32 tmp_ = RREG32(reg); \ + tmp_ &= (mask); \ + tmp_ |= ((val) & ~(mask)); \ + WREG32(reg, tmp_); \ + } while (0) +#define WREG32_AND(reg, and) WREG32_P(reg, 0, and) +#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) + +#define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT +#define REG_FIELD_MASK(reg, field) reg##_##field##_MASK +#define WREG32_FIELD(reg, field, val) \ + WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \ + (val) << REG_FIELD_SHIFT(reg, field)) + +struct hwmon_chip_info; + +/** + * struct hl_device_reset_work - reset workqueue task wrapper. + * @reset_work: reset work to be done. + * @hdev: habanalabs device structure. + */ +struct hl_device_reset_work { + struct work_struct reset_work; + struct hl_device *hdev; +}; + +/** + * struct hl_device - habanalabs device structure. + * @pdev: pointer to PCI device, can be NULL in case of simulator device. + * @pcie_bar: array of available PCIe bars. + * @rmmio: configuration area address on SRAM. + * @cdev: related char device. + * @dev: realted kernel basic device structure. + * @work_freq: delayed work to lower device frequency if possible. + * @work_heartbeat: delayed work for ArmCP is-alive check. + * @asic_name: ASIC specific nmae. + * @asic_type: ASIC specific type. + * @completion_queue: array of hl_cq. + * @cq_wq: work queue of completion queues for executing work in process context + * @eq_wq: work queue of event queue for executing work in process context. + * @kernel_ctx: KMD context structure. + * @kernel_queues: array of hl_hw_queue. + * @hw_queues_mirror_list: CS mirror list for TDR. + * @hw_queues_mirror_lock: protects hw_queues_mirror_list. + * @kernel_cb_mgr: command buffer manager for creating/destroying/handling CGs. + * @event_queue: event queue for IRQ from ArmCP. + * @dma_pool: DMA pool for small allocations. + * @cpu_accessible_dma_mem: KMD <-> ArmCP shared memory CPU address. + * @cpu_accessible_dma_address: KMD <-> ArmCP shared memory DMA address. + * @cpu_accessible_dma_pool: KMD <-> ArmCP shared memory pool. + * @asid_bitmap: holds used/available ASIDs. + * @asid_mutex: protects asid_bitmap. + * @fd_open_cnt_lock: lock for updating fd_open_cnt in hl_device_open. Although + * fd_open_cnt is atomic, we need this lock to serialize + * the open function because the driver currently supports + * only a single process at a time. In addition, we need a + * lock here so we can flush user processes which are opening + * the device while we are trying to hard reset it + * @send_cpu_message_lock: enforces only one message in KMD <-> ArmCP queue. + * @asic_prop: ASIC specific immutable properties. + * @asic_funcs: ASIC specific functions. + * @asic_specific: ASIC specific information to use only from ASIC files. + * @mmu_pgt_pool: pool of available MMU hops. + * @vm: virtual memory manager for MMU. + * @mmu_cache_lock: protects MMU cache invalidation as it can serve one context + * @hwmon_dev: H/W monitor device. + * @pm_mng_profile: current power management profile. + * @hl_chip_info: ASIC's sensors information. + * @hl_debugfs: device's debugfs manager. + * @cb_pool: list of preallocated CBs. + * @cb_pool_lock: protects the CB pool. + * @user_ctx: current user context executing. + * @dram_used_mem: current DRAM memory consumption. + * @in_reset: is device in reset flow. + * @curr_pll_profile: current PLL profile. + * @fd_open_cnt: number of open user processes. + * @timeout_jiffies: device CS timeout value. + * @max_power: the max power of the device, as configured by the sysadmin. This + * value is saved so in case of hard-reset, KMD will restore this + * value and update the F/W after the re-initialization + * @major: habanalabs KMD major. + * @high_pll: high PLL profile frequency. + * @soft_reset_cnt: number of soft reset since KMD loading. + * @hard_reset_cnt: number of hard reset since KMD loading. + * @id: device minor. + * @disabled: is device disabled. + * @late_init_done: is late init stage was done during initialization. + * @hwmon_initialized: is H/W monitor sensors was initialized. + * @hard_reset_pending: is there a hard reset work pending. + * @heartbeat: is heartbeat sanity check towards ArmCP enabled. + * @reset_on_lockup: true if a reset should be done in case of stuck CS, false + * otherwise. + * @dram_supports_virtual_memory: is MMU enabled towards DRAM. + * @dram_default_page_mapping: is DRAM default page mapping enabled. + * @init_done: is the initialization of the device done. + * @mmu_enable: is MMU enabled. + * @device_cpu_disabled: is the device CPU disabled (due to timeouts) + */ +struct hl_device { + struct pci_dev *pdev; + void __iomem *pcie_bar[6]; + void __iomem *rmmio; + struct cdev cdev; + struct device *dev; + struct delayed_work work_freq; + struct delayed_work work_heartbeat; + char asic_name[16]; + enum hl_asic_type asic_type; + struct hl_cq *completion_queue; + struct workqueue_struct *cq_wq; + struct workqueue_struct *eq_wq; + struct hl_ctx *kernel_ctx; + struct hl_hw_queue *kernel_queues; + struct list_head hw_queues_mirror_list; + spinlock_t hw_queues_mirror_lock; + struct hl_cb_mgr kernel_cb_mgr; + struct hl_eq event_queue; + struct dma_pool *dma_pool; + void *cpu_accessible_dma_mem; + dma_addr_t cpu_accessible_dma_address; + struct gen_pool *cpu_accessible_dma_pool; + unsigned long *asid_bitmap; + struct mutex asid_mutex; + /* TODO: remove fd_open_cnt_lock for multiple process support */ + struct mutex fd_open_cnt_lock; + struct mutex send_cpu_message_lock; + struct asic_fixed_properties asic_prop; + const struct hl_asic_funcs *asic_funcs; + void *asic_specific; + struct gen_pool *mmu_pgt_pool; + struct hl_vm vm; + struct mutex mmu_cache_lock; + struct device *hwmon_dev; + enum hl_pm_mng_profile pm_mng_profile; + struct hwmon_chip_info *hl_chip_info; + + struct hl_dbg_device_entry hl_debugfs; + + struct list_head cb_pool; + spinlock_t cb_pool_lock; + + /* TODO: remove user_ctx for multiple process support */ + struct hl_ctx *user_ctx; + + atomic64_t dram_used_mem; + atomic_t in_reset; + atomic_t curr_pll_profile; + atomic_t fd_open_cnt; + u64 timeout_jiffies; + u64 max_power; + u32 major; + u32 high_pll; + u32 soft_reset_cnt; + u32 hard_reset_cnt; + u16 id; + u8 disabled; + u8 late_init_done; + u8 hwmon_initialized; + u8 hard_reset_pending; + u8 heartbeat; + u8 reset_on_lockup; + u8 dram_supports_virtual_memory; + u8 dram_default_page_mapping; + u8 init_done; + u8 device_cpu_disabled; + + /* Parameters for bring-up */ + u8 mmu_enable; + u8 cpu_enable; + u8 reset_pcilink; + u8 cpu_queues_enable; + u8 fw_loading; + u8 pldm; +}; + + +/* + * IOCTLs + */ + +/** + * typedef hl_ioctl_t - typedef for ioctl function in the driver + * @hpriv: pointer to the FD's private data, which contains state of + * user process + * @data: pointer to the input/output arguments structure of the IOCTL + * + * Return: 0 for success, negative value for error + */ +typedef int hl_ioctl_t(struct hl_fpriv *hpriv, void *data); + +/** + * struct hl_ioctl_desc - describes an IOCTL entry of the driver. + * @cmd: the IOCTL code as created by the kernel macros. + * @func: pointer to the driver's function that should be called for this IOCTL. + */ +struct hl_ioctl_desc { + unsigned int cmd; + hl_ioctl_t *func; +}; + + +/* + * Kernel module functions that can be accessed by entire module + */ + +/** + * hl_mem_area_inside_range() - Checks whether address+size are inside a range. + * @address: The start address of the area we want to validate. + * @size: The size in bytes of the area we want to validate. + * @range_start_address: The start address of the valid range. + * @range_end_address: The end address of the valid range. + * + * Return: true if the area is inside the valid range, false otherwise. + */ +static inline bool hl_mem_area_inside_range(u64 address, u32 size, + u64 range_start_address, u64 range_end_address) +{ + u64 end_address = address + size; + + if ((address >= range_start_address) && + (end_address <= range_end_address) && + (end_address > address)) + return true; + + return false; +} + +/** + * hl_mem_area_crosses_range() - Checks whether address+size crossing a range. + * @address: The start address of the area we want to validate. + * @size: The size in bytes of the area we want to validate. + * @range_start_address: The start address of the valid range. + * @range_end_address: The end address of the valid range. + * + * Return: true if the area overlaps part or all of the valid range, + * false otherwise. + */ +static inline bool hl_mem_area_crosses_range(u64 address, u32 size, + u64 range_start_address, u64 range_end_address) +{ + u64 end_address = address + size; + + if ((address >= range_start_address) && + (address < range_end_address)) + return true; + + if ((end_address >= range_start_address) && + (end_address < range_end_address)) + return true; + + if ((address < range_start_address) && + (end_address >= range_end_address)) + return true; + + return false; +} + +int hl_device_open(struct inode *inode, struct file *filp); +bool hl_device_disabled_or_in_reset(struct hl_device *hdev); +int create_hdev(struct hl_device **dev, struct pci_dev *pdev, + enum hl_asic_type asic_type, int minor); +void destroy_hdev(struct hl_device *hdev); +int hl_poll_timeout_memory(struct hl_device *hdev, u64 addr, u32 timeout_us, + u32 *val); +int hl_poll_timeout_device_memory(struct hl_device *hdev, void __iomem *addr, + u32 timeout_us, u32 *val); +int hl_hw_queues_create(struct hl_device *hdev); +void hl_hw_queues_destroy(struct hl_device *hdev); +int hl_hw_queue_send_cb_no_cmpl(struct hl_device *hdev, u32 hw_queue_id, + u32 cb_size, u64 cb_ptr); +int hl_hw_queue_schedule_cs(struct hl_cs *cs); +u32 hl_hw_queue_add_ptr(u32 ptr, u16 val); +void hl_hw_queue_inc_ci_kernel(struct hl_device *hdev, u32 hw_queue_id); +void hl_int_hw_queue_update_ci(struct hl_cs *cs); +void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset); + +#define hl_queue_inc_ptr(p) hl_hw_queue_add_ptr(p, 1) +#define hl_pi_2_offset(pi) ((pi) & (HL_QUEUE_LENGTH - 1)) + +int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id); +void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q); +int hl_eq_init(struct hl_device *hdev, struct hl_eq *q); +void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q); +void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q); +void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q); +irqreturn_t hl_irq_handler_cq(int irq, void *arg); +irqreturn_t hl_irq_handler_eq(int irq, void *arg); +u32 hl_cq_inc_ptr(u32 ptr); + +int hl_asid_init(struct hl_device *hdev); +void hl_asid_fini(struct hl_device *hdev); +unsigned long hl_asid_alloc(struct hl_device *hdev); +void hl_asid_free(struct hl_device *hdev, unsigned long asid); + +int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv); +void hl_ctx_free(struct hl_device *hdev, struct hl_ctx *ctx); +int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx); +void hl_ctx_do_release(struct kref *ref); +void hl_ctx_get(struct hl_device *hdev, struct hl_ctx *ctx); +int hl_ctx_put(struct hl_ctx *ctx); +struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq); +void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr); +void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr); + +int hl_device_init(struct hl_device *hdev, struct class *hclass); +void hl_device_fini(struct hl_device *hdev); +int hl_device_suspend(struct hl_device *hdev); +int hl_device_resume(struct hl_device *hdev); +int hl_device_reset(struct hl_device *hdev, bool hard_reset, + bool from_hard_reset_thread); +void hl_hpriv_get(struct hl_fpriv *hpriv); +void hl_hpriv_put(struct hl_fpriv *hpriv); +int hl_device_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq); + +int hl_build_hwmon_channel_info(struct hl_device *hdev, + struct armcp_sensor *sensors_arr); + +int hl_sysfs_init(struct hl_device *hdev); +void hl_sysfs_fini(struct hl_device *hdev); + +int hl_hwmon_init(struct hl_device *hdev); +void hl_hwmon_fini(struct hl_device *hdev); + +int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, u32 cb_size, + u64 *handle, int ctx_id); +int hl_cb_destroy(struct hl_device *hdev, struct hl_cb_mgr *mgr, u64 cb_handle); +int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma); +struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr, + u32 handle); +void hl_cb_put(struct hl_cb *cb); +void hl_cb_mgr_init(struct hl_cb_mgr *mgr); +void hl_cb_mgr_fini(struct hl_device *hdev, struct hl_cb_mgr *mgr); +struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size); +int hl_cb_pool_init(struct hl_device *hdev); +int hl_cb_pool_fini(struct hl_device *hdev); + +void hl_cs_rollback_all(struct hl_device *hdev); +struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, bool ext_queue); + +void goya_set_asic_funcs(struct hl_device *hdev); + +int hl_vm_ctx_init(struct hl_ctx *ctx); +void hl_vm_ctx_fini(struct hl_ctx *ctx); + +int hl_vm_init(struct hl_device *hdev); +void hl_vm_fini(struct hl_device *hdev); + +int hl_pin_host_memory(struct hl_device *hdev, u64 addr, u64 size, + struct hl_userptr *userptr); +int hl_unpin_host_memory(struct hl_device *hdev, struct hl_userptr *userptr); +void hl_userptr_delete_list(struct hl_device *hdev, + struct list_head *userptr_list); +bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, u32 size, + struct list_head *userptr_list, + struct hl_userptr **userptr); + +int hl_mmu_init(struct hl_device *hdev); +void hl_mmu_fini(struct hl_device *hdev); +int hl_mmu_ctx_init(struct hl_ctx *ctx); +void hl_mmu_ctx_fini(struct hl_ctx *ctx); +int hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size); +int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size); +void hl_mmu_swap_out(struct hl_ctx *ctx); +void hl_mmu_swap_in(struct hl_ctx *ctx); + +long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr); +void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq); +long hl_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr); +long hl_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr); +long hl_get_current(struct hl_device *hdev, int sensor_index, u32 attr); +long hl_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr); +long hl_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr); +void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, + long value); +u64 hl_get_max_power(struct hl_device *hdev); +void hl_set_max_power(struct hl_device *hdev, u64 value); + +#ifdef CONFIG_DEBUG_FS + +void hl_debugfs_init(void); +void hl_debugfs_fini(void); +void hl_debugfs_add_device(struct hl_device *hdev); +void hl_debugfs_remove_device(struct hl_device *hdev); +void hl_debugfs_add_file(struct hl_fpriv *hpriv); +void hl_debugfs_remove_file(struct hl_fpriv *hpriv); +void hl_debugfs_add_cb(struct hl_cb *cb); +void hl_debugfs_remove_cb(struct hl_cb *cb); +void hl_debugfs_add_cs(struct hl_cs *cs); +void hl_debugfs_remove_cs(struct hl_cs *cs); +void hl_debugfs_add_job(struct hl_device *hdev, struct hl_cs_job *job); +void hl_debugfs_remove_job(struct hl_device *hdev, struct hl_cs_job *job); +void hl_debugfs_add_userptr(struct hl_device *hdev, struct hl_userptr *userptr); +void hl_debugfs_remove_userptr(struct hl_device *hdev, + struct hl_userptr *userptr); +void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx); +void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx); + +#else + +static inline void __init hl_debugfs_init(void) +{ +} + +static inline void hl_debugfs_fini(void) +{ +} + +static inline void hl_debugfs_add_device(struct hl_device *hdev) +{ +} + +static inline void hl_debugfs_remove_device(struct hl_device *hdev) +{ +} + +static inline void hl_debugfs_add_file(struct hl_fpriv *hpriv) +{ +} + +static inline void hl_debugfs_remove_file(struct hl_fpriv *hpriv) +{ +} + +static inline void hl_debugfs_add_cb(struct hl_cb *cb) +{ +} + +static inline void hl_debugfs_remove_cb(struct hl_cb *cb) +{ +} + +static inline void hl_debugfs_add_cs(struct hl_cs *cs) +{ +} + +static inline void hl_debugfs_remove_cs(struct hl_cs *cs) +{ +} + +static inline void hl_debugfs_add_job(struct hl_device *hdev, + struct hl_cs_job *job) +{ +} + +static inline void hl_debugfs_remove_job(struct hl_device *hdev, + struct hl_cs_job *job) +{ +} + +static inline void hl_debugfs_add_userptr(struct hl_device *hdev, + struct hl_userptr *userptr) +{ +} + +static inline void hl_debugfs_remove_userptr(struct hl_device *hdev, + struct hl_userptr *userptr) +{ +} + +static inline void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, + struct hl_ctx *ctx) +{ +} + +static inline void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, + struct hl_ctx *ctx) +{ +} + +#endif + +/* IOCTLs */ +long hl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); +int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data); +int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data); +int hl_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data); +int hl_mem_ioctl(struct hl_fpriv *hpriv, void *data); + +#endif /* HABANALABSP_H_ */ diff --git a/drivers/misc/habanalabs/habanalabs_drv.c b/drivers/misc/habanalabs/habanalabs_drv.c new file mode 100644 index 000000000000..748601463f11 --- /dev/null +++ b/drivers/misc/habanalabs/habanalabs_drv.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#include "habanalabs.h" + +#include <linux/pci.h> +#include <linux/module.h> + +#define HL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team" + +#define HL_DRIVER_DESC "Driver for HabanaLabs's AI Accelerators" + +MODULE_AUTHOR(HL_DRIVER_AUTHOR); +MODULE_DESCRIPTION(HL_DRIVER_DESC); +MODULE_LICENSE("GPL v2"); + +static int hl_major; +static struct class *hl_class; +static DEFINE_IDR(hl_devs_idr); +static DEFINE_MUTEX(hl_devs_idr_lock); + +static int timeout_locked = 5; +static int reset_on_lockup = 1; + +module_param(timeout_locked, int, 0444); +MODULE_PARM_DESC(timeout_locked, + "Device lockup timeout in seconds (0 = disabled, default 5s)"); + +module_param(reset_on_lockup, int, 0444); +MODULE_PARM_DESC(reset_on_lockup, + "Do device reset on lockup (0 = no, 1 = yes, default yes)"); + +#define PCI_VENDOR_ID_HABANALABS 0x1da3 + +#define PCI_IDS_GOYA 0x0001 + +static const struct pci_device_id ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GOYA), }, + { 0, } +}; +MODULE_DEVICE_TABLE(pci, ids); + +/* + * get_asic_type - translate device id to asic type + * + * @device: id of the PCI device + * + * Translate device id to asic type. + * In case of unidentified device, return -1 + */ +static enum hl_asic_type get_asic_type(u16 device) +{ + enum hl_asic_type asic_type; + + switch (device) { + case PCI_IDS_GOYA: + asic_type = ASIC_GOYA; + break; + default: + asic_type = ASIC_INVALID; + break; + } + + return asic_type; +} + +/* + * hl_device_open - open function for habanalabs device + * + * @inode: pointer to inode structure + * @filp: pointer to file structure + * + * Called when process opens an habanalabs device. + */ +int hl_device_open(struct inode *inode, struct file *filp) +{ + struct hl_device *hdev; + struct hl_fpriv *hpriv; + int rc; + + mutex_lock(&hl_devs_idr_lock); + hdev = idr_find(&hl_devs_idr, iminor(inode)); + mutex_unlock(&hl_devs_idr_lock); + + if (!hdev) { + pr_err("Couldn't find device %d:%d\n", + imajor(inode), iminor(inode)); + return -ENXIO; + } + + mutex_lock(&hdev->fd_open_cnt_lock); + + if (hl_device_disabled_or_in_reset(hdev)) { + dev_err_ratelimited(hdev->dev, + "Can't open %s because it is disabled or in reset\n", + dev_name(hdev->dev)); + mutex_unlock(&hdev->fd_open_cnt_lock); + return -EPERM; + } + + if (atomic_read(&hdev->fd_open_cnt)) { + dev_info_ratelimited(hdev->dev, + "Device %s is already attached to application\n", + dev_name(hdev->dev)); + mutex_unlock(&hdev->fd_open_cnt_lock); + return -EBUSY; + } + + atomic_inc(&hdev->fd_open_cnt); + + mutex_unlock(&hdev->fd_open_cnt_lock); + + hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); + if (!hpriv) { + rc = -ENOMEM; + goto close_device; + } + + hpriv->hdev = hdev; + filp->private_data = hpriv; + hpriv->filp = filp; + mutex_init(&hpriv->restore_phase_mutex); + kref_init(&hpriv->refcount); + nonseekable_open(inode, filp); + + hl_cb_mgr_init(&hpriv->cb_mgr); + hl_ctx_mgr_init(&hpriv->ctx_mgr); + + rc = hl_ctx_create(hdev, hpriv); + if (rc) { + dev_err(hdev->dev, "Failed to open FD (CTX fail)\n"); + goto out_err; + } + + hpriv->taskpid = find_get_pid(current->pid); + + /* + * Device is IDLE at this point so it is legal to change PLLs. There + * is no need to check anything because if the PLL is already HIGH, the + * set function will return without doing anything + */ + hl_device_set_frequency(hdev, PLL_HIGH); + + hl_debugfs_add_file(hpriv); + + return 0; + +out_err: + filp->private_data = NULL; + hl_ctx_mgr_fini(hpriv->hdev, &hpriv->ctx_mgr); + hl_cb_mgr_fini(hpriv->hdev, &hpriv->cb_mgr); + mutex_destroy(&hpriv->restore_phase_mutex); + kfree(hpriv); + +close_device: + atomic_dec(&hdev->fd_open_cnt); + return rc; +} + +/* + * create_hdev - create habanalabs device instance + * + * @dev: will hold the pointer to the new habanalabs device structure + * @pdev: pointer to the pci device + * @asic_type: in case of simulator device, which device is it + * @minor: in case of simulator device, the minor of the device + * + * Allocate memory for habanalabs device and initialize basic fields + * Identify the ASIC type + * Allocate ID (minor) for the device (only for real devices) + */ +int create_hdev(struct hl_device **dev, struct pci_dev *pdev, + enum hl_asic_type asic_type, int minor) +{ + struct hl_device *hdev; + int rc; + + *dev = NULL; + + hdev = kzalloc(sizeof(*hdev), GFP_KERNEL); + if (!hdev) + return -ENOMEM; + + hdev->major = hl_major; + hdev->reset_on_lockup = reset_on_lockup; + + /* Parameters for bring-up - set them to defaults */ + hdev->mmu_enable = 1; + hdev->cpu_enable = 1; + hdev->reset_pcilink = 0; + hdev->cpu_queues_enable = 1; + hdev->fw_loading = 1; + hdev->pldm = 0; + hdev->heartbeat = 1; + + /* If CPU is disabled, no point in loading FW */ + if (!hdev->cpu_enable) + hdev->fw_loading = 0; + + /* If we don't load FW, no need to initialize CPU queues */ + if (!hdev->fw_loading) + hdev->cpu_queues_enable = 0; + + /* If CPU queues not enabled, no way to do heartbeat */ + if (!hdev->cpu_queues_enable) + hdev->heartbeat = 0; + + if (timeout_locked) + hdev->timeout_jiffies = msecs_to_jiffies(timeout_locked * 1000); + else + hdev->timeout_jiffies = MAX_SCHEDULE_TIMEOUT; + + hdev->disabled = true; + hdev->pdev = pdev; /* can be NULL in case of simulator device */ + + if (asic_type == ASIC_AUTO_DETECT) { + hdev->asic_type = get_asic_type(pdev->device); + if (hdev->asic_type == ASIC_INVALID) { + dev_err(&pdev->dev, "Unsupported ASIC\n"); + rc = -ENODEV; + goto free_hdev; + } + } else { + hdev->asic_type = asic_type; + } + + mutex_lock(&hl_devs_idr_lock); + + if (minor == -1) { + rc = idr_alloc(&hl_devs_idr, hdev, 0, HL_MAX_MINORS, + GFP_KERNEL); + } else { + void *old_idr = idr_replace(&hl_devs_idr, hdev, minor); + + if (IS_ERR_VALUE(old_idr)) { + rc = PTR_ERR(old_idr); + pr_err("Error %d when trying to replace minor %d\n", + rc, minor); + mutex_unlock(&hl_devs_idr_lock); + goto free_hdev; + } + rc = minor; + } + + mutex_unlock(&hl_devs_idr_lock); + + if (rc < 0) { + if (rc == -ENOSPC) { + pr_err("too many devices in the system\n"); + rc = -EBUSY; + } + goto free_hdev; + } + + hdev->id = rc; + + *dev = hdev; + + return 0; + +free_hdev: + kfree(hdev); + return rc; +} + +/* + * destroy_hdev - destroy habanalabs device instance + * + * @dev: pointer to the habanalabs device structure + * + */ +void destroy_hdev(struct hl_device *hdev) +{ + /* Remove device from the device list */ + mutex_lock(&hl_devs_idr_lock); + idr_remove(&hl_devs_idr, hdev->id); + mutex_unlock(&hl_devs_idr_lock); + + kfree(hdev); +} + +static int hl_pmops_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct hl_device *hdev = pci_get_drvdata(pdev); + + pr_debug("Going to suspend PCI device\n"); + + if (!hdev) { + pr_err("device pointer is NULL in suspend\n"); + return 0; + } + + return hl_device_suspend(hdev); +} + +static int hl_pmops_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct hl_device *hdev = pci_get_drvdata(pdev); + + pr_debug("Going to resume PCI device\n"); + + if (!hdev) { + pr_err("device pointer is NULL in resume\n"); + return 0; + } + + return hl_device_resume(hdev); +} + +/* + * hl_pci_probe - probe PCI habanalabs devices + * + * @pdev: pointer to pci device + * @id: pointer to pci device id structure + * + * Standard PCI probe function for habanalabs device. + * Create a new habanalabs device and initialize it according to the + * device's type + */ +static int hl_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct hl_device *hdev; + int rc; + + dev_info(&pdev->dev, HL_NAME + " device found [%04x:%04x] (rev %x)\n", + (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); + + rc = create_hdev(&hdev, pdev, ASIC_AUTO_DETECT, -1); + if (rc) + return rc; + + pci_set_drvdata(pdev, hdev); + + rc = hl_device_init(hdev, hl_class); + if (rc) { + dev_err(&pdev->dev, "Fatal error during habanalabs device init\n"); + rc = -ENODEV; + goto disable_device; + } + + return 0; + +disable_device: + pci_set_drvdata(pdev, NULL); + destroy_hdev(hdev); + + return rc; +} + +/* + * hl_pci_remove - remove PCI habanalabs devices + * + * @pdev: pointer to pci device + * + * Standard PCI remove function for habanalabs device + */ +static void hl_pci_remove(struct pci_dev *pdev) +{ + struct hl_device *hdev; + + hdev = pci_get_drvdata(pdev); + if (!hdev) + return; + + hl_device_fini(hdev); + pci_set_drvdata(pdev, NULL); + + destroy_hdev(hdev); +} + +static const struct dev_pm_ops hl_pm_ops = { + .suspend = hl_pmops_suspend, + .resume = hl_pmops_resume, +}; + +static struct pci_driver hl_pci_driver = { + .name = HL_NAME, + .id_table = ids, + .probe = hl_pci_probe, + .remove = hl_pci_remove, + .driver.pm = &hl_pm_ops, +}; + +/* + * hl_init - Initialize the habanalabs kernel driver + */ +static int __init hl_init(void) +{ + int rc; + dev_t dev; + + pr_info("loading driver\n"); + + rc = alloc_chrdev_region(&dev, 0, HL_MAX_MINORS, HL_NAME); + if (rc < 0) { + pr_err("unable to get major\n"); + return rc; + } + + hl_major = MAJOR(dev); + + hl_class = class_create(THIS_MODULE, HL_NAME); + if (IS_ERR(hl_class)) { + pr_err("failed to allocate class\n"); + rc = PTR_ERR(hl_class); + goto remove_major; + } + + hl_debugfs_init(); + + rc = pci_register_driver(&hl_pci_driver); + if (rc) { + pr_err("failed to register pci device\n"); + goto remove_debugfs; + } + + pr_debug("driver loaded\n"); + + return 0; + +remove_debugfs: + hl_debugfs_fini(); + class_destroy(hl_class); +remove_major: + unregister_chrdev_region(MKDEV(hl_major, 0), HL_MAX_MINORS); + return rc; +} + +/* + * hl_exit - Release all resources of the habanalabs kernel driver + */ +static void __exit hl_exit(void) +{ + pci_unregister_driver(&hl_pci_driver); + + /* + * Removing debugfs must be after all devices or simulator devices + * have been removed because otherwise we get a bug in the + * debugfs module for referencing NULL objects + */ + hl_debugfs_fini(); + + class_destroy(hl_class); + unregister_chrdev_region(MKDEV(hl_major, 0), HL_MAX_MINORS); + + idr_destroy(&hl_devs_idr); + + pr_debug("driver removed\n"); +} + +module_init(hl_init); +module_exit(hl_exit); diff --git a/drivers/misc/habanalabs/habanalabs_ioctl.c b/drivers/misc/habanalabs/habanalabs_ioctl.c new file mode 100644 index 000000000000..2c2739a3c5ec --- /dev/null +++ b/drivers/misc/habanalabs/habanalabs_ioctl.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include <uapi/misc/habanalabs.h> +#include "habanalabs.h" + +#include <linux/fs.h> +#include <linux/uaccess.h> +#include <linux/slab.h> + +static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) +{ + struct hl_info_hw_ip_info hw_ip = {0}; + u32 size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 sram_kmd_size, dram_kmd_size; + + if ((!size) || (!out)) + return -EINVAL; + + sram_kmd_size = (prop->sram_user_base_address - + prop->sram_base_address); + dram_kmd_size = (prop->dram_user_base_address - + prop->dram_base_address); + + hw_ip.device_id = hdev->asic_funcs->get_pci_id(hdev); + hw_ip.sram_base_address = prop->sram_user_base_address; + hw_ip.dram_base_address = prop->dram_user_base_address; + hw_ip.tpc_enabled_mask = prop->tpc_enabled_mask; + hw_ip.sram_size = prop->sram_size - sram_kmd_size; + hw_ip.dram_size = prop->dram_size - dram_kmd_size; + if (hw_ip.dram_size > 0) + hw_ip.dram_enabled = 1; + hw_ip.num_of_events = prop->num_of_events; + memcpy(hw_ip.armcp_version, + prop->armcp_info.armcp_version, VERSION_MAX_LEN); + hw_ip.armcp_cpld_version = __le32_to_cpu(prop->armcp_info.cpld_version); + hw_ip.psoc_pci_pll_nr = prop->psoc_pci_pll_nr; + hw_ip.psoc_pci_pll_nf = prop->psoc_pci_pll_nf; + hw_ip.psoc_pci_pll_od = prop->psoc_pci_pll_od; + hw_ip.psoc_pci_pll_div_factor = prop->psoc_pci_pll_div_factor; + + return copy_to_user(out, &hw_ip, + min((size_t)size, sizeof(hw_ip))) ? -EFAULT : 0; +} + +static int hw_events_info(struct hl_device *hdev, struct hl_info_args *args) +{ + u32 size, max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + void *arr; + + if ((!max_size) || (!out)) + return -EINVAL; + + arr = hdev->asic_funcs->get_events_stat(hdev, &size); + + return copy_to_user(out, arr, min(max_size, size)) ? -EFAULT : 0; +} + +static int dram_usage_info(struct hl_device *hdev, struct hl_info_args *args) +{ + struct hl_info_dram_usage dram_usage = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 dram_kmd_size; + + if ((!max_size) || (!out)) + return -EINVAL; + + dram_kmd_size = (prop->dram_user_base_address - + prop->dram_base_address); + dram_usage.dram_free_mem = (prop->dram_size - dram_kmd_size) - + atomic64_read(&hdev->dram_used_mem); + dram_usage.ctx_dram_mem = atomic64_read(&hdev->user_ctx->dram_phys_mem); + + return copy_to_user(out, &dram_usage, + min((size_t) max_size, sizeof(dram_usage))) ? -EFAULT : 0; +} + +static int hw_idle(struct hl_device *hdev, struct hl_info_args *args) +{ + struct hl_info_hw_idle hw_idle = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + + if ((!max_size) || (!out)) + return -EINVAL; + + hw_idle.is_idle = hdev->asic_funcs->is_device_idle(hdev); + + return copy_to_user(out, &hw_idle, + min((size_t) max_size, sizeof(hw_idle))) ? -EFAULT : 0; +} + +static int hl_info_ioctl(struct hl_fpriv *hpriv, void *data) +{ + struct hl_info_args *args = data; + struct hl_device *hdev = hpriv->hdev; + int rc; + + if (hl_device_disabled_or_in_reset(hdev)) { + dev_err(hdev->dev, + "Device is disabled or in reset. Can't execute INFO IOCTL\n"); + return -EBUSY; + } + + switch (args->op) { + case HL_INFO_HW_IP_INFO: + rc = hw_ip_info(hdev, args); + break; + + case HL_INFO_HW_EVENTS: + rc = hw_events_info(hdev, args); + break; + + case HL_INFO_DRAM_USAGE: + rc = dram_usage_info(hdev, args); + break; + + case HL_INFO_HW_IDLE: + rc = hw_idle(hdev, args); + break; + + default: + dev_err(hdev->dev, "Invalid request %d\n", args->op); + rc = -ENOTTY; + break; + } + + return rc; +} + +#define HL_IOCTL_DEF(ioctl, _func) \ + [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func} + +static const struct hl_ioctl_desc hl_ioctls[] = { + HL_IOCTL_DEF(HL_IOCTL_INFO, hl_info_ioctl), + HL_IOCTL_DEF(HL_IOCTL_CB, hl_cb_ioctl), + HL_IOCTL_DEF(HL_IOCTL_CS, hl_cs_ioctl), + HL_IOCTL_DEF(HL_IOCTL_WAIT_CS, hl_cs_wait_ioctl), + HL_IOCTL_DEF(HL_IOCTL_MEMORY, hl_mem_ioctl) +}; + +#define HL_CORE_IOCTL_COUNT ARRAY_SIZE(hl_ioctls) + +long hl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) +{ + struct hl_fpriv *hpriv = filep->private_data; + struct hl_device *hdev = hpriv->hdev; + hl_ioctl_t *func; + const struct hl_ioctl_desc *ioctl = NULL; + unsigned int nr = _IOC_NR(cmd); + char stack_kdata[128] = {0}; + char *kdata = NULL; + unsigned int usize, asize; + int retcode; + + if (hdev->hard_reset_pending) { + dev_crit_ratelimited(hdev->dev, + "Device HARD reset pending! Please close FD\n"); + return -ENODEV; + } + + if ((nr >= HL_COMMAND_START) && (nr < HL_COMMAND_END)) { + u32 hl_size; + + ioctl = &hl_ioctls[nr]; + + hl_size = _IOC_SIZE(ioctl->cmd); + usize = asize = _IOC_SIZE(cmd); + if (hl_size > asize) + asize = hl_size; + + cmd = ioctl->cmd; + } else { + dev_err(hdev->dev, "invalid ioctl: pid=%d, nr=0x%02x\n", + task_pid_nr(current), nr); + return -ENOTTY; + } + + /* Do not trust userspace, use our own definition */ + func = ioctl->func; + + if (unlikely(!func)) { + dev_dbg(hdev->dev, "no function\n"); + retcode = -ENOTTY; + goto out_err; + } + + if (cmd & (IOC_IN | IOC_OUT)) { + if (asize <= sizeof(stack_kdata)) { + kdata = stack_kdata; + } else { + kdata = kzalloc(asize, GFP_KERNEL); + if (!kdata) { + retcode = -ENOMEM; + goto out_err; + } + } + } + + if (cmd & IOC_IN) { + if (copy_from_user(kdata, (void __user *)arg, usize)) { + retcode = -EFAULT; + goto out_err; + } + } else if (cmd & IOC_OUT) { + memset(kdata, 0, usize); + } + + retcode = func(hpriv, kdata); + + if (cmd & IOC_OUT) + if (copy_to_user((void __user *)arg, kdata, usize)) + retcode = -EFAULT; + +out_err: + if (retcode) + dev_dbg(hdev->dev, + "error in ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", + task_pid_nr(current), cmd, nr); + + if (kdata != stack_kdata) + kfree(kdata); + + return retcode; +} diff --git a/drivers/misc/habanalabs/hw_queue.c b/drivers/misc/habanalabs/hw_queue.c new file mode 100644 index 000000000000..67bece26417c --- /dev/null +++ b/drivers/misc/habanalabs/hw_queue.c @@ -0,0 +1,635 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#include <linux/slab.h> + +/* + * hl_queue_add_ptr - add to pi or ci and checks if it wraps around + * + * @ptr: the current pi/ci value + * @val: the amount to add + * + * Add val to ptr. It can go until twice the queue length. + */ +inline u32 hl_hw_queue_add_ptr(u32 ptr, u16 val) +{ + ptr += val; + ptr &= ((HL_QUEUE_LENGTH << 1) - 1); + return ptr; +} + +static inline int queue_free_slots(struct hl_hw_queue *q, u32 queue_len) +{ + int delta = (q->pi - q->ci); + + if (delta >= 0) + return (queue_len - delta); + else + return (abs(delta) - queue_len); +} + +void hl_int_hw_queue_update_ci(struct hl_cs *cs) +{ + struct hl_device *hdev = cs->ctx->hdev; + struct hl_hw_queue *q; + int i; + + hdev->asic_funcs->hw_queues_lock(hdev); + + if (hdev->disabled) + goto out; + + q = &hdev->kernel_queues[0]; + for (i = 0 ; i < HL_MAX_QUEUES ; i++, q++) { + if (q->queue_type == QUEUE_TYPE_INT) { + q->ci += cs->jobs_in_queue_cnt[i]; + q->ci &= ((q->int_queue_len << 1) - 1); + } + } + +out: + hdev->asic_funcs->hw_queues_unlock(hdev); +} + +/* + * ext_queue_submit_bd - Submit a buffer descriptor to an external queue + * + * @hdev: pointer to habanalabs device structure + * @q: pointer to habanalabs queue structure + * @ctl: BD's control word + * @len: BD's length + * @ptr: BD's pointer + * + * This function assumes there is enough space on the queue to submit a new + * BD to it. It initializes the next BD and calls the device specific + * function to set the pi (and doorbell) + * + * This function must be called when the scheduler mutex is taken + * + */ +static void ext_queue_submit_bd(struct hl_device *hdev, struct hl_hw_queue *q, + u32 ctl, u32 len, u64 ptr) +{ + struct hl_bd *bd; + + bd = (struct hl_bd *) (uintptr_t) q->kernel_address; + bd += hl_pi_2_offset(q->pi); + bd->ctl = __cpu_to_le32(ctl); + bd->len = __cpu_to_le32(len); + bd->ptr = __cpu_to_le64(ptr + hdev->asic_prop.host_phys_base_address); + + q->pi = hl_queue_inc_ptr(q->pi); + hdev->asic_funcs->ring_doorbell(hdev, q->hw_queue_id, q->pi); +} + +/* + * ext_queue_sanity_checks - perform some sanity checks on external queue + * + * @hdev : pointer to hl_device structure + * @q : pointer to hl_hw_queue structure + * @num_of_entries : how many entries to check for space + * @reserve_cq_entry : whether to reserve an entry in the cq + * + * H/W queues spinlock should be taken before calling this function + * + * Perform the following: + * - Make sure we have enough space in the h/w queue + * - Make sure we have enough space in the completion queue + * - Reserve space in the completion queue (needs to be reversed if there + * is a failure down the road before the actual submission of work). Only + * do this action if reserve_cq_entry is true + * + */ +static int ext_queue_sanity_checks(struct hl_device *hdev, + struct hl_hw_queue *q, int num_of_entries, + bool reserve_cq_entry) +{ + atomic_t *free_slots = + &hdev->completion_queue[q->hw_queue_id].free_slots_cnt; + int free_slots_cnt; + + /* Check we have enough space in the queue */ + free_slots_cnt = queue_free_slots(q, HL_QUEUE_LENGTH); + + if (free_slots_cnt < num_of_entries) { + dev_dbg(hdev->dev, "Queue %d doesn't have room for %d CBs\n", + q->hw_queue_id, num_of_entries); + return -EAGAIN; + } + + if (reserve_cq_entry) { + /* + * Check we have enough space in the completion queue + * Add -1 to counter (decrement) unless counter was already 0 + * In that case, CQ is full so we can't submit a new CB because + * we won't get ack on its completion + * atomic_add_unless will return 0 if counter was already 0 + */ + if (atomic_add_negative(num_of_entries * -1, free_slots)) { + dev_dbg(hdev->dev, "No space for %d on CQ %d\n", + num_of_entries, q->hw_queue_id); + atomic_add(num_of_entries, free_slots); + return -EAGAIN; + } + } + + return 0; +} + +/* + * int_queue_sanity_checks - perform some sanity checks on internal queue + * + * @hdev : pointer to hl_device structure + * @q : pointer to hl_hw_queue structure + * @num_of_entries : how many entries to check for space + * + * H/W queues spinlock should be taken before calling this function + * + * Perform the following: + * - Make sure we have enough space in the h/w queue + * + */ +static int int_queue_sanity_checks(struct hl_device *hdev, + struct hl_hw_queue *q, + int num_of_entries) +{ + int free_slots_cnt; + + /* Check we have enough space in the queue */ + free_slots_cnt = queue_free_slots(q, q->int_queue_len); + + if (free_slots_cnt < num_of_entries) { + dev_dbg(hdev->dev, "Queue %d doesn't have room for %d CBs\n", + q->hw_queue_id, num_of_entries); + return -EAGAIN; + } + + return 0; +} + +/* + * hl_hw_queue_send_cb_no_cmpl - send a single CB (not a JOB) without completion + * + * @hdev: pointer to hl_device structure + * @hw_queue_id: Queue's type + * @cb_size: size of CB + * @cb_ptr: pointer to CB location + * + * This function sends a single CB, that must NOT generate a completion entry + * + */ +int hl_hw_queue_send_cb_no_cmpl(struct hl_device *hdev, u32 hw_queue_id, + u32 cb_size, u64 cb_ptr) +{ + struct hl_hw_queue *q = &hdev->kernel_queues[hw_queue_id]; + int rc; + + /* + * The CPU queue is a synchronous queue with an effective depth of + * a single entry (although it is allocated with room for multiple + * entries). Therefore, there is a different lock, called + * send_cpu_message_lock, that serializes accesses to the CPU queue. + * As a result, we don't need to lock the access to the entire H/W + * queues module when submitting a JOB to the CPU queue + */ + if (q->queue_type != QUEUE_TYPE_CPU) + hdev->asic_funcs->hw_queues_lock(hdev); + + if (hdev->disabled) { + rc = -EPERM; + goto out; + } + + rc = ext_queue_sanity_checks(hdev, q, 1, false); + if (rc) + goto out; + + ext_queue_submit_bd(hdev, q, 0, cb_size, cb_ptr); + +out: + if (q->queue_type != QUEUE_TYPE_CPU) + hdev->asic_funcs->hw_queues_unlock(hdev); + + return rc; +} + +/* + * ext_hw_queue_schedule_job - submit an JOB to an external queue + * + * @job: pointer to the job that needs to be submitted to the queue + * + * This function must be called when the scheduler mutex is taken + * + */ +static void ext_hw_queue_schedule_job(struct hl_cs_job *job) +{ + struct hl_device *hdev = job->cs->ctx->hdev; + struct hl_hw_queue *q = &hdev->kernel_queues[job->hw_queue_id]; + struct hl_cq_entry cq_pkt; + struct hl_cq *cq; + u64 cq_addr; + struct hl_cb *cb; + u32 ctl; + u32 len; + u64 ptr; + + /* + * Update the JOB ID inside the BD CTL so the device would know what + * to write in the completion queue + */ + ctl = ((q->pi << BD_CTL_SHADOW_INDEX_SHIFT) & BD_CTL_SHADOW_INDEX_MASK); + + cb = job->patched_cb; + len = job->job_cb_size; + ptr = cb->bus_address; + + cq_pkt.data = __cpu_to_le32( + ((q->pi << CQ_ENTRY_SHADOW_INDEX_SHIFT) + & CQ_ENTRY_SHADOW_INDEX_MASK) | + (1 << CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT) | + (1 << CQ_ENTRY_READY_SHIFT)); + + /* + * No need to protect pi_offset because scheduling to the + * H/W queues is done under the scheduler mutex + * + * No need to check if CQ is full because it was already + * checked in hl_queue_sanity_checks + */ + cq = &hdev->completion_queue[q->hw_queue_id]; + cq_addr = cq->bus_address + + hdev->asic_prop.host_phys_base_address; + cq_addr += cq->pi * sizeof(struct hl_cq_entry); + + hdev->asic_funcs->add_end_of_cb_packets(cb->kernel_address, len, + cq_addr, + __le32_to_cpu(cq_pkt.data), + q->hw_queue_id); + + q->shadow_queue[hl_pi_2_offset(q->pi)] = job; + + cq->pi = hl_cq_inc_ptr(cq->pi); + + ext_queue_submit_bd(hdev, q, ctl, len, ptr); +} + +/* + * int_hw_queue_schedule_job - submit an JOB to an internal queue + * + * @job: pointer to the job that needs to be submitted to the queue + * + * This function must be called when the scheduler mutex is taken + * + */ +static void int_hw_queue_schedule_job(struct hl_cs_job *job) +{ + struct hl_device *hdev = job->cs->ctx->hdev; + struct hl_hw_queue *q = &hdev->kernel_queues[job->hw_queue_id]; + struct hl_bd bd; + u64 *pi, *pbd = (u64 *) &bd; + + bd.ctl = 0; + bd.len = __cpu_to_le32(job->job_cb_size); + bd.ptr = __cpu_to_le64((u64) (uintptr_t) job->user_cb); + + pi = (u64 *) (uintptr_t) (q->kernel_address + + ((q->pi & (q->int_queue_len - 1)) * sizeof(bd))); + + pi[0] = pbd[0]; + pi[1] = pbd[1]; + + q->pi++; + q->pi &= ((q->int_queue_len << 1) - 1); + + /* Flush PQ entry write. Relevant only for specific ASICs */ + hdev->asic_funcs->flush_pq_write(hdev, pi, pbd[0]); + + hdev->asic_funcs->ring_doorbell(hdev, q->hw_queue_id, q->pi); +} + +/* + * hl_hw_queue_schedule_cs - schedule a command submission + * + * @job : pointer to the CS + * + */ +int hl_hw_queue_schedule_cs(struct hl_cs *cs) +{ + struct hl_device *hdev = cs->ctx->hdev; + struct hl_cs_job *job, *tmp; + struct hl_hw_queue *q; + int rc = 0, i, cq_cnt; + + hdev->asic_funcs->hw_queues_lock(hdev); + + if (hl_device_disabled_or_in_reset(hdev)) { + dev_err(hdev->dev, + "device is disabled or in reset, CS rejected!\n"); + rc = -EPERM; + goto out; + } + + q = &hdev->kernel_queues[0]; + /* This loop assumes all external queues are consecutive */ + for (i = 0, cq_cnt = 0 ; i < HL_MAX_QUEUES ; i++, q++) { + if (q->queue_type == QUEUE_TYPE_EXT) { + if (cs->jobs_in_queue_cnt[i]) { + rc = ext_queue_sanity_checks(hdev, q, + cs->jobs_in_queue_cnt[i], true); + if (rc) + goto unroll_cq_resv; + cq_cnt++; + } + } else if (q->queue_type == QUEUE_TYPE_INT) { + if (cs->jobs_in_queue_cnt[i]) { + rc = int_queue_sanity_checks(hdev, q, + cs->jobs_in_queue_cnt[i]); + if (rc) + goto unroll_cq_resv; + } + } + } + + spin_lock(&hdev->hw_queues_mirror_lock); + list_add_tail(&cs->mirror_node, &hdev->hw_queues_mirror_list); + + /* Queue TDR if the CS is the first entry and if timeout is wanted */ + if ((hdev->timeout_jiffies != MAX_SCHEDULE_TIMEOUT) && + (list_first_entry(&hdev->hw_queues_mirror_list, + struct hl_cs, mirror_node) == cs)) { + cs->tdr_active = true; + schedule_delayed_work(&cs->work_tdr, hdev->timeout_jiffies); + spin_unlock(&hdev->hw_queues_mirror_lock); + } else { + spin_unlock(&hdev->hw_queues_mirror_lock); + } + + list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node) { + if (job->ext_queue) + ext_hw_queue_schedule_job(job); + else + int_hw_queue_schedule_job(job); + } + + cs->submitted = true; + + goto out; + +unroll_cq_resv: + /* This loop assumes all external queues are consecutive */ + q = &hdev->kernel_queues[0]; + for (i = 0 ; (i < HL_MAX_QUEUES) && (cq_cnt > 0) ; i++, q++) { + if ((q->queue_type == QUEUE_TYPE_EXT) && + (cs->jobs_in_queue_cnt[i])) { + atomic_t *free_slots = + &hdev->completion_queue[i].free_slots_cnt; + atomic_add(cs->jobs_in_queue_cnt[i], free_slots); + cq_cnt--; + } + } + +out: + hdev->asic_funcs->hw_queues_unlock(hdev); + + return rc; +} + +/* + * hl_hw_queue_inc_ci_kernel - increment ci for kernel's queue + * + * @hdev: pointer to hl_device structure + * @hw_queue_id: which queue to increment its ci + */ +void hl_hw_queue_inc_ci_kernel(struct hl_device *hdev, u32 hw_queue_id) +{ + struct hl_hw_queue *q = &hdev->kernel_queues[hw_queue_id]; + + q->ci = hl_queue_inc_ptr(q->ci); +} + +static int ext_and_cpu_hw_queue_init(struct hl_device *hdev, + struct hl_hw_queue *q) +{ + void *p; + int rc; + + p = hdev->asic_funcs->dma_alloc_coherent(hdev, + HL_QUEUE_SIZE_IN_BYTES, + &q->bus_address, GFP_KERNEL | __GFP_ZERO); + if (!p) + return -ENOMEM; + + q->kernel_address = (u64) (uintptr_t) p; + + q->shadow_queue = kmalloc_array(HL_QUEUE_LENGTH, + sizeof(*q->shadow_queue), + GFP_KERNEL); + if (!q->shadow_queue) { + dev_err(hdev->dev, + "Failed to allocate shadow queue for H/W queue %d\n", + q->hw_queue_id); + rc = -ENOMEM; + goto free_queue; + } + + /* Make sure read/write pointers are initialized to start of queue */ + q->ci = 0; + q->pi = 0; + + return 0; + +free_queue: + hdev->asic_funcs->dma_free_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, + (void *) (uintptr_t) q->kernel_address, q->bus_address); + + return rc; +} + +static int int_hw_queue_init(struct hl_device *hdev, struct hl_hw_queue *q) +{ + void *p; + + p = hdev->asic_funcs->get_int_queue_base(hdev, q->hw_queue_id, + &q->bus_address, &q->int_queue_len); + if (!p) { + dev_err(hdev->dev, + "Failed to get base address for internal queue %d\n", + q->hw_queue_id); + return -EFAULT; + } + + q->kernel_address = (u64) (uintptr_t) p; + q->pi = 0; + q->ci = 0; + + return 0; +} + +static int cpu_hw_queue_init(struct hl_device *hdev, struct hl_hw_queue *q) +{ + return ext_and_cpu_hw_queue_init(hdev, q); +} + +static int ext_hw_queue_init(struct hl_device *hdev, struct hl_hw_queue *q) +{ + return ext_and_cpu_hw_queue_init(hdev, q); +} + +/* + * hw_queue_init - main initialization function for H/W queue object + * + * @hdev: pointer to hl_device device structure + * @q: pointer to hl_hw_queue queue structure + * @hw_queue_id: The id of the H/W queue + * + * Allocate dma-able memory for the queue and initialize fields + * Returns 0 on success + */ +static int hw_queue_init(struct hl_device *hdev, struct hl_hw_queue *q, + u32 hw_queue_id) +{ + int rc; + + BUILD_BUG_ON(HL_QUEUE_SIZE_IN_BYTES > HL_PAGE_SIZE); + + q->hw_queue_id = hw_queue_id; + + switch (q->queue_type) { + case QUEUE_TYPE_EXT: + rc = ext_hw_queue_init(hdev, q); + break; + + case QUEUE_TYPE_INT: + rc = int_hw_queue_init(hdev, q); + break; + + case QUEUE_TYPE_CPU: + rc = cpu_hw_queue_init(hdev, q); + break; + + case QUEUE_TYPE_NA: + q->valid = 0; + return 0; + + default: + dev_crit(hdev->dev, "wrong queue type %d during init\n", + q->queue_type); + rc = -EINVAL; + break; + } + + if (rc) + return rc; + + q->valid = 1; + + return 0; +} + +/* + * hw_queue_fini - destroy queue + * + * @hdev: pointer to hl_device device structure + * @q: pointer to hl_hw_queue queue structure + * + * Free the queue memory + */ +static void hw_queue_fini(struct hl_device *hdev, struct hl_hw_queue *q) +{ + if (!q->valid) + return; + + /* + * If we arrived here, there are no jobs waiting on this queue + * so we can safely remove it. + * This is because this function can only called when: + * 1. Either a context is deleted, which only can occur if all its + * jobs were finished + * 2. A context wasn't able to be created due to failure or timeout, + * which means there are no jobs on the queue yet + * + * The only exception are the queues of the kernel context, but + * if they are being destroyed, it means that the entire module is + * being removed. If the module is removed, it means there is no open + * user context. It also means that if a job was submitted by + * the kernel driver (e.g. context creation), the job itself was + * released by the kernel driver when a timeout occurred on its + * Completion. Thus, we don't need to release it again. + */ + + if (q->queue_type == QUEUE_TYPE_INT) + return; + + kfree(q->shadow_queue); + + hdev->asic_funcs->dma_free_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, + (void *) (uintptr_t) q->kernel_address, q->bus_address); +} + +int hl_hw_queues_create(struct hl_device *hdev) +{ + struct asic_fixed_properties *asic = &hdev->asic_prop; + struct hl_hw_queue *q; + int i, rc, q_ready_cnt; + + hdev->kernel_queues = kcalloc(HL_MAX_QUEUES, + sizeof(*hdev->kernel_queues), GFP_KERNEL); + + if (!hdev->kernel_queues) { + dev_err(hdev->dev, "Not enough memory for H/W queues\n"); + return -ENOMEM; + } + + /* Initialize the H/W queues */ + for (i = 0, q_ready_cnt = 0, q = hdev->kernel_queues; + i < HL_MAX_QUEUES ; i++, q_ready_cnt++, q++) { + + q->queue_type = asic->hw_queues_props[i].type; + rc = hw_queue_init(hdev, q, i); + if (rc) { + dev_err(hdev->dev, + "failed to initialize queue %d\n", i); + goto release_queues; + } + } + + return 0; + +release_queues: + for (i = 0, q = hdev->kernel_queues ; i < q_ready_cnt ; i++, q++) + hw_queue_fini(hdev, q); + + kfree(hdev->kernel_queues); + + return rc; +} + +void hl_hw_queues_destroy(struct hl_device *hdev) +{ + struct hl_hw_queue *q; + int i; + + for (i = 0, q = hdev->kernel_queues ; i < HL_MAX_QUEUES ; i++, q++) + hw_queue_fini(hdev, q); + + kfree(hdev->kernel_queues); +} + +void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset) +{ + struct hl_hw_queue *q; + int i; + + for (i = 0, q = hdev->kernel_queues ; i < HL_MAX_QUEUES ; i++, q++) { + if ((!q->valid) || + ((!hard_reset) && (q->queue_type == QUEUE_TYPE_CPU))) + continue; + q->pi = q->ci = 0; + } +} diff --git a/drivers/misc/habanalabs/hwmon.c b/drivers/misc/habanalabs/hwmon.c new file mode 100644 index 000000000000..77facd25c4a2 --- /dev/null +++ b/drivers/misc/habanalabs/hwmon.c @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#include <linux/pci.h> +#include <linux/hwmon.h> + +#define SENSORS_PKT_TIMEOUT 1000000 /* 1s */ +#define HWMON_NR_SENSOR_TYPES (hwmon_pwm + 1) + +int hl_build_hwmon_channel_info(struct hl_device *hdev, + struct armcp_sensor *sensors_arr) +{ + u32 counts[HWMON_NR_SENSOR_TYPES] = {0}; + u32 *sensors_by_type[HWMON_NR_SENSOR_TYPES] = {NULL}; + u32 sensors_by_type_next_index[HWMON_NR_SENSOR_TYPES] = {0}; + struct hwmon_channel_info **channels_info; + u32 num_sensors_for_type, num_active_sensor_types = 0, + arr_size = 0, *curr_arr; + enum hwmon_sensor_types type; + int rc, i, j; + + for (i = 0 ; i < ARMCP_MAX_SENSORS ; i++) { + type = __le32_to_cpu(sensors_arr[i].type); + + if ((type == 0) && (sensors_arr[i].flags == 0)) + break; + + if (type >= HWMON_NR_SENSOR_TYPES) { + dev_err(hdev->dev, + "Got wrong sensor type %d from device\n", type); + return -EINVAL; + } + + counts[type]++; + arr_size++; + } + + for (i = 0 ; i < HWMON_NR_SENSOR_TYPES ; i++) { + if (counts[i] == 0) + continue; + + num_sensors_for_type = counts[i] + 1; + curr_arr = kcalloc(num_sensors_for_type, sizeof(*curr_arr), + GFP_KERNEL); + if (!curr_arr) { + rc = -ENOMEM; + goto sensors_type_err; + } + + num_active_sensor_types++; + sensors_by_type[i] = curr_arr; + } + + for (i = 0 ; i < arr_size ; i++) { + type = __le32_to_cpu(sensors_arr[i].type); + curr_arr = sensors_by_type[type]; + curr_arr[sensors_by_type_next_index[type]++] = + __le32_to_cpu(sensors_arr[i].flags); + } + + channels_info = kcalloc(num_active_sensor_types + 1, + sizeof(*channels_info), GFP_KERNEL); + if (!channels_info) { + rc = -ENOMEM; + goto channels_info_array_err; + } + + for (i = 0 ; i < num_active_sensor_types ; i++) { + channels_info[i] = kzalloc(sizeof(*channels_info[i]), + GFP_KERNEL); + if (!channels_info[i]) { + rc = -ENOMEM; + goto channel_info_err; + } + } + + for (i = 0, j = 0 ; i < HWMON_NR_SENSOR_TYPES ; i++) { + if (!sensors_by_type[i]) + continue; + + channels_info[j]->type = i; + channels_info[j]->config = sensors_by_type[i]; + j++; + } + + hdev->hl_chip_info->info = + (const struct hwmon_channel_info **)channels_info; + + return 0; + +channel_info_err: + for (i = 0 ; i < num_active_sensor_types ; i++) + if (channels_info[i]) { + kfree(channels_info[i]->config); + kfree(channels_info[i]); + } + kfree(channels_info); +channels_info_array_err: +sensors_type_err: + for (i = 0 ; i < HWMON_NR_SENSOR_TYPES ; i++) + kfree(sensors_by_type[i]); + + return rc; +} + +static int hl_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_max: + case hwmon_temp_crit: + case hwmon_temp_max_hyst: + case hwmon_temp_crit_hyst: + break; + default: + return -EINVAL; + } + + *val = hl_get_temperature(hdev, channel, attr); + break; + case hwmon_in: + switch (attr) { + case hwmon_in_input: + case hwmon_in_min: + case hwmon_in_max: + break; + default: + return -EINVAL; + } + + *val = hl_get_voltage(hdev, channel, attr); + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_min: + case hwmon_curr_max: + break; + default: + return -EINVAL; + } + + *val = hl_get_current(hdev, channel, attr); + break; + case hwmon_fan: + switch (attr) { + case hwmon_fan_input: + case hwmon_fan_min: + case hwmon_fan_max: + break; + default: + return -EINVAL; + } + *val = hl_get_fan_speed(hdev, channel, attr); + break; + case hwmon_pwm: + switch (attr) { + case hwmon_pwm_input: + case hwmon_pwm_enable: + break; + default: + return -EINVAL; + } + *val = hl_get_pwm_info(hdev, channel, attr); + break; + default: + return -EINVAL; + } + return 0; +} + +static int hl_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + switch (type) { + case hwmon_pwm: + switch (attr) { + case hwmon_pwm_input: + case hwmon_pwm_enable: + break; + default: + return -EINVAL; + } + hl_set_pwm_info(hdev, channel, attr, val); + break; + default: + return -EINVAL; + } + return 0; +} + +static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_max: + case hwmon_temp_max_hyst: + case hwmon_temp_crit: + case hwmon_temp_crit_hyst: + return 0444; + } + break; + case hwmon_in: + switch (attr) { + case hwmon_in_input: + case hwmon_in_min: + case hwmon_in_max: + return 0444; + } + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_min: + case hwmon_curr_max: + return 0444; + } + break; + case hwmon_fan: + switch (attr) { + case hwmon_fan_input: + case hwmon_fan_min: + case hwmon_fan_max: + return 0444; + } + break; + case hwmon_pwm: + switch (attr) { + case hwmon_pwm_input: + case hwmon_pwm_enable: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_ops hl_hwmon_ops = { + .is_visible = hl_is_visible, + .read = hl_read, + .write = hl_write +}; + +long hl_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_TEMPERATURE_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to get temperature from sensor %d, error %d\n", + sensor_index, rc); + result = 0; + } + + return result; +} + +long hl_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_VOLTAGE_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to get voltage from sensor %d, error %d\n", + sensor_index, rc); + result = 0; + } + + return result; +} + +long hl_get_current(struct hl_device *hdev, int sensor_index, u32 attr) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_CURRENT_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to get current from sensor %d, error %d\n", + sensor_index, rc); + result = 0; + } + + return result; +} + +long hl_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_FAN_SPEED_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to get fan speed from sensor %d, error %d\n", + sensor_index, rc); + result = 0; + } + + return result; +} + +long hl_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_PWM_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to get pwm info from sensor %d, error %d\n", + sensor_index, rc); + result = 0; + } + + return result; +} + +void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, + long value) +{ + struct armcp_packet pkt; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_PWM_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + pkt.value = __cpu_to_le64(value); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, NULL); + + if (rc) + dev_err(hdev->dev, + "Failed to set pwm info to sensor %d, error %d\n", + sensor_index, rc); +} + +int hl_hwmon_init(struct hl_device *hdev) +{ + struct device *dev = hdev->pdev ? &hdev->pdev->dev : hdev->dev; + int rc; + + if ((hdev->hwmon_initialized) || !(hdev->fw_loading)) + return 0; + + if (hdev->hl_chip_info->info) { + hdev->hl_chip_info->ops = &hl_hwmon_ops; + + hdev->hwmon_dev = hwmon_device_register_with_info(dev, + "habanalabs", hdev, hdev->hl_chip_info, NULL); + if (IS_ERR(hdev->hwmon_dev)) { + rc = PTR_ERR(hdev->hwmon_dev); + dev_err(hdev->dev, + "Unable to register hwmon device: %d\n", rc); + return rc; + } + + dev_info(hdev->dev, "%s: add sensors information\n", + dev_name(hdev->hwmon_dev)); + + hdev->hwmon_initialized = true; + } else { + dev_info(hdev->dev, "no available sensors\n"); + } + + return 0; +} + +void hl_hwmon_fini(struct hl_device *hdev) +{ + if (!hdev->hwmon_initialized) + return; + + hwmon_device_unregister(hdev->hwmon_dev); +} diff --git a/drivers/misc/habanalabs/include/armcp_if.h b/drivers/misc/habanalabs/include/armcp_if.h new file mode 100644 index 000000000000..9dddb917e72c --- /dev/null +++ b/drivers/misc/habanalabs/include/armcp_if.h @@ -0,0 +1,335 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ARMCP_IF_H +#define ARMCP_IF_H + +#include <linux/types.h> + +/* + * EVENT QUEUE + */ + +struct hl_eq_header { + __le32 reserved; + __le32 ctl; +}; + +struct hl_eq_entry { + struct hl_eq_header hdr; + __le64 data[7]; +}; + +#define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) + +#define EQ_CTL_READY_SHIFT 31 +#define EQ_CTL_READY_MASK 0x80000000 + +#define EQ_CTL_EVENT_TYPE_SHIFT 16 +#define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000 + +#define EVENT_QUEUE_MSIX_IDX 5 + +enum pq_init_status { + PQ_INIT_STATUS_NA = 0, + PQ_INIT_STATUS_READY_FOR_CP, + PQ_INIT_STATUS_READY_FOR_HOST +}; + +/* + * ArmCP Primary Queue Packets + * + * During normal operation, KMD needs to send various messages to ArmCP, + * usually either to SET some value into a H/W periphery or to GET the current + * value of some H/W periphery. For example, SET the frequency of MME/TPC and + * GET the value of the thermal sensor. + * + * These messages can be initiated either by the User application or by KMD + * itself, e.g. power management code. In either case, the communication from + * KMD to ArmCP will *always* be in synchronous mode, meaning that KMD will + * send a single message and poll until the message was acknowledged and the + * results are ready (if results are needed). + * + * This means that only a single message can be sent at a time and KMD must + * wait for its result before sending the next message. Having said that, + * because these are control messages which are sent in a relatively low + * frequency, this limitation seems acceptable. It's important to note that + * in case of multiple devices, messages to different devices *can* be sent + * at the same time. + * + * The message, inputs/outputs (if relevant) and fence object will be located + * on the device DDR at an address that will be determined by KMD. During + * device initialization phase, KMD will pass to ArmCP that address. Most of + * the message types will contain inputs/outputs inside the message itself. + * The common part of each message will contain the opcode of the message (its + * type) and a field representing a fence object. + * + * When KMD wishes to send a message to ArmCP, it will write the message + * contents to the device DDR, clear the fence object and then write the + * value 484 to the mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR register to issue + * the 484 interrupt-id to the ARM core. + * + * Upon receiving the 484 interrupt-id, ArmCP will read the message from the + * DDR. In case the message is a SET operation, ArmCP will first perform the + * operation and then write to the fence object on the device DDR. In case the + * message is a GET operation, ArmCP will first fill the results section on the + * device DDR and then write to the fence object. If an error occurred, ArmCP + * will fill the rc field with the right error code. + * + * In the meantime, KMD will poll on the fence object. Once KMD sees that the + * fence object is signaled, it will read the results from the device DDR + * (if relevant) and resume the code execution in KMD. + * + * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 + * so the value being put by the KMD matches the value read by ArmCP + * + * Non-QMAN packets should be limited to values 1 through (2^8 - 1) + * + * Detailed description: + * + * ARMCP_PACKET_DISABLE_PCI_ACCESS - + * After receiving this packet the embedded CPU must NOT issue PCI + * transactions (read/write) towards the Host CPU. This also include + * sending MSI-X interrupts. + * This packet is usually sent before the device is moved to D3Hot state. + * + * ARMCP_PACKET_ENABLE_PCI_ACCESS - + * After receiving this packet the embedded CPU is allowed to issue PCI + * transactions towards the Host CPU, including sending MSI-X interrupts. + * This packet is usually send after the device is moved to D0 state. + * + * ARMCP_PACKET_TEMPERATURE_GET - + * Fetch the current temperature / Max / Max Hyst / Critical / + * Critical Hyst of a specified thermal sensor. The packet's + * arguments specify the desired sensor and the field to get. + * + * ARMCP_PACKET_VOLTAGE_GET - + * Fetch the voltage / Max / Min of a specified sensor. The packet's + * arguments specify the sensor and type. + * + * ARMCP_PACKET_CURRENT_GET - + * Fetch the current / Max / Min of a specified sensor. The packet's + * arguments specify the sensor and type. + * + * ARMCP_PACKET_FAN_SPEED_GET - + * Fetch the speed / Max / Min of a specified fan. The packet's + * arguments specify the sensor and type. + * + * ARMCP_PACKET_PWM_GET - + * Fetch the pwm value / mode of a specified pwm. The packet's + * arguments specify the sensor and type. + * + * ARMCP_PACKET_PWM_SET - + * Set the pwm value / mode of a specified pwm. The packet's + * arguments specify the sensor, type and value. + * + * ARMCP_PACKET_FREQUENCY_SET - + * Set the frequency of a specified PLL. The packet's arguments specify + * the PLL and the desired frequency. The actual frequency in the device + * might differ from the requested frequency. + * + * ARMCP_PACKET_FREQUENCY_GET - + * Fetch the frequency of a specified PLL. The packet's arguments specify + * the PLL. + * + * ARMCP_PACKET_LED_SET - + * Set the state of a specified led. The packet's arguments + * specify the led and the desired state. + * + * ARMCP_PACKET_I2C_WR - + * Write 32-bit value to I2C device. The packet's arguments specify the + * I2C bus, address and value. + * + * ARMCP_PACKET_I2C_RD - + * Read 32-bit value from I2C device. The packet's arguments specify the + * I2C bus and address. + * + * ARMCP_PACKET_INFO_GET - + * Fetch information from the device as specified in the packet's + * structure. KMD passes the max size it allows the ArmCP to write to + * the structure, to prevent data corruption in case of mismatched + * KMD/FW versions. + * + * ARMCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed + * + * ARMCP_PACKET_UNMASK_RAZWI_IRQ - + * Unmask the given IRQ. The IRQ number is specified in the value field. + * The packet is sent after receiving an interrupt and printing its + * relevant information. + * + * ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - + * Unmask the given IRQs. The IRQs numbers are specified in an array right + * after the armcp_packet structure, where its first element is the array + * length. The packet is sent after a soft reset was done in order to + * handle any interrupts that were sent during the reset process. + * + * ARMCP_PACKET_TEST - + * Test packet for ArmCP connectivity. The CPU will put the fence value + * in the result field. + * + * ARMCP_PACKET_FREQUENCY_CURR_GET - + * Fetch the current frequency of a specified PLL. The packet's arguments + * specify the PLL. + * + * ARMCP_PACKET_MAX_POWER_GET - + * Fetch the maximal power of the device. + * + * ARMCP_PACKET_MAX_POWER_SET - + * Set the maximal power of the device. The packet's arguments specify + * the power. + * + * ARMCP_PACKET_EEPROM_DATA_GET - + * Get EEPROM data from the ArmCP kernel. The buffer is specified in the + * addr field. The CPU will put the returned data size in the result + * field. In addition, KMD passes the max size it allows the ArmCP to + * write to the structure, to prevent data corruption in case of + * mismatched KMD/FW versions. + * + */ + +enum armcp_packet_id { + ARMCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ + ARMCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ + ARMCP_PACKET_TEMPERATURE_GET, /* sysfs */ + ARMCP_PACKET_VOLTAGE_GET, /* sysfs */ + ARMCP_PACKET_CURRENT_GET, /* sysfs */ + ARMCP_PACKET_FAN_SPEED_GET, /* sysfs */ + ARMCP_PACKET_PWM_GET, /* sysfs */ + ARMCP_PACKET_PWM_SET, /* sysfs */ + ARMCP_PACKET_FREQUENCY_SET, /* sysfs */ + ARMCP_PACKET_FREQUENCY_GET, /* sysfs */ + ARMCP_PACKET_LED_SET, /* debugfs */ + ARMCP_PACKET_I2C_WR, /* debugfs */ + ARMCP_PACKET_I2C_RD, /* debugfs */ + ARMCP_PACKET_INFO_GET, /* IOCTL */ + ARMCP_PACKET_FLASH_PROGRAM_REMOVED, + ARMCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ + ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ + ARMCP_PACKET_TEST, /* internal */ + ARMCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ + ARMCP_PACKET_MAX_POWER_GET, /* sysfs */ + ARMCP_PACKET_MAX_POWER_SET, /* sysfs */ + ARMCP_PACKET_EEPROM_DATA_GET, /* sysfs */ +}; + +#define ARMCP_PACKET_FENCE_VAL 0xFE8CE7A5 + +#define ARMCP_PKT_CTL_RC_SHIFT 12 +#define ARMCP_PKT_CTL_RC_MASK 0x0000F000 + +#define ARMCP_PKT_CTL_OPCODE_SHIFT 16 +#define ARMCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 + +struct armcp_packet { + union { + __le64 value; /* For SET packets */ + __le64 result; /* For GET packets */ + __le64 addr; /* For PQ */ + }; + + __le32 ctl; + + __le32 fence; /* Signal to KMD that message is completed */ + + union { + struct {/* For temperature/current/voltage/fan/pwm get/set */ + __le16 sensor_index; + __le16 type; + }; + + struct { /* For I2C read/write */ + __u8 i2c_bus; + __u8 i2c_addr; + __u8 i2c_reg; + __u8 pad; /* unused */ + }; + + /* For frequency get/set */ + __le32 pll_index; + + /* For led set */ + __le32 led_index; + + /* For get Armcp info/EEPROM data */ + __le32 data_max_size; + }; +}; + +struct armcp_unmask_irq_arr_packet { + struct armcp_packet armcp_pkt; + __le32 length; + __le32 irqs[0]; +}; + +enum armcp_packet_rc { + armcp_packet_success, + armcp_packet_invalid, + armcp_packet_fault +}; + +enum armcp_temp_type { + armcp_temp_input, + armcp_temp_max = 6, + armcp_temp_max_hyst, + armcp_temp_crit, + armcp_temp_crit_hyst +}; + +enum armcp_in_attributes { + armcp_in_input, + armcp_in_min, + armcp_in_max +}; + +enum armcp_curr_attributes { + armcp_curr_input, + armcp_curr_min, + armcp_curr_max +}; + +enum armcp_fan_attributes { + armcp_fan_input, + armcp_fan_min = 2, + armcp_fan_max +}; + +enum armcp_pwm_attributes { + armcp_pwm_input, + armcp_pwm_enable +}; + +/* Event Queue Packets */ + +struct eq_generic_event { + __le64 data[7]; +}; + +/* + * ArmCP info + */ + +#define VERSION_MAX_LEN 128 +#define ARMCP_MAX_SENSORS 128 + +struct armcp_sensor { + __le32 type; + __le32 flags; +}; + +struct armcp_info { + struct armcp_sensor sensors[ARMCP_MAX_SENSORS]; + __u8 kernel_version[VERSION_MAX_LEN]; + __le32 reserved[3]; + __le32 cpld_version; + __le32 infineon_version; + __u8 fuse_version[VERSION_MAX_LEN]; + __u8 thermal_version[VERSION_MAX_LEN]; + __u8 armcp_version[VERSION_MAX_LEN]; + __le64 dram_size; +}; + +#endif /* ARMCP_IF_H */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h new file mode 100644 index 000000000000..2cf5c46b6e8e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_ +#define ASIC_REG_CPU_CA53_CFG_MASKS_H_ + +/* + ***************************************** + * CPU_CA53_CFG (Prototype: CA53_CFG) + ***************************************** + */ + +/* CPU_CA53_CFG_ARM_CFG */ +#define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0 +#define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3 +#define CPU_CA53_CFG_ARM_CFG_END_SHIFT 4 +#define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30 +#define CPU_CA53_CFG_ARM_CFG_TE_SHIFT 8 +#define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300 +#define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT 12 +#define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000 + +/* CPU_CA53_CFG_RST_ADDR_LSB */ +#define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0 +#define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF + +/* CPU_CA53_CFG_RST_ADDR_MSB */ +#define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0 +#define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF + +/* CPU_CA53_CFG_ARM_RST_CONTROL */ +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 + +/* CPU_CA53_CFG_ARM_AFFINITY */ +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT 0 +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK 0xFF +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT 8 +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK 0xFF00 + +/* CPU_CA53_CFG_ARM_DISABLE */ +#define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT 0 +#define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK 0x3 +#define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT 4 +#define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK 0x30 +#define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT 8 +#define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK 0x100 +#define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT 9 +#define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK 0x200 + +/* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */ +#define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT 0 +#define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK 0x3FFFFF + +/* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */ +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT 0 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK 0x3 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT 4 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK 0x30 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT 8 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK 0x300 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT 12 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK 0x3000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT 16 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK 0x30000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK 0x300000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT 24 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK 0x3000000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT 31 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK 0x80000000 + +/* CPU_CA53_CFG_ARM_PWR_MNG */ +#define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT 0 +#define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK 0x1 +#define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT 1 +#define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK 0x2 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT 2 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK 0x4 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT 3 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK 0x8 +#define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT 4 +#define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK 0x30 +#define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_SHIFT 8 +#define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_MASK 0x300 +#define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_SHIFT 12 +#define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_MASK 0x3000 + +/* CPU_CA53_CFG_ARB_DBG_ROM_ADDR */ +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_SHIFT 0 +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_MASK 0xFFFFFFF +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_SHIFT 31 +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_MASK 0x80000000 + +/* CPU_CA53_CFG_ARM_DBG_MODES */ +#define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_SHIFT 0 +#define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK 0x3 +#define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_SHIFT 4 +#define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_MASK 0x30 +#define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_SHIFT 8 +#define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_MASK 0x300 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_SHIFT 12 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_MASK 0x3000 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_SHIFT 16 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_MASK 0x30000 + +/* CPU_CA53_CFG_ARM_PWR_STAT_0 */ +#define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_SHIFT 0 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_MASK 0x1 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_SHIFT 1 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_MASK 0x2 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_SHIFT 4 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_MASK 0x30 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_SHIFT 8 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_MASK 0x300 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_SHIFT 12 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_MASK 0x1000 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_SHIFT 13 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_MASK 0x2000 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_SHIFT 16 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_MASK 0x30000 + +/* CPU_CA53_CFG_ARM_PWR_STAT_1 */ +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_SHIFT 0 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK 0x3 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_SHIFT 4 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_MASK 0x30 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_SHIFT 8 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_MASK 0x300 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_SHIFT 12 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_MASK 0x3000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_SHIFT 16 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_MASK 0x30000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_SHIFT 20 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_MASK 0x300000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_SHIFT 24 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_MASK 0x1000000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_SHIFT 25 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_MASK 0x2000000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_SHIFT 26 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_MASK 0x4000000 + +/* CPU_CA53_CFG_ARM_DBG_STATUS */ +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_SHIFT 0 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK 0x3 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_SHIFT 4 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_MASK 0x30 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_SHIFT 8 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_MASK 0x300 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_SHIFT 12 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_MASK 0x3000 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_SHIFT 16 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_MASK 0x30000 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_MASK 0x300000 + +/* CPU_CA53_CFG_ARM_MEM_ATTR */ +#define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_SHIFT 0 +#define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_MASK 0xFF +#define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_SHIFT 8 +#define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_MASK 0xFF00 +#define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_SHIFT 16 +#define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_MASK 0x10000 +#define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_SHIFT 20 +#define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_MASK 0x100000 + +/* CPU_CA53_CFG_ARM_PMU */ +#define CPU_CA53_CFG_ARM_PMU_EVENT_SHIFT 0 +#define CPU_CA53_CFG_ARM_PMU_EVENT_MASK 0x3FFFFFFF + +#endif /* ASIC_REG_CPU_CA53_CFG_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h new file mode 100644 index 000000000000..840ccffa1081 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_ +#define ASIC_REG_CPU_CA53_CFG_REGS_H_ + +/* + ***************************************** + * CPU_CA53_CFG (Prototype: CA53_CFG) + ***************************************** + */ + +#define mmCPU_CA53_CFG_ARM_CFG 0x441100 + +#define mmCPU_CA53_CFG_RST_ADDR_LSB_0 0x441104 + +#define mmCPU_CA53_CFG_RST_ADDR_LSB_1 0x441108 + +#define mmCPU_CA53_CFG_RST_ADDR_MSB_0 0x441114 + +#define mmCPU_CA53_CFG_RST_ADDR_MSB_1 0x441118 + +#define mmCPU_CA53_CFG_ARM_RST_CONTROL 0x441124 + +#define mmCPU_CA53_CFG_ARM_AFFINITY 0x441128 + +#define mmCPU_CA53_CFG_ARM_DISABLE 0x44112C + +#define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE 0x441130 + +#define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG 0x441134 + +#define mmCPU_CA53_CFG_ARM_PWR_MNG 0x441138 + +#define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR 0x44113C + +#define mmCPU_CA53_CFG_ARM_DBG_MODES 0x441140 + +#define mmCPU_CA53_CFG_ARM_PWR_STAT_0 0x441200 + +#define mmCPU_CA53_CFG_ARM_PWR_STAT_1 0x441204 + +#define mmCPU_CA53_CFG_ARM_DBG_STATUS 0x441208 + +#define mmCPU_CA53_CFG_ARM_MEM_ATTR 0x44120C + +#define mmCPU_CA53_CFG_ARM_PMU_0 0x441210 + +#define mmCPU_CA53_CFG_ARM_PMU_1 0x441214 + +#endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000000..f23cb3e41c30 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_PF_PQ_PI 0x442100 + +#define mmCPU_IF_ARUSER_OVR 0x442104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x442108 + +#define mmCPU_IF_AWUSER_OVR 0x44210C + +#define mmCPU_IF_AWUSER_OVR_EN 0x442110 + +#define mmCPU_IF_AXCACHE_OVR 0x442114 + +#define mmCPU_IF_LOCK_OVR 0x442118 + +#define mmCPU_IF_PROT_OVR 0x44211C + +#define mmCPU_IF_MAX_OUTSTANDING 0x442120 + +#define mmCPU_IF_EARLY_BRESP_EN 0x442124 + +#define mmCPU_IF_FORCE_RSP_OK 0x442128 + +#define mmCPU_IF_CPU_MSB_ADDR 0x44212C + +#define mmCPU_IF_AXI_SPLIT_INTR 0x442130 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h new file mode 100644 index 000000000000..8fc97f838ada --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_PLL_REGS_H_ +#define ASIC_REG_CPU_PLL_REGS_H_ + +/* + ***************************************** + * CPU_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmCPU_PLL_NR 0x4A2100 + +#define mmCPU_PLL_NF 0x4A2104 + +#define mmCPU_PLL_OD 0x4A2108 + +#define mmCPU_PLL_NB 0x4A210C + +#define mmCPU_PLL_CFG 0x4A2110 + +#define mmCPU_PLL_LOSE_MASK 0x4A2120 + +#define mmCPU_PLL_LOCK_INTR 0x4A2128 + +#define mmCPU_PLL_LOCK_BYPASS 0x4A212C + +#define mmCPU_PLL_DATA_CHNG 0x4A2130 + +#define mmCPU_PLL_RST 0x4A2134 + +#define mmCPU_PLL_SLIP_WD_CNTR 0x4A2150 + +#define mmCPU_PLL_DIV_FACTOR_0 0x4A2200 + +#define mmCPU_PLL_DIV_FACTOR_1 0x4A2204 + +#define mmCPU_PLL_DIV_FACTOR_2 0x4A2208 + +#define mmCPU_PLL_DIV_FACTOR_3 0x4A220C + +#define mmCPU_PLL_DIV_FACTOR_CMD_0 0x4A2220 + +#define mmCPU_PLL_DIV_FACTOR_CMD_1 0x4A2224 + +#define mmCPU_PLL_DIV_FACTOR_CMD_2 0x4A2228 + +#define mmCPU_PLL_DIV_FACTOR_CMD_3 0x4A222C + +#define mmCPU_PLL_DIV_SEL_0 0x4A2280 + +#define mmCPU_PLL_DIV_SEL_1 0x4A2284 + +#define mmCPU_PLL_DIV_SEL_2 0x4A2288 + +#define mmCPU_PLL_DIV_SEL_3 0x4A228C + +#define mmCPU_PLL_DIV_EN_0 0x4A22A0 + +#define mmCPU_PLL_DIV_EN_1 0x4A22A4 + +#define mmCPU_PLL_DIV_EN_2 0x4A22A8 + +#define mmCPU_PLL_DIV_EN_3 0x4A22AC + +#define mmCPU_PLL_DIV_FACTOR_BUSY_0 0x4A22C0 + +#define mmCPU_PLL_DIV_FACTOR_BUSY_1 0x4A22C4 + +#define mmCPU_PLL_DIV_FACTOR_BUSY_2 0x4A22C8 + +#define mmCPU_PLL_DIV_FACTOR_BUSY_3 0x4A22CC + +#define mmCPU_PLL_CLK_GATER 0x4A2300 + +#define mmCPU_PLL_CLK_RLX_0 0x4A2310 + +#define mmCPU_PLL_CLK_RLX_1 0x4A2314 + +#define mmCPU_PLL_CLK_RLX_2 0x4A2318 + +#define mmCPU_PLL_CLK_RLX_3 0x4A231C + +#define mmCPU_PLL_REF_CNTR_PERIOD 0x4A2400 + +#define mmCPU_PLL_REF_LOW_THRESHOLD 0x4A2410 + +#define mmCPU_PLL_REF_HIGH_THRESHOLD 0x4A2420 + +#define mmCPU_PLL_PLL_NOT_STABLE 0x4A2430 + +#define mmCPU_PLL_FREQ_CALC_EN 0x4A2440 + +#endif /* ASIC_REG_CPU_PLL_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h new file mode 100644 index 000000000000..61c8cd9ce58b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_0_REGS_H_ +#define ASIC_REG_DMA_CH_0_REGS_H_ + +/* + ***************************************** + * DMA_CH_0 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_0_CFG0 0x401000 + +#define mmDMA_CH_0_CFG1 0x401004 + +#define mmDMA_CH_0_ERRMSG_ADDR_LO 0x401008 + +#define mmDMA_CH_0_ERRMSG_ADDR_HI 0x40100C + +#define mmDMA_CH_0_ERRMSG_WDATA 0x401010 + +#define mmDMA_CH_0_RD_COMP_ADDR_LO 0x401014 + +#define mmDMA_CH_0_RD_COMP_ADDR_HI 0x401018 + +#define mmDMA_CH_0_RD_COMP_WDATA 0x40101C + +#define mmDMA_CH_0_WR_COMP_ADDR_LO 0x401020 + +#define mmDMA_CH_0_WR_COMP_ADDR_HI 0x401024 + +#define mmDMA_CH_0_WR_COMP_WDATA 0x401028 + +#define mmDMA_CH_0_LDMA_SRC_ADDR_LO 0x40102C + +#define mmDMA_CH_0_LDMA_SRC_ADDR_HI 0x401030 + +#define mmDMA_CH_0_LDMA_DST_ADDR_LO 0x401034 + +#define mmDMA_CH_0_LDMA_DST_ADDR_HI 0x401038 + +#define mmDMA_CH_0_LDMA_TSIZE 0x40103C + +#define mmDMA_CH_0_COMIT_TRANSFER 0x401040 + +#define mmDMA_CH_0_STS0 0x401044 + +#define mmDMA_CH_0_STS1 0x401048 + +#define mmDMA_CH_0_STS2 0x40104C + +#define mmDMA_CH_0_STS3 0x401050 + +#define mmDMA_CH_0_STS4 0x401054 + +#define mmDMA_CH_0_SRC_ADDR_LO_STS 0x401058 + +#define mmDMA_CH_0_SRC_ADDR_HI_STS 0x40105C + +#define mmDMA_CH_0_SRC_TSIZE_STS 0x401060 + +#define mmDMA_CH_0_DST_ADDR_LO_STS 0x401064 + +#define mmDMA_CH_0_DST_ADDR_HI_STS 0x401068 + +#define mmDMA_CH_0_DST_TSIZE_STS 0x40106C + +#define mmDMA_CH_0_RD_RATE_LIM_EN 0x401070 + +#define mmDMA_CH_0_RD_RATE_LIM_RST_TOKEN 0x401074 + +#define mmDMA_CH_0_RD_RATE_LIM_SAT 0x401078 + +#define mmDMA_CH_0_RD_RATE_LIM_TOUT 0x40107C + +#define mmDMA_CH_0_WR_RATE_LIM_EN 0x401080 + +#define mmDMA_CH_0_WR_RATE_LIM_RST_TOKEN 0x401084 + +#define mmDMA_CH_0_WR_RATE_LIM_SAT 0x401088 + +#define mmDMA_CH_0_WR_RATE_LIM_TOUT 0x40108C + +#define mmDMA_CH_0_CFG2 0x401090 + +#define mmDMA_CH_0_TDMA_CTL 0x401100 + +#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_LO 0x401104 + +#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_HI 0x401108 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_0 0x40110C + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_0 0x401110 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0 0x401114 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_0 0x401118 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_0 0x40111C + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_1 0x401120 + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_1 0x401124 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1 0x401128 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_1 0x40112C + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_1 0x401130 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_2 0x401134 + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_2 0x401138 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2 0x40113C + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_2 0x401140 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_2 0x401144 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_3 0x401148 + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_3 0x40114C + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3 0x401150 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_3 0x401154 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_3 0x401158 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_4 0x40115C + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_4 0x401160 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4 0x401164 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_4 0x401168 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_4 0x40116C + +#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_LO 0x401170 + +#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_HI 0x401174 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_0 0x401178 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_0 0x40117C + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_0 0x401180 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_0 0x401184 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_0 0x401188 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_1 0x40118C + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_1 0x401190 + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_1 0x401194 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_1 0x401198 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_1 0x40119C + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_2 0x4011A0 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_2 0x4011A4 + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_2 0x4011A8 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_2 0x4011AC + +#define mmDMA_CH_0_TDMA_DST_STRIDE_2 0x4011B0 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_3 0x4011B4 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_3 0x4011B8 + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_3 0x4011BC + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_3 0x4011C0 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_3 0x4011C4 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_4 0x4011C8 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_4 0x4011CC + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_4 0x4011D0 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_4 0x4011D4 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_4 0x4011D8 + +#define mmDMA_CH_0_MEM_INIT_BUSY 0x4011FC + +#endif /* ASIC_REG_DMA_CH_0_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h new file mode 100644 index 000000000000..92960ef5e308 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_1_REGS_H_ +#define ASIC_REG_DMA_CH_1_REGS_H_ + +/* + ***************************************** + * DMA_CH_1 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_1_CFG0 0x409000 + +#define mmDMA_CH_1_CFG1 0x409004 + +#define mmDMA_CH_1_ERRMSG_ADDR_LO 0x409008 + +#define mmDMA_CH_1_ERRMSG_ADDR_HI 0x40900C + +#define mmDMA_CH_1_ERRMSG_WDATA 0x409010 + +#define mmDMA_CH_1_RD_COMP_ADDR_LO 0x409014 + +#define mmDMA_CH_1_RD_COMP_ADDR_HI 0x409018 + +#define mmDMA_CH_1_RD_COMP_WDATA 0x40901C + +#define mmDMA_CH_1_WR_COMP_ADDR_LO 0x409020 + +#define mmDMA_CH_1_WR_COMP_ADDR_HI 0x409024 + +#define mmDMA_CH_1_WR_COMP_WDATA 0x409028 + +#define mmDMA_CH_1_LDMA_SRC_ADDR_LO 0x40902C + +#define mmDMA_CH_1_LDMA_SRC_ADDR_HI 0x409030 + +#define mmDMA_CH_1_LDMA_DST_ADDR_LO 0x409034 + +#define mmDMA_CH_1_LDMA_DST_ADDR_HI 0x409038 + +#define mmDMA_CH_1_LDMA_TSIZE 0x40903C + +#define mmDMA_CH_1_COMIT_TRANSFER 0x409040 + +#define mmDMA_CH_1_STS0 0x409044 + +#define mmDMA_CH_1_STS1 0x409048 + +#define mmDMA_CH_1_STS2 0x40904C + +#define mmDMA_CH_1_STS3 0x409050 + +#define mmDMA_CH_1_STS4 0x409054 + +#define mmDMA_CH_1_SRC_ADDR_LO_STS 0x409058 + +#define mmDMA_CH_1_SRC_ADDR_HI_STS 0x40905C + +#define mmDMA_CH_1_SRC_TSIZE_STS 0x409060 + +#define mmDMA_CH_1_DST_ADDR_LO_STS 0x409064 + +#define mmDMA_CH_1_DST_ADDR_HI_STS 0x409068 + +#define mmDMA_CH_1_DST_TSIZE_STS 0x40906C + +#define mmDMA_CH_1_RD_RATE_LIM_EN 0x409070 + +#define mmDMA_CH_1_RD_RATE_LIM_RST_TOKEN 0x409074 + +#define mmDMA_CH_1_RD_RATE_LIM_SAT 0x409078 + +#define mmDMA_CH_1_RD_RATE_LIM_TOUT 0x40907C + +#define mmDMA_CH_1_WR_RATE_LIM_EN 0x409080 + +#define mmDMA_CH_1_WR_RATE_LIM_RST_TOKEN 0x409084 + +#define mmDMA_CH_1_WR_RATE_LIM_SAT 0x409088 + +#define mmDMA_CH_1_WR_RATE_LIM_TOUT 0x40908C + +#define mmDMA_CH_1_CFG2 0x409090 + +#define mmDMA_CH_1_TDMA_CTL 0x409100 + +#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_LO 0x409104 + +#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_HI 0x409108 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_0 0x40910C + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_0 0x409110 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_0 0x409114 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_0 0x409118 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_0 0x40911C + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_1 0x409120 + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_1 0x409124 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_1 0x409128 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_1 0x40912C + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_1 0x409130 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_2 0x409134 + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_2 0x409138 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_2 0x40913C + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_2 0x409140 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_2 0x409144 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_3 0x409148 + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_3 0x40914C + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_3 0x409150 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_3 0x409154 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_3 0x409158 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_4 0x40915C + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_4 0x409160 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_4 0x409164 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_4 0x409168 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_4 0x40916C + +#define mmDMA_CH_1_TDMA_DST_BASE_ADDR_LO 0x409170 + +#define mmDMA_CH_1_TDMA_DST_BASE_ADDR_HI 0x409174 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_0 0x409178 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_0 0x40917C + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_0 0x409180 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_0 0x409184 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_0 0x409188 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_1 0x40918C + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_1 0x409190 + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_1 0x409194 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_1 0x409198 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_1 0x40919C + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_2 0x4091A0 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_2 0x4091A4 + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_2 0x4091A8 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_2 0x4091AC + +#define mmDMA_CH_1_TDMA_DST_STRIDE_2 0x4091B0 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_3 0x4091B4 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_3 0x4091B8 + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_3 0x4091BC + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_3 0x4091C0 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_3 0x4091C4 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_4 0x4091C8 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_4 0x4091CC + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_4 0x4091D0 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_4 0x4091D4 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_4 0x4091D8 + +#define mmDMA_CH_1_MEM_INIT_BUSY 0x4091FC + +#endif /* ASIC_REG_DMA_CH_1_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h new file mode 100644 index 000000000000..4e37871a51bb --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_2_REGS_H_ +#define ASIC_REG_DMA_CH_2_REGS_H_ + +/* + ***************************************** + * DMA_CH_2 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_2_CFG0 0x411000 + +#define mmDMA_CH_2_CFG1 0x411004 + +#define mmDMA_CH_2_ERRMSG_ADDR_LO 0x411008 + +#define mmDMA_CH_2_ERRMSG_ADDR_HI 0x41100C + +#define mmDMA_CH_2_ERRMSG_WDATA 0x411010 + +#define mmDMA_CH_2_RD_COMP_ADDR_LO 0x411014 + +#define mmDMA_CH_2_RD_COMP_ADDR_HI 0x411018 + +#define mmDMA_CH_2_RD_COMP_WDATA 0x41101C + +#define mmDMA_CH_2_WR_COMP_ADDR_LO 0x411020 + +#define mmDMA_CH_2_WR_COMP_ADDR_HI 0x411024 + +#define mmDMA_CH_2_WR_COMP_WDATA 0x411028 + +#define mmDMA_CH_2_LDMA_SRC_ADDR_LO 0x41102C + +#define mmDMA_CH_2_LDMA_SRC_ADDR_HI 0x411030 + +#define mmDMA_CH_2_LDMA_DST_ADDR_LO 0x411034 + +#define mmDMA_CH_2_LDMA_DST_ADDR_HI 0x411038 + +#define mmDMA_CH_2_LDMA_TSIZE 0x41103C + +#define mmDMA_CH_2_COMIT_TRANSFER 0x411040 + +#define mmDMA_CH_2_STS0 0x411044 + +#define mmDMA_CH_2_STS1 0x411048 + +#define mmDMA_CH_2_STS2 0x41104C + +#define mmDMA_CH_2_STS3 0x411050 + +#define mmDMA_CH_2_STS4 0x411054 + +#define mmDMA_CH_2_SRC_ADDR_LO_STS 0x411058 + +#define mmDMA_CH_2_SRC_ADDR_HI_STS 0x41105C + +#define mmDMA_CH_2_SRC_TSIZE_STS 0x411060 + +#define mmDMA_CH_2_DST_ADDR_LO_STS 0x411064 + +#define mmDMA_CH_2_DST_ADDR_HI_STS 0x411068 + +#define mmDMA_CH_2_DST_TSIZE_STS 0x41106C + +#define mmDMA_CH_2_RD_RATE_LIM_EN 0x411070 + +#define mmDMA_CH_2_RD_RATE_LIM_RST_TOKEN 0x411074 + +#define mmDMA_CH_2_RD_RATE_LIM_SAT 0x411078 + +#define mmDMA_CH_2_RD_RATE_LIM_TOUT 0x41107C + +#define mmDMA_CH_2_WR_RATE_LIM_EN 0x411080 + +#define mmDMA_CH_2_WR_RATE_LIM_RST_TOKEN 0x411084 + +#define mmDMA_CH_2_WR_RATE_LIM_SAT 0x411088 + +#define mmDMA_CH_2_WR_RATE_LIM_TOUT 0x41108C + +#define mmDMA_CH_2_CFG2 0x411090 + +#define mmDMA_CH_2_TDMA_CTL 0x411100 + +#define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_LO 0x411104 + +#define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_HI 0x411108 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_0 0x41110C + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_0 0x411110 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_0 0x411114 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_0 0x411118 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_0 0x41111C + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_1 0x411120 + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_1 0x411124 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_1 0x411128 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_1 0x41112C + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_1 0x411130 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_2 0x411134 + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_2 0x411138 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_2 0x41113C + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_2 0x411140 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_2 0x411144 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_3 0x411148 + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_3 0x41114C + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_3 0x411150 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_3 0x411154 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_3 0x411158 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_4 0x41115C + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_4 0x411160 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_4 0x411164 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_4 0x411168 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_4 0x41116C + +#define mmDMA_CH_2_TDMA_DST_BASE_ADDR_LO 0x411170 + +#define mmDMA_CH_2_TDMA_DST_BASE_ADDR_HI 0x411174 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_0 0x411178 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_0 0x41117C + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_0 0x411180 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_0 0x411184 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_0 0x411188 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_1 0x41118C + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_1 0x411190 + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_1 0x411194 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_1 0x411198 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_1 0x41119C + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_2 0x4111A0 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_2 0x4111A4 + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_2 0x4111A8 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_2 0x4111AC + +#define mmDMA_CH_2_TDMA_DST_STRIDE_2 0x4111B0 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_3 0x4111B4 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_3 0x4111B8 + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_3 0x4111BC + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_3 0x4111C0 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_3 0x4111C4 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_4 0x4111C8 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_4 0x4111CC + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_4 0x4111D0 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_4 0x4111D4 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_4 0x4111D8 + +#define mmDMA_CH_2_MEM_INIT_BUSY 0x4111FC + +#endif /* ASIC_REG_DMA_CH_2_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h new file mode 100644 index 000000000000..a2d6aeb32a18 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_3_REGS_H_ +#define ASIC_REG_DMA_CH_3_REGS_H_ + +/* + ***************************************** + * DMA_CH_3 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_3_CFG0 0x419000 + +#define mmDMA_CH_3_CFG1 0x419004 + +#define mmDMA_CH_3_ERRMSG_ADDR_LO 0x419008 + +#define mmDMA_CH_3_ERRMSG_ADDR_HI 0x41900C + +#define mmDMA_CH_3_ERRMSG_WDATA 0x419010 + +#define mmDMA_CH_3_RD_COMP_ADDR_LO 0x419014 + +#define mmDMA_CH_3_RD_COMP_ADDR_HI 0x419018 + +#define mmDMA_CH_3_RD_COMP_WDATA 0x41901C + +#define mmDMA_CH_3_WR_COMP_ADDR_LO 0x419020 + +#define mmDMA_CH_3_WR_COMP_ADDR_HI 0x419024 + +#define mmDMA_CH_3_WR_COMP_WDATA 0x419028 + +#define mmDMA_CH_3_LDMA_SRC_ADDR_LO 0x41902C + +#define mmDMA_CH_3_LDMA_SRC_ADDR_HI 0x419030 + +#define mmDMA_CH_3_LDMA_DST_ADDR_LO 0x419034 + +#define mmDMA_CH_3_LDMA_DST_ADDR_HI 0x419038 + +#define mmDMA_CH_3_LDMA_TSIZE 0x41903C + +#define mmDMA_CH_3_COMIT_TRANSFER 0x419040 + +#define mmDMA_CH_3_STS0 0x419044 + +#define mmDMA_CH_3_STS1 0x419048 + +#define mmDMA_CH_3_STS2 0x41904C + +#define mmDMA_CH_3_STS3 0x419050 + +#define mmDMA_CH_3_STS4 0x419054 + +#define mmDMA_CH_3_SRC_ADDR_LO_STS 0x419058 + +#define mmDMA_CH_3_SRC_ADDR_HI_STS 0x41905C + +#define mmDMA_CH_3_SRC_TSIZE_STS 0x419060 + +#define mmDMA_CH_3_DST_ADDR_LO_STS 0x419064 + +#define mmDMA_CH_3_DST_ADDR_HI_STS 0x419068 + +#define mmDMA_CH_3_DST_TSIZE_STS 0x41906C + +#define mmDMA_CH_3_RD_RATE_LIM_EN 0x419070 + +#define mmDMA_CH_3_RD_RATE_LIM_RST_TOKEN 0x419074 + +#define mmDMA_CH_3_RD_RATE_LIM_SAT 0x419078 + +#define mmDMA_CH_3_RD_RATE_LIM_TOUT 0x41907C + +#define mmDMA_CH_3_WR_RATE_LIM_EN 0x419080 + +#define mmDMA_CH_3_WR_RATE_LIM_RST_TOKEN 0x419084 + +#define mmDMA_CH_3_WR_RATE_LIM_SAT 0x419088 + +#define mmDMA_CH_3_WR_RATE_LIM_TOUT 0x41908C + +#define mmDMA_CH_3_CFG2 0x419090 + +#define mmDMA_CH_3_TDMA_CTL 0x419100 + +#define mmDMA_CH_3_TDMA_SRC_BASE_ADDR_LO 0x419104 + +#define mmDMA_CH_3_TDMA_SRC_BASE_ADDR_HI 0x419108 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_0 0x41910C + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_0 0x419110 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_0 0x419114 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_0 0x419118 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_0 0x41911C + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_1 0x419120 + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_1 0x419124 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_1 0x419128 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_1 0x41912C + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_1 0x419130 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_2 0x419134 + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_2 0x419138 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_2 0x41913C + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_2 0x419140 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_2 0x419144 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_3 0x419148 + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_3 0x41914C + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_3 0x419150 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_3 0x419154 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_3 0x419158 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_4 0x41915C + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_4 0x419160 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_4 0x419164 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_4 0x419168 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_4 0x41916C + +#define mmDMA_CH_3_TDMA_DST_BASE_ADDR_LO 0x419170 + +#define mmDMA_CH_3_TDMA_DST_BASE_ADDR_HI 0x419174 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_0 0x419178 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_0 0x41917C + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_0 0x419180 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_0 0x419184 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_0 0x419188 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_1 0x41918C + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_1 0x419190 + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_1 0x419194 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_1 0x419198 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_1 0x41919C + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_2 0x4191A0 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_2 0x4191A4 + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_2 0x4191A8 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_2 0x4191AC + +#define mmDMA_CH_3_TDMA_DST_STRIDE_2 0x4191B0 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_3 0x4191B4 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_3 0x4191B8 + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_3 0x4191BC + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_3 0x4191C0 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_3 0x4191C4 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_4 0x4191C8 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_4 0x4191CC + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_4 0x4191D0 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_4 0x4191D4 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_4 0x4191D8 + +#define mmDMA_CH_3_MEM_INIT_BUSY 0x4191FC + +#endif /* ASIC_REG_DMA_CH_3_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h new file mode 100644 index 000000000000..400d6fd3acf5 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_4_REGS_H_ +#define ASIC_REG_DMA_CH_4_REGS_H_ + +/* + ***************************************** + * DMA_CH_4 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_4_CFG0 0x421000 + +#define mmDMA_CH_4_CFG1 0x421004 + +#define mmDMA_CH_4_ERRMSG_ADDR_LO 0x421008 + +#define mmDMA_CH_4_ERRMSG_ADDR_HI 0x42100C + +#define mmDMA_CH_4_ERRMSG_WDATA 0x421010 + +#define mmDMA_CH_4_RD_COMP_ADDR_LO 0x421014 + +#define mmDMA_CH_4_RD_COMP_ADDR_HI 0x421018 + +#define mmDMA_CH_4_RD_COMP_WDATA 0x42101C + +#define mmDMA_CH_4_WR_COMP_ADDR_LO 0x421020 + +#define mmDMA_CH_4_WR_COMP_ADDR_HI 0x421024 + +#define mmDMA_CH_4_WR_COMP_WDATA 0x421028 + +#define mmDMA_CH_4_LDMA_SRC_ADDR_LO 0x42102C + +#define mmDMA_CH_4_LDMA_SRC_ADDR_HI 0x421030 + +#define mmDMA_CH_4_LDMA_DST_ADDR_LO 0x421034 + +#define mmDMA_CH_4_LDMA_DST_ADDR_HI 0x421038 + +#define mmDMA_CH_4_LDMA_TSIZE 0x42103C + +#define mmDMA_CH_4_COMIT_TRANSFER 0x421040 + +#define mmDMA_CH_4_STS0 0x421044 + +#define mmDMA_CH_4_STS1 0x421048 + +#define mmDMA_CH_4_STS2 0x42104C + +#define mmDMA_CH_4_STS3 0x421050 + +#define mmDMA_CH_4_STS4 0x421054 + +#define mmDMA_CH_4_SRC_ADDR_LO_STS 0x421058 + +#define mmDMA_CH_4_SRC_ADDR_HI_STS 0x42105C + +#define mmDMA_CH_4_SRC_TSIZE_STS 0x421060 + +#define mmDMA_CH_4_DST_ADDR_LO_STS 0x421064 + +#define mmDMA_CH_4_DST_ADDR_HI_STS 0x421068 + +#define mmDMA_CH_4_DST_TSIZE_STS 0x42106C + +#define mmDMA_CH_4_RD_RATE_LIM_EN 0x421070 + +#define mmDMA_CH_4_RD_RATE_LIM_RST_TOKEN 0x421074 + +#define mmDMA_CH_4_RD_RATE_LIM_SAT 0x421078 + +#define mmDMA_CH_4_RD_RATE_LIM_TOUT 0x42107C + +#define mmDMA_CH_4_WR_RATE_LIM_EN 0x421080 + +#define mmDMA_CH_4_WR_RATE_LIM_RST_TOKEN 0x421084 + +#define mmDMA_CH_4_WR_RATE_LIM_SAT 0x421088 + +#define mmDMA_CH_4_WR_RATE_LIM_TOUT 0x42108C + +#define mmDMA_CH_4_CFG2 0x421090 + +#define mmDMA_CH_4_TDMA_CTL 0x421100 + +#define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_LO 0x421104 + +#define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_HI 0x421108 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_0 0x42110C + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_0 0x421110 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_0 0x421114 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_0 0x421118 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_0 0x42111C + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_1 0x421120 + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_1 0x421124 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_1 0x421128 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_1 0x42112C + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_1 0x421130 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_2 0x421134 + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_2 0x421138 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_2 0x42113C + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_2 0x421140 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_2 0x421144 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_3 0x421148 + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_3 0x42114C + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_3 0x421150 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_3 0x421154 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_3 0x421158 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_4 0x42115C + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_4 0x421160 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_4 0x421164 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_4 0x421168 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_4 0x42116C + +#define mmDMA_CH_4_TDMA_DST_BASE_ADDR_LO 0x421170 + +#define mmDMA_CH_4_TDMA_DST_BASE_ADDR_HI 0x421174 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_0 0x421178 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_0 0x42117C + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_0 0x421180 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_0 0x421184 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_0 0x421188 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_1 0x42118C + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_1 0x421190 + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_1 0x421194 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_1 0x421198 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_1 0x42119C + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_2 0x4211A0 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_2 0x4211A4 + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_2 0x4211A8 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_2 0x4211AC + +#define mmDMA_CH_4_TDMA_DST_STRIDE_2 0x4211B0 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_3 0x4211B4 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_3 0x4211B8 + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_3 0x4211BC + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_3 0x4211C0 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_3 0x4211C4 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_4 0x4211C8 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_4 0x4211CC + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_4 0x4211D0 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_4 0x4211D4 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_4 0x4211D8 + +#define mmDMA_CH_4_MEM_INIT_BUSY 0x4211FC + +#endif /* ASIC_REG_DMA_CH_4_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h new file mode 100644 index 000000000000..8d965443c51e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_MACRO_MASKS_H_ +#define ASIC_REG_DMA_MACRO_MASKS_H_ + +/* + ***************************************** + * DMA_MACRO (Prototype: DMA_MACRO) + ***************************************** + */ + +/* DMA_MACRO_LBW_RANGE_HIT_BLOCK */ +#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0 +#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF + +/* DMA_MACRO_LBW_RANGE_MASK */ +#define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0 +#define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF + +/* DMA_MACRO_LBW_RANGE_BASE */ +#define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0 +#define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF + +/* DMA_MACRO_HBW_RANGE_HIT_BLOCK */ +#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF + +/* DMA_MACRO_HBW_RANGE_MASK_49_32 */ +#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF + +/* DMA_MACRO_HBW_RANGE_MASK_31_0 */ +#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK 0xFFFFFFFF + +/* DMA_MACRO_HBW_RANGE_BASE_49_32 */ +#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK 0x3FFFF + +/* DMA_MACRO_HBW_RANGE_BASE_31_0 */ +#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK 0xFFFFFFFF + +/* DMA_MACRO_WRITE_EN */ +#define DMA_MACRO_WRITE_EN_R_SHIFT 0 +#define DMA_MACRO_WRITE_EN_R_MASK 0x1 + +/* DMA_MACRO_WRITE_CREDIT */ +#define DMA_MACRO_WRITE_CREDIT_R_SHIFT 0 +#define DMA_MACRO_WRITE_CREDIT_R_MASK 0x3FF + +/* DMA_MACRO_READ_EN */ +#define DMA_MACRO_READ_EN_R_SHIFT 0 +#define DMA_MACRO_READ_EN_R_MASK 0x1 + +/* DMA_MACRO_READ_CREDIT */ +#define DMA_MACRO_READ_CREDIT_R_SHIFT 0 +#define DMA_MACRO_READ_CREDIT_R_MASK 0x3FF + +/* DMA_MACRO_SRAM_BUSY */ + +/* DMA_MACRO_RAZWI_LBW_WT_VLD */ +#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_LBW_WT_ID */ +#define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK 0x7FFF + +/* DMA_MACRO_RAZWI_LBW_RD_VLD */ +#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_LBW_RD_ID */ +#define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK 0x7FFF + +/* DMA_MACRO_RAZWI_HBW_WT_VLD */ +#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_HBW_WT_ID */ +#define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK 0x1FFFFFFF + +/* DMA_MACRO_RAZWI_HBW_RD_VLD */ +#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_HBW_RD_ID */ +#define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK 0x1FFFFFFF + +#endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h new file mode 100644 index 000000000000..8bfcb001189d --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_MACRO_REGS_H_ +#define ASIC_REG_DMA_MACRO_REGS_H_ + +/* + ***************************************** + * DMA_MACRO (Prototype: DMA_MACRO) + ***************************************** + */ + +#define mmDMA_MACRO_LBW_RANGE_HIT_BLOCK 0x4B0000 + +#define mmDMA_MACRO_LBW_RANGE_MASK_0 0x4B0004 + +#define mmDMA_MACRO_LBW_RANGE_MASK_1 0x4B0008 + +#define mmDMA_MACRO_LBW_RANGE_MASK_2 0x4B000C + +#define mmDMA_MACRO_LBW_RANGE_MASK_3 0x4B0010 + +#define mmDMA_MACRO_LBW_RANGE_MASK_4 0x4B0014 + +#define mmDMA_MACRO_LBW_RANGE_MASK_5 0x4B0018 + +#define mmDMA_MACRO_LBW_RANGE_MASK_6 0x4B001C + +#define mmDMA_MACRO_LBW_RANGE_MASK_7 0x4B0020 + +#define mmDMA_MACRO_LBW_RANGE_MASK_8 0x4B0024 + +#define mmDMA_MACRO_LBW_RANGE_MASK_9 0x4B0028 + +#define mmDMA_MACRO_LBW_RANGE_MASK_10 0x4B002C + +#define mmDMA_MACRO_LBW_RANGE_MASK_11 0x4B0030 + +#define mmDMA_MACRO_LBW_RANGE_MASK_12 0x4B0034 + +#define mmDMA_MACRO_LBW_RANGE_MASK_13 0x4B0038 + +#define mmDMA_MACRO_LBW_RANGE_MASK_14 0x4B003C + +#define mmDMA_MACRO_LBW_RANGE_MASK_15 0x4B0040 + +#define mmDMA_MACRO_LBW_RANGE_BASE_0 0x4B0044 + +#define mmDMA_MACRO_LBW_RANGE_BASE_1 0x4B0048 + +#define mmDMA_MACRO_LBW_RANGE_BASE_2 0x4B004C + +#define mmDMA_MACRO_LBW_RANGE_BASE_3 0x4B0050 + +#define mmDMA_MACRO_LBW_RANGE_BASE_4 0x4B0054 + +#define mmDMA_MACRO_LBW_RANGE_BASE_5 0x4B0058 + +#define mmDMA_MACRO_LBW_RANGE_BASE_6 0x4B005C + +#define mmDMA_MACRO_LBW_RANGE_BASE_7 0x4B0060 + +#define mmDMA_MACRO_LBW_RANGE_BASE_8 0x4B0064 + +#define mmDMA_MACRO_LBW_RANGE_BASE_9 0x4B0068 + +#define mmDMA_MACRO_LBW_RANGE_BASE_10 0x4B006C + +#define mmDMA_MACRO_LBW_RANGE_BASE_11 0x4B0070 + +#define mmDMA_MACRO_LBW_RANGE_BASE_12 0x4B0074 + +#define mmDMA_MACRO_LBW_RANGE_BASE_13 0x4B0078 + +#define mmDMA_MACRO_LBW_RANGE_BASE_14 0x4B007C + +#define mmDMA_MACRO_LBW_RANGE_BASE_15 0x4B0080 + +#define mmDMA_MACRO_HBW_RANGE_HIT_BLOCK 0x4B0084 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_0 0x4B00A8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_1 0x4B00AC + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_2 0x4B00B0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_3 0x4B00B4 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_4 0x4B00B8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_5 0x4B00BC + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_6 0x4B00C0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_7 0x4B00C4 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_0 0x4B00C8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_1 0x4B00CC + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_2 0x4B00D0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_3 0x4B00D4 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_4 0x4B00D8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_5 0x4B00DC + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_6 0x4B00E0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_7 0x4B00E4 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_0 0x4B00E8 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_1 0x4B00EC + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_2 0x4B00F0 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_3 0x4B00F4 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_4 0x4B00F8 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_5 0x4B00FC + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_6 0x4B0100 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_7 0x4B0104 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_0 0x4B0108 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_1 0x4B010C + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_2 0x4B0110 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_3 0x4B0114 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_4 0x4B0118 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_5 0x4B011C + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_6 0x4B0120 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_7 0x4B0124 + +#define mmDMA_MACRO_WRITE_EN 0x4B0128 + +#define mmDMA_MACRO_WRITE_CREDIT 0x4B012C + +#define mmDMA_MACRO_READ_EN 0x4B0130 + +#define mmDMA_MACRO_READ_CREDIT 0x4B0134 + +#define mmDMA_MACRO_SRAM_BUSY 0x4B0138 + +#define mmDMA_MACRO_RAZWI_LBW_WT_VLD 0x4B013C + +#define mmDMA_MACRO_RAZWI_LBW_WT_ID 0x4B0140 + +#define mmDMA_MACRO_RAZWI_LBW_RD_VLD 0x4B0144 + +#define mmDMA_MACRO_RAZWI_LBW_RD_ID 0x4B0148 + +#define mmDMA_MACRO_RAZWI_HBW_WT_VLD 0x4B014C + +#define mmDMA_MACRO_RAZWI_HBW_WT_ID 0x4B0150 + +#define mmDMA_MACRO_RAZWI_HBW_RD_VLD 0x4B0154 + +#define mmDMA_MACRO_RAZWI_HBW_RD_ID 0x4B0158 + +#endif /* ASIC_REG_DMA_MACRO_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h new file mode 100644 index 000000000000..9f33f351a3c1 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_NRTR_MASKS_H_ +#define ASIC_REG_DMA_NRTR_MASKS_H_ + +/* + ***************************************** + * DMA_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +/* DMA_NRTR_HBW_MAX_CRED */ +#define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 +#define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F +#define DMA_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8 +#define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define DMA_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16 +#define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define DMA_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24 +#define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* DMA_NRTR_LBW_MAX_CRED */ +#define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 +#define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F +#define DMA_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8 +#define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define DMA_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16 +#define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define DMA_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24 +#define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* DMA_NRTR_DBG_E_ARB */ +#define DMA_NRTR_DBG_E_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_E_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_E_ARB_S_SHIFT 8 +#define DMA_NRTR_DBG_E_ARB_S_MASK 0x700 +#define DMA_NRTR_DBG_E_ARB_N_SHIFT 16 +#define DMA_NRTR_DBG_E_ARB_N_MASK 0x70000 +#define DMA_NRTR_DBG_E_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_E_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_W_ARB */ +#define DMA_NRTR_DBG_W_ARB_E_SHIFT 0 +#define DMA_NRTR_DBG_W_ARB_E_MASK 0x7 +#define DMA_NRTR_DBG_W_ARB_S_SHIFT 8 +#define DMA_NRTR_DBG_W_ARB_S_MASK 0x700 +#define DMA_NRTR_DBG_W_ARB_N_SHIFT 16 +#define DMA_NRTR_DBG_W_ARB_N_MASK 0x70000 +#define DMA_NRTR_DBG_W_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_W_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_N_ARB */ +#define DMA_NRTR_DBG_N_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_N_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_N_ARB_E_SHIFT 8 +#define DMA_NRTR_DBG_N_ARB_E_MASK 0x700 +#define DMA_NRTR_DBG_N_ARB_S_SHIFT 16 +#define DMA_NRTR_DBG_N_ARB_S_MASK 0x70000 +#define DMA_NRTR_DBG_N_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_N_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_S_ARB */ +#define DMA_NRTR_DBG_S_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_S_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_S_ARB_E_SHIFT 8 +#define DMA_NRTR_DBG_S_ARB_E_MASK 0x700 +#define DMA_NRTR_DBG_S_ARB_N_SHIFT 16 +#define DMA_NRTR_DBG_S_ARB_N_MASK 0x70000 +#define DMA_NRTR_DBG_S_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_S_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_L_ARB */ +#define DMA_NRTR_DBG_L_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_L_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_L_ARB_E_SHIFT 8 +#define DMA_NRTR_DBG_L_ARB_E_MASK 0x700 +#define DMA_NRTR_DBG_L_ARB_S_SHIFT 16 +#define DMA_NRTR_DBG_L_ARB_S_MASK 0x70000 +#define DMA_NRTR_DBG_L_ARB_N_SHIFT 24 +#define DMA_NRTR_DBG_L_ARB_N_MASK 0x7000000 + +/* DMA_NRTR_DBG_E_ARB_MAX */ +#define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_W_ARB_MAX */ +#define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_N_ARB_MAX */ +#define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_S_ARB_MAX */ +#define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_L_ARB_MAX */ +#define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_SPLIT_COEF */ +#define DMA_NRTR_SPLIT_COEF_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_CFG */ +#define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4 +#define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10 +#define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5 +#define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20 +#define DMA_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define DMA_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* DMA_NRTR_SPLIT_RD_SAT */ +#define DMA_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_RD_RST_TOKEN */ +#define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_RD_TIMEOUT */ +#define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_SPLIT_WR_SAT */ +#define DMA_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* DMA_NRTR_WPLIT_WR_TST_TOLEN */ +#define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_WR_TIMEOUT */ +#define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_HBW_RANGE_HIT */ +#define DMA_NRTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* DMA_NRTR_HBW_RANGE_MASK_L */ +#define DMA_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_HBW_RANGE_MASK_H */ +#define DMA_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* DMA_NRTR_HBW_RANGE_BASE_L */ +#define DMA_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_HBW_RANGE_BASE_H */ +#define DMA_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* DMA_NRTR_LBW_RANGE_HIT */ +#define DMA_NRTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define DMA_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* DMA_NRTR_LBW_RANGE_MASK */ +#define DMA_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define DMA_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* DMA_NRTR_LBW_RANGE_BASE */ +#define DMA_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define DMA_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* DMA_NRTR_RGLTR */ +#define DMA_NRTR_RGLTR_WR_EN_SHIFT 0 +#define DMA_NRTR_RGLTR_WR_EN_MASK 0x1 +#define DMA_NRTR_RGLTR_RD_EN_SHIFT 4 +#define DMA_NRTR_RGLTR_RD_EN_MASK 0x10 + +/* DMA_NRTR_RGLTR_WR_RESULT */ +#define DMA_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define DMA_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* DMA_NRTR_RGLTR_RD_RESULT */ +#define DMA_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define DMA_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* DMA_NRTR_SCRAMB_EN */ +#define DMA_NRTR_SCRAMB_EN_VAL_SHIFT 0 +#define DMA_NRTR_SCRAMB_EN_VAL_MASK 0x1 + +/* DMA_NRTR_NON_LIN_SCRAMB */ +#define DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define DMA_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_DMA_NRTR_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h new file mode 100644 index 000000000000..d8293745a02b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_NRTR_REGS_H_ +#define ASIC_REG_DMA_NRTR_REGS_H_ + +/* + ***************************************** + * DMA_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmDMA_NRTR_HBW_MAX_CRED 0x1C0100 + +#define mmDMA_NRTR_LBW_MAX_CRED 0x1C0120 + +#define mmDMA_NRTR_DBG_E_ARB 0x1C0300 + +#define mmDMA_NRTR_DBG_W_ARB 0x1C0304 + +#define mmDMA_NRTR_DBG_N_ARB 0x1C0308 + +#define mmDMA_NRTR_DBG_S_ARB 0x1C030C + +#define mmDMA_NRTR_DBG_L_ARB 0x1C0310 + +#define mmDMA_NRTR_DBG_E_ARB_MAX 0x1C0320 + +#define mmDMA_NRTR_DBG_W_ARB_MAX 0x1C0324 + +#define mmDMA_NRTR_DBG_N_ARB_MAX 0x1C0328 + +#define mmDMA_NRTR_DBG_S_ARB_MAX 0x1C032C + +#define mmDMA_NRTR_DBG_L_ARB_MAX 0x1C0330 + +#define mmDMA_NRTR_SPLIT_COEF_0 0x1C0400 + +#define mmDMA_NRTR_SPLIT_COEF_1 0x1C0404 + +#define mmDMA_NRTR_SPLIT_COEF_2 0x1C0408 + +#define mmDMA_NRTR_SPLIT_COEF_3 0x1C040C + +#define mmDMA_NRTR_SPLIT_COEF_4 0x1C0410 + +#define mmDMA_NRTR_SPLIT_COEF_5 0x1C0414 + +#define mmDMA_NRTR_SPLIT_COEF_6 0x1C0418 + +#define mmDMA_NRTR_SPLIT_COEF_7 0x1C041C + +#define mmDMA_NRTR_SPLIT_COEF_8 0x1C0420 + +#define mmDMA_NRTR_SPLIT_COEF_9 0x1C0424 + +#define mmDMA_NRTR_SPLIT_CFG 0x1C0440 + +#define mmDMA_NRTR_SPLIT_RD_SAT 0x1C0444 + +#define mmDMA_NRTR_SPLIT_RD_RST_TOKEN 0x1C0448 + +#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_0 0x1C044C + +#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_1 0x1C0450 + +#define mmDMA_NRTR_SPLIT_WR_SAT 0x1C0454 + +#define mmDMA_NRTR_WPLIT_WR_TST_TOLEN 0x1C0458 + +#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_0 0x1C045C + +#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_1 0x1C0460 + +#define mmDMA_NRTR_HBW_RANGE_HIT 0x1C0470 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_0 0x1C0480 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_1 0x1C0484 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_2 0x1C0488 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_3 0x1C048C + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_4 0x1C0490 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_5 0x1C0494 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_6 0x1C0498 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_7 0x1C049C + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_0 0x1C04A0 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_1 0x1C04A4 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_2 0x1C04A8 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_3 0x1C04AC + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_4 0x1C04B0 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_5 0x1C04B4 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_6 0x1C04B8 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_7 0x1C04BC + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_0 0x1C04C0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_1 0x1C04C4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_2 0x1C04C8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_3 0x1C04CC + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_4 0x1C04D0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_5 0x1C04D4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_6 0x1C04D8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_7 0x1C04DC + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_0 0x1C04E0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_1 0x1C04E4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_2 0x1C04E8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_3 0x1C04EC + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_4 0x1C04F0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_5 0x1C04F4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_6 0x1C04F8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_7 0x1C04FC + +#define mmDMA_NRTR_LBW_RANGE_HIT 0x1C0500 + +#define mmDMA_NRTR_LBW_RANGE_MASK_0 0x1C0510 + +#define mmDMA_NRTR_LBW_RANGE_MASK_1 0x1C0514 + +#define mmDMA_NRTR_LBW_RANGE_MASK_2 0x1C0518 + +#define mmDMA_NRTR_LBW_RANGE_MASK_3 0x1C051C + +#define mmDMA_NRTR_LBW_RANGE_MASK_4 0x1C0520 + +#define mmDMA_NRTR_LBW_RANGE_MASK_5 0x1C0524 + +#define mmDMA_NRTR_LBW_RANGE_MASK_6 0x1C0528 + +#define mmDMA_NRTR_LBW_RANGE_MASK_7 0x1C052C + +#define mmDMA_NRTR_LBW_RANGE_MASK_8 0x1C0530 + +#define mmDMA_NRTR_LBW_RANGE_MASK_9 0x1C0534 + +#define mmDMA_NRTR_LBW_RANGE_MASK_10 0x1C0538 + +#define mmDMA_NRTR_LBW_RANGE_MASK_11 0x1C053C + +#define mmDMA_NRTR_LBW_RANGE_MASK_12 0x1C0540 + +#define mmDMA_NRTR_LBW_RANGE_MASK_13 0x1C0544 + +#define mmDMA_NRTR_LBW_RANGE_MASK_14 0x1C0548 + +#define mmDMA_NRTR_LBW_RANGE_MASK_15 0x1C054C + +#define mmDMA_NRTR_LBW_RANGE_BASE_0 0x1C0550 + +#define mmDMA_NRTR_LBW_RANGE_BASE_1 0x1C0554 + +#define mmDMA_NRTR_LBW_RANGE_BASE_2 0x1C0558 + +#define mmDMA_NRTR_LBW_RANGE_BASE_3 0x1C055C + +#define mmDMA_NRTR_LBW_RANGE_BASE_4 0x1C0560 + +#define mmDMA_NRTR_LBW_RANGE_BASE_5 0x1C0564 + +#define mmDMA_NRTR_LBW_RANGE_BASE_6 0x1C0568 + +#define mmDMA_NRTR_LBW_RANGE_BASE_7 0x1C056C + +#define mmDMA_NRTR_LBW_RANGE_BASE_8 0x1C0570 + +#define mmDMA_NRTR_LBW_RANGE_BASE_9 0x1C0574 + +#define mmDMA_NRTR_LBW_RANGE_BASE_10 0x1C0578 + +#define mmDMA_NRTR_LBW_RANGE_BASE_11 0x1C057C + +#define mmDMA_NRTR_LBW_RANGE_BASE_12 0x1C0580 + +#define mmDMA_NRTR_LBW_RANGE_BASE_13 0x1C0584 + +#define mmDMA_NRTR_LBW_RANGE_BASE_14 0x1C0588 + +#define mmDMA_NRTR_LBW_RANGE_BASE_15 0x1C058C + +#define mmDMA_NRTR_RGLTR 0x1C0590 + +#define mmDMA_NRTR_RGLTR_WR_RESULT 0x1C0594 + +#define mmDMA_NRTR_RGLTR_RD_RESULT 0x1C0598 + +#define mmDMA_NRTR_SCRAMB_EN 0x1C0600 + +#define mmDMA_NRTR_NON_LIN_SCRAMB 0x1C0604 + +#endif /* ASIC_REG_DMA_NRTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h new file mode 100644 index 000000000000..10619dbb9b17 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h @@ -0,0 +1,465 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_0_MASKS_H_ +#define ASIC_REG_DMA_QM_0_MASKS_H_ + +/* + ***************************************** + * DMA_QM_0 (Prototype: QMAN) + ***************************************** + */ + +/* DMA_QM_0_GLBL_CFG0 */ +#define DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT 0 +#define DMA_QM_0_GLBL_CFG0_PQF_EN_MASK 0x1 +#define DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT 1 +#define DMA_QM_0_GLBL_CFG0_CQF_EN_MASK 0x2 +#define DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT 2 +#define DMA_QM_0_GLBL_CFG0_CP_EN_MASK 0x4 +#define DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT 3 +#define DMA_QM_0_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* DMA_QM_0_GLBL_CFG1 */ +#define DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define DMA_QM_0_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define DMA_QM_0_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT 2 +#define DMA_QM_0_GLBL_CFG1_CP_STOP_MASK 0x4 +#define DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define DMA_QM_0_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define DMA_QM_0_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define DMA_QM_0_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define DMA_QM_0_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define DMA_QM_0_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* DMA_QM_0_GLBL_PROT */ +#define DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT 0 +#define DMA_QM_0_GLBL_PROT_PQF_PROT_MASK 0x1 +#define DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT 1 +#define DMA_QM_0_GLBL_PROT_CQF_PROT_MASK 0x2 +#define DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT 2 +#define DMA_QM_0_GLBL_PROT_CP_PROT_MASK 0x4 +#define DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT 3 +#define DMA_QM_0_GLBL_PROT_DMA_PROT_MASK 0x8 +#define DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define DMA_QM_0_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* DMA_QM_0_GLBL_ERR_CFG */ +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* DMA_QM_0_GLBL_ERR_ADDR_LO */ +#define DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_GLBL_ERR_ADDR_HI */ +#define DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_GLBL_ERR_WDATA */ +#define DMA_QM_0_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_GLBL_SECURE_PROPS */ +#define DMA_QM_0_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define DMA_QM_0_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA_QM_0_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA_QM_0_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA_QM_0_GLBL_NON_SECURE_PROPS */ +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA_QM_0_GLBL_STS0 */ +#define DMA_QM_0_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define DMA_QM_0_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define DMA_QM_0_GLBL_STS0_CP_IDLE_SHIFT 2 +#define DMA_QM_0_GLBL_STS0_CP_IDLE_MASK 0x4 +#define DMA_QM_0_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define DMA_QM_0_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define DMA_QM_0_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define DMA_QM_0_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define DMA_QM_0_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* DMA_QM_0_GLBL_STS1 */ +#define DMA_QM_0_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define DMA_QM_0_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define DMA_QM_0_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define DMA_QM_0_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define DMA_QM_0_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define DMA_QM_0_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA_QM_0_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define DMA_QM_0_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define DMA_QM_0_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define DMA_QM_0_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* DMA_QM_0_PQ_BASE_LO */ +#define DMA_QM_0_PQ_BASE_LO_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_BASE_HI */ +#define DMA_QM_0_PQ_BASE_HI_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_SIZE */ +#define DMA_QM_0_PQ_SIZE_VAL_SHIFT 0 +#define DMA_QM_0_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PI */ +#define DMA_QM_0_PQ_PI_VAL_SHIFT 0 +#define DMA_QM_0_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_CI */ +#define DMA_QM_0_PQ_CI_VAL_SHIFT 0 +#define DMA_QM_0_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_CFG0 */ +#define DMA_QM_0_PQ_CFG0_RESERVED_SHIFT 0 +#define DMA_QM_0_PQ_CFG0_RESERVED_MASK 0x1 + +/* DMA_QM_0_PQ_CFG1 */ +#define DMA_QM_0_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA_QM_0_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA_QM_0_PQ_ARUSER */ +#define DMA_QM_0_PQ_ARUSER_NOSNOOP_SHIFT 0 +#define DMA_QM_0_PQ_ARUSER_NOSNOOP_MASK 0x1 +#define DMA_QM_0_PQ_ARUSER_WORD_SHIFT 1 +#define DMA_QM_0_PQ_ARUSER_WORD_MASK 0x2 + +/* DMA_QM_0_PQ_PUSH0 */ +#define DMA_QM_0_PQ_PUSH0_PTR_LO_SHIFT 0 +#define DMA_QM_0_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PUSH1 */ +#define DMA_QM_0_PQ_PUSH1_PTR_HI_SHIFT 0 +#define DMA_QM_0_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PUSH2 */ +#define DMA_QM_0_PQ_PUSH2_TSIZE_SHIFT 0 +#define DMA_QM_0_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PUSH3 */ +#define DMA_QM_0_PQ_PUSH3_RPT_SHIFT 0 +#define DMA_QM_0_PQ_PUSH3_RPT_MASK 0xFFFF +#define DMA_QM_0_PQ_PUSH3_CTL_SHIFT 16 +#define DMA_QM_0_PQ_PUSH3_CTL_MASK 0xFFFF0000 + +/* DMA_QM_0_PQ_STS0 */ +#define DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define DMA_QM_0_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define DMA_QM_0_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA_QM_0_PQ_STS1 */ +#define DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define DMA_QM_0_PQ_STS1_PQ_BUSY_SHIFT 31 +#define DMA_QM_0_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* DMA_QM_0_PQ_RD_RATE_LIM_EN */ +#define DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN */ +#define DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_QM_0_PQ_RD_RATE_LIM_SAT */ +#define DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* DMA_QM_0_PQ_RD_RATE_LIM_TOUT */ +#define DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* DMA_QM_0_CQ_CFG0 */ +#define DMA_QM_0_CQ_CFG0_RESERVED_SHIFT 0 +#define DMA_QM_0_CQ_CFG0_RESERVED_MASK 0x1 + +/* DMA_QM_0_CQ_CFG1 */ +#define DMA_QM_0_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA_QM_0_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_ARUSER */ +#define DMA_QM_0_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define DMA_QM_0_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define DMA_QM_0_CQ_ARUSER_WORD_SHIFT 1 +#define DMA_QM_0_CQ_ARUSER_WORD_MASK 0x2 + +/* DMA_QM_0_CQ_PTR_LO */ +#define DMA_QM_0_CQ_PTR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_PTR_HI */ +#define DMA_QM_0_CQ_PTR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_TSIZE */ +#define DMA_QM_0_CQ_TSIZE_VAL_SHIFT 0 +#define DMA_QM_0_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_CTL */ +#define DMA_QM_0_CQ_CTL_RPT_SHIFT 0 +#define DMA_QM_0_CQ_CTL_RPT_MASK 0xFFFF +#define DMA_QM_0_CQ_CTL_CTL_SHIFT 16 +#define DMA_QM_0_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_PTR_LO_STS */ +#define DMA_QM_0_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_PTR_HI_STS */ +#define DMA_QM_0_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_TSIZE_STS */ +#define DMA_QM_0_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DMA_QM_0_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_CTL_STS */ +#define DMA_QM_0_CQ_CTL_STS_RPT_SHIFT 0 +#define DMA_QM_0_CQ_CTL_STS_RPT_MASK 0xFFFF +#define DMA_QM_0_CQ_CTL_STS_CTL_SHIFT 16 +#define DMA_QM_0_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_STS0 */ +#define DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define DMA_QM_0_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define DMA_QM_0_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_STS1 */ +#define DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define DMA_QM_0_CQ_STS1_CQ_BUSY_SHIFT 31 +#define DMA_QM_0_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* DMA_QM_0_CQ_RD_RATE_LIM_EN */ +#define DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN */ +#define DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_QM_0_CQ_RD_RATE_LIM_SAT */ +#define DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* DMA_QM_0_CQ_RD_RATE_LIM_TOUT */ +#define DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* DMA_QM_0_CQ_IFIFO_CNT */ +#define DMA_QM_0_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* DMA_QM_0_CP_MSG_BASE0_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE0_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE1_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE1_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE2_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE2_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE3_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE3_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_TSIZE_OFFSET */ +#define DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET */ +#define DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET */ +#define DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_COMMIT_OFFSET */ +#define DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_FENCE0_RDATA */ +#define DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE1_RDATA */ +#define DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE2_RDATA */ +#define DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE3_RDATA */ +#define DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE0_CNT */ +#define DMA_QM_0_CP_FENCE0_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_FENCE1_CNT */ +#define DMA_QM_0_CP_FENCE1_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_FENCE2_CNT */ +#define DMA_QM_0_CP_FENCE2_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_FENCE3_CNT */ +#define DMA_QM_0_CP_FENCE3_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_STS */ +#define DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define DMA_QM_0_CP_STS_ERDY_SHIFT 16 +#define DMA_QM_0_CP_STS_ERDY_MASK 0x10000 +#define DMA_QM_0_CP_STS_RRDY_SHIFT 17 +#define DMA_QM_0_CP_STS_RRDY_MASK 0x20000 +#define DMA_QM_0_CP_STS_MRDY_SHIFT 18 +#define DMA_QM_0_CP_STS_MRDY_MASK 0x40000 +#define DMA_QM_0_CP_STS_SW_STOP_SHIFT 19 +#define DMA_QM_0_CP_STS_SW_STOP_MASK 0x80000 +#define DMA_QM_0_CP_STS_FENCE_ID_SHIFT 20 +#define DMA_QM_0_CP_STS_FENCE_ID_MASK 0x300000 +#define DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* DMA_QM_0_CP_CURRENT_INST_LO */ +#define DMA_QM_0_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_CURRENT_INST_HI */ +#define DMA_QM_0_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_BARRIER_CFG */ +#define DMA_QM_0_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define DMA_QM_0_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* DMA_QM_0_CP_DBG_0 */ +#define DMA_QM_0_CP_DBG_0_VAL_SHIFT 0 +#define DMA_QM_0_CP_DBG_0_VAL_MASK 0xFF + +/* DMA_QM_0_PQ_BUF_ADDR */ +#define DMA_QM_0_PQ_BUF_ADDR_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_BUF_RDATA */ +#define DMA_QM_0_PQ_BUF_RDATA_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_BUF_ADDR */ +#define DMA_QM_0_CQ_BUF_ADDR_VAL_SHIFT 0 +#define DMA_QM_0_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_BUF_RDATA */ +#define DMA_QM_0_CQ_BUF_RDATA_VAL_SHIFT 0 +#define DMA_QM_0_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DMA_QM_0_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h new file mode 100644 index 000000000000..c693bc5dcb22 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_0_REGS_H_ +#define ASIC_REG_DMA_QM_0_REGS_H_ + +/* + ***************************************** + * DMA_QM_0 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_0_GLBL_CFG0 0x400000 + +#define mmDMA_QM_0_GLBL_CFG1 0x400004 + +#define mmDMA_QM_0_GLBL_PROT 0x400008 + +#define mmDMA_QM_0_GLBL_ERR_CFG 0x40000C + +#define mmDMA_QM_0_GLBL_ERR_ADDR_LO 0x400010 + +#define mmDMA_QM_0_GLBL_ERR_ADDR_HI 0x400014 + +#define mmDMA_QM_0_GLBL_ERR_WDATA 0x400018 + +#define mmDMA_QM_0_GLBL_SECURE_PROPS 0x40001C + +#define mmDMA_QM_0_GLBL_NON_SECURE_PROPS 0x400020 + +#define mmDMA_QM_0_GLBL_STS0 0x400024 + +#define mmDMA_QM_0_GLBL_STS1 0x400028 + +#define mmDMA_QM_0_PQ_BASE_LO 0x400060 + +#define mmDMA_QM_0_PQ_BASE_HI 0x400064 + +#define mmDMA_QM_0_PQ_SIZE 0x400068 + +#define mmDMA_QM_0_PQ_PI 0x40006C + +#define mmDMA_QM_0_PQ_CI 0x400070 + +#define mmDMA_QM_0_PQ_CFG0 0x400074 + +#define mmDMA_QM_0_PQ_CFG1 0x400078 + +#define mmDMA_QM_0_PQ_ARUSER 0x40007C + +#define mmDMA_QM_0_PQ_PUSH0 0x400080 + +#define mmDMA_QM_0_PQ_PUSH1 0x400084 + +#define mmDMA_QM_0_PQ_PUSH2 0x400088 + +#define mmDMA_QM_0_PQ_PUSH3 0x40008C + +#define mmDMA_QM_0_PQ_STS0 0x400090 + +#define mmDMA_QM_0_PQ_STS1 0x400094 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_EN 0x4000A0 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN 0x4000A4 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_SAT 0x4000A8 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT 0x4000AC + +#define mmDMA_QM_0_CQ_CFG0 0x4000B0 + +#define mmDMA_QM_0_CQ_CFG1 0x4000B4 + +#define mmDMA_QM_0_CQ_ARUSER 0x4000B8 + +#define mmDMA_QM_0_CQ_PTR_LO 0x4000C0 + +#define mmDMA_QM_0_CQ_PTR_HI 0x4000C4 + +#define mmDMA_QM_0_CQ_TSIZE 0x4000C8 + +#define mmDMA_QM_0_CQ_CTL 0x4000CC + +#define mmDMA_QM_0_CQ_PTR_LO_STS 0x4000D4 + +#define mmDMA_QM_0_CQ_PTR_HI_STS 0x4000D8 + +#define mmDMA_QM_0_CQ_TSIZE_STS 0x4000DC + +#define mmDMA_QM_0_CQ_CTL_STS 0x4000E0 + +#define mmDMA_QM_0_CQ_STS0 0x4000E4 + +#define mmDMA_QM_0_CQ_STS1 0x4000E8 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_EN 0x4000F0 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN 0x4000F4 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_SAT 0x4000F8 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT 0x4000FC + +#define mmDMA_QM_0_CQ_IFIFO_CNT 0x400108 + +#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO 0x400120 + +#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI 0x400124 + +#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO 0x400128 + +#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI 0x40012C + +#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO 0x400130 + +#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI 0x400134 + +#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO 0x400138 + +#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI 0x40013C + +#define mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET 0x400140 + +#define mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET 0x400144 + +#define mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET 0x400148 + +#define mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET 0x40014C + +#define mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET 0x400150 + +#define mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET 0x400154 + +#define mmDMA_QM_0_CP_FENCE0_RDATA 0x400158 + +#define mmDMA_QM_0_CP_FENCE1_RDATA 0x40015C + +#define mmDMA_QM_0_CP_FENCE2_RDATA 0x400160 + +#define mmDMA_QM_0_CP_FENCE3_RDATA 0x400164 + +#define mmDMA_QM_0_CP_FENCE0_CNT 0x400168 + +#define mmDMA_QM_0_CP_FENCE1_CNT 0x40016C + +#define mmDMA_QM_0_CP_FENCE2_CNT 0x400170 + +#define mmDMA_QM_0_CP_FENCE3_CNT 0x400174 + +#define mmDMA_QM_0_CP_STS 0x400178 + +#define mmDMA_QM_0_CP_CURRENT_INST_LO 0x40017C + +#define mmDMA_QM_0_CP_CURRENT_INST_HI 0x400180 + +#define mmDMA_QM_0_CP_BARRIER_CFG 0x400184 + +#define mmDMA_QM_0_CP_DBG_0 0x400188 + +#define mmDMA_QM_0_PQ_BUF_ADDR 0x400300 + +#define mmDMA_QM_0_PQ_BUF_RDATA 0x400304 + +#define mmDMA_QM_0_CQ_BUF_ADDR 0x400308 + +#define mmDMA_QM_0_CQ_BUF_RDATA 0x40030C + +#endif /* ASIC_REG_DMA_QM_0_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h new file mode 100644 index 000000000000..da928390f89c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_1_REGS_H_ +#define ASIC_REG_DMA_QM_1_REGS_H_ + +/* + ***************************************** + * DMA_QM_1 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_1_GLBL_CFG0 0x408000 + +#define mmDMA_QM_1_GLBL_CFG1 0x408004 + +#define mmDMA_QM_1_GLBL_PROT 0x408008 + +#define mmDMA_QM_1_GLBL_ERR_CFG 0x40800C + +#define mmDMA_QM_1_GLBL_ERR_ADDR_LO 0x408010 + +#define mmDMA_QM_1_GLBL_ERR_ADDR_HI 0x408014 + +#define mmDMA_QM_1_GLBL_ERR_WDATA 0x408018 + +#define mmDMA_QM_1_GLBL_SECURE_PROPS 0x40801C + +#define mmDMA_QM_1_GLBL_NON_SECURE_PROPS 0x408020 + +#define mmDMA_QM_1_GLBL_STS0 0x408024 + +#define mmDMA_QM_1_GLBL_STS1 0x408028 + +#define mmDMA_QM_1_PQ_BASE_LO 0x408060 + +#define mmDMA_QM_1_PQ_BASE_HI 0x408064 + +#define mmDMA_QM_1_PQ_SIZE 0x408068 + +#define mmDMA_QM_1_PQ_PI 0x40806C + +#define mmDMA_QM_1_PQ_CI 0x408070 + +#define mmDMA_QM_1_PQ_CFG0 0x408074 + +#define mmDMA_QM_1_PQ_CFG1 0x408078 + +#define mmDMA_QM_1_PQ_ARUSER 0x40807C + +#define mmDMA_QM_1_PQ_PUSH0 0x408080 + +#define mmDMA_QM_1_PQ_PUSH1 0x408084 + +#define mmDMA_QM_1_PQ_PUSH2 0x408088 + +#define mmDMA_QM_1_PQ_PUSH3 0x40808C + +#define mmDMA_QM_1_PQ_STS0 0x408090 + +#define mmDMA_QM_1_PQ_STS1 0x408094 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_EN 0x4080A0 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN 0x4080A4 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_SAT 0x4080A8 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT 0x4080AC + +#define mmDMA_QM_1_CQ_CFG0 0x4080B0 + +#define mmDMA_QM_1_CQ_CFG1 0x4080B4 + +#define mmDMA_QM_1_CQ_ARUSER 0x4080B8 + +#define mmDMA_QM_1_CQ_PTR_LO 0x4080C0 + +#define mmDMA_QM_1_CQ_PTR_HI 0x4080C4 + +#define mmDMA_QM_1_CQ_TSIZE 0x4080C8 + +#define mmDMA_QM_1_CQ_CTL 0x4080CC + +#define mmDMA_QM_1_CQ_PTR_LO_STS 0x4080D4 + +#define mmDMA_QM_1_CQ_PTR_HI_STS 0x4080D8 + +#define mmDMA_QM_1_CQ_TSIZE_STS 0x4080DC + +#define mmDMA_QM_1_CQ_CTL_STS 0x4080E0 + +#define mmDMA_QM_1_CQ_STS0 0x4080E4 + +#define mmDMA_QM_1_CQ_STS1 0x4080E8 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_EN 0x4080F0 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN 0x4080F4 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_SAT 0x4080F8 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT 0x4080FC + +#define mmDMA_QM_1_CQ_IFIFO_CNT 0x408108 + +#define mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO 0x408120 + +#define mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI 0x408124 + +#define mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO 0x408128 + +#define mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI 0x40812C + +#define mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO 0x408130 + +#define mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI 0x408134 + +#define mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO 0x408138 + +#define mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI 0x40813C + +#define mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET 0x408140 + +#define mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET 0x408144 + +#define mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET 0x408148 + +#define mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET 0x40814C + +#define mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET 0x408150 + +#define mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET 0x408154 + +#define mmDMA_QM_1_CP_FENCE0_RDATA 0x408158 + +#define mmDMA_QM_1_CP_FENCE1_RDATA 0x40815C + +#define mmDMA_QM_1_CP_FENCE2_RDATA 0x408160 + +#define mmDMA_QM_1_CP_FENCE3_RDATA 0x408164 + +#define mmDMA_QM_1_CP_FENCE0_CNT 0x408168 + +#define mmDMA_QM_1_CP_FENCE1_CNT 0x40816C + +#define mmDMA_QM_1_CP_FENCE2_CNT 0x408170 + +#define mmDMA_QM_1_CP_FENCE3_CNT 0x408174 + +#define mmDMA_QM_1_CP_STS 0x408178 + +#define mmDMA_QM_1_CP_CURRENT_INST_LO 0x40817C + +#define mmDMA_QM_1_CP_CURRENT_INST_HI 0x408180 + +#define mmDMA_QM_1_CP_BARRIER_CFG 0x408184 + +#define mmDMA_QM_1_CP_DBG_0 0x408188 + +#define mmDMA_QM_1_PQ_BUF_ADDR 0x408300 + +#define mmDMA_QM_1_PQ_BUF_RDATA 0x408304 + +#define mmDMA_QM_1_CQ_BUF_ADDR 0x408308 + +#define mmDMA_QM_1_CQ_BUF_RDATA 0x40830C + +#endif /* ASIC_REG_DMA_QM_1_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h new file mode 100644 index 000000000000..b4f06e9b71d6 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_2_REGS_H_ +#define ASIC_REG_DMA_QM_2_REGS_H_ + +/* + ***************************************** + * DMA_QM_2 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_2_GLBL_CFG0 0x410000 + +#define mmDMA_QM_2_GLBL_CFG1 0x410004 + +#define mmDMA_QM_2_GLBL_PROT 0x410008 + +#define mmDMA_QM_2_GLBL_ERR_CFG 0x41000C + +#define mmDMA_QM_2_GLBL_ERR_ADDR_LO 0x410010 + +#define mmDMA_QM_2_GLBL_ERR_ADDR_HI 0x410014 + +#define mmDMA_QM_2_GLBL_ERR_WDATA 0x410018 + +#define mmDMA_QM_2_GLBL_SECURE_PROPS 0x41001C + +#define mmDMA_QM_2_GLBL_NON_SECURE_PROPS 0x410020 + +#define mmDMA_QM_2_GLBL_STS0 0x410024 + +#define mmDMA_QM_2_GLBL_STS1 0x410028 + +#define mmDMA_QM_2_PQ_BASE_LO 0x410060 + +#define mmDMA_QM_2_PQ_BASE_HI 0x410064 + +#define mmDMA_QM_2_PQ_SIZE 0x410068 + +#define mmDMA_QM_2_PQ_PI 0x41006C + +#define mmDMA_QM_2_PQ_CI 0x410070 + +#define mmDMA_QM_2_PQ_CFG0 0x410074 + +#define mmDMA_QM_2_PQ_CFG1 0x410078 + +#define mmDMA_QM_2_PQ_ARUSER 0x41007C + +#define mmDMA_QM_2_PQ_PUSH0 0x410080 + +#define mmDMA_QM_2_PQ_PUSH1 0x410084 + +#define mmDMA_QM_2_PQ_PUSH2 0x410088 + +#define mmDMA_QM_2_PQ_PUSH3 0x41008C + +#define mmDMA_QM_2_PQ_STS0 0x410090 + +#define mmDMA_QM_2_PQ_STS1 0x410094 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_EN 0x4100A0 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN 0x4100A4 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_SAT 0x4100A8 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT 0x4100AC + +#define mmDMA_QM_2_CQ_CFG0 0x4100B0 + +#define mmDMA_QM_2_CQ_CFG1 0x4100B4 + +#define mmDMA_QM_2_CQ_ARUSER 0x4100B8 + +#define mmDMA_QM_2_CQ_PTR_LO 0x4100C0 + +#define mmDMA_QM_2_CQ_PTR_HI 0x4100C4 + +#define mmDMA_QM_2_CQ_TSIZE 0x4100C8 + +#define mmDMA_QM_2_CQ_CTL 0x4100CC + +#define mmDMA_QM_2_CQ_PTR_LO_STS 0x4100D4 + +#define mmDMA_QM_2_CQ_PTR_HI_STS 0x4100D8 + +#define mmDMA_QM_2_CQ_TSIZE_STS 0x4100DC + +#define mmDMA_QM_2_CQ_CTL_STS 0x4100E0 + +#define mmDMA_QM_2_CQ_STS0 0x4100E4 + +#define mmDMA_QM_2_CQ_STS1 0x4100E8 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_EN 0x4100F0 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN 0x4100F4 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_SAT 0x4100F8 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT 0x4100FC + +#define mmDMA_QM_2_CQ_IFIFO_CNT 0x410108 + +#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO 0x410120 + +#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI 0x410124 + +#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO 0x410128 + +#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI 0x41012C + +#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO 0x410130 + +#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI 0x410134 + +#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO 0x410138 + +#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI 0x41013C + +#define mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET 0x410140 + +#define mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET 0x410144 + +#define mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET 0x410148 + +#define mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET 0x41014C + +#define mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET 0x410150 + +#define mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET 0x410154 + +#define mmDMA_QM_2_CP_FENCE0_RDATA 0x410158 + +#define mmDMA_QM_2_CP_FENCE1_RDATA 0x41015C + +#define mmDMA_QM_2_CP_FENCE2_RDATA 0x410160 + +#define mmDMA_QM_2_CP_FENCE3_RDATA 0x410164 + +#define mmDMA_QM_2_CP_FENCE0_CNT 0x410168 + +#define mmDMA_QM_2_CP_FENCE1_CNT 0x41016C + +#define mmDMA_QM_2_CP_FENCE2_CNT 0x410170 + +#define mmDMA_QM_2_CP_FENCE3_CNT 0x410174 + +#define mmDMA_QM_2_CP_STS 0x410178 + +#define mmDMA_QM_2_CP_CURRENT_INST_LO 0x41017C + +#define mmDMA_QM_2_CP_CURRENT_INST_HI 0x410180 + +#define mmDMA_QM_2_CP_BARRIER_CFG 0x410184 + +#define mmDMA_QM_2_CP_DBG_0 0x410188 + +#define mmDMA_QM_2_PQ_BUF_ADDR 0x410300 + +#define mmDMA_QM_2_PQ_BUF_RDATA 0x410304 + +#define mmDMA_QM_2_CQ_BUF_ADDR 0x410308 + +#define mmDMA_QM_2_CQ_BUF_RDATA 0x41030C + +#endif /* ASIC_REG_DMA_QM_2_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h new file mode 100644 index 000000000000..53e3cd78a06b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_3_REGS_H_ +#define ASIC_REG_DMA_QM_3_REGS_H_ + +/* + ***************************************** + * DMA_QM_3 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_3_GLBL_CFG0 0x418000 + +#define mmDMA_QM_3_GLBL_CFG1 0x418004 + +#define mmDMA_QM_3_GLBL_PROT 0x418008 + +#define mmDMA_QM_3_GLBL_ERR_CFG 0x41800C + +#define mmDMA_QM_3_GLBL_ERR_ADDR_LO 0x418010 + +#define mmDMA_QM_3_GLBL_ERR_ADDR_HI 0x418014 + +#define mmDMA_QM_3_GLBL_ERR_WDATA 0x418018 + +#define mmDMA_QM_3_GLBL_SECURE_PROPS 0x41801C + +#define mmDMA_QM_3_GLBL_NON_SECURE_PROPS 0x418020 + +#define mmDMA_QM_3_GLBL_STS0 0x418024 + +#define mmDMA_QM_3_GLBL_STS1 0x418028 + +#define mmDMA_QM_3_PQ_BASE_LO 0x418060 + +#define mmDMA_QM_3_PQ_BASE_HI 0x418064 + +#define mmDMA_QM_3_PQ_SIZE 0x418068 + +#define mmDMA_QM_3_PQ_PI 0x41806C + +#define mmDMA_QM_3_PQ_CI 0x418070 + +#define mmDMA_QM_3_PQ_CFG0 0x418074 + +#define mmDMA_QM_3_PQ_CFG1 0x418078 + +#define mmDMA_QM_3_PQ_ARUSER 0x41807C + +#define mmDMA_QM_3_PQ_PUSH0 0x418080 + +#define mmDMA_QM_3_PQ_PUSH1 0x418084 + +#define mmDMA_QM_3_PQ_PUSH2 0x418088 + +#define mmDMA_QM_3_PQ_PUSH3 0x41808C + +#define mmDMA_QM_3_PQ_STS0 0x418090 + +#define mmDMA_QM_3_PQ_STS1 0x418094 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_EN 0x4180A0 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN 0x4180A4 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_SAT 0x4180A8 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT 0x4180AC + +#define mmDMA_QM_3_CQ_CFG0 0x4180B0 + +#define mmDMA_QM_3_CQ_CFG1 0x4180B4 + +#define mmDMA_QM_3_CQ_ARUSER 0x4180B8 + +#define mmDMA_QM_3_CQ_PTR_LO 0x4180C0 + +#define mmDMA_QM_3_CQ_PTR_HI 0x4180C4 + +#define mmDMA_QM_3_CQ_TSIZE 0x4180C8 + +#define mmDMA_QM_3_CQ_CTL 0x4180CC + +#define mmDMA_QM_3_CQ_PTR_LO_STS 0x4180D4 + +#define mmDMA_QM_3_CQ_PTR_HI_STS 0x4180D8 + +#define mmDMA_QM_3_CQ_TSIZE_STS 0x4180DC + +#define mmDMA_QM_3_CQ_CTL_STS 0x4180E0 + +#define mmDMA_QM_3_CQ_STS0 0x4180E4 + +#define mmDMA_QM_3_CQ_STS1 0x4180E8 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_EN 0x4180F0 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN 0x4180F4 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_SAT 0x4180F8 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT 0x4180FC + +#define mmDMA_QM_3_CQ_IFIFO_CNT 0x418108 + +#define mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO 0x418120 + +#define mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI 0x418124 + +#define mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO 0x418128 + +#define mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI 0x41812C + +#define mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO 0x418130 + +#define mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI 0x418134 + +#define mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO 0x418138 + +#define mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI 0x41813C + +#define mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET 0x418140 + +#define mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET 0x418144 + +#define mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET 0x418148 + +#define mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET 0x41814C + +#define mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET 0x418150 + +#define mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET 0x418154 + +#define mmDMA_QM_3_CP_FENCE0_RDATA 0x418158 + +#define mmDMA_QM_3_CP_FENCE1_RDATA 0x41815C + +#define mmDMA_QM_3_CP_FENCE2_RDATA 0x418160 + +#define mmDMA_QM_3_CP_FENCE3_RDATA 0x418164 + +#define mmDMA_QM_3_CP_FENCE0_CNT 0x418168 + +#define mmDMA_QM_3_CP_FENCE1_CNT 0x41816C + +#define mmDMA_QM_3_CP_FENCE2_CNT 0x418170 + +#define mmDMA_QM_3_CP_FENCE3_CNT 0x418174 + +#define mmDMA_QM_3_CP_STS 0x418178 + +#define mmDMA_QM_3_CP_CURRENT_INST_LO 0x41817C + +#define mmDMA_QM_3_CP_CURRENT_INST_HI 0x418180 + +#define mmDMA_QM_3_CP_BARRIER_CFG 0x418184 + +#define mmDMA_QM_3_CP_DBG_0 0x418188 + +#define mmDMA_QM_3_PQ_BUF_ADDR 0x418300 + +#define mmDMA_QM_3_PQ_BUF_RDATA 0x418304 + +#define mmDMA_QM_3_CQ_BUF_ADDR 0x418308 + +#define mmDMA_QM_3_CQ_BUF_RDATA 0x41830C + +#endif /* ASIC_REG_DMA_QM_3_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h new file mode 100644 index 000000000000..e0eb5f260201 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_4_REGS_H_ +#define ASIC_REG_DMA_QM_4_REGS_H_ + +/* + ***************************************** + * DMA_QM_4 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_4_GLBL_CFG0 0x420000 + +#define mmDMA_QM_4_GLBL_CFG1 0x420004 + +#define mmDMA_QM_4_GLBL_PROT 0x420008 + +#define mmDMA_QM_4_GLBL_ERR_CFG 0x42000C + +#define mmDMA_QM_4_GLBL_ERR_ADDR_LO 0x420010 + +#define mmDMA_QM_4_GLBL_ERR_ADDR_HI 0x420014 + +#define mmDMA_QM_4_GLBL_ERR_WDATA 0x420018 + +#define mmDMA_QM_4_GLBL_SECURE_PROPS 0x42001C + +#define mmDMA_QM_4_GLBL_NON_SECURE_PROPS 0x420020 + +#define mmDMA_QM_4_GLBL_STS0 0x420024 + +#define mmDMA_QM_4_GLBL_STS1 0x420028 + +#define mmDMA_QM_4_PQ_BASE_LO 0x420060 + +#define mmDMA_QM_4_PQ_BASE_HI 0x420064 + +#define mmDMA_QM_4_PQ_SIZE 0x420068 + +#define mmDMA_QM_4_PQ_PI 0x42006C + +#define mmDMA_QM_4_PQ_CI 0x420070 + +#define mmDMA_QM_4_PQ_CFG0 0x420074 + +#define mmDMA_QM_4_PQ_CFG1 0x420078 + +#define mmDMA_QM_4_PQ_ARUSER 0x42007C + +#define mmDMA_QM_4_PQ_PUSH0 0x420080 + +#define mmDMA_QM_4_PQ_PUSH1 0x420084 + +#define mmDMA_QM_4_PQ_PUSH2 0x420088 + +#define mmDMA_QM_4_PQ_PUSH3 0x42008C + +#define mmDMA_QM_4_PQ_STS0 0x420090 + +#define mmDMA_QM_4_PQ_STS1 0x420094 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_EN 0x4200A0 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN 0x4200A4 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_SAT 0x4200A8 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT 0x4200AC + +#define mmDMA_QM_4_CQ_CFG0 0x4200B0 + +#define mmDMA_QM_4_CQ_CFG1 0x4200B4 + +#define mmDMA_QM_4_CQ_ARUSER 0x4200B8 + +#define mmDMA_QM_4_CQ_PTR_LO 0x4200C0 + +#define mmDMA_QM_4_CQ_PTR_HI 0x4200C4 + +#define mmDMA_QM_4_CQ_TSIZE 0x4200C8 + +#define mmDMA_QM_4_CQ_CTL 0x4200CC + +#define mmDMA_QM_4_CQ_PTR_LO_STS 0x4200D4 + +#define mmDMA_QM_4_CQ_PTR_HI_STS 0x4200D8 + +#define mmDMA_QM_4_CQ_TSIZE_STS 0x4200DC + +#define mmDMA_QM_4_CQ_CTL_STS 0x4200E0 + +#define mmDMA_QM_4_CQ_STS0 0x4200E4 + +#define mmDMA_QM_4_CQ_STS1 0x4200E8 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_EN 0x4200F0 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN 0x4200F4 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_SAT 0x4200F8 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT 0x4200FC + +#define mmDMA_QM_4_CQ_IFIFO_CNT 0x420108 + +#define mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO 0x420120 + +#define mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI 0x420124 + +#define mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO 0x420128 + +#define mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI 0x42012C + +#define mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO 0x420130 + +#define mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI 0x420134 + +#define mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO 0x420138 + +#define mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI 0x42013C + +#define mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET 0x420140 + +#define mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET 0x420144 + +#define mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET 0x420148 + +#define mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET 0x42014C + +#define mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET 0x420150 + +#define mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET 0x420154 + +#define mmDMA_QM_4_CP_FENCE0_RDATA 0x420158 + +#define mmDMA_QM_4_CP_FENCE1_RDATA 0x42015C + +#define mmDMA_QM_4_CP_FENCE2_RDATA 0x420160 + +#define mmDMA_QM_4_CP_FENCE3_RDATA 0x420164 + +#define mmDMA_QM_4_CP_FENCE0_CNT 0x420168 + +#define mmDMA_QM_4_CP_FENCE1_CNT 0x42016C + +#define mmDMA_QM_4_CP_FENCE2_CNT 0x420170 + +#define mmDMA_QM_4_CP_FENCE3_CNT 0x420174 + +#define mmDMA_QM_4_CP_STS 0x420178 + +#define mmDMA_QM_4_CP_CURRENT_INST_LO 0x42017C + +#define mmDMA_QM_4_CP_CURRENT_INST_HI 0x420180 + +#define mmDMA_QM_4_CP_BARRIER_CFG 0x420184 + +#define mmDMA_QM_4_CP_DBG_0 0x420188 + +#define mmDMA_QM_4_PQ_BUF_ADDR 0x420300 + +#define mmDMA_QM_4_PQ_BUF_RDATA 0x420304 + +#define mmDMA_QM_4_CQ_BUF_ADDR 0x420308 + +#define mmDMA_QM_4_CQ_BUF_RDATA 0x42030C + +#endif /* ASIC_REG_DMA_QM_4_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h new file mode 100644 index 000000000000..85b15010cd7a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h @@ -0,0 +1,1372 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GOYA_BLOCKS_H_ +#define GOYA_BLOCKS_H_ + +#define mmPCI_NRTR_BASE 0x7FFC000000ull +#define PCI_NRTR_MAX_OFFSET 0x608 +#define PCI_NRTR_SECTION 0x4000 +#define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull +#define PCI_RD_REGULATOR_MAX_OFFSET 0x74 +#define PCI_RD_REGULATOR_SECTION 0x1000 +#define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull +#define PCI_WR_REGULATOR_MAX_OFFSET 0x74 +#define PCI_WR_REGULATOR_SECTION 0x3B000 +#define mmMME1_RTR_BASE 0x7FFC040000ull +#define MME1_RTR_MAX_OFFSET 0x608 +#define MME1_RTR_SECTION 0x4000 +#define mmMME1_RD_REGULATOR_BASE 0x7FFC044000ull +#define MME1_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME1_RD_REGULATOR_SECTION 0x1000 +#define mmMME1_WR_REGULATOR_BASE 0x7FFC045000ull +#define MME1_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME1_WR_REGULATOR_SECTION 0x3B000 +#define mmMME2_RTR_BASE 0x7FFC080000ull +#define MME2_RTR_MAX_OFFSET 0x608 +#define MME2_RTR_SECTION 0x4000 +#define mmMME2_RD_REGULATOR_BASE 0x7FFC084000ull +#define MME2_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME2_RD_REGULATOR_SECTION 0x1000 +#define mmMME2_WR_REGULATOR_BASE 0x7FFC085000ull +#define MME2_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME2_WR_REGULATOR_SECTION 0x3B000 +#define mmMME3_RTR_BASE 0x7FFC0C0000ull +#define MME3_RTR_MAX_OFFSET 0x608 +#define MME3_RTR_SECTION 0x4000 +#define mmMME3_RD_REGULATOR_BASE 0x7FFC0C4000ull +#define MME3_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME3_RD_REGULATOR_SECTION 0x1000 +#define mmMME3_WR_REGULATOR_BASE 0x7FFC0C5000ull +#define MME3_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME3_WR_REGULATOR_SECTION 0xB000 +#define mmMME_BASE 0x7FFC0D0000ull +#define MME_MAX_OFFSET 0xBB0 +#define MME_SECTION 0x8000 +#define mmMME_QM_BASE 0x7FFC0D8000ull +#define MME_QM_MAX_OFFSET 0x310 +#define MME_QM_SECTION 0x1000 +#define mmMME_CMDQ_BASE 0x7FFC0D9000ull +#define MME_CMDQ_MAX_OFFSET 0x310 +#define MME_CMDQ_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_0_BASE 0x7FFC0DA000ull +#define ACC_MS_ECC_MEM_0_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_0_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_1_BASE 0x7FFC0DB000ull +#define ACC_MS_ECC_MEM_1_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_1_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_2_BASE 0x7FFC0DC000ull +#define ACC_MS_ECC_MEM_2_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_2_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_3_BASE 0x7FFC0DD000ull +#define ACC_MS_ECC_MEM_3_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_3_SECTION 0x1000 +#define mmSBA_ECC_MEM_BASE 0x7FFC0DE000ull +#define SBA_ECC_MEM_MAX_OFFSET 0x0 +#define SBA_ECC_MEM_SECTION 0x1000 +#define mmSBB_ECC_MEM_BASE 0x7FFC0DF000ull +#define SBB_ECC_MEM_MAX_OFFSET 0x0 +#define SBB_ECC_MEM_SECTION 0x21000 +#define mmMME4_RTR_BASE 0x7FFC100000ull +#define MME4_RTR_MAX_OFFSET 0x608 +#define MME4_RTR_SECTION 0x4000 +#define mmMME4_RD_REGULATOR_BASE 0x7FFC104000ull +#define MME4_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME4_RD_REGULATOR_SECTION 0x1000 +#define mmMME4_WR_REGULATOR_BASE 0x7FFC105000ull +#define MME4_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME4_WR_REGULATOR_SECTION 0xB000 +#define mmSYNC_MNGR_BASE 0x7FFC110000ull +#define SYNC_MNGR_MAX_OFFSET 0x4400 +#define SYNC_MNGR_SECTION 0x30000 +#define mmMME5_RTR_BASE 0x7FFC140000ull +#define MME5_RTR_MAX_OFFSET 0x608 +#define MME5_RTR_SECTION 0x4000 +#define mmMME5_RD_REGULATOR_BASE 0x7FFC144000ull +#define MME5_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME5_RD_REGULATOR_SECTION 0x1000 +#define mmMME5_WR_REGULATOR_BASE 0x7FFC145000ull +#define MME5_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME5_WR_REGULATOR_SECTION 0x3B000 +#define mmMME6_RTR_BASE 0x7FFC180000ull +#define MME6_RTR_MAX_OFFSET 0x608 +#define MME6_RTR_SECTION 0x4000 +#define mmMME6_RD_REGULATOR_BASE 0x7FFC184000ull +#define MME6_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME6_RD_REGULATOR_SECTION 0x1000 +#define mmMME6_WR_REGULATOR_BASE 0x7FFC185000ull +#define MME6_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME6_WR_REGULATOR_SECTION 0x3B000 +#define mmDMA_NRTR_BASE 0x7FFC1C0000ull +#define DMA_NRTR_MAX_OFFSET 0x608 +#define DMA_NRTR_SECTION 0x4000 +#define mmDMA_RD_REGULATOR_BASE 0x7FFC1C4000ull +#define DMA_RD_REGULATOR_MAX_OFFSET 0x74 +#define DMA_RD_REGULATOR_SECTION 0x1000 +#define mmDMA_WR_REGULATOR_BASE 0x7FFC1C5000ull +#define DMA_WR_REGULATOR_MAX_OFFSET 0x74 +#define DMA_WR_REGULATOR_SECTION 0x3B000 +#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull +#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull +#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC204000ull +#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC205000ull +#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC208000ull +#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC209000ull +#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC20C000ull +#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC20D000ull +#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC210000ull +#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC211000ull +#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC220000ull +#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC221000ull +#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC224000ull +#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC225000ull +#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC228000ull +#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC229000ull +#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC22C000ull +#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC22D000ull +#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC230000ull +#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC231000ull +#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC240000ull +#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC241000ull +#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC244000ull +#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC245000ull +#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC248000ull +#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC249000ull +#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC24C000ull +#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC24D000ull +#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC250000ull +#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC251000ull +#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC260000ull +#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC261000ull +#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC264000ull +#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC265000ull +#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC268000ull +#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC269000ull +#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC26C000ull +#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC26D000ull +#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC270000ull +#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC271000ull +#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y4_X0_BANK_BASE 0x7FFC280000ull +#define SRAM_Y4_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X0_RTR_BASE 0x7FFC281000ull +#define SRAM_Y4_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X1_BANK_BASE 0x7FFC284000ull +#define SRAM_Y4_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X1_RTR_BASE 0x7FFC285000ull +#define SRAM_Y4_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X2_BANK_BASE 0x7FFC288000ull +#define SRAM_Y4_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X2_RTR_BASE 0x7FFC289000ull +#define SRAM_Y4_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X3_BANK_BASE 0x7FFC28C000ull +#define SRAM_Y4_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X3_RTR_BASE 0x7FFC28D000ull +#define SRAM_Y4_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X4_BANK_BASE 0x7FFC290000ull +#define SRAM_Y4_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X4_RTR_BASE 0x7FFC291000ull +#define SRAM_Y4_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y5_X0_BANK_BASE 0x7FFC2A0000ull +#define SRAM_Y5_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X0_RTR_BASE 0x7FFC2A1000ull +#define SRAM_Y5_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X1_BANK_BASE 0x7FFC2A4000ull +#define SRAM_Y5_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X1_RTR_BASE 0x7FFC2A5000ull +#define SRAM_Y5_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X2_BANK_BASE 0x7FFC2A8000ull +#define SRAM_Y5_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X2_RTR_BASE 0x7FFC2A9000ull +#define SRAM_Y5_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X3_BANK_BASE 0x7FFC2AC000ull +#define SRAM_Y5_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X3_RTR_BASE 0x7FFC2AD000ull +#define SRAM_Y5_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X4_BANK_BASE 0x7FFC2B0000ull +#define SRAM_Y5_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X4_RTR_BASE 0x7FFC2B1000ull +#define SRAM_Y5_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X4_RTR_SECTION 0x14F000 +#define mmDMA_QM_0_BASE 0x7FFC400000ull +#define DMA_QM_0_MAX_OFFSET 0x310 +#define DMA_QM_0_SECTION 0x1000 +#define mmDMA_CH_0_BASE 0x7FFC401000ull +#define DMA_CH_0_MAX_OFFSET 0x200 +#define DMA_CH_0_SECTION 0x7000 +#define mmDMA_QM_1_BASE 0x7FFC408000ull +#define DMA_QM_1_MAX_OFFSET 0x310 +#define DMA_QM_1_SECTION 0x1000 +#define mmDMA_CH_1_BASE 0x7FFC409000ull +#define DMA_CH_1_MAX_OFFSET 0x200 +#define DMA_CH_1_SECTION 0x7000 +#define mmDMA_QM_2_BASE 0x7FFC410000ull +#define DMA_QM_2_MAX_OFFSET 0x310 +#define DMA_QM_2_SECTION 0x1000 +#define mmDMA_CH_2_BASE 0x7FFC411000ull +#define DMA_CH_2_MAX_OFFSET 0x200 +#define DMA_CH_2_SECTION 0x7000 +#define mmDMA_QM_3_BASE 0x7FFC418000ull +#define DMA_QM_3_MAX_OFFSET 0x310 +#define DMA_QM_3_SECTION 0x1000 +#define mmDMA_CH_3_BASE 0x7FFC419000ull +#define DMA_CH_3_MAX_OFFSET 0x200 +#define DMA_CH_3_SECTION 0x7000 +#define mmDMA_QM_4_BASE 0x7FFC420000ull +#define DMA_QM_4_MAX_OFFSET 0x310 +#define DMA_QM_4_SECTION 0x1000 +#define mmDMA_CH_4_BASE 0x7FFC421000ull +#define DMA_CH_4_MAX_OFFSET 0x200 +#define DMA_CH_4_SECTION 0x20000 +#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x218 +#define CPU_CA53_CFG_SECTION 0x1000 +#define mmCPU_IF_BASE 0x7FFC442000ull +#define CPU_IF_MAX_OFFSET 0x134 +#define CPU_IF_SECTION 0x2000 +#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x3C000 +#define mmMMU_BASE 0x7FFC480000ull +#define MMU_MAX_OFFSET 0x44 +#define MMU_SECTION 0x10000 +#define mmSTLB_BASE 0x7FFC490000ull +#define STLB_MAX_OFFSET 0x50 +#define STLB_SECTION 0x10000 +#define mmNORTH_THERMAL_SENSOR_BASE 0x7FFC4A0000ull +#define NORTH_THERMAL_SENSOR_MAX_OFFSET 0xE64 +#define NORTH_THERMAL_SENSOR_SECTION 0x1000 +#define mmMC_PLL_BASE 0x7FFC4A1000ull +#define MC_PLL_MAX_OFFSET 0x444 +#define MC_PLL_SECTION 0x1000 +#define mmCPU_PLL_BASE 0x7FFC4A2000ull +#define CPU_PLL_MAX_OFFSET 0x444 +#define CPU_PLL_SECTION 0x1000 +#define mmIC_PLL_BASE 0x7FFC4A3000ull +#define IC_PLL_MAX_OFFSET 0x444 +#define IC_PLL_SECTION 0x1000 +#define mmDMA_PROCESS_MON_BASE 0x7FFC4A4000ull +#define DMA_PROCESS_MON_MAX_OFFSET 0x4 +#define DMA_PROCESS_MON_SECTION 0xC000 +#define mmDMA_MACRO_BASE 0x7FFC4B0000ull +#define DMA_MACRO_MAX_OFFSET 0x15C +#define DMA_MACRO_SECTION 0x150000 +#define mmDDR_PHY_CH0_BASE 0x7FFC600000ull +#define DDR_PHY_CH0_MAX_OFFSET 0x0 +#define DDR_PHY_CH0_SECTION 0x40000 +#define mmDDR_MC_CH0_BASE 0x7FFC640000ull +#define DDR_MC_CH0_MAX_OFFSET 0xF34 +#define DDR_MC_CH0_SECTION 0x8000 +#define mmDDR_MISC_CH0_BASE 0x7FFC648000ull +#define DDR_MISC_CH0_MAX_OFFSET 0x204 +#define DDR_MISC_CH0_SECTION 0xB8000 +#define mmDDR_PHY_CH1_BASE 0x7FFC700000ull +#define DDR_PHY_CH1_MAX_OFFSET 0x0 +#define DDR_PHY_CH1_SECTION 0x40000 +#define mmDDR_MC_CH1_BASE 0x7FFC740000ull +#define DDR_MC_CH1_MAX_OFFSET 0xF34 +#define DDR_MC_CH1_SECTION 0x8000 +#define mmDDR_MISC_CH1_BASE 0x7FFC748000ull +#define DDR_MISC_CH1_MAX_OFFSET 0x204 +#define DDR_MISC_CH1_SECTION 0xB8000 +#define mmGIC_BASE 0x7FFC800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 +#define mmPCIE_WRAP_BASE 0x7FFCC01000ull +#define PCIE_WRAP_MAX_OFFSET 0xDF4 +#define PCIE_WRAP_SECTION 0x1000 +#define mmPCIE_DBI_BASE 0x7FFCC02000ull +#define PCIE_DBI_MAX_OFFSET 0xC04 +#define PCIE_DBI_SECTION 0x2000 +#define mmPCIE_CORE_BASE 0x7FFCC04000ull +#define PCIE_CORE_MAX_OFFSET 0x9B8 +#define PCIE_CORE_SECTION 0x1000 +#define mmPCIE_DB_CFG_BASE 0x7FFCC05000ull +#define PCIE_DB_CFG_MAX_OFFSET 0xE34 +#define PCIE_DB_CFG_SECTION 0x1000 +#define mmPCIE_DB_CMD_BASE 0x7FFCC06000ull +#define PCIE_DB_CMD_MAX_OFFSET 0x810 +#define PCIE_DB_CMD_SECTION 0x1000 +#define mmPCIE_AUX_BASE 0x7FFCC07000ull +#define PCIE_AUX_MAX_OFFSET 0x9BC +#define PCIE_AUX_SECTION 0x1000 +#define mmPCIE_DB_RSV_BASE 0x7FFCC08000ull +#define PCIE_DB_RSV_MAX_OFFSET 0x800 +#define PCIE_DB_RSV_SECTION 0x8000 +#define mmPCIE_PHY_BASE 0x7FFCC10000ull +#define PCIE_PHY_MAX_OFFSET 0x924 +#define PCIE_PHY_SECTION 0x30000 +#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x100 +#define PSOC_I2C_M0_SECTION 0x1000 +#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x100 +#define PSOC_I2C_M1_SECTION 0x1000 +#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x100 +#define PSOC_I2C_S_SECTION 0x1000 +#define mmPSOC_SPI_BASE 0x7FFCC43000ull +#define PSOC_SPI_MAX_OFFSET 0x100 +#define PSOC_SPI_SECTION 0x1000 +#define mmPSOC_EMMC_BASE 0x7FFCC44000ull +#define PSOC_EMMC_MAX_OFFSET 0xF70 +#define PSOC_EMMC_SECTION 0x1000 +#define mmPSOC_UART_0_BASE 0x7FFCC45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 +#define mmPSOC_UART_1_BASE 0x7FFCC46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 +#define mmPSOC_TIMER_BASE 0x7FFCC47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 +#define mmPSOC_WDOG_BASE 0x7FFCC48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 +#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 +#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x10C +#define PSOC_EFUSE_SECTION 0x1000 +#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xA48 +#define PSOC_GLOBAL_CONF_SECTION 0x1000 +#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 +#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 +#define mmPSOC_BTL_BASE 0x7FFCC4E000ull +#define PSOC_BTL_MAX_OFFSET 0x124 +#define PSOC_BTL_SECTION 0x1000 +#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x0 +#define PSOC_CS_TRACE_SECTION 0x1000 +#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 +#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x1000 +#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 +#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x10C +#define PSOC_DFT_EFUSE_SECTION 0x1000 +#define mmPSOC_PM_BASE 0x7FFCC54000ull +#define PSOC_PM_MAX_OFFSET 0x4 +#define PSOC_PM_SECTION 0x1000 +#define mmPSOC_TS_BASE 0x7FFCC55000ull +#define PSOC_TS_MAX_OFFSET 0xE64 +#define PSOC_TS_SECTION 0xB000 +#define mmPSOC_MII_BASE 0x7FFCC60000ull +#define PSOC_MII_MAX_OFFSET 0x105C +#define PSOC_MII_SECTION 0x10000 +#define mmPSOC_EMMC_PLL_BASE 0x7FFCC70000ull +#define PSOC_EMMC_PLL_MAX_OFFSET 0x444 +#define PSOC_EMMC_PLL_SECTION 0x1000 +#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull +#define PSOC_MME_PLL_MAX_OFFSET 0x444 +#define PSOC_MME_PLL_SECTION 0x1000 +#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull +#define PSOC_PCI_PLL_MAX_OFFSET 0x444 +#define PSOC_PCI_PLL_SECTION 0x6000 +#define mmPSOC_PWM0_BASE 0x7FFCC78000ull +#define PSOC_PWM0_MAX_OFFSET 0x58 +#define PSOC_PWM0_SECTION 0x1000 +#define mmPSOC_PWM1_BASE 0x7FFCC79000ull +#define PSOC_PWM1_MAX_OFFSET 0x58 +#define PSOC_PWM1_SECTION 0x1000 +#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull +#define PSOC_PWM2_MAX_OFFSET 0x58 +#define PSOC_PWM2_SECTION 0x1000 +#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull +#define PSOC_PWM3_MAX_OFFSET 0x58 +#define PSOC_PWM3_SECTION 0x185000 +#define mmTPC0_NRTR_BASE 0x7FFCE00000ull +#define TPC0_NRTR_MAX_OFFSET 0x608 +#define TPC0_NRTR_SECTION 0x1000 +#define mmTPC_PLL_BASE 0x7FFCE01000ull +#define TPC_PLL_MAX_OFFSET 0x444 +#define TPC_PLL_SECTION 0x1000 +#define mmTPC_THEMAL_SENSOR_BASE 0x7FFCE02000ull +#define TPC_THEMAL_SENSOR_MAX_OFFSET 0xE64 +#define TPC_THEMAL_SENSOR_SECTION 0x1000 +#define mmTPC_PROCESS_MON_BASE 0x7FFCE03000ull +#define TPC_PROCESS_MON_MAX_OFFSET 0x4 +#define TPC_PROCESS_MON_SECTION 0x1000 +#define mmTPC0_RD_REGULATOR_BASE 0x7FFCE04000ull +#define TPC0_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC0_RD_REGULATOR_SECTION 0x1000 +#define mmTPC0_WR_REGULATOR_BASE 0x7FFCE05000ull +#define TPC0_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC0_WR_REGULATOR_SECTION 0x1000 +#define mmTPC0_CFG_BASE 0x7FFCE06000ull +#define TPC0_CFG_MAX_OFFSET 0xE30 +#define TPC0_CFG_SECTION 0x2000 +#define mmTPC0_QM_BASE 0x7FFCE08000ull +#define TPC0_QM_MAX_OFFSET 0x310 +#define TPC0_QM_SECTION 0x1000 +#define mmTPC0_CMDQ_BASE 0x7FFCE09000ull +#define TPC0_CMDQ_MAX_OFFSET 0x310 +#define TPC0_CMDQ_SECTION 0x37000 +#define mmTPC1_RTR_BASE 0x7FFCE40000ull +#define TPC1_RTR_MAX_OFFSET 0x608 +#define TPC1_RTR_SECTION 0x4000 +#define mmTPC1_WR_REGULATOR_BASE 0x7FFCE44000ull +#define TPC1_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC1_WR_REGULATOR_SECTION 0x1000 +#define mmTPC1_RD_REGULATOR_BASE 0x7FFCE45000ull +#define TPC1_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC1_RD_REGULATOR_SECTION 0x1000 +#define mmTPC1_CFG_BASE 0x7FFCE46000ull +#define TPC1_CFG_MAX_OFFSET 0xE30 +#define TPC1_CFG_SECTION 0x2000 +#define mmTPC1_QM_BASE 0x7FFCE48000ull +#define TPC1_QM_MAX_OFFSET 0x310 +#define TPC1_QM_SECTION 0x1000 +#define mmTPC1_CMDQ_BASE 0x7FFCE49000ull +#define TPC1_CMDQ_MAX_OFFSET 0x310 +#define TPC1_CMDQ_SECTION 0x37000 +#define mmTPC2_RTR_BASE 0x7FFCE80000ull +#define TPC2_RTR_MAX_OFFSET 0x608 +#define TPC2_RTR_SECTION 0x4000 +#define mmTPC2_RD_REGULATOR_BASE 0x7FFCE84000ull +#define TPC2_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC2_RD_REGULATOR_SECTION 0x1000 +#define mmTPC2_WR_REGULATOR_BASE 0x7FFCE85000ull +#define TPC2_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC2_WR_REGULATOR_SECTION 0x1000 +#define mmTPC2_CFG_BASE 0x7FFCE86000ull +#define TPC2_CFG_MAX_OFFSET 0xE30 +#define TPC2_CFG_SECTION 0x2000 +#define mmTPC2_QM_BASE 0x7FFCE88000ull +#define TPC2_QM_MAX_OFFSET 0x310 +#define TPC2_QM_SECTION 0x1000 +#define mmTPC2_CMDQ_BASE 0x7FFCE89000ull +#define TPC2_CMDQ_MAX_OFFSET 0x310 +#define TPC2_CMDQ_SECTION 0x37000 +#define mmTPC3_RTR_BASE 0x7FFCEC0000ull +#define TPC3_RTR_MAX_OFFSET 0x608 +#define TPC3_RTR_SECTION 0x4000 +#define mmTPC3_RD_REGULATOR_BASE 0x7FFCEC4000ull +#define TPC3_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC3_RD_REGULATOR_SECTION 0x1000 +#define mmTPC3_WR_REGULATOR_BASE 0x7FFCEC5000ull +#define TPC3_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC3_WR_REGULATOR_SECTION 0x1000 +#define mmTPC3_CFG_BASE 0x7FFCEC6000ull +#define TPC3_CFG_MAX_OFFSET 0xE30 +#define TPC3_CFG_SECTION 0x2000 +#define mmTPC3_QM_BASE 0x7FFCEC8000ull +#define TPC3_QM_MAX_OFFSET 0x310 +#define TPC3_QM_SECTION 0x1000 +#define mmTPC3_CMDQ_BASE 0x7FFCEC9000ull +#define TPC3_CMDQ_MAX_OFFSET 0x310 +#define TPC3_CMDQ_SECTION 0x37000 +#define mmTPC4_RTR_BASE 0x7FFCF00000ull +#define TPC4_RTR_MAX_OFFSET 0x608 +#define TPC4_RTR_SECTION 0x4000 +#define mmTPC4_RD_REGULATOR_BASE 0x7FFCF04000ull +#define TPC4_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC4_RD_REGULATOR_SECTION 0x1000 +#define mmTPC4_WR_REGULATOR_BASE 0x7FFCF05000ull +#define TPC4_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC4_WR_REGULATOR_SECTION 0x1000 +#define mmTPC4_CFG_BASE 0x7FFCF06000ull +#define TPC4_CFG_MAX_OFFSET 0xE30 +#define TPC4_CFG_SECTION 0x2000 +#define mmTPC4_QM_BASE 0x7FFCF08000ull +#define TPC4_QM_MAX_OFFSET 0x310 +#define TPC4_QM_SECTION 0x1000 +#define mmTPC4_CMDQ_BASE 0x7FFCF09000ull +#define TPC4_CMDQ_MAX_OFFSET 0x310 +#define TPC4_CMDQ_SECTION 0x37000 +#define mmTPC5_RTR_BASE 0x7FFCF40000ull +#define TPC5_RTR_MAX_OFFSET 0x608 +#define TPC5_RTR_SECTION 0x4000 +#define mmTPC5_RD_REGULATOR_BASE 0x7FFCF44000ull +#define TPC5_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC5_RD_REGULATOR_SECTION 0x1000 +#define mmTPC5_WR_REGULATOR_BASE 0x7FFCF45000ull +#define TPC5_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC5_WR_REGULATOR_SECTION 0x1000 +#define mmTPC5_CFG_BASE 0x7FFCF46000ull +#define TPC5_CFG_MAX_OFFSET 0xE30 +#define TPC5_CFG_SECTION 0x2000 +#define mmTPC5_QM_BASE 0x7FFCF48000ull +#define TPC5_QM_MAX_OFFSET 0x310 +#define TPC5_QM_SECTION 0x1000 +#define mmTPC5_CMDQ_BASE 0x7FFCF49000ull +#define TPC5_CMDQ_MAX_OFFSET 0x310 +#define TPC5_CMDQ_SECTION 0x37000 +#define mmTPC6_RTR_BASE 0x7FFCF80000ull +#define TPC6_RTR_MAX_OFFSET 0x608 +#define TPC6_RTR_SECTION 0x4000 +#define mmTPC6_RD_REGULATOR_BASE 0x7FFCF84000ull +#define TPC6_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC6_RD_REGULATOR_SECTION 0x1000 +#define mmTPC6_WR_REGULATOR_BASE 0x7FFCF85000ull +#define TPC6_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC6_WR_REGULATOR_SECTION 0x1000 +#define mmTPC6_CFG_BASE 0x7FFCF86000ull +#define TPC6_CFG_MAX_OFFSET 0xE30 +#define TPC6_CFG_SECTION 0x2000 +#define mmTPC6_QM_BASE 0x7FFCF88000ull +#define TPC6_QM_MAX_OFFSET 0x310 +#define TPC6_QM_SECTION 0x1000 +#define mmTPC6_CMDQ_BASE 0x7FFCF89000ull +#define TPC6_CMDQ_MAX_OFFSET 0x310 +#define TPC6_CMDQ_SECTION 0x37000 +#define mmTPC7_NRTR_BASE 0x7FFCFC0000ull +#define TPC7_NRTR_MAX_OFFSET 0x608 +#define TPC7_NRTR_SECTION 0x4000 +#define mmTPC7_RD_REGULATOR_BASE 0x7FFCFC4000ull +#define TPC7_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC7_RD_REGULATOR_SECTION 0x1000 +#define mmTPC7_WR_REGULATOR_BASE 0x7FFCFC5000ull +#define TPC7_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC7_WR_REGULATOR_SECTION 0x1000 +#define mmTPC7_CFG_BASE 0x7FFCFC6000ull +#define TPC7_CFG_MAX_OFFSET 0xE30 +#define TPC7_CFG_SECTION 0x2000 +#define mmTPC7_QM_BASE 0x7FFCFC8000ull +#define TPC7_QM_MAX_OFFSET 0x310 +#define TPC7_QM_SECTION 0x1000 +#define mmTPC7_CMDQ_BASE 0x7FFCFC9000ull +#define TPC7_CMDQ_MAX_OFFSET 0x310 +#define TPC7_CMDQ_SECTION 0x1037000 +#define mmMME_TOP_TABLE_BASE 0x7FFE000000ull +#define MME_TOP_TABLE_MAX_OFFSET 0x1000 +#define MME_TOP_TABLE_SECTION 0x1000 +#define mmMME0_RTR_FUNNEL_BASE 0x7FFE001000ull +#define MME0_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME0_RTR_FUNNEL_SECTION 0x40000 +#define mmMME1_RTR_FUNNEL_BASE 0x7FFE041000ull +#define MME1_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME1_RTR_FUNNEL_SECTION 0x1000 +#define mmMME1_SBA_STM_BASE 0x7FFE042000ull +#define MME1_SBA_STM_MAX_OFFSET 0x1000 +#define MME1_SBA_STM_SECTION 0x1000 +#define mmMME1_SBA_CTI_BASE 0x7FFE043000ull +#define MME1_SBA_CTI_MAX_OFFSET 0x1000 +#define MME1_SBA_CTI_SECTION 0x1000 +#define mmMME1_SBA_ETF_BASE 0x7FFE044000ull +#define MME1_SBA_ETF_MAX_OFFSET 0x1000 +#define MME1_SBA_ETF_SECTION 0x1000 +#define mmMME1_SBA_SPMU_BASE 0x7FFE045000ull +#define MME1_SBA_SPMU_MAX_OFFSET 0x1000 +#define MME1_SBA_SPMU_SECTION 0x1000 +#define mmMME1_SBA_CTI0_BASE 0x7FFE046000ull +#define MME1_SBA_CTI0_MAX_OFFSET 0x1000 +#define MME1_SBA_CTI0_SECTION 0x1000 +#define mmMME1_SBA_CTI1_BASE 0x7FFE047000ull +#define MME1_SBA_CTI1_MAX_OFFSET 0x1000 +#define MME1_SBA_CTI1_SECTION 0x1000 +#define mmMME1_SBA_BMON0_BASE 0x7FFE048000ull +#define MME1_SBA_BMON0_MAX_OFFSET 0x1000 +#define MME1_SBA_BMON0_SECTION 0x1000 +#define mmMME1_SBA_BMON1_BASE 0x7FFE049000ull +#define MME1_SBA_BMON1_MAX_OFFSET 0x1000 +#define MME1_SBA_BMON1_SECTION 0x38000 +#define mmMME2_RTR_FUNNEL_BASE 0x7FFE081000ull +#define MME2_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME2_RTR_FUNNEL_SECTION 0x40000 +#define mmMME3_RTR_FUNNEL_BASE 0x7FFE0C1000ull +#define MME3_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME3_RTR_FUNNEL_SECTION 0x1000 +#define mmMME3_SBB_STM_BASE 0x7FFE0C2000ull +#define MME3_SBB_STM_MAX_OFFSET 0x1000 +#define MME3_SBB_STM_SECTION 0x1000 +#define mmMME3_SBB_CTI_BASE 0x7FFE0C3000ull +#define MME3_SBB_CTI_MAX_OFFSET 0x1000 +#define MME3_SBB_CTI_SECTION 0x1000 +#define mmMME3_SBB_ETF_BASE 0x7FFE0C4000ull +#define MME3_SBB_ETF_MAX_OFFSET 0x1000 +#define MME3_SBB_ETF_SECTION 0x1000 +#define mmMME3_SBB_SPMU_BASE 0x7FFE0C5000ull +#define MME3_SBB_SPMU_MAX_OFFSET 0x1000 +#define MME3_SBB_SPMU_SECTION 0x1000 +#define mmMME3_SBB_CTI0_BASE 0x7FFE0C6000ull +#define MME3_SBB_CTI0_MAX_OFFSET 0x1000 +#define MME3_SBB_CTI0_SECTION 0x1000 +#define mmMME3_SBB_CTI1_BASE 0x7FFE0C7000ull +#define MME3_SBB_CTI1_MAX_OFFSET 0x1000 +#define MME3_SBB_CTI1_SECTION 0x1000 +#define mmMME3_SBB_BMON0_BASE 0x7FFE0C8000ull +#define MME3_SBB_BMON0_MAX_OFFSET 0x1000 +#define MME3_SBB_BMON0_SECTION 0x1000 +#define mmMME3_SBB_BMON1_BASE 0x7FFE0C9000ull +#define MME3_SBB_BMON1_MAX_OFFSET 0x1000 +#define MME3_SBB_BMON1_SECTION 0x38000 +#define mmMME4_RTR_FUNNEL_BASE 0x7FFE101000ull +#define MME4_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME4_RTR_FUNNEL_SECTION 0x1000 +#define mmMME4_WACS_STM_BASE 0x7FFE102000ull +#define MME4_WACS_STM_MAX_OFFSET 0x1000 +#define MME4_WACS_STM_SECTION 0x1000 +#define mmMME4_WACS_CTI_BASE 0x7FFE103000ull +#define MME4_WACS_CTI_MAX_OFFSET 0x1000 +#define MME4_WACS_CTI_SECTION 0x1000 +#define mmMME4_WACS_ETF_BASE 0x7FFE104000ull +#define MME4_WACS_ETF_MAX_OFFSET 0x1000 +#define MME4_WACS_ETF_SECTION 0x1000 +#define mmMME4_WACS_SPMU_BASE 0x7FFE105000ull +#define MME4_WACS_SPMU_MAX_OFFSET 0x1000 +#define MME4_WACS_SPMU_SECTION 0x1000 +#define mmMME4_WACS_CTI0_BASE 0x7FFE106000ull +#define MME4_WACS_CTI0_MAX_OFFSET 0x1000 +#define MME4_WACS_CTI0_SECTION 0x1000 +#define mmMME4_WACS_CTI1_BASE 0x7FFE107000ull +#define MME4_WACS_CTI1_MAX_OFFSET 0x1000 +#define MME4_WACS_CTI1_SECTION 0x1000 +#define mmMME4_WACS_BMON0_BASE 0x7FFE108000ull +#define MME4_WACS_BMON0_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON0_SECTION 0x1000 +#define mmMME4_WACS_BMON1_BASE 0x7FFE109000ull +#define MME4_WACS_BMON1_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON1_SECTION 0x1000 +#define mmMME4_WACS_BMON2_BASE 0x7FFE10A000ull +#define MME4_WACS_BMON2_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON2_SECTION 0x1000 +#define mmMME4_WACS_BMON3_BASE 0x7FFE10B000ull +#define MME4_WACS_BMON3_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON3_SECTION 0x1000 +#define mmMME4_WACS_BMON4_BASE 0x7FFE10C000ull +#define MME4_WACS_BMON4_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON4_SECTION 0x1000 +#define mmMME4_WACS_BMON5_BASE 0x7FFE10D000ull +#define MME4_WACS_BMON5_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON5_SECTION 0x1000 +#define mmMME4_WACS_BMON6_BASE 0x7FFE10E000ull +#define MME4_WACS_BMON6_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON6_SECTION 0x4000 +#define mmMME4_WACS2_STM_BASE 0x7FFE112000ull +#define MME4_WACS2_STM_MAX_OFFSET 0x1000 +#define MME4_WACS2_STM_SECTION 0x1000 +#define mmMME4_WACS2_CTI_BASE 0x7FFE113000ull +#define MME4_WACS2_CTI_MAX_OFFSET 0x1000 +#define MME4_WACS2_CTI_SECTION 0x1000 +#define mmMME4_WACS2_ETF_BASE 0x7FFE114000ull +#define MME4_WACS2_ETF_MAX_OFFSET 0x1000 +#define MME4_WACS2_ETF_SECTION 0x1000 +#define mmMME4_WACS2_SPMU_BASE 0x7FFE115000ull +#define MME4_WACS2_SPMU_MAX_OFFSET 0x1000 +#define MME4_WACS2_SPMU_SECTION 0x1000 +#define mmMME4_WACS2_CTI0_BASE 0x7FFE116000ull +#define MME4_WACS2_CTI0_MAX_OFFSET 0x1000 +#define MME4_WACS2_CTI0_SECTION 0x1000 +#define mmMME4_WACS2_CTI1_BASE 0x7FFE117000ull +#define MME4_WACS2_CTI1_MAX_OFFSET 0x1000 +#define MME4_WACS2_CTI1_SECTION 0x1000 +#define mmMME4_WACS2_BMON0_BASE 0x7FFE118000ull +#define MME4_WACS2_BMON0_MAX_OFFSET 0x1000 +#define MME4_WACS2_BMON0_SECTION 0x1000 +#define mmMME4_WACS2_BMON1_BASE 0x7FFE119000ull +#define MME4_WACS2_BMON1_MAX_OFFSET 0x1000 +#define MME4_WACS2_BMON1_SECTION 0x1000 +#define mmMME4_WACS2_BMON2_BASE 0x7FFE11A000ull +#define MME4_WACS2_BMON2_MAX_OFFSET 0x1000 +#define MME4_WACS2_BMON2_SECTION 0x27000 +#define mmMME5_RTR_FUNNEL_BASE 0x7FFE141000ull +#define MME5_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME5_RTR_FUNNEL_SECTION 0x2BF000 +#define mmDMA_ROM_TABLE_BASE 0x7FFE400000ull +#define DMA_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_ROM_TABLE_SECTION 0x1000 +#define mmDMA_CH_0_CS_STM_BASE 0x7FFE401000ull +#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_STM_SECTION 0x1000 +#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE402000ull +#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE403000ull +#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE404000ull +#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE405000ull +#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE406000ull +#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_0_BMON_0_BASE 0x7FFE407000ull +#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_0_SECTION 0x1000 +#define mmDMA_CH_0_BMON_1_BASE 0x7FFE408000ull +#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_1_SECTION 0x9000 +#define mmDMA_CH_1_CS_STM_BASE 0x7FFE411000ull +#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_STM_SECTION 0x1000 +#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE412000ull +#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE413000ull +#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE414000ull +#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE415000ull +#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE416000ull +#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_1_BMON_0_BASE 0x7FFE417000ull +#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_0_SECTION 0x1000 +#define mmDMA_CH_1_BMON_1_BASE 0x7FFE418000ull +#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_1_SECTION 0x9000 +#define mmDMA_CH_2_CS_STM_BASE 0x7FFE421000ull +#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_STM_SECTION 0x1000 +#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE422000ull +#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE423000ull +#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE424000ull +#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE425000ull +#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE426000ull +#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_2_BMON_0_BASE 0x7FFE427000ull +#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_0_SECTION 0x1000 +#define mmDMA_CH_2_BMON_1_BASE 0x7FFE428000ull +#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_1_SECTION 0x9000 +#define mmDMA_CH_3_CS_STM_BASE 0x7FFE431000ull +#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_STM_SECTION 0x1000 +#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE432000ull +#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE433000ull +#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE434000ull +#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE435000ull +#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE436000ull +#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_3_BMON_0_BASE 0x7FFE437000ull +#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_0_SECTION 0x1000 +#define mmDMA_CH_3_BMON_1_BASE 0x7FFE438000ull +#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_1_SECTION 0x9000 +#define mmDMA_CH_4_CS_STM_BASE 0x7FFE441000ull +#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_STM_SECTION 0x1000 +#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE442000ull +#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE443000ull +#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE444000ull +#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE445000ull +#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE446000ull +#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_4_BMON_0_BASE 0x7FFE447000ull +#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_0_SECTION 0x1000 +#define mmDMA_CH_4_BMON_1_BASE 0x7FFE448000ull +#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_1_SECTION 0x8000 +#define mmDMA_CH_FUNNEL_6_1_BASE 0x7FFE450000ull +#define DMA_CH_FUNNEL_6_1_MAX_OFFSET 0x1000 +#define DMA_CH_FUNNEL_6_1_SECTION 0x11000 +#define mmDMA_MACRO_CS_STM_BASE 0x7FFE461000ull +#define DMA_MACRO_CS_STM_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_STM_SECTION 0x1000 +#define mmDMA_MACRO_CS_CTI_BASE 0x7FFE462000ull +#define DMA_MACRO_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_CTI_SECTION 0x1000 +#define mmDMA_MACRO_CS_ETF_BASE 0x7FFE463000ull +#define DMA_MACRO_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_ETF_SECTION 0x1000 +#define mmDMA_MACRO_CS_SPMU_BASE 0x7FFE464000ull +#define DMA_MACRO_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_SPMU_SECTION 0x1000 +#define mmDMA_MACRO_BMON_CTI_BASE 0x7FFE465000ull +#define DMA_MACRO_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_CTI_SECTION 0x1000 +#define mmDMA_MACRO_USER_CTI_BASE 0x7FFE466000ull +#define DMA_MACRO_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_MACRO_USER_CTI_SECTION 0x1000 +#define mmDMA_MACRO_BMON_0_BASE 0x7FFE467000ull +#define DMA_MACRO_BMON_0_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_0_SECTION 0x1000 +#define mmDMA_MACRO_BMON_1_BASE 0x7FFE468000ull +#define DMA_MACRO_BMON_1_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_1_SECTION 0x1000 +#define mmDMA_MACRO_BMON_2_BASE 0x7FFE469000ull +#define DMA_MACRO_BMON_2_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_2_SECTION 0x1000 +#define mmDMA_MACRO_BMON_3_BASE 0x7FFE46A000ull +#define DMA_MACRO_BMON_3_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_3_SECTION 0x1000 +#define mmDMA_MACRO_BMON_4_BASE 0x7FFE46B000ull +#define DMA_MACRO_BMON_4_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_4_SECTION 0x1000 +#define mmDMA_MACRO_BMON_5_BASE 0x7FFE46C000ull +#define DMA_MACRO_BMON_5_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_5_SECTION 0x1000 +#define mmDMA_MACRO_BMON_6_BASE 0x7FFE46D000ull +#define DMA_MACRO_BMON_6_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_6_SECTION 0x1000 +#define mmDMA_MACRO_BMON_7_BASE 0x7FFE46E000ull +#define DMA_MACRO_BMON_7_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_7_SECTION 0x2000 +#define mmDMA_MACRO_FUNNEL_3_1_BASE 0x7FFE470000ull +#define DMA_MACRO_FUNNEL_3_1_MAX_OFFSET 0x1000 +#define DMA_MACRO_FUNNEL_3_1_SECTION 0x10000 +#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull +#define CPU_ROM_TABLE_MAX_OFFSET 0x1000 +#define CPU_ROM_TABLE_SECTION 0x1000 +#define mmCPU_ETF_0_BASE 0x7FFE481000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 +#define mmCPU_ETF_1_BASE 0x7FFE482000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 +#define mmCPU_CTI_BASE 0x7FFE484000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 +#define mmCPU_FUNNEL_BASE 0x7FFE485000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 +#define mmCPU_STM_BASE 0x7FFE486000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 +#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 +#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 +#define mmCPU_WR_BMON_BASE 0x7FFE489000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 +#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x37000 +#define mmMMU_CS_STM_BASE 0x7FFE4C1000ull +#define MMU_CS_STM_MAX_OFFSET 0x1000 +#define MMU_CS_STM_SECTION 0x1000 +#define mmMMU_CS_CTI_BASE 0x7FFE4C2000ull +#define MMU_CS_CTI_MAX_OFFSET 0x1000 +#define MMU_CS_CTI_SECTION 0x1000 +#define mmMMU_CS_ETF_BASE 0x7FFE4C3000ull +#define MMU_CS_ETF_MAX_OFFSET 0x1000 +#define MMU_CS_ETF_SECTION 0x1000 +#define mmMMU_CS_SPMU_BASE 0x7FFE4C4000ull +#define MMU_CS_SPMU_MAX_OFFSET 0x1000 +#define MMU_CS_SPMU_SECTION 0x1000 +#define mmMMU_BMON_CTI_BASE 0x7FFE4C5000ull +#define MMU_BMON_CTI_MAX_OFFSET 0x1000 +#define MMU_BMON_CTI_SECTION 0x1000 +#define mmMMU_USER_CTI_BASE 0x7FFE4C6000ull +#define MMU_USER_CTI_MAX_OFFSET 0x1000 +#define MMU_USER_CTI_SECTION 0x1000 +#define mmMMU_BMON_0_BASE 0x7FFE4C7000ull +#define MMU_BMON_0_MAX_OFFSET 0x1000 +#define MMU_BMON_0_SECTION 0x1000 +#define mmMMU_BMON_1_BASE 0x7FFE4C8000ull +#define MMU_BMON_1_MAX_OFFSET 0x1000 +#define MMU_BMON_1_SECTION 0x338000 +#define mmCA53_BASE 0x7FFE800000ull +#define CA53_MAX_OFFSET 0x1000 +#define CA53_SECTION 0x400000 +#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 +#define mmPCIE_STM_BASE 0x7FFEC01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 +#define mmPCIE_ETF_BASE 0x7FFEC02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 +#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 +#define mmPCIE_SPMU_BASE 0x7FFEC04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 +#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x1000 +#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull +#define PCIE_FUNNEL_MAX_OFFSET 0x1000 +#define PCIE_FUNNEL_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 +#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 +#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x36000 +#define mmPSOC_CTI_BASE 0x7FFEC40000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 +#define mmPSOC_STM_BASE 0x7FFEC41000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 +#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 +#define mmPSOC_ETR_BASE 0x7FFEC43000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 +#define mmPSOC_ETF_BASE 0x7FFEC44000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 +#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xB000 +#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x1F0000 +#define mmTPC1_RTR_FUNNEL_BASE 0x7FFEE40000ull +#define TPC1_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC1_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC2_RTR_FUNNEL_BASE 0x7FFEE80000ull +#define TPC2_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC2_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC3_RTR_FUNNEL_BASE 0x7FFEEC0000ull +#define TPC3_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC3_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC4_RTR_FUNNEL_BASE 0x7FFEF00000ull +#define TPC4_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC4_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC5_RTR_FUNNEL_BASE 0x7FFEF40000ull +#define TPC5_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC5_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC6_RTR_FUNNEL_BASE 0x7FFEF80000ull +#define TPC6_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC6_RTR_FUNNEL_SECTION 0x81000 +#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull +#define TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC0_EML_SPMU_SECTION 0x1000 +#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull +#define TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define TPC0_EML_ETF_SECTION 0x1000 +#define mmTPC0_EML_STM_BASE 0x7FFF003000ull +#define TPC0_EML_STM_MAX_OFFSET 0x1000 +#define TPC0_EML_STM_SECTION 0x1000 +#define mmTPC0_EML_ETM_R4_BASE 0x7FFF004000ull +#define TPC0_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC0_EML_ETM_R4_SECTION 0x1000 +#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull +#define TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define TPC0_EML_CTI_SECTION 0x1000 +#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull +#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull +#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull +#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull +#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull +#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull +#define TPC0_EML_CFG_MAX_OFFSET 0x338 +#define TPC0_EML_CFG_SECTION 0x1BF000 +#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull +#define TPC0_EML_CS_MAX_OFFSET 0x1000 +#define TPC0_EML_CS_SECTION 0x2000 +#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull +#define TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC1_EML_SPMU_SECTION 0x1000 +#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull +#define TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define TPC1_EML_ETF_SECTION 0x1000 +#define mmTPC1_EML_STM_BASE 0x7FFF203000ull +#define TPC1_EML_STM_MAX_OFFSET 0x1000 +#define TPC1_EML_STM_SECTION 0x1000 +#define mmTPC1_EML_ETM_R4_BASE 0x7FFF204000ull +#define TPC1_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC1_EML_ETM_R4_SECTION 0x1000 +#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull +#define TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define TPC1_EML_CTI_SECTION 0x1000 +#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull +#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull +#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull +#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull +#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull +#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull +#define TPC1_EML_CFG_MAX_OFFSET 0x338 +#define TPC1_EML_CFG_SECTION 0x1BF000 +#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull +#define TPC1_EML_CS_MAX_OFFSET 0x1000 +#define TPC1_EML_CS_SECTION 0x2000 +#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull +#define TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC2_EML_SPMU_SECTION 0x1000 +#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull +#define TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define TPC2_EML_ETF_SECTION 0x1000 +#define mmTPC2_EML_STM_BASE 0x7FFF403000ull +#define TPC2_EML_STM_MAX_OFFSET 0x1000 +#define TPC2_EML_STM_SECTION 0x1000 +#define mmTPC2_EML_ETM_R4_BASE 0x7FFF404000ull +#define TPC2_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC2_EML_ETM_R4_SECTION 0x1000 +#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull +#define TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define TPC2_EML_CTI_SECTION 0x1000 +#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull +#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull +#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull +#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull +#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull +#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull +#define TPC2_EML_CFG_MAX_OFFSET 0x338 +#define TPC2_EML_CFG_SECTION 0x1BF000 +#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull +#define TPC2_EML_CS_MAX_OFFSET 0x1000 +#define TPC2_EML_CS_SECTION 0x2000 +#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull +#define TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC3_EML_SPMU_SECTION 0x1000 +#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull +#define TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define TPC3_EML_ETF_SECTION 0x1000 +#define mmTPC3_EML_STM_BASE 0x7FFF603000ull +#define TPC3_EML_STM_MAX_OFFSET 0x1000 +#define TPC3_EML_STM_SECTION 0x1000 +#define mmTPC3_EML_ETM_R4_BASE 0x7FFF604000ull +#define TPC3_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC3_EML_ETM_R4_SECTION 0x1000 +#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull +#define TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define TPC3_EML_CTI_SECTION 0x1000 +#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull +#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull +#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull +#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull +#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull +#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull +#define TPC3_EML_CFG_MAX_OFFSET 0x338 +#define TPC3_EML_CFG_SECTION 0x1BF000 +#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull +#define TPC3_EML_CS_MAX_OFFSET 0x1000 +#define TPC3_EML_CS_SECTION 0x2000 +#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull +#define TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC4_EML_SPMU_SECTION 0x1000 +#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull +#define TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define TPC4_EML_ETF_SECTION 0x1000 +#define mmTPC4_EML_STM_BASE 0x7FFF803000ull +#define TPC4_EML_STM_MAX_OFFSET 0x1000 +#define TPC4_EML_STM_SECTION 0x1000 +#define mmTPC4_EML_ETM_R4_BASE 0x7FFF804000ull +#define TPC4_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC4_EML_ETM_R4_SECTION 0x1000 +#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull +#define TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define TPC4_EML_CTI_SECTION 0x1000 +#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull +#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull +#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull +#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull +#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull +#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull +#define TPC4_EML_CFG_MAX_OFFSET 0x338 +#define TPC4_EML_CFG_SECTION 0x1BF000 +#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull +#define TPC4_EML_CS_MAX_OFFSET 0x1000 +#define TPC4_EML_CS_SECTION 0x2000 +#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull +#define TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC5_EML_SPMU_SECTION 0x1000 +#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull +#define TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define TPC5_EML_ETF_SECTION 0x1000 +#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull +#define TPC5_EML_STM_MAX_OFFSET 0x1000 +#define TPC5_EML_STM_SECTION 0x1000 +#define mmTPC5_EML_ETM_R4_BASE 0x7FFFA04000ull +#define TPC5_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC5_EML_ETM_R4_SECTION 0x1000 +#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull +#define TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define TPC5_EML_CTI_SECTION 0x1000 +#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull +#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull +#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull +#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull +#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull +#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull +#define TPC5_EML_CFG_MAX_OFFSET 0x338 +#define TPC5_EML_CFG_SECTION 0x1BF000 +#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull +#define TPC5_EML_CS_MAX_OFFSET 0x1000 +#define TPC5_EML_CS_SECTION 0x2000 +#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull +#define TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC6_EML_SPMU_SECTION 0x1000 +#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull +#define TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define TPC6_EML_ETF_SECTION 0x1000 +#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull +#define TPC6_EML_STM_MAX_OFFSET 0x1000 +#define TPC6_EML_STM_SECTION 0x1000 +#define mmTPC6_EML_ETM_R4_BASE 0x7FFFC04000ull +#define TPC6_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC6_EML_ETM_R4_SECTION 0x1000 +#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull +#define TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define TPC6_EML_CTI_SECTION 0x1000 +#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull +#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC6_EML_FUNNEL_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull +#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull +#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull +#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull +#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull +#define TPC6_EML_CFG_MAX_OFFSET 0x338 +#define TPC6_EML_CFG_SECTION 0x1BF000 +#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull +#define TPC6_EML_CS_MAX_OFFSET 0x1000 +#define TPC6_EML_CS_SECTION 0x2000 +#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull +#define TPC7_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC7_EML_SPMU_SECTION 0x1000 +#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull +#define TPC7_EML_ETF_MAX_OFFSET 0x1000 +#define TPC7_EML_ETF_SECTION 0x1000 +#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull +#define TPC7_EML_STM_MAX_OFFSET 0x1000 +#define TPC7_EML_STM_SECTION 0x1000 +#define mmTPC7_EML_ETM_R4_BASE 0x7FFFE04000ull +#define TPC7_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC7_EML_ETM_R4_SECTION 0x1000 +#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull +#define TPC7_EML_CTI_MAX_OFFSET 0x1000 +#define TPC7_EML_CTI_SECTION 0x1000 +#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull +#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC7_EML_FUNNEL_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull +#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull +#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull +#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull +#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull +#define TPC7_EML_CFG_MAX_OFFSET 0x338 +#define TPC7_EML_CFG_SECTION 0x1BF000 +#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull +#define TPC7_EML_CS_MAX_OFFSET 0x1000 + +#endif /* GOYA_BLOCKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h new file mode 100644 index 000000000000..a161ecfe74de --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GOYA_MASKS_H_ +#define ASIC_REG_GOYA_MASKS_H_ + +#include "goya_regs.h" + +/* Useful masks for bits in various registers */ +#define QMAN_DMA_ENABLE (\ + (1 << DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT)) + +#define QMAN_DMA_FULLY_TRUSTED (\ + (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define QMAN_DMA_PARTLY_TRUSTED (\ + (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define QMAN_DMA_STOP (\ + (1 << DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT)) + +#define QMAN_DMA_IS_STOPPED (\ + (1 << DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT)) + +#define QMAN_DMA_ERR_MSG_EN (\ + (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define QMAN_MME_ENABLE (\ + (1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (1 << MME_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << MME_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define CMDQ_MME_ENABLE (\ + (1 << MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_MME_STOP (\ + (1 << MME_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \ + (1 << MME_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << MME_QM_GLBL_CFG1_CP_STOP_SHIFT)) + +#define CMDQ_MME_STOP (\ + (1 << MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT)) + +#define QMAN_MME_ERR_MSG_EN (\ + (1 << MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define CMDQ_MME_ERR_MSG_EN (\ + (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define QMAN_MME_ERR_PROT (\ + (1 << MME_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << MME_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << MME_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << MME_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define CMDQ_MME_ERR_PROT (\ + (1 << MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define QMAN_TPC_ENABLE (\ + (1 << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define CMDQ_TPC_ENABLE (\ + (1 << TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_TPC_STOP (\ + (1 << TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT)) + +#define CMDQ_TPC_STOP (\ + (1 << TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT)) + +#define QMAN_TPC_ERR_MSG_EN (\ + (1 << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define CMDQ_TPC_ERR_MSG_EN (\ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define QMAN_TPC_ERR_PROT (\ + (1 << TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define CMDQ_TPC_ERR_PROT (\ + (1 << TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +/* RESETS */ +#define DMA_MME_TPC_RESET (\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT) + +#define RESET_ALL (\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT |\ + PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT) + +#define CA53_RESET (\ + (~\ + (1 << PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT)\ + ) & 0x7FFFFF) + +#define CPU_RESET_ASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +#define CPU_RESET_CORE0_DEASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +/* PCI CONFIGURATION SPACE */ +#define mmPCI_CONFIG_ELBI_ADDR 0xFF0 +#define mmPCI_CONFIG_ELBI_DATA 0xFF4 +#define mmPCI_CONFIG_ELBI_CTRL 0xFF8 +#define PCI_CONFIG_ELBI_CTRL_WRITE (1 << 31) + +#define mmPCI_CONFIG_ELBI_STS 0xFFC +#define PCI_CONFIG_ELBI_STS_ERR (1 << 30) +#define PCI_CONFIG_ELBI_STS_DONE (1 << 31) +#define PCI_CONFIG_ELBI_STS_MASK (PCI_CONFIG_ELBI_STS_ERR | \ + PCI_CONFIG_ELBI_STS_DONE) + +#define GOYA_IRQ_HBW_ID_MASK 0x1FFF +#define GOYA_IRQ_HBW_ID_SHIFT 0 +#define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000 +#define GOYA_IRQ_HBW_INTERNAL_ID_SHIFT 13 +#define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000 +#define GOYA_IRQ_HBW_AGENT_ID_SHIFT 16 +#define GOYA_IRQ_HBW_Y_MASK 0xE00000 +#define GOYA_IRQ_HBW_Y_SHIFT 21 +#define GOYA_IRQ_HBW_X_MASK 0x7000000 +#define GOYA_IRQ_HBW_X_SHIFT 24 +#define GOYA_IRQ_LBW_ID_MASK 0xFF +#define GOYA_IRQ_LBW_ID_SHIFT 0 +#define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700 +#define GOYA_IRQ_LBW_INTERNAL_ID_SHIFT 8 +#define GOYA_IRQ_LBW_AGENT_ID_MASK 0xF800 +#define GOYA_IRQ_LBW_AGENT_ID_SHIFT 11 +#define GOYA_IRQ_LBW_Y_MASK 0x70000 +#define GOYA_IRQ_LBW_Y_SHIFT 16 +#define GOYA_IRQ_LBW_X_MASK 0x380000 +#define GOYA_IRQ_LBW_X_SHIFT 19 + +#define DMA_QM_IDLE_MASK (DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK | \ + DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK | \ + DMA_QM_0_GLBL_STS0_CP_IDLE_MASK | \ + DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK) + +#define TPC_QM_IDLE_MASK (TPC0_QM_GLBL_STS0_PQF_IDLE_MASK | \ + TPC0_QM_GLBL_STS0_CQF_IDLE_MASK | \ + TPC0_QM_GLBL_STS0_CP_IDLE_MASK) + +#define TPC_CMDQ_IDLE_MASK (TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \ + TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK) + +#define TPC_CFG_IDLE_MASK (TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \ + TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \ + TPC0_CFG_STATUS_IQ_EMPTY_MASK | \ + TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK) + +#define MME_QM_IDLE_MASK (MME_QM_GLBL_STS0_PQF_IDLE_MASK | \ + MME_QM_GLBL_STS0_CQF_IDLE_MASK | \ + MME_QM_GLBL_STS0_CP_IDLE_MASK) + +#define MME_CMDQ_IDLE_MASK (MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \ + MME_CMDQ_GLBL_STS0_CP_IDLE_MASK) + +#define MME_ARCH_IDLE_MASK (MME_ARCH_STATUS_SB_A_EMPTY_MASK | \ + MME_ARCH_STATUS_SB_B_EMPTY_MASK | \ + MME_ARCH_STATUS_SB_CIN_EMPTY_MASK | \ + MME_ARCH_STATUS_SB_COUT_EMPTY_MASK) + +#define MME_SHADOW_IDLE_MASK (MME_SHADOW_0_STATUS_A_MASK | \ + MME_SHADOW_0_STATUS_B_MASK | \ + MME_SHADOW_0_STATUS_CIN_MASK | \ + MME_SHADOW_0_STATUS_COUT_MASK | \ + MME_SHADOW_0_STATUS_TE_MASK | \ + MME_SHADOW_0_STATUS_LD_MASK | \ + MME_SHADOW_0_STATUS_ST_MASK) + +#define TPC1_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC2_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC3_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC4_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC5_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC6_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC7_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT + +#define DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT +#define DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT +#define DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT +#define DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT + +#endif /* ASIC_REG_GOYA_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h new file mode 100644 index 000000000000..6cb0b6e54d41 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GOYA_REGS_H_ +#define ASIC_REG_GOYA_REGS_H_ + +#include "goya_blocks.h" +#include "stlb_regs.h" +#include "mmu_regs.h" +#include "pcie_aux_regs.h" +#include "psoc_global_conf_regs.h" +#include "psoc_spi_regs.h" +#include "psoc_mme_pll_regs.h" +#include "psoc_pci_pll_regs.h" +#include "psoc_emmc_pll_regs.h" +#include "cpu_if_regs.h" +#include "cpu_ca53_cfg_regs.h" +#include "cpu_pll_regs.h" +#include "ic_pll_regs.h" +#include "mc_pll_regs.h" +#include "tpc_pll_regs.h" +#include "dma_qm_0_regs.h" +#include "dma_qm_1_regs.h" +#include "dma_qm_2_regs.h" +#include "dma_qm_3_regs.h" +#include "dma_qm_4_regs.h" +#include "dma_ch_0_regs.h" +#include "dma_ch_1_regs.h" +#include "dma_ch_2_regs.h" +#include "dma_ch_3_regs.h" +#include "dma_ch_4_regs.h" +#include "dma_macro_regs.h" +#include "dma_nrtr_regs.h" +#include "pci_nrtr_regs.h" +#include "sram_y0_x0_rtr_regs.h" +#include "sram_y0_x1_rtr_regs.h" +#include "sram_y0_x2_rtr_regs.h" +#include "sram_y0_x3_rtr_regs.h" +#include "sram_y0_x4_rtr_regs.h" +#include "mme_regs.h" +#include "mme_qm_regs.h" +#include "mme_cmdq_regs.h" +#include "mme1_rtr_regs.h" +#include "mme2_rtr_regs.h" +#include "mme3_rtr_regs.h" +#include "mme4_rtr_regs.h" +#include "mme5_rtr_regs.h" +#include "mme6_rtr_regs.h" +#include "tpc0_cfg_regs.h" +#include "tpc1_cfg_regs.h" +#include "tpc2_cfg_regs.h" +#include "tpc3_cfg_regs.h" +#include "tpc4_cfg_regs.h" +#include "tpc5_cfg_regs.h" +#include "tpc6_cfg_regs.h" +#include "tpc7_cfg_regs.h" +#include "tpc0_qm_regs.h" +#include "tpc1_qm_regs.h" +#include "tpc2_qm_regs.h" +#include "tpc3_qm_regs.h" +#include "tpc4_qm_regs.h" +#include "tpc5_qm_regs.h" +#include "tpc6_qm_regs.h" +#include "tpc7_qm_regs.h" +#include "tpc0_cmdq_regs.h" +#include "tpc1_cmdq_regs.h" +#include "tpc2_cmdq_regs.h" +#include "tpc3_cmdq_regs.h" +#include "tpc4_cmdq_regs.h" +#include "tpc5_cmdq_regs.h" +#include "tpc6_cmdq_regs.h" +#include "tpc7_cmdq_regs.h" +#include "tpc0_nrtr_regs.h" +#include "tpc1_rtr_regs.h" +#include "tpc2_rtr_regs.h" +#include "tpc3_rtr_regs.h" +#include "tpc4_rtr_regs.h" +#include "tpc5_rtr_regs.h" +#include "tpc6_rtr_regs.h" +#include "tpc7_nrtr_regs.h" +#include "tpc0_eml_cfg_regs.h" + +#include "psoc_global_conf_masks.h" +#include "dma_macro_masks.h" +#include "dma_qm_0_masks.h" +#include "tpc0_qm_masks.h" +#include "tpc0_cmdq_masks.h" +#include "mme_qm_masks.h" +#include "mme_cmdq_masks.h" +#include "tpc0_cfg_masks.h" +#include "tpc0_eml_cfg_masks.h" +#include "mme1_rtr_masks.h" +#include "tpc0_nrtr_masks.h" +#include "dma_nrtr_masks.h" +#include "pci_nrtr_masks.h" +#include "stlb_masks.h" +#include "cpu_ca53_cfg_masks.h" +#include "mmu_masks.h" +#include "mme_masks.h" + +#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000 +#define mmPCIE_DBI_MSIX_DOORBELL_OFF 0xC02948 + +#define mmSYNC_MNGR_MON_PAY_ADDRL_0 0x113000 +#define mmSYNC_MNGR_SOB_OBJ_0 0x112000 +#define mmSYNC_MNGR_SOB_OBJ_1000 0x112FA0 +#define mmSYNC_MNGR_SOB_OBJ_1007 0x112FBC +#define mmSYNC_MNGR_SOB_OBJ_1023 0x112FFC +#define mmSYNC_MNGR_MON_STATUS_0 0x114000 +#define mmSYNC_MNGR_MON_STATUS_255 0x1143FC + +#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 + +#endif /* ASIC_REG_GOYA_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h new file mode 100644 index 000000000000..0a743817aad7 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_IC_PLL_REGS_H_ +#define ASIC_REG_IC_PLL_REGS_H_ + +/* + ***************************************** + * IC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmIC_PLL_NR 0x4A3100 + +#define mmIC_PLL_NF 0x4A3104 + +#define mmIC_PLL_OD 0x4A3108 + +#define mmIC_PLL_NB 0x4A310C + +#define mmIC_PLL_CFG 0x4A3110 + +#define mmIC_PLL_LOSE_MASK 0x4A3120 + +#define mmIC_PLL_LOCK_INTR 0x4A3128 + +#define mmIC_PLL_LOCK_BYPASS 0x4A312C + +#define mmIC_PLL_DATA_CHNG 0x4A3130 + +#define mmIC_PLL_RST 0x4A3134 + +#define mmIC_PLL_SLIP_WD_CNTR 0x4A3150 + +#define mmIC_PLL_DIV_FACTOR_0 0x4A3200 + +#define mmIC_PLL_DIV_FACTOR_1 0x4A3204 + +#define mmIC_PLL_DIV_FACTOR_2 0x4A3208 + +#define mmIC_PLL_DIV_FACTOR_3 0x4A320C + +#define mmIC_PLL_DIV_FACTOR_CMD_0 0x4A3220 + +#define mmIC_PLL_DIV_FACTOR_CMD_1 0x4A3224 + +#define mmIC_PLL_DIV_FACTOR_CMD_2 0x4A3228 + +#define mmIC_PLL_DIV_FACTOR_CMD_3 0x4A322C + +#define mmIC_PLL_DIV_SEL_0 0x4A3280 + +#define mmIC_PLL_DIV_SEL_1 0x4A3284 + +#define mmIC_PLL_DIV_SEL_2 0x4A3288 + +#define mmIC_PLL_DIV_SEL_3 0x4A328C + +#define mmIC_PLL_DIV_EN_0 0x4A32A0 + +#define mmIC_PLL_DIV_EN_1 0x4A32A4 + +#define mmIC_PLL_DIV_EN_2 0x4A32A8 + +#define mmIC_PLL_DIV_EN_3 0x4A32AC + +#define mmIC_PLL_DIV_FACTOR_BUSY_0 0x4A32C0 + +#define mmIC_PLL_DIV_FACTOR_BUSY_1 0x4A32C4 + +#define mmIC_PLL_DIV_FACTOR_BUSY_2 0x4A32C8 + +#define mmIC_PLL_DIV_FACTOR_BUSY_3 0x4A32CC + +#define mmIC_PLL_CLK_GATER 0x4A3300 + +#define mmIC_PLL_CLK_RLX_0 0x4A3310 + +#define mmIC_PLL_CLK_RLX_1 0x4A3314 + +#define mmIC_PLL_CLK_RLX_2 0x4A3318 + +#define mmIC_PLL_CLK_RLX_3 0x4A331C + +#define mmIC_PLL_REF_CNTR_PERIOD 0x4A3400 + +#define mmIC_PLL_REF_LOW_THRESHOLD 0x4A3410 + +#define mmIC_PLL_REF_HIGH_THRESHOLD 0x4A3420 + +#define mmIC_PLL_PLL_NOT_STABLE 0x4A3430 + +#define mmIC_PLL_FREQ_CALC_EN 0x4A3440 + +#endif /* ASIC_REG_IC_PLL_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h new file mode 100644 index 000000000000..4408188aa067 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MC_PLL_REGS_H_ +#define ASIC_REG_MC_PLL_REGS_H_ + +/* + ***************************************** + * MC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmMC_PLL_NR 0x4A1100 + +#define mmMC_PLL_NF 0x4A1104 + +#define mmMC_PLL_OD 0x4A1108 + +#define mmMC_PLL_NB 0x4A110C + +#define mmMC_PLL_CFG 0x4A1110 + +#define mmMC_PLL_LOSE_MASK 0x4A1120 + +#define mmMC_PLL_LOCK_INTR 0x4A1128 + +#define mmMC_PLL_LOCK_BYPASS 0x4A112C + +#define mmMC_PLL_DATA_CHNG 0x4A1130 + +#define mmMC_PLL_RST 0x4A1134 + +#define mmMC_PLL_SLIP_WD_CNTR 0x4A1150 + +#define mmMC_PLL_DIV_FACTOR_0 0x4A1200 + +#define mmMC_PLL_DIV_FACTOR_1 0x4A1204 + +#define mmMC_PLL_DIV_FACTOR_2 0x4A1208 + +#define mmMC_PLL_DIV_FACTOR_3 0x4A120C + +#define mmMC_PLL_DIV_FACTOR_CMD_0 0x4A1220 + +#define mmMC_PLL_DIV_FACTOR_CMD_1 0x4A1224 + +#define mmMC_PLL_DIV_FACTOR_CMD_2 0x4A1228 + +#define mmMC_PLL_DIV_FACTOR_CMD_3 0x4A122C + +#define mmMC_PLL_DIV_SEL_0 0x4A1280 + +#define mmMC_PLL_DIV_SEL_1 0x4A1284 + +#define mmMC_PLL_DIV_SEL_2 0x4A1288 + +#define mmMC_PLL_DIV_SEL_3 0x4A128C + +#define mmMC_PLL_DIV_EN_0 0x4A12A0 + +#define mmMC_PLL_DIV_EN_1 0x4A12A4 + +#define mmMC_PLL_DIV_EN_2 0x4A12A8 + +#define mmMC_PLL_DIV_EN_3 0x4A12AC + +#define mmMC_PLL_DIV_FACTOR_BUSY_0 0x4A12C0 + +#define mmMC_PLL_DIV_FACTOR_BUSY_1 0x4A12C4 + +#define mmMC_PLL_DIV_FACTOR_BUSY_2 0x4A12C8 + +#define mmMC_PLL_DIV_FACTOR_BUSY_3 0x4A12CC + +#define mmMC_PLL_CLK_GATER 0x4A1300 + +#define mmMC_PLL_CLK_RLX_0 0x4A1310 + +#define mmMC_PLL_CLK_RLX_1 0x4A1314 + +#define mmMC_PLL_CLK_RLX_2 0x4A1318 + +#define mmMC_PLL_CLK_RLX_3 0x4A131C + +#define mmMC_PLL_REF_CNTR_PERIOD 0x4A1400 + +#define mmMC_PLL_REF_LOW_THRESHOLD 0x4A1410 + +#define mmMC_PLL_REF_HIGH_THRESHOLD 0x4A1420 + +#define mmMC_PLL_PLL_NOT_STABLE 0x4A1430 + +#define mmMC_PLL_FREQ_CALC_EN 0x4A1440 + +#endif /* ASIC_REG_MC_PLL_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h new file mode 100644 index 000000000000..687bca5c5fe3 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h @@ -0,0 +1,653 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME1_RTR_MASKS_H_ +#define ASIC_REG_MME1_RTR_MASKS_H_ + +/* + ***************************************** + * MME1_RTR (Prototype: MME_RTR) + ***************************************** + */ + +/* MME1_RTR_HBW_RD_RQ_E_ARB */ +#define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_W_ARB */ +#define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_N_ARB */ +#define MME1_RTR_HBW_RD_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_S_ARB */ +#define MME1_RTR_HBW_RD_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_L_ARB */ +#define MME1_RTR_HBW_RD_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_HBW_E_ARB_MAX */ +#define MME1_RTR_HBW_E_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_E_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_W_ARB_MAX */ +#define MME1_RTR_HBW_W_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_W_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_N_ARB_MAX */ +#define MME1_RTR_HBW_N_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_N_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_S_ARB_MAX */ +#define MME1_RTR_HBW_S_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_S_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_L_ARB_MAX */ +#define MME1_RTR_HBW_L_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_L_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_RD_RS_MAX_CREDIT */ +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_MASK 0x3F +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_MASK 0x3F00 + +/* MME1_RTR_HBW_WR_RQ_MAX_CREDIT */ +#define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_MASK 0x3F + +/* MME1_RTR_HBW_RD_RQ_MAX_CREDIT */ +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_MASK 0x3F +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_MASK 0x3F00 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_MASK 0x3F0000 + +/* MME1_RTR_HBW_RD_RS_E_ARB */ +#define MME1_RTR_HBW_RD_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_W_ARB */ +#define MME1_RTR_HBW_RD_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_N_ARB */ +#define MME1_RTR_HBW_RD_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_S_ARB */ +#define MME1_RTR_HBW_RD_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_L_ARB */ +#define MME1_RTR_HBW_RD_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_E_ARB */ +#define MME1_RTR_HBW_WR_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_W_ARB */ +#define MME1_RTR_HBW_WR_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_N_ARB */ +#define MME1_RTR_HBW_WR_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_S_ARB */ +#define MME1_RTR_HBW_WR_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_L_ARB */ +#define MME1_RTR_HBW_WR_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_E_ARB */ +#define MME1_RTR_HBW_WR_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_W_ARB */ +#define MME1_RTR_HBW_WR_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_N_ARB */ +#define MME1_RTR_HBW_WR_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_S_ARB */ +#define MME1_RTR_HBW_WR_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_L_ARB */ +#define MME1_RTR_HBW_WR_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_E_ARB */ +#define MME1_RTR_LBW_RD_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_W_ARB */ +#define MME1_RTR_LBW_RD_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_N_ARB */ +#define MME1_RTR_LBW_RD_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_S_ARB */ +#define MME1_RTR_LBW_RD_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_L_ARB */ +#define MME1_RTR_LBW_RD_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_E_ARB_MAX */ +#define MME1_RTR_LBW_E_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_E_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_W_ARB_MAX */ +#define MME1_RTR_LBW_W_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_W_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_N_ARB_MAX */ +#define MME1_RTR_LBW_N_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_N_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_S_ARB_MAX */ +#define MME1_RTR_LBW_S_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_S_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_L_ARB_MAX */ +#define MME1_RTR_LBW_L_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_L_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_SRAM_MAX_CREDIT */ +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_SHIFT 0 +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_MASK 0x3F +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_SHIFT 8 +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_MASK 0x3F00 + +/* MME1_RTR_LBW_RD_RS_E_ARB */ +#define MME1_RTR_LBW_RD_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_W_ARB */ +#define MME1_RTR_LBW_RD_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_N_ARB */ +#define MME1_RTR_LBW_RD_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_S_ARB */ +#define MME1_RTR_LBW_RD_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_L_ARB */ +#define MME1_RTR_LBW_RD_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_E_ARB */ +#define MME1_RTR_LBW_WR_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_W_ARB */ +#define MME1_RTR_LBW_WR_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_N_ARB */ +#define MME1_RTR_LBW_WR_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_S_ARB */ +#define MME1_RTR_LBW_WR_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_L_ARB */ +#define MME1_RTR_LBW_WR_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_E_ARB */ +#define MME1_RTR_LBW_WR_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_W_ARB */ +#define MME1_RTR_LBW_WR_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_N_ARB */ +#define MME1_RTR_LBW_WR_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_S_ARB */ +#define MME1_RTR_LBW_WR_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_L_ARB */ +#define MME1_RTR_LBW_WR_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_DBG_E_ARB */ +#define MME1_RTR_DBG_E_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_E_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_E_ARB_S_SHIFT 8 +#define MME1_RTR_DBG_E_ARB_S_MASK 0x700 +#define MME1_RTR_DBG_E_ARB_N_SHIFT 16 +#define MME1_RTR_DBG_E_ARB_N_MASK 0x70000 +#define MME1_RTR_DBG_E_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_W_ARB */ +#define MME1_RTR_DBG_W_ARB_E_SHIFT 0 +#define MME1_RTR_DBG_W_ARB_E_MASK 0x7 +#define MME1_RTR_DBG_W_ARB_S_SHIFT 8 +#define MME1_RTR_DBG_W_ARB_S_MASK 0x700 +#define MME1_RTR_DBG_W_ARB_N_SHIFT 16 +#define MME1_RTR_DBG_W_ARB_N_MASK 0x70000 +#define MME1_RTR_DBG_W_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_N_ARB */ +#define MME1_RTR_DBG_N_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_N_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_N_ARB_E_SHIFT 8 +#define MME1_RTR_DBG_N_ARB_E_MASK 0x700 +#define MME1_RTR_DBG_N_ARB_S_SHIFT 16 +#define MME1_RTR_DBG_N_ARB_S_MASK 0x70000 +#define MME1_RTR_DBG_N_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_S_ARB */ +#define MME1_RTR_DBG_S_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_S_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_S_ARB_E_SHIFT 8 +#define MME1_RTR_DBG_S_ARB_E_MASK 0x700 +#define MME1_RTR_DBG_S_ARB_N_SHIFT 16 +#define MME1_RTR_DBG_S_ARB_N_MASK 0x70000 +#define MME1_RTR_DBG_S_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_L_ARB */ +#define MME1_RTR_DBG_L_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_L_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_L_ARB_E_SHIFT 8 +#define MME1_RTR_DBG_L_ARB_E_MASK 0x700 +#define MME1_RTR_DBG_L_ARB_S_SHIFT 16 +#define MME1_RTR_DBG_L_ARB_S_MASK 0x70000 +#define MME1_RTR_DBG_L_ARB_N_SHIFT 24 +#define MME1_RTR_DBG_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_DBG_E_ARB_MAX */ +#define MME1_RTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_W_ARB_MAX */ +#define MME1_RTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_N_ARB_MAX */ +#define MME1_RTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_S_ARB_MAX */ +#define MME1_RTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_L_ARB_MAX */ +#define MME1_RTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_SPLIT_COEF */ +#define MME1_RTR_SPLIT_COEF_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_CFG */ +#define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 4 +#define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x10 +#define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 5 +#define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x20 +#define MME1_RTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define MME1_RTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* MME1_RTR_SPLIT_RD_SAT */ +#define MME1_RTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_RD_RST_TOKEN */ +#define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_RD_TIMEOUT */ +#define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_SPLIT_WR_SAT */ +#define MME1_RTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* MME1_RTR_WPLIT_WR_TST_TOLEN */ +#define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_WR_TIMEOUT */ +#define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_HBW_RANGE_HIT */ +#define MME1_RTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define MME1_RTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* MME1_RTR_HBW_RANGE_MASK_L */ +#define MME1_RTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_HBW_RANGE_MASK_H */ +#define MME1_RTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* MME1_RTR_HBW_RANGE_BASE_L */ +#define MME1_RTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_HBW_RANGE_BASE_H */ +#define MME1_RTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* MME1_RTR_LBW_RANGE_HIT */ +#define MME1_RTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define MME1_RTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* MME1_RTR_LBW_RANGE_MASK */ +#define MME1_RTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define MME1_RTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* MME1_RTR_LBW_RANGE_BASE */ +#define MME1_RTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define MME1_RTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* MME1_RTR_RGLTR */ +#define MME1_RTR_RGLTR_WR_EN_SHIFT 0 +#define MME1_RTR_RGLTR_WR_EN_MASK 0x1 +#define MME1_RTR_RGLTR_RD_EN_SHIFT 4 +#define MME1_RTR_RGLTR_RD_EN_MASK 0x10 + +/* MME1_RTR_RGLTR_WR_RESULT */ +#define MME1_RTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define MME1_RTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* MME1_RTR_RGLTR_RD_RESULT */ +#define MME1_RTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define MME1_RTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* MME1_RTR_SCRAMB_EN */ +#define MME1_RTR_SCRAMB_EN_VAL_SHIFT 0 +#define MME1_RTR_SCRAMB_EN_VAL_MASK 0x1 + +/* MME1_RTR_NON_LIN_SCRAMB */ +#define MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define MME1_RTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_MME1_RTR_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h new file mode 100644 index 000000000000..c248339a1cbe --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME1_RTR_REGS_H_ +#define ASIC_REG_MME1_RTR_REGS_H_ + +/* + ***************************************** + * MME1_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME1_RTR_HBW_RD_RQ_E_ARB 0x40100 + +#define mmMME1_RTR_HBW_RD_RQ_W_ARB 0x40104 + +#define mmMME1_RTR_HBW_RD_RQ_N_ARB 0x40108 + +#define mmMME1_RTR_HBW_RD_RQ_S_ARB 0x4010C + +#define mmMME1_RTR_HBW_RD_RQ_L_ARB 0x40110 + +#define mmMME1_RTR_HBW_E_ARB_MAX 0x40120 + +#define mmMME1_RTR_HBW_W_ARB_MAX 0x40124 + +#define mmMME1_RTR_HBW_N_ARB_MAX 0x40128 + +#define mmMME1_RTR_HBW_S_ARB_MAX 0x4012C + +#define mmMME1_RTR_HBW_L_ARB_MAX 0x40130 + +#define mmMME1_RTR_HBW_RD_RS_MAX_CREDIT 0x40140 + +#define mmMME1_RTR_HBW_WR_RQ_MAX_CREDIT 0x40144 + +#define mmMME1_RTR_HBW_RD_RQ_MAX_CREDIT 0x40148 + +#define mmMME1_RTR_HBW_RD_RS_E_ARB 0x40150 + +#define mmMME1_RTR_HBW_RD_RS_W_ARB 0x40154 + +#define mmMME1_RTR_HBW_RD_RS_N_ARB 0x40158 + +#define mmMME1_RTR_HBW_RD_RS_S_ARB 0x4015C + +#define mmMME1_RTR_HBW_RD_RS_L_ARB 0x40160 + +#define mmMME1_RTR_HBW_WR_RQ_E_ARB 0x40170 + +#define mmMME1_RTR_HBW_WR_RQ_W_ARB 0x40174 + +#define mmMME1_RTR_HBW_WR_RQ_N_ARB 0x40178 + +#define mmMME1_RTR_HBW_WR_RQ_S_ARB 0x4017C + +#define mmMME1_RTR_HBW_WR_RQ_L_ARB 0x40180 + +#define mmMME1_RTR_HBW_WR_RS_E_ARB 0x40190 + +#define mmMME1_RTR_HBW_WR_RS_W_ARB 0x40194 + +#define mmMME1_RTR_HBW_WR_RS_N_ARB 0x40198 + +#define mmMME1_RTR_HBW_WR_RS_S_ARB 0x4019C + +#define mmMME1_RTR_HBW_WR_RS_L_ARB 0x401A0 + +#define mmMME1_RTR_LBW_RD_RQ_E_ARB 0x40200 + +#define mmMME1_RTR_LBW_RD_RQ_W_ARB 0x40204 + +#define mmMME1_RTR_LBW_RD_RQ_N_ARB 0x40208 + +#define mmMME1_RTR_LBW_RD_RQ_S_ARB 0x4020C + +#define mmMME1_RTR_LBW_RD_RQ_L_ARB 0x40210 + +#define mmMME1_RTR_LBW_E_ARB_MAX 0x40220 + +#define mmMME1_RTR_LBW_W_ARB_MAX 0x40224 + +#define mmMME1_RTR_LBW_N_ARB_MAX 0x40228 + +#define mmMME1_RTR_LBW_S_ARB_MAX 0x4022C + +#define mmMME1_RTR_LBW_L_ARB_MAX 0x40230 + +#define mmMME1_RTR_LBW_SRAM_MAX_CREDIT 0x40240 + +#define mmMME1_RTR_LBW_RD_RS_E_ARB 0x40250 + +#define mmMME1_RTR_LBW_RD_RS_W_ARB 0x40254 + +#define mmMME1_RTR_LBW_RD_RS_N_ARB 0x40258 + +#define mmMME1_RTR_LBW_RD_RS_S_ARB 0x4025C + +#define mmMME1_RTR_LBW_RD_RS_L_ARB 0x40260 + +#define mmMME1_RTR_LBW_WR_RQ_E_ARB 0x40270 + +#define mmMME1_RTR_LBW_WR_RQ_W_ARB 0x40274 + +#define mmMME1_RTR_LBW_WR_RQ_N_ARB 0x40278 + +#define mmMME1_RTR_LBW_WR_RQ_S_ARB 0x4027C + +#define mmMME1_RTR_LBW_WR_RQ_L_ARB 0x40280 + +#define mmMME1_RTR_LBW_WR_RS_E_ARB 0x40290 + +#define mmMME1_RTR_LBW_WR_RS_W_ARB 0x40294 + +#define mmMME1_RTR_LBW_WR_RS_N_ARB 0x40298 + +#define mmMME1_RTR_LBW_WR_RS_S_ARB 0x4029C + +#define mmMME1_RTR_LBW_WR_RS_L_ARB 0x402A0 + +#define mmMME1_RTR_DBG_E_ARB 0x40300 + +#define mmMME1_RTR_DBG_W_ARB 0x40304 + +#define mmMME1_RTR_DBG_N_ARB 0x40308 + +#define mmMME1_RTR_DBG_S_ARB 0x4030C + +#define mmMME1_RTR_DBG_L_ARB 0x40310 + +#define mmMME1_RTR_DBG_E_ARB_MAX 0x40320 + +#define mmMME1_RTR_DBG_W_ARB_MAX 0x40324 + +#define mmMME1_RTR_DBG_N_ARB_MAX 0x40328 + +#define mmMME1_RTR_DBG_S_ARB_MAX 0x4032C + +#define mmMME1_RTR_DBG_L_ARB_MAX 0x40330 + +#define mmMME1_RTR_SPLIT_COEF_0 0x40400 + +#define mmMME1_RTR_SPLIT_COEF_1 0x40404 + +#define mmMME1_RTR_SPLIT_COEF_2 0x40408 + +#define mmMME1_RTR_SPLIT_COEF_3 0x4040C + +#define mmMME1_RTR_SPLIT_COEF_4 0x40410 + +#define mmMME1_RTR_SPLIT_COEF_5 0x40414 + +#define mmMME1_RTR_SPLIT_COEF_6 0x40418 + +#define mmMME1_RTR_SPLIT_COEF_7 0x4041C + +#define mmMME1_RTR_SPLIT_COEF_8 0x40420 + +#define mmMME1_RTR_SPLIT_COEF_9 0x40424 + +#define mmMME1_RTR_SPLIT_CFG 0x40440 + +#define mmMME1_RTR_SPLIT_RD_SAT 0x40444 + +#define mmMME1_RTR_SPLIT_RD_RST_TOKEN 0x40448 + +#define mmMME1_RTR_SPLIT_RD_TIMEOUT_0 0x4044C + +#define mmMME1_RTR_SPLIT_RD_TIMEOUT_1 0x40450 + +#define mmMME1_RTR_SPLIT_WR_SAT 0x40454 + +#define mmMME1_RTR_WPLIT_WR_TST_TOLEN 0x40458 + +#define mmMME1_RTR_SPLIT_WR_TIMEOUT_0 0x4045C + +#define mmMME1_RTR_SPLIT_WR_TIMEOUT_1 0x40460 + +#define mmMME1_RTR_HBW_RANGE_HIT 0x40470 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_0 0x40480 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_1 0x40484 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_2 0x40488 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_3 0x4048C + +#define mmMME1_RTR_HBW_RANGE_MASK_L_4 0x40490 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_5 0x40494 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_6 0x40498 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_7 0x4049C + +#define mmMME1_RTR_HBW_RANGE_MASK_H_0 0x404A0 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_1 0x404A4 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_2 0x404A8 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_3 0x404AC + +#define mmMME1_RTR_HBW_RANGE_MASK_H_4 0x404B0 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_5 0x404B4 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_6 0x404B8 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_7 0x404BC + +#define mmMME1_RTR_HBW_RANGE_BASE_L_0 0x404C0 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_1 0x404C4 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_2 0x404C8 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_3 0x404CC + +#define mmMME1_RTR_HBW_RANGE_BASE_L_4 0x404D0 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_5 0x404D4 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_6 0x404D8 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_7 0x404DC + +#define mmMME1_RTR_HBW_RANGE_BASE_H_0 0x404E0 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_1 0x404E4 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_2 0x404E8 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_3 0x404EC + +#define mmMME1_RTR_HBW_RANGE_BASE_H_4 0x404F0 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_5 0x404F4 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_6 0x404F8 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_7 0x404FC + +#define mmMME1_RTR_LBW_RANGE_HIT 0x40500 + +#define mmMME1_RTR_LBW_RANGE_MASK_0 0x40510 + +#define mmMME1_RTR_LBW_RANGE_MASK_1 0x40514 + +#define mmMME1_RTR_LBW_RANGE_MASK_2 0x40518 + +#define mmMME1_RTR_LBW_RANGE_MASK_3 0x4051C + +#define mmMME1_RTR_LBW_RANGE_MASK_4 0x40520 + +#define mmMME1_RTR_LBW_RANGE_MASK_5 0x40524 + +#define mmMME1_RTR_LBW_RANGE_MASK_6 0x40528 + +#define mmMME1_RTR_LBW_RANGE_MASK_7 0x4052C + +#define mmMME1_RTR_LBW_RANGE_MASK_8 0x40530 + +#define mmMME1_RTR_LBW_RANGE_MASK_9 0x40534 + +#define mmMME1_RTR_LBW_RANGE_MASK_10 0x40538 + +#define mmMME1_RTR_LBW_RANGE_MASK_11 0x4053C + +#define mmMME1_RTR_LBW_RANGE_MASK_12 0x40540 + +#define mmMME1_RTR_LBW_RANGE_MASK_13 0x40544 + +#define mmMME1_RTR_LBW_RANGE_MASK_14 0x40548 + +#define mmMME1_RTR_LBW_RANGE_MASK_15 0x4054C + +#define mmMME1_RTR_LBW_RANGE_BASE_0 0x40550 + +#define mmMME1_RTR_LBW_RANGE_BASE_1 0x40554 + +#define mmMME1_RTR_LBW_RANGE_BASE_2 0x40558 + +#define mmMME1_RTR_LBW_RANGE_BASE_3 0x4055C + +#define mmMME1_RTR_LBW_RANGE_BASE_4 0x40560 + +#define mmMME1_RTR_LBW_RANGE_BASE_5 0x40564 + +#define mmMME1_RTR_LBW_RANGE_BASE_6 0x40568 + +#define mmMME1_RTR_LBW_RANGE_BASE_7 0x4056C + +#define mmMME1_RTR_LBW_RANGE_BASE_8 0x40570 + +#define mmMME1_RTR_LBW_RANGE_BASE_9 0x40574 + +#define mmMME1_RTR_LBW_RANGE_BASE_10 0x40578 + +#define mmMME1_RTR_LBW_RANGE_BASE_11 0x4057C + +#define mmMME1_RTR_LBW_RANGE_BASE_12 0x40580 + +#define mmMME1_RTR_LBW_RANGE_BASE_13 0x40584 + +#define mmMME1_RTR_LBW_RANGE_BASE_14 0x40588 + +#define mmMME1_RTR_LBW_RANGE_BASE_15 0x4058C + +#define mmMME1_RTR_RGLTR 0x40590 + +#define mmMME1_RTR_RGLTR_WR_RESULT 0x40594 + +#define mmMME1_RTR_RGLTR_RD_RESULT 0x40598 + +#define mmMME1_RTR_SCRAMB_EN 0x40600 + +#define mmMME1_RTR_NON_LIN_SCRAMB 0x40604 + +#endif /* ASIC_REG_MME1_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h new file mode 100644 index 000000000000..7a2b777bdc4f --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_RTR_REGS_H_ +#define ASIC_REG_MME2_RTR_REGS_H_ + +/* + ***************************************** + * MME2_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME2_RTR_HBW_RD_RQ_E_ARB 0x80100 + +#define mmMME2_RTR_HBW_RD_RQ_W_ARB 0x80104 + +#define mmMME2_RTR_HBW_RD_RQ_N_ARB 0x80108 + +#define mmMME2_RTR_HBW_RD_RQ_S_ARB 0x8010C + +#define mmMME2_RTR_HBW_RD_RQ_L_ARB 0x80110 + +#define mmMME2_RTR_HBW_E_ARB_MAX 0x80120 + +#define mmMME2_RTR_HBW_W_ARB_MAX 0x80124 + +#define mmMME2_RTR_HBW_N_ARB_MAX 0x80128 + +#define mmMME2_RTR_HBW_S_ARB_MAX 0x8012C + +#define mmMME2_RTR_HBW_L_ARB_MAX 0x80130 + +#define mmMME2_RTR_HBW_RD_RS_MAX_CREDIT 0x80140 + +#define mmMME2_RTR_HBW_WR_RQ_MAX_CREDIT 0x80144 + +#define mmMME2_RTR_HBW_RD_RQ_MAX_CREDIT 0x80148 + +#define mmMME2_RTR_HBW_RD_RS_E_ARB 0x80150 + +#define mmMME2_RTR_HBW_RD_RS_W_ARB 0x80154 + +#define mmMME2_RTR_HBW_RD_RS_N_ARB 0x80158 + +#define mmMME2_RTR_HBW_RD_RS_S_ARB 0x8015C + +#define mmMME2_RTR_HBW_RD_RS_L_ARB 0x80160 + +#define mmMME2_RTR_HBW_WR_RQ_E_ARB 0x80170 + +#define mmMME2_RTR_HBW_WR_RQ_W_ARB 0x80174 + +#define mmMME2_RTR_HBW_WR_RQ_N_ARB 0x80178 + +#define mmMME2_RTR_HBW_WR_RQ_S_ARB 0x8017C + +#define mmMME2_RTR_HBW_WR_RQ_L_ARB 0x80180 + +#define mmMME2_RTR_HBW_WR_RS_E_ARB 0x80190 + +#define mmMME2_RTR_HBW_WR_RS_W_ARB 0x80194 + +#define mmMME2_RTR_HBW_WR_RS_N_ARB 0x80198 + +#define mmMME2_RTR_HBW_WR_RS_S_ARB 0x8019C + +#define mmMME2_RTR_HBW_WR_RS_L_ARB 0x801A0 + +#define mmMME2_RTR_LBW_RD_RQ_E_ARB 0x80200 + +#define mmMME2_RTR_LBW_RD_RQ_W_ARB 0x80204 + +#define mmMME2_RTR_LBW_RD_RQ_N_ARB 0x80208 + +#define mmMME2_RTR_LBW_RD_RQ_S_ARB 0x8020C + +#define mmMME2_RTR_LBW_RD_RQ_L_ARB 0x80210 + +#define mmMME2_RTR_LBW_E_ARB_MAX 0x80220 + +#define mmMME2_RTR_LBW_W_ARB_MAX 0x80224 + +#define mmMME2_RTR_LBW_N_ARB_MAX 0x80228 + +#define mmMME2_RTR_LBW_S_ARB_MAX 0x8022C + +#define mmMME2_RTR_LBW_L_ARB_MAX 0x80230 + +#define mmMME2_RTR_LBW_SRAM_MAX_CREDIT 0x80240 + +#define mmMME2_RTR_LBW_RD_RS_E_ARB 0x80250 + +#define mmMME2_RTR_LBW_RD_RS_W_ARB 0x80254 + +#define mmMME2_RTR_LBW_RD_RS_N_ARB 0x80258 + +#define mmMME2_RTR_LBW_RD_RS_S_ARB 0x8025C + +#define mmMME2_RTR_LBW_RD_RS_L_ARB 0x80260 + +#define mmMME2_RTR_LBW_WR_RQ_E_ARB 0x80270 + +#define mmMME2_RTR_LBW_WR_RQ_W_ARB 0x80274 + +#define mmMME2_RTR_LBW_WR_RQ_N_ARB 0x80278 + +#define mmMME2_RTR_LBW_WR_RQ_S_ARB 0x8027C + +#define mmMME2_RTR_LBW_WR_RQ_L_ARB 0x80280 + +#define mmMME2_RTR_LBW_WR_RS_E_ARB 0x80290 + +#define mmMME2_RTR_LBW_WR_RS_W_ARB 0x80294 + +#define mmMME2_RTR_LBW_WR_RS_N_ARB 0x80298 + +#define mmMME2_RTR_LBW_WR_RS_S_ARB 0x8029C + +#define mmMME2_RTR_LBW_WR_RS_L_ARB 0x802A0 + +#define mmMME2_RTR_DBG_E_ARB 0x80300 + +#define mmMME2_RTR_DBG_W_ARB 0x80304 + +#define mmMME2_RTR_DBG_N_ARB 0x80308 + +#define mmMME2_RTR_DBG_S_ARB 0x8030C + +#define mmMME2_RTR_DBG_L_ARB 0x80310 + +#define mmMME2_RTR_DBG_E_ARB_MAX 0x80320 + +#define mmMME2_RTR_DBG_W_ARB_MAX 0x80324 + +#define mmMME2_RTR_DBG_N_ARB_MAX 0x80328 + +#define mmMME2_RTR_DBG_S_ARB_MAX 0x8032C + +#define mmMME2_RTR_DBG_L_ARB_MAX 0x80330 + +#define mmMME2_RTR_SPLIT_COEF_0 0x80400 + +#define mmMME2_RTR_SPLIT_COEF_1 0x80404 + +#define mmMME2_RTR_SPLIT_COEF_2 0x80408 + +#define mmMME2_RTR_SPLIT_COEF_3 0x8040C + +#define mmMME2_RTR_SPLIT_COEF_4 0x80410 + +#define mmMME2_RTR_SPLIT_COEF_5 0x80414 + +#define mmMME2_RTR_SPLIT_COEF_6 0x80418 + +#define mmMME2_RTR_SPLIT_COEF_7 0x8041C + +#define mmMME2_RTR_SPLIT_COEF_8 0x80420 + +#define mmMME2_RTR_SPLIT_COEF_9 0x80424 + +#define mmMME2_RTR_SPLIT_CFG 0x80440 + +#define mmMME2_RTR_SPLIT_RD_SAT 0x80444 + +#define mmMME2_RTR_SPLIT_RD_RST_TOKEN 0x80448 + +#define mmMME2_RTR_SPLIT_RD_TIMEOUT_0 0x8044C + +#define mmMME2_RTR_SPLIT_RD_TIMEOUT_1 0x80450 + +#define mmMME2_RTR_SPLIT_WR_SAT 0x80454 + +#define mmMME2_RTR_WPLIT_WR_TST_TOLEN 0x80458 + +#define mmMME2_RTR_SPLIT_WR_TIMEOUT_0 0x8045C + +#define mmMME2_RTR_SPLIT_WR_TIMEOUT_1 0x80460 + +#define mmMME2_RTR_HBW_RANGE_HIT 0x80470 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_0 0x80480 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_1 0x80484 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_2 0x80488 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_3 0x8048C + +#define mmMME2_RTR_HBW_RANGE_MASK_L_4 0x80490 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_5 0x80494 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_6 0x80498 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_7 0x8049C + +#define mmMME2_RTR_HBW_RANGE_MASK_H_0 0x804A0 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_1 0x804A4 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_2 0x804A8 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_3 0x804AC + +#define mmMME2_RTR_HBW_RANGE_MASK_H_4 0x804B0 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_5 0x804B4 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_6 0x804B8 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_7 0x804BC + +#define mmMME2_RTR_HBW_RANGE_BASE_L_0 0x804C0 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_1 0x804C4 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_2 0x804C8 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_3 0x804CC + +#define mmMME2_RTR_HBW_RANGE_BASE_L_4 0x804D0 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_5 0x804D4 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_6 0x804D8 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_7 0x804DC + +#define mmMME2_RTR_HBW_RANGE_BASE_H_0 0x804E0 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_1 0x804E4 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_2 0x804E8 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_3 0x804EC + +#define mmMME2_RTR_HBW_RANGE_BASE_H_4 0x804F0 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_5 0x804F4 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_6 0x804F8 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_7 0x804FC + +#define mmMME2_RTR_LBW_RANGE_HIT 0x80500 + +#define mmMME2_RTR_LBW_RANGE_MASK_0 0x80510 + +#define mmMME2_RTR_LBW_RANGE_MASK_1 0x80514 + +#define mmMME2_RTR_LBW_RANGE_MASK_2 0x80518 + +#define mmMME2_RTR_LBW_RANGE_MASK_3 0x8051C + +#define mmMME2_RTR_LBW_RANGE_MASK_4 0x80520 + +#define mmMME2_RTR_LBW_RANGE_MASK_5 0x80524 + +#define mmMME2_RTR_LBW_RANGE_MASK_6 0x80528 + +#define mmMME2_RTR_LBW_RANGE_MASK_7 0x8052C + +#define mmMME2_RTR_LBW_RANGE_MASK_8 0x80530 + +#define mmMME2_RTR_LBW_RANGE_MASK_9 0x80534 + +#define mmMME2_RTR_LBW_RANGE_MASK_10 0x80538 + +#define mmMME2_RTR_LBW_RANGE_MASK_11 0x8053C + +#define mmMME2_RTR_LBW_RANGE_MASK_12 0x80540 + +#define mmMME2_RTR_LBW_RANGE_MASK_13 0x80544 + +#define mmMME2_RTR_LBW_RANGE_MASK_14 0x80548 + +#define mmMME2_RTR_LBW_RANGE_MASK_15 0x8054C + +#define mmMME2_RTR_LBW_RANGE_BASE_0 0x80550 + +#define mmMME2_RTR_LBW_RANGE_BASE_1 0x80554 + +#define mmMME2_RTR_LBW_RANGE_BASE_2 0x80558 + +#define mmMME2_RTR_LBW_RANGE_BASE_3 0x8055C + +#define mmMME2_RTR_LBW_RANGE_BASE_4 0x80560 + +#define mmMME2_RTR_LBW_RANGE_BASE_5 0x80564 + +#define mmMME2_RTR_LBW_RANGE_BASE_6 0x80568 + +#define mmMME2_RTR_LBW_RANGE_BASE_7 0x8056C + +#define mmMME2_RTR_LBW_RANGE_BASE_8 0x80570 + +#define mmMME2_RTR_LBW_RANGE_BASE_9 0x80574 + +#define mmMME2_RTR_LBW_RANGE_BASE_10 0x80578 + +#define mmMME2_RTR_LBW_RANGE_BASE_11 0x8057C + +#define mmMME2_RTR_LBW_RANGE_BASE_12 0x80580 + +#define mmMME2_RTR_LBW_RANGE_BASE_13 0x80584 + +#define mmMME2_RTR_LBW_RANGE_BASE_14 0x80588 + +#define mmMME2_RTR_LBW_RANGE_BASE_15 0x8058C + +#define mmMME2_RTR_RGLTR 0x80590 + +#define mmMME2_RTR_RGLTR_WR_RESULT 0x80594 + +#define mmMME2_RTR_RGLTR_RD_RESULT 0x80598 + +#define mmMME2_RTR_SCRAMB_EN 0x80600 + +#define mmMME2_RTR_NON_LIN_SCRAMB 0x80604 + +#endif /* ASIC_REG_MME2_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h new file mode 100644 index 000000000000..b78f8bc387fc --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME3_RTR_REGS_H_ +#define ASIC_REG_MME3_RTR_REGS_H_ + +/* + ***************************************** + * MME3_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME3_RTR_HBW_RD_RQ_E_ARB 0xC0100 + +#define mmMME3_RTR_HBW_RD_RQ_W_ARB 0xC0104 + +#define mmMME3_RTR_HBW_RD_RQ_N_ARB 0xC0108 + +#define mmMME3_RTR_HBW_RD_RQ_S_ARB 0xC010C + +#define mmMME3_RTR_HBW_RD_RQ_L_ARB 0xC0110 + +#define mmMME3_RTR_HBW_E_ARB_MAX 0xC0120 + +#define mmMME3_RTR_HBW_W_ARB_MAX 0xC0124 + +#define mmMME3_RTR_HBW_N_ARB_MAX 0xC0128 + +#define mmMME3_RTR_HBW_S_ARB_MAX 0xC012C + +#define mmMME3_RTR_HBW_L_ARB_MAX 0xC0130 + +#define mmMME3_RTR_HBW_RD_RS_MAX_CREDIT 0xC0140 + +#define mmMME3_RTR_HBW_WR_RQ_MAX_CREDIT 0xC0144 + +#define mmMME3_RTR_HBW_RD_RQ_MAX_CREDIT 0xC0148 + +#define mmMME3_RTR_HBW_RD_RS_E_ARB 0xC0150 + +#define mmMME3_RTR_HBW_RD_RS_W_ARB 0xC0154 + +#define mmMME3_RTR_HBW_RD_RS_N_ARB 0xC0158 + +#define mmMME3_RTR_HBW_RD_RS_S_ARB 0xC015C + +#define mmMME3_RTR_HBW_RD_RS_L_ARB 0xC0160 + +#define mmMME3_RTR_HBW_WR_RQ_E_ARB 0xC0170 + +#define mmMME3_RTR_HBW_WR_RQ_W_ARB 0xC0174 + +#define mmMME3_RTR_HBW_WR_RQ_N_ARB 0xC0178 + +#define mmMME3_RTR_HBW_WR_RQ_S_ARB 0xC017C + +#define mmMME3_RTR_HBW_WR_RQ_L_ARB 0xC0180 + +#define mmMME3_RTR_HBW_WR_RS_E_ARB 0xC0190 + +#define mmMME3_RTR_HBW_WR_RS_W_ARB 0xC0194 + +#define mmMME3_RTR_HBW_WR_RS_N_ARB 0xC0198 + +#define mmMME3_RTR_HBW_WR_RS_S_ARB 0xC019C + +#define mmMME3_RTR_HBW_WR_RS_L_ARB 0xC01A0 + +#define mmMME3_RTR_LBW_RD_RQ_E_ARB 0xC0200 + +#define mmMME3_RTR_LBW_RD_RQ_W_ARB 0xC0204 + +#define mmMME3_RTR_LBW_RD_RQ_N_ARB 0xC0208 + +#define mmMME3_RTR_LBW_RD_RQ_S_ARB 0xC020C + +#define mmMME3_RTR_LBW_RD_RQ_L_ARB 0xC0210 + +#define mmMME3_RTR_LBW_E_ARB_MAX 0xC0220 + +#define mmMME3_RTR_LBW_W_ARB_MAX 0xC0224 + +#define mmMME3_RTR_LBW_N_ARB_MAX 0xC0228 + +#define mmMME3_RTR_LBW_S_ARB_MAX 0xC022C + +#define mmMME3_RTR_LBW_L_ARB_MAX 0xC0230 + +#define mmMME3_RTR_LBW_SRAM_MAX_CREDIT 0xC0240 + +#define mmMME3_RTR_LBW_RD_RS_E_ARB 0xC0250 + +#define mmMME3_RTR_LBW_RD_RS_W_ARB 0xC0254 + +#define mmMME3_RTR_LBW_RD_RS_N_ARB 0xC0258 + +#define mmMME3_RTR_LBW_RD_RS_S_ARB 0xC025C + +#define mmMME3_RTR_LBW_RD_RS_L_ARB 0xC0260 + +#define mmMME3_RTR_LBW_WR_RQ_E_ARB 0xC0270 + +#define mmMME3_RTR_LBW_WR_RQ_W_ARB 0xC0274 + +#define mmMME3_RTR_LBW_WR_RQ_N_ARB 0xC0278 + +#define mmMME3_RTR_LBW_WR_RQ_S_ARB 0xC027C + +#define mmMME3_RTR_LBW_WR_RQ_L_ARB 0xC0280 + +#define mmMME3_RTR_LBW_WR_RS_E_ARB 0xC0290 + +#define mmMME3_RTR_LBW_WR_RS_W_ARB 0xC0294 + +#define mmMME3_RTR_LBW_WR_RS_N_ARB 0xC0298 + +#define mmMME3_RTR_LBW_WR_RS_S_ARB 0xC029C + +#define mmMME3_RTR_LBW_WR_RS_L_ARB 0xC02A0 + +#define mmMME3_RTR_DBG_E_ARB 0xC0300 + +#define mmMME3_RTR_DBG_W_ARB 0xC0304 + +#define mmMME3_RTR_DBG_N_ARB 0xC0308 + +#define mmMME3_RTR_DBG_S_ARB 0xC030C + +#define mmMME3_RTR_DBG_L_ARB 0xC0310 + +#define mmMME3_RTR_DBG_E_ARB_MAX 0xC0320 + +#define mmMME3_RTR_DBG_W_ARB_MAX 0xC0324 + +#define mmMME3_RTR_DBG_N_ARB_MAX 0xC0328 + +#define mmMME3_RTR_DBG_S_ARB_MAX 0xC032C + +#define mmMME3_RTR_DBG_L_ARB_MAX 0xC0330 + +#define mmMME3_RTR_SPLIT_COEF_0 0xC0400 + +#define mmMME3_RTR_SPLIT_COEF_1 0xC0404 + +#define mmMME3_RTR_SPLIT_COEF_2 0xC0408 + +#define mmMME3_RTR_SPLIT_COEF_3 0xC040C + +#define mmMME3_RTR_SPLIT_COEF_4 0xC0410 + +#define mmMME3_RTR_SPLIT_COEF_5 0xC0414 + +#define mmMME3_RTR_SPLIT_COEF_6 0xC0418 + +#define mmMME3_RTR_SPLIT_COEF_7 0xC041C + +#define mmMME3_RTR_SPLIT_COEF_8 0xC0420 + +#define mmMME3_RTR_SPLIT_COEF_9 0xC0424 + +#define mmMME3_RTR_SPLIT_CFG 0xC0440 + +#define mmMME3_RTR_SPLIT_RD_SAT 0xC0444 + +#define mmMME3_RTR_SPLIT_RD_RST_TOKEN 0xC0448 + +#define mmMME3_RTR_SPLIT_RD_TIMEOUT_0 0xC044C + +#define mmMME3_RTR_SPLIT_RD_TIMEOUT_1 0xC0450 + +#define mmMME3_RTR_SPLIT_WR_SAT 0xC0454 + +#define mmMME3_RTR_WPLIT_WR_TST_TOLEN 0xC0458 + +#define mmMME3_RTR_SPLIT_WR_TIMEOUT_0 0xC045C + +#define mmMME3_RTR_SPLIT_WR_TIMEOUT_1 0xC0460 + +#define mmMME3_RTR_HBW_RANGE_HIT 0xC0470 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_0 0xC0480 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_1 0xC0484 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_2 0xC0488 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_3 0xC048C + +#define mmMME3_RTR_HBW_RANGE_MASK_L_4 0xC0490 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_5 0xC0494 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_6 0xC0498 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_7 0xC049C + +#define mmMME3_RTR_HBW_RANGE_MASK_H_0 0xC04A0 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_1 0xC04A4 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_2 0xC04A8 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_3 0xC04AC + +#define mmMME3_RTR_HBW_RANGE_MASK_H_4 0xC04B0 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_5 0xC04B4 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_6 0xC04B8 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_7 0xC04BC + +#define mmMME3_RTR_HBW_RANGE_BASE_L_0 0xC04C0 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_1 0xC04C4 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_2 0xC04C8 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_3 0xC04CC + +#define mmMME3_RTR_HBW_RANGE_BASE_L_4 0xC04D0 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_5 0xC04D4 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_6 0xC04D8 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_7 0xC04DC + +#define mmMME3_RTR_HBW_RANGE_BASE_H_0 0xC04E0 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_1 0xC04E4 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_2 0xC04E8 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_3 0xC04EC + +#define mmMME3_RTR_HBW_RANGE_BASE_H_4 0xC04F0 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_5 0xC04F4 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_6 0xC04F8 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_7 0xC04FC + +#define mmMME3_RTR_LBW_RANGE_HIT 0xC0500 + +#define mmMME3_RTR_LBW_RANGE_MASK_0 0xC0510 + +#define mmMME3_RTR_LBW_RANGE_MASK_1 0xC0514 + +#define mmMME3_RTR_LBW_RANGE_MASK_2 0xC0518 + +#define mmMME3_RTR_LBW_RANGE_MASK_3 0xC051C + +#define mmMME3_RTR_LBW_RANGE_MASK_4 0xC0520 + +#define mmMME3_RTR_LBW_RANGE_MASK_5 0xC0524 + +#define mmMME3_RTR_LBW_RANGE_MASK_6 0xC0528 + +#define mmMME3_RTR_LBW_RANGE_MASK_7 0xC052C + +#define mmMME3_RTR_LBW_RANGE_MASK_8 0xC0530 + +#define mmMME3_RTR_LBW_RANGE_MASK_9 0xC0534 + +#define mmMME3_RTR_LBW_RANGE_MASK_10 0xC0538 + +#define mmMME3_RTR_LBW_RANGE_MASK_11 0xC053C + +#define mmMME3_RTR_LBW_RANGE_MASK_12 0xC0540 + +#define mmMME3_RTR_LBW_RANGE_MASK_13 0xC0544 + +#define mmMME3_RTR_LBW_RANGE_MASK_14 0xC0548 + +#define mmMME3_RTR_LBW_RANGE_MASK_15 0xC054C + +#define mmMME3_RTR_LBW_RANGE_BASE_0 0xC0550 + +#define mmMME3_RTR_LBW_RANGE_BASE_1 0xC0554 + +#define mmMME3_RTR_LBW_RANGE_BASE_2 0xC0558 + +#define mmMME3_RTR_LBW_RANGE_BASE_3 0xC055C + +#define mmMME3_RTR_LBW_RANGE_BASE_4 0xC0560 + +#define mmMME3_RTR_LBW_RANGE_BASE_5 0xC0564 + +#define mmMME3_RTR_LBW_RANGE_BASE_6 0xC0568 + +#define mmMME3_RTR_LBW_RANGE_BASE_7 0xC056C + +#define mmMME3_RTR_LBW_RANGE_BASE_8 0xC0570 + +#define mmMME3_RTR_LBW_RANGE_BASE_9 0xC0574 + +#define mmMME3_RTR_LBW_RANGE_BASE_10 0xC0578 + +#define mmMME3_RTR_LBW_RANGE_BASE_11 0xC057C + +#define mmMME3_RTR_LBW_RANGE_BASE_12 0xC0580 + +#define mmMME3_RTR_LBW_RANGE_BASE_13 0xC0584 + +#define mmMME3_RTR_LBW_RANGE_BASE_14 0xC0588 + +#define mmMME3_RTR_LBW_RANGE_BASE_15 0xC058C + +#define mmMME3_RTR_RGLTR 0xC0590 + +#define mmMME3_RTR_RGLTR_WR_RESULT 0xC0594 + +#define mmMME3_RTR_RGLTR_RD_RESULT 0xC0598 + +#define mmMME3_RTR_SCRAMB_EN 0xC0600 + +#define mmMME3_RTR_NON_LIN_SCRAMB 0xC0604 + +#endif /* ASIC_REG_MME3_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h new file mode 100644 index 000000000000..d9a4a02cefa3 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME4_RTR_REGS_H_ +#define ASIC_REG_MME4_RTR_REGS_H_ + +/* + ***************************************** + * MME4_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME4_RTR_HBW_RD_RQ_E_ARB 0x100100 + +#define mmMME4_RTR_HBW_RD_RQ_W_ARB 0x100104 + +#define mmMME4_RTR_HBW_RD_RQ_N_ARB 0x100108 + +#define mmMME4_RTR_HBW_RD_RQ_S_ARB 0x10010C + +#define mmMME4_RTR_HBW_RD_RQ_L_ARB 0x100110 + +#define mmMME4_RTR_HBW_E_ARB_MAX 0x100120 + +#define mmMME4_RTR_HBW_W_ARB_MAX 0x100124 + +#define mmMME4_RTR_HBW_N_ARB_MAX 0x100128 + +#define mmMME4_RTR_HBW_S_ARB_MAX 0x10012C + +#define mmMME4_RTR_HBW_L_ARB_MAX 0x100130 + +#define mmMME4_RTR_HBW_RD_RS_MAX_CREDIT 0x100140 + +#define mmMME4_RTR_HBW_WR_RQ_MAX_CREDIT 0x100144 + +#define mmMME4_RTR_HBW_RD_RQ_MAX_CREDIT 0x100148 + +#define mmMME4_RTR_HBW_RD_RS_E_ARB 0x100150 + +#define mmMME4_RTR_HBW_RD_RS_W_ARB 0x100154 + +#define mmMME4_RTR_HBW_RD_RS_N_ARB 0x100158 + +#define mmMME4_RTR_HBW_RD_RS_S_ARB 0x10015C + +#define mmMME4_RTR_HBW_RD_RS_L_ARB 0x100160 + +#define mmMME4_RTR_HBW_WR_RQ_E_ARB 0x100170 + +#define mmMME4_RTR_HBW_WR_RQ_W_ARB 0x100174 + +#define mmMME4_RTR_HBW_WR_RQ_N_ARB 0x100178 + +#define mmMME4_RTR_HBW_WR_RQ_S_ARB 0x10017C + +#define mmMME4_RTR_HBW_WR_RQ_L_ARB 0x100180 + +#define mmMME4_RTR_HBW_WR_RS_E_ARB 0x100190 + +#define mmMME4_RTR_HBW_WR_RS_W_ARB 0x100194 + +#define mmMME4_RTR_HBW_WR_RS_N_ARB 0x100198 + +#define mmMME4_RTR_HBW_WR_RS_S_ARB 0x10019C + +#define mmMME4_RTR_HBW_WR_RS_L_ARB 0x1001A0 + +#define mmMME4_RTR_LBW_RD_RQ_E_ARB 0x100200 + +#define mmMME4_RTR_LBW_RD_RQ_W_ARB 0x100204 + +#define mmMME4_RTR_LBW_RD_RQ_N_ARB 0x100208 + +#define mmMME4_RTR_LBW_RD_RQ_S_ARB 0x10020C + +#define mmMME4_RTR_LBW_RD_RQ_L_ARB 0x100210 + +#define mmMME4_RTR_LBW_E_ARB_MAX 0x100220 + +#define mmMME4_RTR_LBW_W_ARB_MAX 0x100224 + +#define mmMME4_RTR_LBW_N_ARB_MAX 0x100228 + +#define mmMME4_RTR_LBW_S_ARB_MAX 0x10022C + +#define mmMME4_RTR_LBW_L_ARB_MAX 0x100230 + +#define mmMME4_RTR_LBW_SRAM_MAX_CREDIT 0x100240 + +#define mmMME4_RTR_LBW_RD_RS_E_ARB 0x100250 + +#define mmMME4_RTR_LBW_RD_RS_W_ARB 0x100254 + +#define mmMME4_RTR_LBW_RD_RS_N_ARB 0x100258 + +#define mmMME4_RTR_LBW_RD_RS_S_ARB 0x10025C + +#define mmMME4_RTR_LBW_RD_RS_L_ARB 0x100260 + +#define mmMME4_RTR_LBW_WR_RQ_E_ARB 0x100270 + +#define mmMME4_RTR_LBW_WR_RQ_W_ARB 0x100274 + +#define mmMME4_RTR_LBW_WR_RQ_N_ARB 0x100278 + +#define mmMME4_RTR_LBW_WR_RQ_S_ARB 0x10027C + +#define mmMME4_RTR_LBW_WR_RQ_L_ARB 0x100280 + +#define mmMME4_RTR_LBW_WR_RS_E_ARB 0x100290 + +#define mmMME4_RTR_LBW_WR_RS_W_ARB 0x100294 + +#define mmMME4_RTR_LBW_WR_RS_N_ARB 0x100298 + +#define mmMME4_RTR_LBW_WR_RS_S_ARB 0x10029C + +#define mmMME4_RTR_LBW_WR_RS_L_ARB 0x1002A0 + +#define mmMME4_RTR_DBG_E_ARB 0x100300 + +#define mmMME4_RTR_DBG_W_ARB 0x100304 + +#define mmMME4_RTR_DBG_N_ARB 0x100308 + +#define mmMME4_RTR_DBG_S_ARB 0x10030C + +#define mmMME4_RTR_DBG_L_ARB 0x100310 + +#define mmMME4_RTR_DBG_E_ARB_MAX 0x100320 + +#define mmMME4_RTR_DBG_W_ARB_MAX 0x100324 + +#define mmMME4_RTR_DBG_N_ARB_MAX 0x100328 + +#define mmMME4_RTR_DBG_S_ARB_MAX 0x10032C + +#define mmMME4_RTR_DBG_L_ARB_MAX 0x100330 + +#define mmMME4_RTR_SPLIT_COEF_0 0x100400 + +#define mmMME4_RTR_SPLIT_COEF_1 0x100404 + +#define mmMME4_RTR_SPLIT_COEF_2 0x100408 + +#define mmMME4_RTR_SPLIT_COEF_3 0x10040C + +#define mmMME4_RTR_SPLIT_COEF_4 0x100410 + +#define mmMME4_RTR_SPLIT_COEF_5 0x100414 + +#define mmMME4_RTR_SPLIT_COEF_6 0x100418 + +#define mmMME4_RTR_SPLIT_COEF_7 0x10041C + +#define mmMME4_RTR_SPLIT_COEF_8 0x100420 + +#define mmMME4_RTR_SPLIT_COEF_9 0x100424 + +#define mmMME4_RTR_SPLIT_CFG 0x100440 + +#define mmMME4_RTR_SPLIT_RD_SAT 0x100444 + +#define mmMME4_RTR_SPLIT_RD_RST_TOKEN 0x100448 + +#define mmMME4_RTR_SPLIT_RD_TIMEOUT_0 0x10044C + +#define mmMME4_RTR_SPLIT_RD_TIMEOUT_1 0x100450 + +#define mmMME4_RTR_SPLIT_WR_SAT 0x100454 + +#define mmMME4_RTR_WPLIT_WR_TST_TOLEN 0x100458 + +#define mmMME4_RTR_SPLIT_WR_TIMEOUT_0 0x10045C + +#define mmMME4_RTR_SPLIT_WR_TIMEOUT_1 0x100460 + +#define mmMME4_RTR_HBW_RANGE_HIT 0x100470 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_0 0x100480 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_1 0x100484 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_2 0x100488 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_3 0x10048C + +#define mmMME4_RTR_HBW_RANGE_MASK_L_4 0x100490 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_5 0x100494 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_6 0x100498 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_7 0x10049C + +#define mmMME4_RTR_HBW_RANGE_MASK_H_0 0x1004A0 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_1 0x1004A4 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_2 0x1004A8 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_3 0x1004AC + +#define mmMME4_RTR_HBW_RANGE_MASK_H_4 0x1004B0 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_5 0x1004B4 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_6 0x1004B8 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_7 0x1004BC + +#define mmMME4_RTR_HBW_RANGE_BASE_L_0 0x1004C0 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_1 0x1004C4 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_2 0x1004C8 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_3 0x1004CC + +#define mmMME4_RTR_HBW_RANGE_BASE_L_4 0x1004D0 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_5 0x1004D4 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_6 0x1004D8 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_7 0x1004DC + +#define mmMME4_RTR_HBW_RANGE_BASE_H_0 0x1004E0 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_1 0x1004E4 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_2 0x1004E8 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_3 0x1004EC + +#define mmMME4_RTR_HBW_RANGE_BASE_H_4 0x1004F0 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_5 0x1004F4 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_6 0x1004F8 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_7 0x1004FC + +#define mmMME4_RTR_LBW_RANGE_HIT 0x100500 + +#define mmMME4_RTR_LBW_RANGE_MASK_0 0x100510 + +#define mmMME4_RTR_LBW_RANGE_MASK_1 0x100514 + +#define mmMME4_RTR_LBW_RANGE_MASK_2 0x100518 + +#define mmMME4_RTR_LBW_RANGE_MASK_3 0x10051C + +#define mmMME4_RTR_LBW_RANGE_MASK_4 0x100520 + +#define mmMME4_RTR_LBW_RANGE_MASK_5 0x100524 + +#define mmMME4_RTR_LBW_RANGE_MASK_6 0x100528 + +#define mmMME4_RTR_LBW_RANGE_MASK_7 0x10052C + +#define mmMME4_RTR_LBW_RANGE_MASK_8 0x100530 + +#define mmMME4_RTR_LBW_RANGE_MASK_9 0x100534 + +#define mmMME4_RTR_LBW_RANGE_MASK_10 0x100538 + +#define mmMME4_RTR_LBW_RANGE_MASK_11 0x10053C + +#define mmMME4_RTR_LBW_RANGE_MASK_12 0x100540 + +#define mmMME4_RTR_LBW_RANGE_MASK_13 0x100544 + +#define mmMME4_RTR_LBW_RANGE_MASK_14 0x100548 + +#define mmMME4_RTR_LBW_RANGE_MASK_15 0x10054C + +#define mmMME4_RTR_LBW_RANGE_BASE_0 0x100550 + +#define mmMME4_RTR_LBW_RANGE_BASE_1 0x100554 + +#define mmMME4_RTR_LBW_RANGE_BASE_2 0x100558 + +#define mmMME4_RTR_LBW_RANGE_BASE_3 0x10055C + +#define mmMME4_RTR_LBW_RANGE_BASE_4 0x100560 + +#define mmMME4_RTR_LBW_RANGE_BASE_5 0x100564 + +#define mmMME4_RTR_LBW_RANGE_BASE_6 0x100568 + +#define mmMME4_RTR_LBW_RANGE_BASE_7 0x10056C + +#define mmMME4_RTR_LBW_RANGE_BASE_8 0x100570 + +#define mmMME4_RTR_LBW_RANGE_BASE_9 0x100574 + +#define mmMME4_RTR_LBW_RANGE_BASE_10 0x100578 + +#define mmMME4_RTR_LBW_RANGE_BASE_11 0x10057C + +#define mmMME4_RTR_LBW_RANGE_BASE_12 0x100580 + +#define mmMME4_RTR_LBW_RANGE_BASE_13 0x100584 + +#define mmMME4_RTR_LBW_RANGE_BASE_14 0x100588 + +#define mmMME4_RTR_LBW_RANGE_BASE_15 0x10058C + +#define mmMME4_RTR_RGLTR 0x100590 + +#define mmMME4_RTR_RGLTR_WR_RESULT 0x100594 + +#define mmMME4_RTR_RGLTR_RD_RESULT 0x100598 + +#define mmMME4_RTR_SCRAMB_EN 0x100600 + +#define mmMME4_RTR_NON_LIN_SCRAMB 0x100604 + +#endif /* ASIC_REG_MME4_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h new file mode 100644 index 000000000000..205adc988407 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME5_RTR_REGS_H_ +#define ASIC_REG_MME5_RTR_REGS_H_ + +/* + ***************************************** + * MME5_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME5_RTR_HBW_RD_RQ_E_ARB 0x140100 + +#define mmMME5_RTR_HBW_RD_RQ_W_ARB 0x140104 + +#define mmMME5_RTR_HBW_RD_RQ_N_ARB 0x140108 + +#define mmMME5_RTR_HBW_RD_RQ_S_ARB 0x14010C + +#define mmMME5_RTR_HBW_RD_RQ_L_ARB 0x140110 + +#define mmMME5_RTR_HBW_E_ARB_MAX 0x140120 + +#define mmMME5_RTR_HBW_W_ARB_MAX 0x140124 + +#define mmMME5_RTR_HBW_N_ARB_MAX 0x140128 + +#define mmMME5_RTR_HBW_S_ARB_MAX 0x14012C + +#define mmMME5_RTR_HBW_L_ARB_MAX 0x140130 + +#define mmMME5_RTR_HBW_RD_RS_MAX_CREDIT 0x140140 + +#define mmMME5_RTR_HBW_WR_RQ_MAX_CREDIT 0x140144 + +#define mmMME5_RTR_HBW_RD_RQ_MAX_CREDIT 0x140148 + +#define mmMME5_RTR_HBW_RD_RS_E_ARB 0x140150 + +#define mmMME5_RTR_HBW_RD_RS_W_ARB 0x140154 + +#define mmMME5_RTR_HBW_RD_RS_N_ARB 0x140158 + +#define mmMME5_RTR_HBW_RD_RS_S_ARB 0x14015C + +#define mmMME5_RTR_HBW_RD_RS_L_ARB 0x140160 + +#define mmMME5_RTR_HBW_WR_RQ_E_ARB 0x140170 + +#define mmMME5_RTR_HBW_WR_RQ_W_ARB 0x140174 + +#define mmMME5_RTR_HBW_WR_RQ_N_ARB 0x140178 + +#define mmMME5_RTR_HBW_WR_RQ_S_ARB 0x14017C + +#define mmMME5_RTR_HBW_WR_RQ_L_ARB 0x140180 + +#define mmMME5_RTR_HBW_WR_RS_E_ARB 0x140190 + +#define mmMME5_RTR_HBW_WR_RS_W_ARB 0x140194 + +#define mmMME5_RTR_HBW_WR_RS_N_ARB 0x140198 + +#define mmMME5_RTR_HBW_WR_RS_S_ARB 0x14019C + +#define mmMME5_RTR_HBW_WR_RS_L_ARB 0x1401A0 + +#define mmMME5_RTR_LBW_RD_RQ_E_ARB 0x140200 + +#define mmMME5_RTR_LBW_RD_RQ_W_ARB 0x140204 + +#define mmMME5_RTR_LBW_RD_RQ_N_ARB 0x140208 + +#define mmMME5_RTR_LBW_RD_RQ_S_ARB 0x14020C + +#define mmMME5_RTR_LBW_RD_RQ_L_ARB 0x140210 + +#define mmMME5_RTR_LBW_E_ARB_MAX 0x140220 + +#define mmMME5_RTR_LBW_W_ARB_MAX 0x140224 + +#define mmMME5_RTR_LBW_N_ARB_MAX 0x140228 + +#define mmMME5_RTR_LBW_S_ARB_MAX 0x14022C + +#define mmMME5_RTR_LBW_L_ARB_MAX 0x140230 + +#define mmMME5_RTR_LBW_SRAM_MAX_CREDIT 0x140240 + +#define mmMME5_RTR_LBW_RD_RS_E_ARB 0x140250 + +#define mmMME5_RTR_LBW_RD_RS_W_ARB 0x140254 + +#define mmMME5_RTR_LBW_RD_RS_N_ARB 0x140258 + +#define mmMME5_RTR_LBW_RD_RS_S_ARB 0x14025C + +#define mmMME5_RTR_LBW_RD_RS_L_ARB 0x140260 + +#define mmMME5_RTR_LBW_WR_RQ_E_ARB 0x140270 + +#define mmMME5_RTR_LBW_WR_RQ_W_ARB 0x140274 + +#define mmMME5_RTR_LBW_WR_RQ_N_ARB 0x140278 + +#define mmMME5_RTR_LBW_WR_RQ_S_ARB 0x14027C + +#define mmMME5_RTR_LBW_WR_RQ_L_ARB 0x140280 + +#define mmMME5_RTR_LBW_WR_RS_E_ARB 0x140290 + +#define mmMME5_RTR_LBW_WR_RS_W_ARB 0x140294 + +#define mmMME5_RTR_LBW_WR_RS_N_ARB 0x140298 + +#define mmMME5_RTR_LBW_WR_RS_S_ARB 0x14029C + +#define mmMME5_RTR_LBW_WR_RS_L_ARB 0x1402A0 + +#define mmMME5_RTR_DBG_E_ARB 0x140300 + +#define mmMME5_RTR_DBG_W_ARB 0x140304 + +#define mmMME5_RTR_DBG_N_ARB 0x140308 + +#define mmMME5_RTR_DBG_S_ARB 0x14030C + +#define mmMME5_RTR_DBG_L_ARB 0x140310 + +#define mmMME5_RTR_DBG_E_ARB_MAX 0x140320 + +#define mmMME5_RTR_DBG_W_ARB_MAX 0x140324 + +#define mmMME5_RTR_DBG_N_ARB_MAX 0x140328 + +#define mmMME5_RTR_DBG_S_ARB_MAX 0x14032C + +#define mmMME5_RTR_DBG_L_ARB_MAX 0x140330 + +#define mmMME5_RTR_SPLIT_COEF_0 0x140400 + +#define mmMME5_RTR_SPLIT_COEF_1 0x140404 + +#define mmMME5_RTR_SPLIT_COEF_2 0x140408 + +#define mmMME5_RTR_SPLIT_COEF_3 0x14040C + +#define mmMME5_RTR_SPLIT_COEF_4 0x140410 + +#define mmMME5_RTR_SPLIT_COEF_5 0x140414 + +#define mmMME5_RTR_SPLIT_COEF_6 0x140418 + +#define mmMME5_RTR_SPLIT_COEF_7 0x14041C + +#define mmMME5_RTR_SPLIT_COEF_8 0x140420 + +#define mmMME5_RTR_SPLIT_COEF_9 0x140424 + +#define mmMME5_RTR_SPLIT_CFG 0x140440 + +#define mmMME5_RTR_SPLIT_RD_SAT 0x140444 + +#define mmMME5_RTR_SPLIT_RD_RST_TOKEN 0x140448 + +#define mmMME5_RTR_SPLIT_RD_TIMEOUT_0 0x14044C + +#define mmMME5_RTR_SPLIT_RD_TIMEOUT_1 0x140450 + +#define mmMME5_RTR_SPLIT_WR_SAT 0x140454 + +#define mmMME5_RTR_WPLIT_WR_TST_TOLEN 0x140458 + +#define mmMME5_RTR_SPLIT_WR_TIMEOUT_0 0x14045C + +#define mmMME5_RTR_SPLIT_WR_TIMEOUT_1 0x140460 + +#define mmMME5_RTR_HBW_RANGE_HIT 0x140470 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_0 0x140480 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_1 0x140484 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_2 0x140488 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_3 0x14048C + +#define mmMME5_RTR_HBW_RANGE_MASK_L_4 0x140490 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_5 0x140494 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_6 0x140498 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_7 0x14049C + +#define mmMME5_RTR_HBW_RANGE_MASK_H_0 0x1404A0 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_1 0x1404A4 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_2 0x1404A8 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_3 0x1404AC + +#define mmMME5_RTR_HBW_RANGE_MASK_H_4 0x1404B0 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_5 0x1404B4 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_6 0x1404B8 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_7 0x1404BC + +#define mmMME5_RTR_HBW_RANGE_BASE_L_0 0x1404C0 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_1 0x1404C4 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_2 0x1404C8 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_3 0x1404CC + +#define mmMME5_RTR_HBW_RANGE_BASE_L_4 0x1404D0 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_5 0x1404D4 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_6 0x1404D8 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_7 0x1404DC + +#define mmMME5_RTR_HBW_RANGE_BASE_H_0 0x1404E0 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_1 0x1404E4 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_2 0x1404E8 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_3 0x1404EC + +#define mmMME5_RTR_HBW_RANGE_BASE_H_4 0x1404F0 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_5 0x1404F4 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_6 0x1404F8 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_7 0x1404FC + +#define mmMME5_RTR_LBW_RANGE_HIT 0x140500 + +#define mmMME5_RTR_LBW_RANGE_MASK_0 0x140510 + +#define mmMME5_RTR_LBW_RANGE_MASK_1 0x140514 + +#define mmMME5_RTR_LBW_RANGE_MASK_2 0x140518 + +#define mmMME5_RTR_LBW_RANGE_MASK_3 0x14051C + +#define mmMME5_RTR_LBW_RANGE_MASK_4 0x140520 + +#define mmMME5_RTR_LBW_RANGE_MASK_5 0x140524 + +#define mmMME5_RTR_LBW_RANGE_MASK_6 0x140528 + +#define mmMME5_RTR_LBW_RANGE_MASK_7 0x14052C + +#define mmMME5_RTR_LBW_RANGE_MASK_8 0x140530 + +#define mmMME5_RTR_LBW_RANGE_MASK_9 0x140534 + +#define mmMME5_RTR_LBW_RANGE_MASK_10 0x140538 + +#define mmMME5_RTR_LBW_RANGE_MASK_11 0x14053C + +#define mmMME5_RTR_LBW_RANGE_MASK_12 0x140540 + +#define mmMME5_RTR_LBW_RANGE_MASK_13 0x140544 + +#define mmMME5_RTR_LBW_RANGE_MASK_14 0x140548 + +#define mmMME5_RTR_LBW_RANGE_MASK_15 0x14054C + +#define mmMME5_RTR_LBW_RANGE_BASE_0 0x140550 + +#define mmMME5_RTR_LBW_RANGE_BASE_1 0x140554 + +#define mmMME5_RTR_LBW_RANGE_BASE_2 0x140558 + +#define mmMME5_RTR_LBW_RANGE_BASE_3 0x14055C + +#define mmMME5_RTR_LBW_RANGE_BASE_4 0x140560 + +#define mmMME5_RTR_LBW_RANGE_BASE_5 0x140564 + +#define mmMME5_RTR_LBW_RANGE_BASE_6 0x140568 + +#define mmMME5_RTR_LBW_RANGE_BASE_7 0x14056C + +#define mmMME5_RTR_LBW_RANGE_BASE_8 0x140570 + +#define mmMME5_RTR_LBW_RANGE_BASE_9 0x140574 + +#define mmMME5_RTR_LBW_RANGE_BASE_10 0x140578 + +#define mmMME5_RTR_LBW_RANGE_BASE_11 0x14057C + +#define mmMME5_RTR_LBW_RANGE_BASE_12 0x140580 + +#define mmMME5_RTR_LBW_RANGE_BASE_13 0x140584 + +#define mmMME5_RTR_LBW_RANGE_BASE_14 0x140588 + +#define mmMME5_RTR_LBW_RANGE_BASE_15 0x14058C + +#define mmMME5_RTR_RGLTR 0x140590 + +#define mmMME5_RTR_RGLTR_WR_RESULT 0x140594 + +#define mmMME5_RTR_RGLTR_RD_RESULT 0x140598 + +#define mmMME5_RTR_SCRAMB_EN 0x140600 + +#define mmMME5_RTR_NON_LIN_SCRAMB 0x140604 + +#endif /* ASIC_REG_MME5_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h new file mode 100644 index 000000000000..fcec68388278 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME6_RTR_REGS_H_ +#define ASIC_REG_MME6_RTR_REGS_H_ + +/* + ***************************************** + * MME6_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME6_RTR_HBW_RD_RQ_E_ARB 0x180100 + +#define mmMME6_RTR_HBW_RD_RQ_W_ARB 0x180104 + +#define mmMME6_RTR_HBW_RD_RQ_N_ARB 0x180108 + +#define mmMME6_RTR_HBW_RD_RQ_S_ARB 0x18010C + +#define mmMME6_RTR_HBW_RD_RQ_L_ARB 0x180110 + +#define mmMME6_RTR_HBW_E_ARB_MAX 0x180120 + +#define mmMME6_RTR_HBW_W_ARB_MAX 0x180124 + +#define mmMME6_RTR_HBW_N_ARB_MAX 0x180128 + +#define mmMME6_RTR_HBW_S_ARB_MAX 0x18012C + +#define mmMME6_RTR_HBW_L_ARB_MAX 0x180130 + +#define mmMME6_RTR_HBW_RD_RS_MAX_CREDIT 0x180140 + +#define mmMME6_RTR_HBW_WR_RQ_MAX_CREDIT 0x180144 + +#define mmMME6_RTR_HBW_RD_RQ_MAX_CREDIT 0x180148 + +#define mmMME6_RTR_HBW_RD_RS_E_ARB 0x180150 + +#define mmMME6_RTR_HBW_RD_RS_W_ARB 0x180154 + +#define mmMME6_RTR_HBW_RD_RS_N_ARB 0x180158 + +#define mmMME6_RTR_HBW_RD_RS_S_ARB 0x18015C + +#define mmMME6_RTR_HBW_RD_RS_L_ARB 0x180160 + +#define mmMME6_RTR_HBW_WR_RQ_E_ARB 0x180170 + +#define mmMME6_RTR_HBW_WR_RQ_W_ARB 0x180174 + +#define mmMME6_RTR_HBW_WR_RQ_N_ARB 0x180178 + +#define mmMME6_RTR_HBW_WR_RQ_S_ARB 0x18017C + +#define mmMME6_RTR_HBW_WR_RQ_L_ARB 0x180180 + +#define mmMME6_RTR_HBW_WR_RS_E_ARB 0x180190 + +#define mmMME6_RTR_HBW_WR_RS_W_ARB 0x180194 + +#define mmMME6_RTR_HBW_WR_RS_N_ARB 0x180198 + +#define mmMME6_RTR_HBW_WR_RS_S_ARB 0x18019C + +#define mmMME6_RTR_HBW_WR_RS_L_ARB 0x1801A0 + +#define mmMME6_RTR_LBW_RD_RQ_E_ARB 0x180200 + +#define mmMME6_RTR_LBW_RD_RQ_W_ARB 0x180204 + +#define mmMME6_RTR_LBW_RD_RQ_N_ARB 0x180208 + +#define mmMME6_RTR_LBW_RD_RQ_S_ARB 0x18020C + +#define mmMME6_RTR_LBW_RD_RQ_L_ARB 0x180210 + +#define mmMME6_RTR_LBW_E_ARB_MAX 0x180220 + +#define mmMME6_RTR_LBW_W_ARB_MAX 0x180224 + +#define mmMME6_RTR_LBW_N_ARB_MAX 0x180228 + +#define mmMME6_RTR_LBW_S_ARB_MAX 0x18022C + +#define mmMME6_RTR_LBW_L_ARB_MAX 0x180230 + +#define mmMME6_RTR_LBW_SRAM_MAX_CREDIT 0x180240 + +#define mmMME6_RTR_LBW_RD_RS_E_ARB 0x180250 + +#define mmMME6_RTR_LBW_RD_RS_W_ARB 0x180254 + +#define mmMME6_RTR_LBW_RD_RS_N_ARB 0x180258 + +#define mmMME6_RTR_LBW_RD_RS_S_ARB 0x18025C + +#define mmMME6_RTR_LBW_RD_RS_L_ARB 0x180260 + +#define mmMME6_RTR_LBW_WR_RQ_E_ARB 0x180270 + +#define mmMME6_RTR_LBW_WR_RQ_W_ARB 0x180274 + +#define mmMME6_RTR_LBW_WR_RQ_N_ARB 0x180278 + +#define mmMME6_RTR_LBW_WR_RQ_S_ARB 0x18027C + +#define mmMME6_RTR_LBW_WR_RQ_L_ARB 0x180280 + +#define mmMME6_RTR_LBW_WR_RS_E_ARB 0x180290 + +#define mmMME6_RTR_LBW_WR_RS_W_ARB 0x180294 + +#define mmMME6_RTR_LBW_WR_RS_N_ARB 0x180298 + +#define mmMME6_RTR_LBW_WR_RS_S_ARB 0x18029C + +#define mmMME6_RTR_LBW_WR_RS_L_ARB 0x1802A0 + +#define mmMME6_RTR_DBG_E_ARB 0x180300 + +#define mmMME6_RTR_DBG_W_ARB 0x180304 + +#define mmMME6_RTR_DBG_N_ARB 0x180308 + +#define mmMME6_RTR_DBG_S_ARB 0x18030C + +#define mmMME6_RTR_DBG_L_ARB 0x180310 + +#define mmMME6_RTR_DBG_E_ARB_MAX 0x180320 + +#define mmMME6_RTR_DBG_W_ARB_MAX 0x180324 + +#define mmMME6_RTR_DBG_N_ARB_MAX 0x180328 + +#define mmMME6_RTR_DBG_S_ARB_MAX 0x18032C + +#define mmMME6_RTR_DBG_L_ARB_MAX 0x180330 + +#define mmMME6_RTR_SPLIT_COEF_0 0x180400 + +#define mmMME6_RTR_SPLIT_COEF_1 0x180404 + +#define mmMME6_RTR_SPLIT_COEF_2 0x180408 + +#define mmMME6_RTR_SPLIT_COEF_3 0x18040C + +#define mmMME6_RTR_SPLIT_COEF_4 0x180410 + +#define mmMME6_RTR_SPLIT_COEF_5 0x180414 + +#define mmMME6_RTR_SPLIT_COEF_6 0x180418 + +#define mmMME6_RTR_SPLIT_COEF_7 0x18041C + +#define mmMME6_RTR_SPLIT_COEF_8 0x180420 + +#define mmMME6_RTR_SPLIT_COEF_9 0x180424 + +#define mmMME6_RTR_SPLIT_CFG 0x180440 + +#define mmMME6_RTR_SPLIT_RD_SAT 0x180444 + +#define mmMME6_RTR_SPLIT_RD_RST_TOKEN 0x180448 + +#define mmMME6_RTR_SPLIT_RD_TIMEOUT_0 0x18044C + +#define mmMME6_RTR_SPLIT_RD_TIMEOUT_1 0x180450 + +#define mmMME6_RTR_SPLIT_WR_SAT 0x180454 + +#define mmMME6_RTR_WPLIT_WR_TST_TOLEN 0x180458 + +#define mmMME6_RTR_SPLIT_WR_TIMEOUT_0 0x18045C + +#define mmMME6_RTR_SPLIT_WR_TIMEOUT_1 0x180460 + +#define mmMME6_RTR_HBW_RANGE_HIT 0x180470 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_0 0x180480 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_1 0x180484 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_2 0x180488 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_3 0x18048C + +#define mmMME6_RTR_HBW_RANGE_MASK_L_4 0x180490 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_5 0x180494 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_6 0x180498 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_7 0x18049C + +#define mmMME6_RTR_HBW_RANGE_MASK_H_0 0x1804A0 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_1 0x1804A4 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_2 0x1804A8 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_3 0x1804AC + +#define mmMME6_RTR_HBW_RANGE_MASK_H_4 0x1804B0 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_5 0x1804B4 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_6 0x1804B8 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_7 0x1804BC + +#define mmMME6_RTR_HBW_RANGE_BASE_L_0 0x1804C0 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_1 0x1804C4 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_2 0x1804C8 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_3 0x1804CC + +#define mmMME6_RTR_HBW_RANGE_BASE_L_4 0x1804D0 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_5 0x1804D4 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_6 0x1804D8 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_7 0x1804DC + +#define mmMME6_RTR_HBW_RANGE_BASE_H_0 0x1804E0 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_1 0x1804E4 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_2 0x1804E8 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_3 0x1804EC + +#define mmMME6_RTR_HBW_RANGE_BASE_H_4 0x1804F0 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_5 0x1804F4 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_6 0x1804F8 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_7 0x1804FC + +#define mmMME6_RTR_LBW_RANGE_HIT 0x180500 + +#define mmMME6_RTR_LBW_RANGE_MASK_0 0x180510 + +#define mmMME6_RTR_LBW_RANGE_MASK_1 0x180514 + +#define mmMME6_RTR_LBW_RANGE_MASK_2 0x180518 + +#define mmMME6_RTR_LBW_RANGE_MASK_3 0x18051C + +#define mmMME6_RTR_LBW_RANGE_MASK_4 0x180520 + +#define mmMME6_RTR_LBW_RANGE_MASK_5 0x180524 + +#define mmMME6_RTR_LBW_RANGE_MASK_6 0x180528 + +#define mmMME6_RTR_LBW_RANGE_MASK_7 0x18052C + +#define mmMME6_RTR_LBW_RANGE_MASK_8 0x180530 + +#define mmMME6_RTR_LBW_RANGE_MASK_9 0x180534 + +#define mmMME6_RTR_LBW_RANGE_MASK_10 0x180538 + +#define mmMME6_RTR_LBW_RANGE_MASK_11 0x18053C + +#define mmMME6_RTR_LBW_RANGE_MASK_12 0x180540 + +#define mmMME6_RTR_LBW_RANGE_MASK_13 0x180544 + +#define mmMME6_RTR_LBW_RANGE_MASK_14 0x180548 + +#define mmMME6_RTR_LBW_RANGE_MASK_15 0x18054C + +#define mmMME6_RTR_LBW_RANGE_BASE_0 0x180550 + +#define mmMME6_RTR_LBW_RANGE_BASE_1 0x180554 + +#define mmMME6_RTR_LBW_RANGE_BASE_2 0x180558 + +#define mmMME6_RTR_LBW_RANGE_BASE_3 0x18055C + +#define mmMME6_RTR_LBW_RANGE_BASE_4 0x180560 + +#define mmMME6_RTR_LBW_RANGE_BASE_5 0x180564 + +#define mmMME6_RTR_LBW_RANGE_BASE_6 0x180568 + +#define mmMME6_RTR_LBW_RANGE_BASE_7 0x18056C + +#define mmMME6_RTR_LBW_RANGE_BASE_8 0x180570 + +#define mmMME6_RTR_LBW_RANGE_BASE_9 0x180574 + +#define mmMME6_RTR_LBW_RANGE_BASE_10 0x180578 + +#define mmMME6_RTR_LBW_RANGE_BASE_11 0x18057C + +#define mmMME6_RTR_LBW_RANGE_BASE_12 0x180580 + +#define mmMME6_RTR_LBW_RANGE_BASE_13 0x180584 + +#define mmMME6_RTR_LBW_RANGE_BASE_14 0x180588 + +#define mmMME6_RTR_LBW_RANGE_BASE_15 0x18058C + +#define mmMME6_RTR_RGLTR 0x180590 + +#define mmMME6_RTR_RGLTR_WR_RESULT 0x180594 + +#define mmMME6_RTR_RGLTR_RD_RESULT 0x180598 + +#define mmMME6_RTR_SCRAMB_EN 0x180600 + +#define mmMME6_RTR_NON_LIN_SCRAMB 0x180604 + +#endif /* ASIC_REG_MME6_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h new file mode 100644 index 000000000000..a0d4382fbbd0 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_CMDQ_MASKS_H_ +#define ASIC_REG_MME_CMDQ_MASKS_H_ + +/* + ***************************************** + * MME_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +/* MME_CMDQ_GLBL_CFG0 */ +#define MME_CMDQ_GLBL_CFG0_PQF_EN_SHIFT 0 +#define MME_CMDQ_GLBL_CFG0_PQF_EN_MASK 0x1 +#define MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT 1 +#define MME_CMDQ_GLBL_CFG0_CQF_EN_MASK 0x2 +#define MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT 2 +#define MME_CMDQ_GLBL_CFG0_CP_EN_MASK 0x4 +#define MME_CMDQ_GLBL_CFG0_DMA_EN_SHIFT 3 +#define MME_CMDQ_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* MME_CMDQ_GLBL_CFG1 */ +#define MME_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define MME_CMDQ_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define MME_CMDQ_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT 2 +#define MME_CMDQ_GLBL_CFG1_CP_STOP_MASK 0x4 +#define MME_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define MME_CMDQ_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define MME_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define MME_CMDQ_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* MME_CMDQ_GLBL_PROT */ +#define MME_CMDQ_GLBL_PROT_PQF_PROT_SHIFT 0 +#define MME_CMDQ_GLBL_PROT_PQF_PROT_MASK 0x1 +#define MME_CMDQ_GLBL_PROT_CQF_PROT_SHIFT 1 +#define MME_CMDQ_GLBL_PROT_CQF_PROT_MASK 0x2 +#define MME_CMDQ_GLBL_PROT_CP_PROT_SHIFT 2 +#define MME_CMDQ_GLBL_PROT_CP_PROT_MASK 0x4 +#define MME_CMDQ_GLBL_PROT_DMA_PROT_SHIFT 3 +#define MME_CMDQ_GLBL_PROT_DMA_PROT_MASK 0x8 +#define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* MME_CMDQ_GLBL_ERR_CFG */ +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* MME_CMDQ_GLBL_ERR_ADDR_LO */ +#define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_GLBL_ERR_ADDR_HI */ +#define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_GLBL_ERR_WDATA */ +#define MME_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_GLBL_SECURE_PROPS */ +#define MME_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define MME_CMDQ_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_CMDQ_GLBL_NON_SECURE_PROPS */ +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_CMDQ_GLBL_STS0 */ +#define MME_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define MME_CMDQ_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define MME_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define MME_CMDQ_GLBL_STS0_CP_IDLE_SHIFT 2 +#define MME_CMDQ_GLBL_STS0_CP_IDLE_MASK 0x4 +#define MME_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define MME_CMDQ_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define MME_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define MME_CMDQ_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* MME_CMDQ_GLBL_STS1 */ +#define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define MME_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define MME_CMDQ_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define MME_CMDQ_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* MME_CMDQ_CQ_CFG0 */ +#define MME_CMDQ_CQ_CFG0_RESERVED_SHIFT 0 +#define MME_CMDQ_CQ_CFG0_RESERVED_MASK 0x1 + +/* MME_CMDQ_CQ_CFG1 */ +#define MME_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME_CMDQ_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_ARUSER */ +#define MME_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define MME_CMDQ_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define MME_CMDQ_CQ_ARUSER_WORD_SHIFT 1 +#define MME_CMDQ_CQ_ARUSER_WORD_MASK 0x2 + +/* MME_CMDQ_CQ_PTR_LO */ +#define MME_CMDQ_CQ_PTR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_PTR_HI */ +#define MME_CMDQ_CQ_PTR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_TSIZE */ +#define MME_CMDQ_CQ_TSIZE_VAL_SHIFT 0 +#define MME_CMDQ_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_CTL */ +#define MME_CMDQ_CQ_CTL_RPT_SHIFT 0 +#define MME_CMDQ_CQ_CTL_RPT_MASK 0xFFFF +#define MME_CMDQ_CQ_CTL_CTL_SHIFT 16 +#define MME_CMDQ_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_PTR_LO_STS */ +#define MME_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_PTR_HI_STS */ +#define MME_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_TSIZE_STS */ +#define MME_CMDQ_CQ_TSIZE_STS_VAL_SHIFT 0 +#define MME_CMDQ_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_CTL_STS */ +#define MME_CMDQ_CQ_CTL_STS_RPT_SHIFT 0 +#define MME_CMDQ_CQ_CTL_STS_RPT_MASK 0xFFFF +#define MME_CMDQ_CQ_CTL_STS_CTL_SHIFT 16 +#define MME_CMDQ_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_STS0 */ +#define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_STS1 */ +#define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define MME_CMDQ_CQ_STS1_CQ_BUSY_SHIFT 31 +#define MME_CMDQ_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* MME_CMDQ_CQ_RD_RATE_LIM_EN */ +#define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */ +#define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME_CMDQ_CQ_RD_RATE_LIM_SAT */ +#define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* MME_CMDQ_CQ_RD_RATE_LIM_TOUT */ +#define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* MME_CMDQ_CQ_IFIFO_CNT */ +#define MME_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* MME_CMDQ_CP_MSG_BASE0_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE0_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE1_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE1_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE2_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE2_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE3_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE3_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_TSIZE_OFFSET */ +#define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */ +#define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */ +#define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_COMMIT_OFFSET */ +#define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_FENCE0_RDATA */ +#define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE1_RDATA */ +#define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE2_RDATA */ +#define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE3_RDATA */ +#define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE0_CNT */ +#define MME_CMDQ_CP_FENCE0_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_FENCE1_CNT */ +#define MME_CMDQ_CP_FENCE1_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_FENCE2_CNT */ +#define MME_CMDQ_CP_FENCE2_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_FENCE3_CNT */ +#define MME_CMDQ_CP_FENCE3_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_STS */ +#define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define MME_CMDQ_CP_STS_ERDY_SHIFT 16 +#define MME_CMDQ_CP_STS_ERDY_MASK 0x10000 +#define MME_CMDQ_CP_STS_RRDY_SHIFT 17 +#define MME_CMDQ_CP_STS_RRDY_MASK 0x20000 +#define MME_CMDQ_CP_STS_MRDY_SHIFT 18 +#define MME_CMDQ_CP_STS_MRDY_MASK 0x40000 +#define MME_CMDQ_CP_STS_SW_STOP_SHIFT 19 +#define MME_CMDQ_CP_STS_SW_STOP_MASK 0x80000 +#define MME_CMDQ_CP_STS_FENCE_ID_SHIFT 20 +#define MME_CMDQ_CP_STS_FENCE_ID_MASK 0x300000 +#define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* MME_CMDQ_CP_CURRENT_INST_LO */ +#define MME_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_CURRENT_INST_HI */ +#define MME_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_BARRIER_CFG */ +#define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* MME_CMDQ_CP_DBG_0 */ +#define MME_CMDQ_CP_DBG_0_VAL_SHIFT 0 +#define MME_CMDQ_CP_DBG_0_VAL_MASK 0xFF + +/* MME_CMDQ_CQ_BUF_ADDR */ +#define MME_CMDQ_CQ_BUF_ADDR_VAL_SHIFT 0 +#define MME_CMDQ_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_BUF_RDATA */ +#define MME_CMDQ_CQ_BUF_RDATA_VAL_SHIFT 0 +#define MME_CMDQ_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_MME_CMDQ_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h new file mode 100644 index 000000000000..5c2f6b870a58 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_CMDQ_REGS_H_ +#define ASIC_REG_MME_CMDQ_REGS_H_ + +/* + ***************************************** + * MME_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmMME_CMDQ_GLBL_CFG0 0xD9000 + +#define mmMME_CMDQ_GLBL_CFG1 0xD9004 + +#define mmMME_CMDQ_GLBL_PROT 0xD9008 + +#define mmMME_CMDQ_GLBL_ERR_CFG 0xD900C + +#define mmMME_CMDQ_GLBL_ERR_ADDR_LO 0xD9010 + +#define mmMME_CMDQ_GLBL_ERR_ADDR_HI 0xD9014 + +#define mmMME_CMDQ_GLBL_ERR_WDATA 0xD9018 + +#define mmMME_CMDQ_GLBL_SECURE_PROPS 0xD901C + +#define mmMME_CMDQ_GLBL_NON_SECURE_PROPS 0xD9020 + +#define mmMME_CMDQ_GLBL_STS0 0xD9024 + +#define mmMME_CMDQ_GLBL_STS1 0xD9028 + +#define mmMME_CMDQ_CQ_CFG0 0xD90B0 + +#define mmMME_CMDQ_CQ_CFG1 0xD90B4 + +#define mmMME_CMDQ_CQ_ARUSER 0xD90B8 + +#define mmMME_CMDQ_CQ_PTR_LO 0xD90C0 + +#define mmMME_CMDQ_CQ_PTR_HI 0xD90C4 + +#define mmMME_CMDQ_CQ_TSIZE 0xD90C8 + +#define mmMME_CMDQ_CQ_CTL 0xD90CC + +#define mmMME_CMDQ_CQ_PTR_LO_STS 0xD90D4 + +#define mmMME_CMDQ_CQ_PTR_HI_STS 0xD90D8 + +#define mmMME_CMDQ_CQ_TSIZE_STS 0xD90DC + +#define mmMME_CMDQ_CQ_CTL_STS 0xD90E0 + +#define mmMME_CMDQ_CQ_STS0 0xD90E4 + +#define mmMME_CMDQ_CQ_STS1 0xD90E8 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_EN 0xD90F0 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xD90F4 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_SAT 0xD90F8 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT 0xD90FC + +#define mmMME_CMDQ_CQ_IFIFO_CNT 0xD9108 + +#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO 0xD9120 + +#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI 0xD9124 + +#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO 0xD9128 + +#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI 0xD912C + +#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO 0xD9130 + +#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI 0xD9134 + +#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO 0xD9138 + +#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI 0xD913C + +#define mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET 0xD9140 + +#define mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xD9144 + +#define mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xD9148 + +#define mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xD914C + +#define mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xD9150 + +#define mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET 0xD9154 + +#define mmMME_CMDQ_CP_FENCE0_RDATA 0xD9158 + +#define mmMME_CMDQ_CP_FENCE1_RDATA 0xD915C + +#define mmMME_CMDQ_CP_FENCE2_RDATA 0xD9160 + +#define mmMME_CMDQ_CP_FENCE3_RDATA 0xD9164 + +#define mmMME_CMDQ_CP_FENCE0_CNT 0xD9168 + +#define mmMME_CMDQ_CP_FENCE1_CNT 0xD916C + +#define mmMME_CMDQ_CP_FENCE2_CNT 0xD9170 + +#define mmMME_CMDQ_CP_FENCE3_CNT 0xD9174 + +#define mmMME_CMDQ_CP_STS 0xD9178 + +#define mmMME_CMDQ_CP_CURRENT_INST_LO 0xD917C + +#define mmMME_CMDQ_CP_CURRENT_INST_HI 0xD9180 + +#define mmMME_CMDQ_CP_BARRIER_CFG 0xD9184 + +#define mmMME_CMDQ_CP_DBG_0 0xD9188 + +#define mmMME_CMDQ_CQ_BUF_ADDR 0xD9308 + +#define mmMME_CMDQ_CQ_BUF_RDATA 0xD930C + +#endif /* ASIC_REG_MME_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h new file mode 100644 index 000000000000..c7b1b0bb3384 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h @@ -0,0 +1,1537 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_MASKS_H_ +#define ASIC_REG_MME_MASKS_H_ + +/* + ***************************************** + * MME (Prototype: MME) + ***************************************** + */ + +/* MME_ARCH_STATUS */ +#define MME_ARCH_STATUS_A_SHIFT 0 +#define MME_ARCH_STATUS_A_MASK 0x1 +#define MME_ARCH_STATUS_B_SHIFT 1 +#define MME_ARCH_STATUS_B_MASK 0x2 +#define MME_ARCH_STATUS_CIN_SHIFT 2 +#define MME_ARCH_STATUS_CIN_MASK 0x4 +#define MME_ARCH_STATUS_COUT_SHIFT 3 +#define MME_ARCH_STATUS_COUT_MASK 0x8 +#define MME_ARCH_STATUS_TE_SHIFT 4 +#define MME_ARCH_STATUS_TE_MASK 0x10 +#define MME_ARCH_STATUS_LD_SHIFT 5 +#define MME_ARCH_STATUS_LD_MASK 0x20 +#define MME_ARCH_STATUS_ST_SHIFT 6 +#define MME_ARCH_STATUS_ST_MASK 0x40 +#define MME_ARCH_STATUS_SB_A_EMPTY_SHIFT 7 +#define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 +#define MME_ARCH_STATUS_SB_B_EMPTY_SHIFT 8 +#define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 +#define MME_ARCH_STATUS_SB_CIN_EMPTY_SHIFT 9 +#define MME_ARCH_STATUS_SB_CIN_EMPTY_MASK 0x200 +#define MME_ARCH_STATUS_SB_COUT_EMPTY_SHIFT 10 +#define MME_ARCH_STATUS_SB_COUT_EMPTY_MASK 0x400 +#define MME_ARCH_STATUS_SM_IDLE_SHIFT 11 +#define MME_ARCH_STATUS_SM_IDLE_MASK 0x800 +#define MME_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 12 +#define MME_ARCH_STATUS_WBC_AXI_IDLE_MASK 0xF000 +#define MME_ARCH_STATUS_SBC_AXI_IDLE_SHIFT 16 +#define MME_ARCH_STATUS_SBC_AXI_IDLE_MASK 0x30000 +#define MME_ARCH_STATUS_SBB_AXI_IDLE_SHIFT 18 +#define MME_ARCH_STATUS_SBB_AXI_IDLE_MASK 0xC0000 +#define MME_ARCH_STATUS_SBA_AXI_IDLE_SHIFT 20 +#define MME_ARCH_STATUS_SBA_AXI_IDLE_MASK 0x300000 +#define MME_ARCH_STATUS_FREE_ACCUMS_SHIFT 22 +#define MME_ARCH_STATUS_FREE_ACCUMS_MASK 0x1C00000 + +/* MME_ARCH_A_BASE_ADDR_HIGH */ +#define MME_ARCH_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_BASE_ADDR_HIGH */ +#define MME_ARCH_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_CIN_BASE_ADDR_HIGH */ +#define MME_ARCH_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_COUT_BASE_ADDR_HIGH */ +#define MME_ARCH_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_BIAS_BASE_ADDR_HIGH */ +#define MME_ARCH_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_BASE_ADDR_LOW */ +#define MME_ARCH_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_BASE_ADDR_LOW */ +#define MME_ARCH_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_CIN_BASE_ADDR_LOW */ +#define MME_ARCH_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_COUT_BASE_ADDR_LOW */ +#define MME_ARCH_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_BIAS_BASE_ADDR_LOW */ +#define MME_ARCH_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_HEADER */ +#define MME_ARCH_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_ARCH_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_ARCH_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_ARCH_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_ARCH_HEADER_TRANS_A_SHIFT 6 +#define MME_ARCH_HEADER_TRANS_A_MASK 0x40 +#define MME_ARCH_HEADER_LOWER_A_SHIFT 7 +#define MME_ARCH_HEADER_LOWER_A_MASK 0x80 +#define MME_ARCH_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_ARCH_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_ARCH_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_ARCH_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_ARCH_HEADER_LOAD_CIN_SHIFT 13 +#define MME_ARCH_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_ARCH_HEADER_STORE_OUT_SHIFT 15 +#define MME_ARCH_HEADER_STORE_OUT_MASK 0x8000 +#define MME_ARCH_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_ARCH_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_ARCH_HEADER_ADVANCE_A_SHIFT 17 +#define MME_ARCH_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_ARCH_HEADER_ADVANCE_B_SHIFT 18 +#define MME_ARCH_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_ARCH_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_ARCH_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_ARCH_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_ARCH_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_ARCH_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_ARCH_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_ARCH_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_ARCH_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_ARCH_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_ARCH_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_ARCH_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_ARCH_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_ARCH_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_ARCH_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_ARCH_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_ARCH_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_ARCH_KERNEL_SIZE_MINUS_1 */ +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_ARCH_ASSOCIATED_DIMS */ +#define MME_ARCH_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_ARCH_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_ARCH_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_ARCH_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_ARCH_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_ARCH_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_ARCH_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_ARCH_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_ARCH_COUT_SCALE */ +#define MME_ARCH_COUT_SCALE_V_SHIFT 0 +#define MME_ARCH_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_CIN_SCALE */ +#define MME_ARCH_CIN_SCALE_V_SHIFT 0 +#define MME_ARCH_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_GEMMLOWP_ZP */ +#define MME_ARCH_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_ARCH_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_ARCH_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_ARCH_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_ARCH_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_ARCH_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_ARCH_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_ARCH_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_ARCH_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_ARCH_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_ARCH_GEMMLOWP_EXPONENT */ +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_ARCH_A_ROI_BASE_OFFSET */ +#define MME_ARCH_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_ARCH_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_VALID_ELEMENTS */ +#define MME_ARCH_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_ARCH_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_LOOP_STRIDE */ +#define MME_ARCH_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_ARCH_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_ROI_SIZE */ +#define MME_ARCH_A_ROI_SIZE_V_SHIFT 0 +#define MME_ARCH_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_SPATIAL_START_OFFSET */ +#define MME_ARCH_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_ARCH_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_SPATIAL_STRIDE */ +#define MME_ARCH_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_ARCH_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_ARCH_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_ARCH_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_ROI_BASE_OFFSET */ +#define MME_ARCH_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_ARCH_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_VALID_ELEMENTS */ +#define MME_ARCH_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_ARCH_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_LOOP_STRIDE */ +#define MME_ARCH_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_ARCH_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_ROI_SIZE */ +#define MME_ARCH_B_ROI_SIZE_V_SHIFT 0 +#define MME_ARCH_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_SPATIAL_START_OFFSET */ +#define MME_ARCH_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_ARCH_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_SPATIAL_STRIDE */ +#define MME_ARCH_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_ARCH_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_ARCH_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_ARCH_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_ROI_BASE_OFFSET */ +#define MME_ARCH_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_ARCH_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_VALID_ELEMENTS */ +#define MME_ARCH_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_ARCH_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_LOOP_STRIDE */ +#define MME_ARCH_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_ARCH_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_ROI_SIZE */ +#define MME_ARCH_C_ROI_SIZE_V_SHIFT 0 +#define MME_ARCH_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_SPATIAL_START_OFFSET */ +#define MME_ARCH_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_ARCH_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_SPATIAL_STRIDE */ +#define MME_ARCH_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_ARCH_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_ARCH_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_ARCH_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_SYNC_OBJECT_MESSAGE */ +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_ARCH_E_PADDING_VALUE_A */ +#define MME_ARCH_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_ARCH_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_ARCH_E_NUM_ITERATION_MINUS_1 */ +#define MME_ARCH_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_ARCH_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_E_BUBBLES_PER_SPLIT */ +#define MME_ARCH_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_ARCH_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_CMD */ +#define MME_CMD_EXECUTE_SHIFT 0 +#define MME_CMD_EXECUTE_MASK 0x1 + +/* MME_DUMMY */ +#define MME_DUMMY_V_SHIFT 0 +#define MME_DUMMY_V_MASK 0xFFFFFFFF + +/* MME_RESET */ +#define MME_RESET_V_SHIFT 0 +#define MME_RESET_V_MASK 0x1 + +/* MME_STALL */ +#define MME_STALL_V_SHIFT 0 +#define MME_STALL_V_MASK 0xFFFFFFFF + +/* MME_SM_BASE_ADDRESS_LOW */ +#define MME_SM_BASE_ADDRESS_LOW_V_SHIFT 0 +#define MME_SM_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* MME_SM_BASE_ADDRESS_HIGH */ +#define MME_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define MME_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_ADD */ +#define MME_DBGMEM_ADD_V_SHIFT 0 +#define MME_DBGMEM_ADD_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_DATA_WR */ +#define MME_DBGMEM_DATA_WR_V_SHIFT 0 +#define MME_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_DATA_RD */ +#define MME_DBGMEM_DATA_RD_V_SHIFT 0 +#define MME_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_CTRL */ +#define MME_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define MME_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* MME_DBGMEM_RC */ +#define MME_DBGMEM_RC_VALID_SHIFT 0 +#define MME_DBGMEM_RC_VALID_MASK 0x1 +#define MME_DBGMEM_RC_FULL_SHIFT 1 +#define MME_DBGMEM_RC_FULL_MASK 0x2 + +/* MME_LOG_SHADOW */ +#define MME_LOG_SHADOW_MASK_0_SHIFT 0 +#define MME_LOG_SHADOW_MASK_0_MASK 0x7F +#define MME_LOG_SHADOW_MASK_1_SHIFT 8 +#define MME_LOG_SHADOW_MASK_1_MASK 0x7F00 +#define MME_LOG_SHADOW_MASK_2_SHIFT 16 +#define MME_LOG_SHADOW_MASK_2_MASK 0x7F0000 +#define MME_LOG_SHADOW_MASK_3_SHIFT 24 +#define MME_LOG_SHADOW_MASK_3_MASK 0x7F000000 + +/* MME_STORE_MAX_CREDIT */ +#define MME_STORE_MAX_CREDIT_V_SHIFT 0 +#define MME_STORE_MAX_CREDIT_V_MASK 0x3F + +/* MME_AGU */ +#define MME_AGU_SBA_MAX_CREDIT_SHIFT 0 +#define MME_AGU_SBA_MAX_CREDIT_MASK 0x1F +#define MME_AGU_SBB_MAX_CREDIT_SHIFT 8 +#define MME_AGU_SBB_MAX_CREDIT_MASK 0x1F00 +#define MME_AGU_SBC_MAX_CREDIT_SHIFT 16 +#define MME_AGU_SBC_MAX_CREDIT_MASK 0x1F0000 +#define MME_AGU_WBC_MAX_CREDIT_SHIFT 24 +#define MME_AGU_WBC_MAX_CREDIT_MASK 0x3F000000 + +/* MME_SBA */ +#define MME_SBA_MAX_SIZE_SHIFT 0 +#define MME_SBA_MAX_SIZE_MASK 0x3FF +#define MME_SBA_EU_MAX_CREDIT_SHIFT 16 +#define MME_SBA_EU_MAX_CREDIT_MASK 0x1F0000 + +/* MME_SBB */ +#define MME_SBB_MAX_SIZE_SHIFT 0 +#define MME_SBB_MAX_SIZE_MASK 0x3FF +#define MME_SBB_EU_MAX_CREDIT_SHIFT 16 +#define MME_SBB_EU_MAX_CREDIT_MASK 0x1F0000 + +/* MME_SBC */ +#define MME_SBC_MAX_SIZE_SHIFT 0 +#define MME_SBC_MAX_SIZE_MASK 0x3FF +#define MME_SBC_EU_MAX_CREDIT_SHIFT 16 +#define MME_SBC_EU_MAX_CREDIT_MASK 0x1F0000 + +/* MME_WBC */ +#define MME_WBC_MAX_OUTSTANDING_SHIFT 0 +#define MME_WBC_MAX_OUTSTANDING_MASK 0xFFF +#define MME_WBC_DISABLE_FAST_END_PE_SHIFT 12 +#define MME_WBC_DISABLE_FAST_END_PE_MASK 0x1000 +#define MME_WBC_LD_INSERT_BUBBLE_DIS_SHIFT 13 +#define MME_WBC_LD_INSERT_BUBBLE_DIS_MASK 0x2000 + +/* MME_SBA_CONTROL_DATA */ +#define MME_SBA_CONTROL_DATA_ASID_SHIFT 0 +#define MME_SBA_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_SBA_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_SBA_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_SBB_CONTROL_DATA */ +#define MME_SBB_CONTROL_DATA_ASID_SHIFT 0 +#define MME_SBB_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_SBB_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_SBB_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_SBC_CONTROL_DATA */ +#define MME_SBC_CONTROL_DATA_ASID_SHIFT 0 +#define MME_SBC_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_SBC_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_SBC_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_WBC_CONTROL_DATA */ +#define MME_WBC_CONTROL_DATA_ASID_SHIFT 0 +#define MME_WBC_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_WBC_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_WBC_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_TE */ +#define MME_TE_MAX_CREDIT_SHIFT 0 +#define MME_TE_MAX_CREDIT_MASK 0x1F +#define MME_TE_DESC_MAX_CREDIT_SHIFT 8 +#define MME_TE_DESC_MAX_CREDIT_MASK 0x1F00 + +/* MME_TE2DEC */ +#define MME_TE2DEC_MAX_CREDIT_SHIFT 0 +#define MME_TE2DEC_MAX_CREDIT_MASK 0x1F + +/* MME_REI_STATUS */ +#define MME_REI_STATUS_V_SHIFT 0 +#define MME_REI_STATUS_V_MASK 0xFFFFFFFF + +/* MME_REI_MASK */ +#define MME_REI_MASK_V_SHIFT 0 +#define MME_REI_MASK_V_MASK 0xFFFFFFFF + +/* MME_SEI_STATUS */ +#define MME_SEI_STATUS_V_SHIFT 0 +#define MME_SEI_STATUS_V_MASK 0xFFFFFFFF + +/* MME_SEI_MASK */ +#define MME_SEI_MASK_V_SHIFT 0 +#define MME_SEI_MASK_V_MASK 0xFFFFFFFF + +/* MME_SPI_STATUS */ +#define MME_SPI_STATUS_V_SHIFT 0 +#define MME_SPI_STATUS_V_MASK 0xFFFFFFFF + +/* MME_SPI_MASK */ +#define MME_SPI_MASK_V_SHIFT 0 +#define MME_SPI_MASK_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_STATUS */ +#define MME_SHADOW_0_STATUS_A_SHIFT 0 +#define MME_SHADOW_0_STATUS_A_MASK 0x1 +#define MME_SHADOW_0_STATUS_B_SHIFT 1 +#define MME_SHADOW_0_STATUS_B_MASK 0x2 +#define MME_SHADOW_0_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_0_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_0_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_0_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_0_STATUS_TE_SHIFT 4 +#define MME_SHADOW_0_STATUS_TE_MASK 0x10 +#define MME_SHADOW_0_STATUS_LD_SHIFT 5 +#define MME_SHADOW_0_STATUS_LD_MASK 0x20 +#define MME_SHADOW_0_STATUS_ST_SHIFT 6 +#define MME_SHADOW_0_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_0_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_BASE_ADDR_LOW */ +#define MME_SHADOW_0_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_BASE_ADDR_LOW */ +#define MME_SHADOW_0_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_0_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_0_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_0_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_HEADER */ +#define MME_SHADOW_0_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_0_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_0_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_0_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_0_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_0_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_0_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_0_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_0_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_0_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_0_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_0_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_0_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_0_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_0_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_0_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_0_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_0_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_0_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_0_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_0_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_0_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_0_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_0_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_0_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_0_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_0_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_0_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_0_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_0_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_0_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_0_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_0_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_0_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_0_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_0_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_0_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_0_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_0_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_0_ASSOCIATED_DIMS */ +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_0_COUT_SCALE */ +#define MME_SHADOW_0_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_0_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_CIN_SCALE */ +#define MME_SHADOW_0_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_0_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_GEMMLOWP_ZP */ +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_0_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_0_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_0_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_0_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_0_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_0_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_0_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_VALID_ELEMENTS */ +#define MME_SHADOW_0_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_0_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_LOOP_STRIDE */ +#define MME_SHADOW_0_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_ROI_SIZE */ +#define MME_SHADOW_0_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_0_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_0_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_SPATIAL_STRIDE */ +#define MME_SHADOW_0_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_0_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_VALID_ELEMENTS */ +#define MME_SHADOW_0_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_0_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_LOOP_STRIDE */ +#define MME_SHADOW_0_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_ROI_SIZE */ +#define MME_SHADOW_0_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_0_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_0_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_SPATIAL_STRIDE */ +#define MME_SHADOW_0_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_0_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_VALID_ELEMENTS */ +#define MME_SHADOW_0_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_0_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_LOOP_STRIDE */ +#define MME_SHADOW_0_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_ROI_SIZE */ +#define MME_SHADOW_0_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_0_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_0_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_SPATIAL_STRIDE */ +#define MME_SHADOW_0_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_0_E_PADDING_VALUE_A */ +#define MME_SHADOW_0_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_0_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_0_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_0_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_SHADOW_1_STATUS */ +#define MME_SHADOW_1_STATUS_A_SHIFT 0 +#define MME_SHADOW_1_STATUS_A_MASK 0x1 +#define MME_SHADOW_1_STATUS_B_SHIFT 1 +#define MME_SHADOW_1_STATUS_B_MASK 0x2 +#define MME_SHADOW_1_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_1_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_1_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_1_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_1_STATUS_TE_SHIFT 4 +#define MME_SHADOW_1_STATUS_TE_MASK 0x10 +#define MME_SHADOW_1_STATUS_LD_SHIFT 5 +#define MME_SHADOW_1_STATUS_LD_MASK 0x20 +#define MME_SHADOW_1_STATUS_ST_SHIFT 6 +#define MME_SHADOW_1_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_1_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_BASE_ADDR_LOW */ +#define MME_SHADOW_1_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_BASE_ADDR_LOW */ +#define MME_SHADOW_1_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_1_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_1_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_1_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_HEADER */ +#define MME_SHADOW_1_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_1_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_1_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_1_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_1_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_1_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_1_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_1_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_1_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_1_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_1_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_1_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_1_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_1_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_1_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_1_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_1_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_1_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_1_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_1_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_1_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_1_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_1_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_1_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_1_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_1_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_1_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_1_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_1_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_1_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_1_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_1_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_1_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_1_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_1_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_1_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_1_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_1_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_1_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_1_ASSOCIATED_DIMS */ +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_1_COUT_SCALE */ +#define MME_SHADOW_1_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_1_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_CIN_SCALE */ +#define MME_SHADOW_1_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_1_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_GEMMLOWP_ZP */ +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_1_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_1_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_1_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_1_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_1_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_1_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_1_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_VALID_ELEMENTS */ +#define MME_SHADOW_1_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_1_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_LOOP_STRIDE */ +#define MME_SHADOW_1_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_ROI_SIZE */ +#define MME_SHADOW_1_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_1_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_1_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_SPATIAL_STRIDE */ +#define MME_SHADOW_1_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_1_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_VALID_ELEMENTS */ +#define MME_SHADOW_1_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_1_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_LOOP_STRIDE */ +#define MME_SHADOW_1_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_ROI_SIZE */ +#define MME_SHADOW_1_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_1_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_1_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_SPATIAL_STRIDE */ +#define MME_SHADOW_1_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_1_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_VALID_ELEMENTS */ +#define MME_SHADOW_1_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_1_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_LOOP_STRIDE */ +#define MME_SHADOW_1_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_ROI_SIZE */ +#define MME_SHADOW_1_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_1_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_1_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_SPATIAL_STRIDE */ +#define MME_SHADOW_1_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_1_E_PADDING_VALUE_A */ +#define MME_SHADOW_1_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_1_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_1_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_1_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_SHADOW_2_STATUS */ +#define MME_SHADOW_2_STATUS_A_SHIFT 0 +#define MME_SHADOW_2_STATUS_A_MASK 0x1 +#define MME_SHADOW_2_STATUS_B_SHIFT 1 +#define MME_SHADOW_2_STATUS_B_MASK 0x2 +#define MME_SHADOW_2_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_2_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_2_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_2_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_2_STATUS_TE_SHIFT 4 +#define MME_SHADOW_2_STATUS_TE_MASK 0x10 +#define MME_SHADOW_2_STATUS_LD_SHIFT 5 +#define MME_SHADOW_2_STATUS_LD_MASK 0x20 +#define MME_SHADOW_2_STATUS_ST_SHIFT 6 +#define MME_SHADOW_2_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_2_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_BASE_ADDR_LOW */ +#define MME_SHADOW_2_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_BASE_ADDR_LOW */ +#define MME_SHADOW_2_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_2_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_2_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_2_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_HEADER */ +#define MME_SHADOW_2_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_2_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_2_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_2_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_2_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_2_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_2_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_2_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_2_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_2_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_2_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_2_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_2_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_2_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_2_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_2_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_2_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_2_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_2_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_2_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_2_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_2_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_2_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_2_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_2_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_2_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_2_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_2_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_2_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_2_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_2_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_2_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_2_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_2_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_2_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_2_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_2_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_2_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_2_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_2_ASSOCIATED_DIMS */ +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_2_COUT_SCALE */ +#define MME_SHADOW_2_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_2_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_CIN_SCALE */ +#define MME_SHADOW_2_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_2_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_GEMMLOWP_ZP */ +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_2_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_2_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_2_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_2_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_2_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_2_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_2_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_VALID_ELEMENTS */ +#define MME_SHADOW_2_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_2_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_LOOP_STRIDE */ +#define MME_SHADOW_2_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_ROI_SIZE */ +#define MME_SHADOW_2_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_2_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_2_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_SPATIAL_STRIDE */ +#define MME_SHADOW_2_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_2_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_VALID_ELEMENTS */ +#define MME_SHADOW_2_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_2_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_LOOP_STRIDE */ +#define MME_SHADOW_2_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_ROI_SIZE */ +#define MME_SHADOW_2_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_2_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_2_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_SPATIAL_STRIDE */ +#define MME_SHADOW_2_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_2_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_VALID_ELEMENTS */ +#define MME_SHADOW_2_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_2_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_LOOP_STRIDE */ +#define MME_SHADOW_2_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_ROI_SIZE */ +#define MME_SHADOW_2_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_2_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_2_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_SPATIAL_STRIDE */ +#define MME_SHADOW_2_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_2_E_PADDING_VALUE_A */ +#define MME_SHADOW_2_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_2_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_2_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_2_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_SHADOW_3_STATUS */ +#define MME_SHADOW_3_STATUS_A_SHIFT 0 +#define MME_SHADOW_3_STATUS_A_MASK 0x1 +#define MME_SHADOW_3_STATUS_B_SHIFT 1 +#define MME_SHADOW_3_STATUS_B_MASK 0x2 +#define MME_SHADOW_3_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_3_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_3_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_3_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_3_STATUS_TE_SHIFT 4 +#define MME_SHADOW_3_STATUS_TE_MASK 0x10 +#define MME_SHADOW_3_STATUS_LD_SHIFT 5 +#define MME_SHADOW_3_STATUS_LD_MASK 0x20 +#define MME_SHADOW_3_STATUS_ST_SHIFT 6 +#define MME_SHADOW_3_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_3_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_BASE_ADDR_LOW */ +#define MME_SHADOW_3_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_BASE_ADDR_LOW */ +#define MME_SHADOW_3_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_3_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_3_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_3_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_HEADER */ +#define MME_SHADOW_3_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_3_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_3_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_3_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_3_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_3_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_3_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_3_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_3_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_3_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_3_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_3_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_3_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_3_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_3_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_3_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_3_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_3_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_3_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_3_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_3_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_3_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_3_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_3_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_3_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_3_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_3_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_3_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_3_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_3_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_3_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_3_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_3_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_3_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_3_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_3_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_3_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_3_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_3_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_3_ASSOCIATED_DIMS */ +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_3_COUT_SCALE */ +#define MME_SHADOW_3_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_3_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_CIN_SCALE */ +#define MME_SHADOW_3_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_3_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_GEMMLOWP_ZP */ +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_3_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_3_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_3_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_3_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_3_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_3_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_3_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_VALID_ELEMENTS */ +#define MME_SHADOW_3_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_3_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_LOOP_STRIDE */ +#define MME_SHADOW_3_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_ROI_SIZE */ +#define MME_SHADOW_3_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_3_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_3_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_SPATIAL_STRIDE */ +#define MME_SHADOW_3_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_3_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_VALID_ELEMENTS */ +#define MME_SHADOW_3_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_3_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_LOOP_STRIDE */ +#define MME_SHADOW_3_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_ROI_SIZE */ +#define MME_SHADOW_3_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_3_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_3_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_SPATIAL_STRIDE */ +#define MME_SHADOW_3_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_3_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_VALID_ELEMENTS */ +#define MME_SHADOW_3_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_3_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_LOOP_STRIDE */ +#define MME_SHADOW_3_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_ROI_SIZE */ +#define MME_SHADOW_3_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_3_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_3_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_SPATIAL_STRIDE */ +#define MME_SHADOW_3_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_3_E_PADDING_VALUE_A */ +#define MME_SHADOW_3_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_3_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_3_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_3_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +#endif /* ASIC_REG_MME_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h new file mode 100644 index 000000000000..d4bfa58dce19 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h @@ -0,0 +1,465 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_QM_MASKS_H_ +#define ASIC_REG_MME_QM_MASKS_H_ + +/* + ***************************************** + * MME_QM (Prototype: QMAN) + ***************************************** + */ + +/* MME_QM_GLBL_CFG0 */ +#define MME_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define MME_QM_GLBL_CFG0_PQF_EN_MASK 0x1 +#define MME_QM_GLBL_CFG0_CQF_EN_SHIFT 1 +#define MME_QM_GLBL_CFG0_CQF_EN_MASK 0x2 +#define MME_QM_GLBL_CFG0_CP_EN_SHIFT 2 +#define MME_QM_GLBL_CFG0_CP_EN_MASK 0x4 +#define MME_QM_GLBL_CFG0_DMA_EN_SHIFT 3 +#define MME_QM_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* MME_QM_GLBL_CFG1 */ +#define MME_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define MME_QM_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define MME_QM_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define MME_QM_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define MME_QM_GLBL_CFG1_CP_STOP_SHIFT 2 +#define MME_QM_GLBL_CFG1_CP_STOP_MASK 0x4 +#define MME_QM_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define MME_QM_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define MME_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define MME_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define MME_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define MME_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define MME_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define MME_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define MME_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define MME_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* MME_QM_GLBL_PROT */ +#define MME_QM_GLBL_PROT_PQF_PROT_SHIFT 0 +#define MME_QM_GLBL_PROT_PQF_PROT_MASK 0x1 +#define MME_QM_GLBL_PROT_CQF_PROT_SHIFT 1 +#define MME_QM_GLBL_PROT_CQF_PROT_MASK 0x2 +#define MME_QM_GLBL_PROT_CP_PROT_SHIFT 2 +#define MME_QM_GLBL_PROT_CP_PROT_MASK 0x4 +#define MME_QM_GLBL_PROT_DMA_PROT_SHIFT 3 +#define MME_QM_GLBL_PROT_DMA_PROT_MASK 0x8 +#define MME_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define MME_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define MME_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define MME_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define MME_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define MME_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define MME_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define MME_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* MME_QM_GLBL_ERR_CFG */ +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* MME_QM_GLBL_ERR_ADDR_LO */ +#define MME_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_GLBL_ERR_ADDR_HI */ +#define MME_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_GLBL_ERR_WDATA */ +#define MME_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define MME_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME_QM_GLBL_SECURE_PROPS */ +#define MME_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define MME_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_QM_GLBL_NON_SECURE_PROPS */ +#define MME_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define MME_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_QM_GLBL_STS0 */ +#define MME_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define MME_QM_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define MME_QM_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define MME_QM_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define MME_QM_GLBL_STS0_CP_IDLE_SHIFT 2 +#define MME_QM_GLBL_STS0_CP_IDLE_MASK 0x4 +#define MME_QM_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define MME_QM_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define MME_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define MME_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define MME_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define MME_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define MME_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define MME_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define MME_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define MME_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* MME_QM_GLBL_STS1 */ +#define MME_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define MME_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define MME_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define MME_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define MME_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define MME_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define MME_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define MME_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define MME_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define MME_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define MME_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define MME_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define MME_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define MME_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define MME_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define MME_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define MME_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define MME_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* MME_QM_PQ_BASE_LO */ +#define MME_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define MME_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_BASE_HI */ +#define MME_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define MME_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_SIZE */ +#define MME_QM_PQ_SIZE_VAL_SHIFT 0 +#define MME_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PI */ +#define MME_QM_PQ_PI_VAL_SHIFT 0 +#define MME_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_CI */ +#define MME_QM_PQ_CI_VAL_SHIFT 0 +#define MME_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_CFG0 */ +#define MME_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define MME_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* MME_QM_PQ_CFG1 */ +#define MME_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME_QM_PQ_ARUSER */ +#define MME_QM_PQ_ARUSER_NOSNOOP_SHIFT 0 +#define MME_QM_PQ_ARUSER_NOSNOOP_MASK 0x1 +#define MME_QM_PQ_ARUSER_WORD_SHIFT 1 +#define MME_QM_PQ_ARUSER_WORD_MASK 0x2 + +/* MME_QM_PQ_PUSH0 */ +#define MME_QM_PQ_PUSH0_PTR_LO_SHIFT 0 +#define MME_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PUSH1 */ +#define MME_QM_PQ_PUSH1_PTR_HI_SHIFT 0 +#define MME_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PUSH2 */ +#define MME_QM_PQ_PUSH2_TSIZE_SHIFT 0 +#define MME_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PUSH3 */ +#define MME_QM_PQ_PUSH3_RPT_SHIFT 0 +#define MME_QM_PQ_PUSH3_RPT_MASK 0xFFFF +#define MME_QM_PQ_PUSH3_CTL_SHIFT 16 +#define MME_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000 + +/* MME_QM_PQ_STS0 */ +#define MME_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define MME_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define MME_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define MME_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME_QM_PQ_STS1 */ +#define MME_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define MME_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define MME_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define MME_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define MME_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* MME_QM_PQ_RD_RATE_LIM_EN */ +#define MME_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* MME_QM_PQ_RD_RATE_LIM_RST_TOKEN */ +#define MME_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME_QM_PQ_RD_RATE_LIM_SAT */ +#define MME_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* MME_QM_PQ_RD_RATE_LIM_TOUT */ +#define MME_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* MME_QM_CQ_CFG0 */ +#define MME_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define MME_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* MME_QM_CQ_CFG1 */ +#define MME_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME_QM_CQ_ARUSER */ +#define MME_QM_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define MME_QM_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define MME_QM_CQ_ARUSER_WORD_SHIFT 1 +#define MME_QM_CQ_ARUSER_WORD_MASK 0x2 + +/* MME_QM_CQ_PTR_LO */ +#define MME_QM_CQ_PTR_LO_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_PTR_HI */ +#define MME_QM_CQ_PTR_HI_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_TSIZE */ +#define MME_QM_CQ_TSIZE_VAL_SHIFT 0 +#define MME_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_CTL */ +#define MME_QM_CQ_CTL_RPT_SHIFT 0 +#define MME_QM_CQ_CTL_RPT_MASK 0xFFFF +#define MME_QM_CQ_CTL_CTL_SHIFT 16 +#define MME_QM_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* MME_QM_CQ_PTR_LO_STS */ +#define MME_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_PTR_HI_STS */ +#define MME_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_TSIZE_STS */ +#define MME_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define MME_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_CTL_STS */ +#define MME_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define MME_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define MME_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define MME_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* MME_QM_CQ_STS0 */ +#define MME_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define MME_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define MME_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define MME_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME_QM_CQ_STS1 */ +#define MME_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define MME_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define MME_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define MME_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define MME_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* MME_QM_CQ_RD_RATE_LIM_EN */ +#define MME_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* MME_QM_CQ_RD_RATE_LIM_RST_TOKEN */ +#define MME_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME_QM_CQ_RD_RATE_LIM_SAT */ +#define MME_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* MME_QM_CQ_RD_RATE_LIM_TOUT */ +#define MME_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* MME_QM_CQ_IFIFO_CNT */ +#define MME_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define MME_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* MME_QM_CP_MSG_BASE0_ADDR_LO */ +#define MME_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE0_ADDR_HI */ +#define MME_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE1_ADDR_LO */ +#define MME_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE1_ADDR_HI */ +#define MME_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE2_ADDR_LO */ +#define MME_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE2_ADDR_HI */ +#define MME_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE3_ADDR_LO */ +#define MME_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE3_ADDR_HI */ +#define MME_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_TSIZE_OFFSET */ +#define MME_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define MME_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define MME_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_DST_BASE_HI_OFFSET */ +#define MME_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_COMMIT_OFFSET */ +#define MME_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_FENCE0_RDATA */ +#define MME_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE1_RDATA */ +#define MME_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE2_RDATA */ +#define MME_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE3_RDATA */ +#define MME_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE0_CNT */ +#define MME_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_FENCE1_CNT */ +#define MME_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_FENCE2_CNT */ +#define MME_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_FENCE3_CNT */ +#define MME_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_STS */ +#define MME_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define MME_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define MME_QM_CP_STS_ERDY_SHIFT 16 +#define MME_QM_CP_STS_ERDY_MASK 0x10000 +#define MME_QM_CP_STS_RRDY_SHIFT 17 +#define MME_QM_CP_STS_RRDY_MASK 0x20000 +#define MME_QM_CP_STS_MRDY_SHIFT 18 +#define MME_QM_CP_STS_MRDY_MASK 0x40000 +#define MME_QM_CP_STS_SW_STOP_SHIFT 19 +#define MME_QM_CP_STS_SW_STOP_MASK 0x80000 +#define MME_QM_CP_STS_FENCE_ID_SHIFT 20 +#define MME_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define MME_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define MME_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* MME_QM_CP_CURRENT_INST_LO */ +#define MME_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define MME_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_CURRENT_INST_HI */ +#define MME_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define MME_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_BARRIER_CFG */ +#define MME_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define MME_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* MME_QM_CP_DBG_0 */ +#define MME_QM_CP_DBG_0_VAL_SHIFT 0 +#define MME_QM_CP_DBG_0_VAL_MASK 0xFF + +/* MME_QM_PQ_BUF_ADDR */ +#define MME_QM_PQ_BUF_ADDR_VAL_SHIFT 0 +#define MME_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_BUF_RDATA */ +#define MME_QM_PQ_BUF_RDATA_VAL_SHIFT 0 +#define MME_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_BUF_ADDR */ +#define MME_QM_CQ_BUF_ADDR_VAL_SHIFT 0 +#define MME_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_BUF_RDATA */ +#define MME_QM_CQ_BUF_RDATA_VAL_SHIFT 0 +#define MME_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_MME_QM_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h new file mode 100644 index 000000000000..b5b1c776f6c3 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_QM_REGS_H_ +#define ASIC_REG_MME_QM_REGS_H_ + +/* + ***************************************** + * MME_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME_QM_GLBL_CFG0 0xD8000 + +#define mmMME_QM_GLBL_CFG1 0xD8004 + +#define mmMME_QM_GLBL_PROT 0xD8008 + +#define mmMME_QM_GLBL_ERR_CFG 0xD800C + +#define mmMME_QM_GLBL_ERR_ADDR_LO 0xD8010 + +#define mmMME_QM_GLBL_ERR_ADDR_HI 0xD8014 + +#define mmMME_QM_GLBL_ERR_WDATA 0xD8018 + +#define mmMME_QM_GLBL_SECURE_PROPS 0xD801C + +#define mmMME_QM_GLBL_NON_SECURE_PROPS 0xD8020 + +#define mmMME_QM_GLBL_STS0 0xD8024 + +#define mmMME_QM_GLBL_STS1 0xD8028 + +#define mmMME_QM_PQ_BASE_LO 0xD8060 + +#define mmMME_QM_PQ_BASE_HI 0xD8064 + +#define mmMME_QM_PQ_SIZE 0xD8068 + +#define mmMME_QM_PQ_PI 0xD806C + +#define mmMME_QM_PQ_CI 0xD8070 + +#define mmMME_QM_PQ_CFG0 0xD8074 + +#define mmMME_QM_PQ_CFG1 0xD8078 + +#define mmMME_QM_PQ_ARUSER 0xD807C + +#define mmMME_QM_PQ_PUSH0 0xD8080 + +#define mmMME_QM_PQ_PUSH1 0xD8084 + +#define mmMME_QM_PQ_PUSH2 0xD8088 + +#define mmMME_QM_PQ_PUSH3 0xD808C + +#define mmMME_QM_PQ_STS0 0xD8090 + +#define mmMME_QM_PQ_STS1 0xD8094 + +#define mmMME_QM_PQ_RD_RATE_LIM_EN 0xD80A0 + +#define mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xD80A4 + +#define mmMME_QM_PQ_RD_RATE_LIM_SAT 0xD80A8 + +#define mmMME_QM_PQ_RD_RATE_LIM_TOUT 0xD80AC + +#define mmMME_QM_CQ_CFG0 0xD80B0 + +#define mmMME_QM_CQ_CFG1 0xD80B4 + +#define mmMME_QM_CQ_ARUSER 0xD80B8 + +#define mmMME_QM_CQ_PTR_LO 0xD80C0 + +#define mmMME_QM_CQ_PTR_HI 0xD80C4 + +#define mmMME_QM_CQ_TSIZE 0xD80C8 + +#define mmMME_QM_CQ_CTL 0xD80CC + +#define mmMME_QM_CQ_PTR_LO_STS 0xD80D4 + +#define mmMME_QM_CQ_PTR_HI_STS 0xD80D8 + +#define mmMME_QM_CQ_TSIZE_STS 0xD80DC + +#define mmMME_QM_CQ_CTL_STS 0xD80E0 + +#define mmMME_QM_CQ_STS0 0xD80E4 + +#define mmMME_QM_CQ_STS1 0xD80E8 + +#define mmMME_QM_CQ_RD_RATE_LIM_EN 0xD80F0 + +#define mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xD80F4 + +#define mmMME_QM_CQ_RD_RATE_LIM_SAT 0xD80F8 + +#define mmMME_QM_CQ_RD_RATE_LIM_TOUT 0xD80FC + +#define mmMME_QM_CQ_IFIFO_CNT 0xD8108 + +#define mmMME_QM_CP_MSG_BASE0_ADDR_LO 0xD8120 + +#define mmMME_QM_CP_MSG_BASE0_ADDR_HI 0xD8124 + +#define mmMME_QM_CP_MSG_BASE1_ADDR_LO 0xD8128 + +#define mmMME_QM_CP_MSG_BASE1_ADDR_HI 0xD812C + +#define mmMME_QM_CP_MSG_BASE2_ADDR_LO 0xD8130 + +#define mmMME_QM_CP_MSG_BASE2_ADDR_HI 0xD8134 + +#define mmMME_QM_CP_MSG_BASE3_ADDR_LO 0xD8138 + +#define mmMME_QM_CP_MSG_BASE3_ADDR_HI 0xD813C + +#define mmMME_QM_CP_LDMA_TSIZE_OFFSET 0xD8140 + +#define mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xD8144 + +#define mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xD8148 + +#define mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xD814C + +#define mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xD8150 + +#define mmMME_QM_CP_LDMA_COMMIT_OFFSET 0xD8154 + +#define mmMME_QM_CP_FENCE0_RDATA 0xD8158 + +#define mmMME_QM_CP_FENCE1_RDATA 0xD815C + +#define mmMME_QM_CP_FENCE2_RDATA 0xD8160 + +#define mmMME_QM_CP_FENCE3_RDATA 0xD8164 + +#define mmMME_QM_CP_FENCE0_CNT 0xD8168 + +#define mmMME_QM_CP_FENCE1_CNT 0xD816C + +#define mmMME_QM_CP_FENCE2_CNT 0xD8170 + +#define mmMME_QM_CP_FENCE3_CNT 0xD8174 + +#define mmMME_QM_CP_STS 0xD8178 + +#define mmMME_QM_CP_CURRENT_INST_LO 0xD817C + +#define mmMME_QM_CP_CURRENT_INST_HI 0xD8180 + +#define mmMME_QM_CP_BARRIER_CFG 0xD8184 + +#define mmMME_QM_CP_DBG_0 0xD8188 + +#define mmMME_QM_PQ_BUF_ADDR 0xD8300 + +#define mmMME_QM_PQ_BUF_RDATA 0xD8304 + +#define mmMME_QM_CQ_BUF_ADDR 0xD8308 + +#define mmMME_QM_CQ_BUF_RDATA 0xD830C + +#endif /* ASIC_REG_MME_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h new file mode 100644 index 000000000000..9436b1e2705a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h @@ -0,0 +1,1153 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_REGS_H_ +#define ASIC_REG_MME_REGS_H_ + +/* + ***************************************** + * MME (Prototype: MME) + ***************************************** + */ + +#define mmMME_ARCH_STATUS 0xD0000 + +#define mmMME_ARCH_A_BASE_ADDR_HIGH 0xD0008 + +#define mmMME_ARCH_B_BASE_ADDR_HIGH 0xD000C + +#define mmMME_ARCH_CIN_BASE_ADDR_HIGH 0xD0010 + +#define mmMME_ARCH_COUT_BASE_ADDR_HIGH 0xD0014 + +#define mmMME_ARCH_BIAS_BASE_ADDR_HIGH 0xD0018 + +#define mmMME_ARCH_A_BASE_ADDR_LOW 0xD001C + +#define mmMME_ARCH_B_BASE_ADDR_LOW 0xD0020 + +#define mmMME_ARCH_CIN_BASE_ADDR_LOW 0xD0024 + +#define mmMME_ARCH_COUT_BASE_ADDR_LOW 0xD0028 + +#define mmMME_ARCH_BIAS_BASE_ADDR_LOW 0xD002C + +#define mmMME_ARCH_HEADER 0xD0030 + +#define mmMME_ARCH_KERNEL_SIZE_MINUS_1 0xD0034 + +#define mmMME_ARCH_ASSOCIATED_DIMS_0 0xD0038 + +#define mmMME_ARCH_ASSOCIATED_DIMS_1 0xD003C + +#define mmMME_ARCH_COUT_SCALE 0xD0040 + +#define mmMME_ARCH_CIN_SCALE 0xD0044 + +#define mmMME_ARCH_GEMMLOWP_ZP 0xD0048 + +#define mmMME_ARCH_GEMMLOWP_EXPONENT 0xD004C + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_0 0xD0050 + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_1 0xD0054 + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_2 0xD0058 + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_3 0xD005C + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_4 0xD0060 + +#define mmMME_ARCH_A_VALID_ELEMENTS_0 0xD0064 + +#define mmMME_ARCH_A_VALID_ELEMENTS_1 0xD0068 + +#define mmMME_ARCH_A_VALID_ELEMENTS_2 0xD006C + +#define mmMME_ARCH_A_VALID_ELEMENTS_3 0xD0070 + +#define mmMME_ARCH_A_VALID_ELEMENTS_4 0xD0074 + +#define mmMME_ARCH_A_LOOP_STRIDE_0 0xD0078 + +#define mmMME_ARCH_A_LOOP_STRIDE_1 0xD007C + +#define mmMME_ARCH_A_LOOP_STRIDE_2 0xD0080 + +#define mmMME_ARCH_A_LOOP_STRIDE_3 0xD0084 + +#define mmMME_ARCH_A_LOOP_STRIDE_4 0xD0088 + +#define mmMME_ARCH_A_ROI_SIZE_0 0xD008C + +#define mmMME_ARCH_A_ROI_SIZE_1 0xD0090 + +#define mmMME_ARCH_A_ROI_SIZE_2 0xD0094 + +#define mmMME_ARCH_A_ROI_SIZE_3 0xD0098 + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_0 0xD009C + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_1 0xD00A0 + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_2 0xD00A4 + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_3 0xD00A8 + +#define mmMME_ARCH_A_SPATIAL_STRIDE_0 0xD00AC + +#define mmMME_ARCH_A_SPATIAL_STRIDE_1 0xD00B0 + +#define mmMME_ARCH_A_SPATIAL_STRIDE_2 0xD00B4 + +#define mmMME_ARCH_A_SPATIAL_STRIDE_3 0xD00B8 + +#define mmMME_ARCH_A_SPATIAL_SIZE_MINUS_1 0xD00BC + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_0 0xD00C0 + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_1 0xD00C4 + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_2 0xD00C8 + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_3 0xD00CC + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_4 0xD00D0 + +#define mmMME_ARCH_B_VALID_ELEMENTS_0 0xD00D4 + +#define mmMME_ARCH_B_VALID_ELEMENTS_1 0xD00D8 + +#define mmMME_ARCH_B_VALID_ELEMENTS_2 0xD00DC + +#define mmMME_ARCH_B_VALID_ELEMENTS_3 0xD00E0 + +#define mmMME_ARCH_B_VALID_ELEMENTS_4 0xD00E4 + +#define mmMME_ARCH_B_LOOP_STRIDE_0 0xD00E8 + +#define mmMME_ARCH_B_LOOP_STRIDE_1 0xD00EC + +#define mmMME_ARCH_B_LOOP_STRIDE_2 0xD00F0 + +#define mmMME_ARCH_B_LOOP_STRIDE_3 0xD00F4 + +#define mmMME_ARCH_B_LOOP_STRIDE_4 0xD00F8 + +#define mmMME_ARCH_B_ROI_SIZE_0 0xD00FC + +#define mmMME_ARCH_B_ROI_SIZE_1 0xD0100 + +#define mmMME_ARCH_B_ROI_SIZE_2 0xD0104 + +#define mmMME_ARCH_B_ROI_SIZE_3 0xD0108 + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_0 0xD010C + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_1 0xD0110 + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_2 0xD0114 + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_3 0xD0118 + +#define mmMME_ARCH_B_SPATIAL_STRIDE_0 0xD011C + +#define mmMME_ARCH_B_SPATIAL_STRIDE_1 0xD0120 + +#define mmMME_ARCH_B_SPATIAL_STRIDE_2 0xD0124 + +#define mmMME_ARCH_B_SPATIAL_STRIDE_3 0xD0128 + +#define mmMME_ARCH_B_SPATIAL_SIZE_MINUS_1 0xD012C + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_0 0xD0130 + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_1 0xD0134 + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_2 0xD0138 + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_3 0xD013C + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_4 0xD0140 + +#define mmMME_ARCH_C_VALID_ELEMENTS_0 0xD0144 + +#define mmMME_ARCH_C_VALID_ELEMENTS_1 0xD0148 + +#define mmMME_ARCH_C_VALID_ELEMENTS_2 0xD014C + +#define mmMME_ARCH_C_VALID_ELEMENTS_3 0xD0150 + +#define mmMME_ARCH_C_VALID_ELEMENTS_4 0xD0154 + +#define mmMME_ARCH_C_LOOP_STRIDE_0 0xD0158 + +#define mmMME_ARCH_C_LOOP_STRIDE_1 0xD015C + +#define mmMME_ARCH_C_LOOP_STRIDE_2 0xD0160 + +#define mmMME_ARCH_C_LOOP_STRIDE_3 0xD0164 + +#define mmMME_ARCH_C_LOOP_STRIDE_4 0xD0168 + +#define mmMME_ARCH_C_ROI_SIZE_0 0xD016C + +#define mmMME_ARCH_C_ROI_SIZE_1 0xD0170 + +#define mmMME_ARCH_C_ROI_SIZE_2 0xD0174 + +#define mmMME_ARCH_C_ROI_SIZE_3 0xD0178 + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_0 0xD017C + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_1 0xD0180 + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_2 0xD0184 + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_3 0xD0188 + +#define mmMME_ARCH_C_SPATIAL_STRIDE_0 0xD018C + +#define mmMME_ARCH_C_SPATIAL_STRIDE_1 0xD0190 + +#define mmMME_ARCH_C_SPATIAL_STRIDE_2 0xD0194 + +#define mmMME_ARCH_C_SPATIAL_STRIDE_3 0xD0198 + +#define mmMME_ARCH_C_SPATIAL_SIZE_MINUS_1 0xD019C + +#define mmMME_ARCH_SYNC_OBJECT_MESSAGE 0xD01A0 + +#define mmMME_ARCH_E_PADDING_VALUE_A 0xD01A4 + +#define mmMME_ARCH_E_NUM_ITERATION_MINUS_1 0xD01A8 + +#define mmMME_ARCH_E_BUBBLES_PER_SPLIT 0xD01AC + +#define mmMME_CMD 0xD0200 + +#define mmMME_DUMMY 0xD0204 + +#define mmMME_RESET 0xD0208 + +#define mmMME_STALL 0xD020C + +#define mmMME_SM_BASE_ADDRESS_LOW 0xD0210 + +#define mmMME_SM_BASE_ADDRESS_HIGH 0xD0214 + +#define mmMME_DBGMEM_ADD 0xD0218 + +#define mmMME_DBGMEM_DATA_WR 0xD021C + +#define mmMME_DBGMEM_DATA_RD 0xD0220 + +#define mmMME_DBGMEM_CTRL 0xD0224 + +#define mmMME_DBGMEM_RC 0xD0228 + +#define mmMME_LOG_SHADOW 0xD022C + +#define mmMME_STORE_MAX_CREDIT 0xD0300 + +#define mmMME_AGU 0xD0304 + +#define mmMME_SBA 0xD0308 + +#define mmMME_SBB 0xD030C + +#define mmMME_SBC 0xD0310 + +#define mmMME_WBC 0xD0314 + +#define mmMME_SBA_CONTROL_DATA 0xD0318 + +#define mmMME_SBB_CONTROL_DATA 0xD031C + +#define mmMME_SBC_CONTROL_DATA 0xD0320 + +#define mmMME_WBC_CONTROL_DATA 0xD0324 + +#define mmMME_TE 0xD0328 + +#define mmMME_TE2DEC 0xD032C + +#define mmMME_REI_STATUS 0xD0330 + +#define mmMME_REI_MASK 0xD0334 + +#define mmMME_SEI_STATUS 0xD0338 + +#define mmMME_SEI_MASK 0xD033C + +#define mmMME_SPI_STATUS 0xD0340 + +#define mmMME_SPI_MASK 0xD0344 + +#define mmMME_SHADOW_0_STATUS 0xD0400 + +#define mmMME_SHADOW_0_A_BASE_ADDR_HIGH 0xD0408 + +#define mmMME_SHADOW_0_B_BASE_ADDR_HIGH 0xD040C + +#define mmMME_SHADOW_0_CIN_BASE_ADDR_HIGH 0xD0410 + +#define mmMME_SHADOW_0_COUT_BASE_ADDR_HIGH 0xD0414 + +#define mmMME_SHADOW_0_BIAS_BASE_ADDR_HIGH 0xD0418 + +#define mmMME_SHADOW_0_A_BASE_ADDR_LOW 0xD041C + +#define mmMME_SHADOW_0_B_BASE_ADDR_LOW 0xD0420 + +#define mmMME_SHADOW_0_CIN_BASE_ADDR_LOW 0xD0424 + +#define mmMME_SHADOW_0_COUT_BASE_ADDR_LOW 0xD0428 + +#define mmMME_SHADOW_0_BIAS_BASE_ADDR_LOW 0xD042C + +#define mmMME_SHADOW_0_HEADER 0xD0430 + +#define mmMME_SHADOW_0_KERNEL_SIZE_MINUS_1 0xD0434 + +#define mmMME_SHADOW_0_ASSOCIATED_DIMS_0 0xD0438 + +#define mmMME_SHADOW_0_ASSOCIATED_DIMS_1 0xD043C + +#define mmMME_SHADOW_0_COUT_SCALE 0xD0440 + +#define mmMME_SHADOW_0_CIN_SCALE 0xD0444 + +#define mmMME_SHADOW_0_GEMMLOWP_ZP 0xD0448 + +#define mmMME_SHADOW_0_GEMMLOWP_EXPONENT 0xD044C + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_0 0xD0450 + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_1 0xD0454 + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_2 0xD0458 + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_3 0xD045C + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_4 0xD0460 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_0 0xD0464 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_1 0xD0468 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_2 0xD046C + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_3 0xD0470 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_4 0xD0474 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_0 0xD0478 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_1 0xD047C + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_2 0xD0480 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_3 0xD0484 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_4 0xD0488 + +#define mmMME_SHADOW_0_A_ROI_SIZE_0 0xD048C + +#define mmMME_SHADOW_0_A_ROI_SIZE_1 0xD0490 + +#define mmMME_SHADOW_0_A_ROI_SIZE_2 0xD0494 + +#define mmMME_SHADOW_0_A_ROI_SIZE_3 0xD0498 + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_0 0xD049C + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_1 0xD04A0 + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_2 0xD04A4 + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_3 0xD04A8 + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_0 0xD04AC + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_1 0xD04B0 + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_2 0xD04B4 + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_3 0xD04B8 + +#define mmMME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1 0xD04BC + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_0 0xD04C0 + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_1 0xD04C4 + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_2 0xD04C8 + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_3 0xD04CC + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_4 0xD04D0 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_0 0xD04D4 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_1 0xD04D8 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_2 0xD04DC + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_3 0xD04E0 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_4 0xD04E4 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_0 0xD04E8 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_1 0xD04EC + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_2 0xD04F0 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_3 0xD04F4 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_4 0xD04F8 + +#define mmMME_SHADOW_0_B_ROI_SIZE_0 0xD04FC + +#define mmMME_SHADOW_0_B_ROI_SIZE_1 0xD0500 + +#define mmMME_SHADOW_0_B_ROI_SIZE_2 0xD0504 + +#define mmMME_SHADOW_0_B_ROI_SIZE_3 0xD0508 + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_0 0xD050C + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_1 0xD0510 + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_2 0xD0514 + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_3 0xD0518 + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_0 0xD051C + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_1 0xD0520 + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_2 0xD0524 + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_3 0xD0528 + +#define mmMME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1 0xD052C + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_0 0xD0530 + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_1 0xD0534 + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_2 0xD0538 + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_3 0xD053C + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_4 0xD0540 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_0 0xD0544 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_1 0xD0548 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_2 0xD054C + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_3 0xD0550 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_4 0xD0554 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_0 0xD0558 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_1 0xD055C + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_2 0xD0560 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_3 0xD0564 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_4 0xD0568 + +#define mmMME_SHADOW_0_C_ROI_SIZE_0 0xD056C + +#define mmMME_SHADOW_0_C_ROI_SIZE_1 0xD0570 + +#define mmMME_SHADOW_0_C_ROI_SIZE_2 0xD0574 + +#define mmMME_SHADOW_0_C_ROI_SIZE_3 0xD0578 + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_0 0xD057C + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_1 0xD0580 + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_2 0xD0584 + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_3 0xD0588 + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_0 0xD058C + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_1 0xD0590 + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_2 0xD0594 + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_3 0xD0598 + +#define mmMME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1 0xD059C + +#define mmMME_SHADOW_0_SYNC_OBJECT_MESSAGE 0xD05A0 + +#define mmMME_SHADOW_0_E_PADDING_VALUE_A 0xD05A4 + +#define mmMME_SHADOW_0_E_NUM_ITERATION_MINUS_1 0xD05A8 + +#define mmMME_SHADOW_0_E_BUBBLES_PER_SPLIT 0xD05AC + +#define mmMME_SHADOW_1_STATUS 0xD0600 + +#define mmMME_SHADOW_1_A_BASE_ADDR_HIGH 0xD0608 + +#define mmMME_SHADOW_1_B_BASE_ADDR_HIGH 0xD060C + +#define mmMME_SHADOW_1_CIN_BASE_ADDR_HIGH 0xD0610 + +#define mmMME_SHADOW_1_COUT_BASE_ADDR_HIGH 0xD0614 + +#define mmMME_SHADOW_1_BIAS_BASE_ADDR_HIGH 0xD0618 + +#define mmMME_SHADOW_1_A_BASE_ADDR_LOW 0xD061C + +#define mmMME_SHADOW_1_B_BASE_ADDR_LOW 0xD0620 + +#define mmMME_SHADOW_1_CIN_BASE_ADDR_LOW 0xD0624 + +#define mmMME_SHADOW_1_COUT_BASE_ADDR_LOW 0xD0628 + +#define mmMME_SHADOW_1_BIAS_BASE_ADDR_LOW 0xD062C + +#define mmMME_SHADOW_1_HEADER 0xD0630 + +#define mmMME_SHADOW_1_KERNEL_SIZE_MINUS_1 0xD0634 + +#define mmMME_SHADOW_1_ASSOCIATED_DIMS_0 0xD0638 + +#define mmMME_SHADOW_1_ASSOCIATED_DIMS_1 0xD063C + +#define mmMME_SHADOW_1_COUT_SCALE 0xD0640 + +#define mmMME_SHADOW_1_CIN_SCALE 0xD0644 + +#define mmMME_SHADOW_1_GEMMLOWP_ZP 0xD0648 + +#define mmMME_SHADOW_1_GEMMLOWP_EXPONENT 0xD064C + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_0 0xD0650 + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_1 0xD0654 + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_2 0xD0658 + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_3 0xD065C + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_4 0xD0660 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_0 0xD0664 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_1 0xD0668 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_2 0xD066C + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_3 0xD0670 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_4 0xD0674 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_0 0xD0678 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_1 0xD067C + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_2 0xD0680 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_3 0xD0684 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_4 0xD0688 + +#define mmMME_SHADOW_1_A_ROI_SIZE_0 0xD068C + +#define mmMME_SHADOW_1_A_ROI_SIZE_1 0xD0690 + +#define mmMME_SHADOW_1_A_ROI_SIZE_2 0xD0694 + +#define mmMME_SHADOW_1_A_ROI_SIZE_3 0xD0698 + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_0 0xD069C + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_1 0xD06A0 + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_2 0xD06A4 + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_3 0xD06A8 + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_0 0xD06AC + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_1 0xD06B0 + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_2 0xD06B4 + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_3 0xD06B8 + +#define mmMME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1 0xD06BC + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_0 0xD06C0 + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_1 0xD06C4 + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_2 0xD06C8 + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_3 0xD06CC + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_4 0xD06D0 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_0 0xD06D4 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_1 0xD06D8 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_2 0xD06DC + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_3 0xD06E0 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_4 0xD06E4 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_0 0xD06E8 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_1 0xD06EC + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_2 0xD06F0 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_3 0xD06F4 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_4 0xD06F8 + +#define mmMME_SHADOW_1_B_ROI_SIZE_0 0xD06FC + +#define mmMME_SHADOW_1_B_ROI_SIZE_1 0xD0700 + +#define mmMME_SHADOW_1_B_ROI_SIZE_2 0xD0704 + +#define mmMME_SHADOW_1_B_ROI_SIZE_3 0xD0708 + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_0 0xD070C + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_1 0xD0710 + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_2 0xD0714 + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_3 0xD0718 + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_0 0xD071C + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_1 0xD0720 + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_2 0xD0724 + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_3 0xD0728 + +#define mmMME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1 0xD072C + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_0 0xD0730 + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_1 0xD0734 + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_2 0xD0738 + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_3 0xD073C + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_4 0xD0740 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_0 0xD0744 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_1 0xD0748 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_2 0xD074C + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_3 0xD0750 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_4 0xD0754 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_0 0xD0758 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_1 0xD075C + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_2 0xD0760 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_3 0xD0764 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_4 0xD0768 + +#define mmMME_SHADOW_1_C_ROI_SIZE_0 0xD076C + +#define mmMME_SHADOW_1_C_ROI_SIZE_1 0xD0770 + +#define mmMME_SHADOW_1_C_ROI_SIZE_2 0xD0774 + +#define mmMME_SHADOW_1_C_ROI_SIZE_3 0xD0778 + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_0 0xD077C + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_1 0xD0780 + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_2 0xD0784 + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_3 0xD0788 + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_0 0xD078C + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_1 0xD0790 + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_2 0xD0794 + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_3 0xD0798 + +#define mmMME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1 0xD079C + +#define mmMME_SHADOW_1_SYNC_OBJECT_MESSAGE 0xD07A0 + +#define mmMME_SHADOW_1_E_PADDING_VALUE_A 0xD07A4 + +#define mmMME_SHADOW_1_E_NUM_ITERATION_MINUS_1 0xD07A8 + +#define mmMME_SHADOW_1_E_BUBBLES_PER_SPLIT 0xD07AC + +#define mmMME_SHADOW_2_STATUS 0xD0800 + +#define mmMME_SHADOW_2_A_BASE_ADDR_HIGH 0xD0808 + +#define mmMME_SHADOW_2_B_BASE_ADDR_HIGH 0xD080C + +#define mmMME_SHADOW_2_CIN_BASE_ADDR_HIGH 0xD0810 + +#define mmMME_SHADOW_2_COUT_BASE_ADDR_HIGH 0xD0814 + +#define mmMME_SHADOW_2_BIAS_BASE_ADDR_HIGH 0xD0818 + +#define mmMME_SHADOW_2_A_BASE_ADDR_LOW 0xD081C + +#define mmMME_SHADOW_2_B_BASE_ADDR_LOW 0xD0820 + +#define mmMME_SHADOW_2_CIN_BASE_ADDR_LOW 0xD0824 + +#define mmMME_SHADOW_2_COUT_BASE_ADDR_LOW 0xD0828 + +#define mmMME_SHADOW_2_BIAS_BASE_ADDR_LOW 0xD082C + +#define mmMME_SHADOW_2_HEADER 0xD0830 + +#define mmMME_SHADOW_2_KERNEL_SIZE_MINUS_1 0xD0834 + +#define mmMME_SHADOW_2_ASSOCIATED_DIMS_0 0xD0838 + +#define mmMME_SHADOW_2_ASSOCIATED_DIMS_1 0xD083C + +#define mmMME_SHADOW_2_COUT_SCALE 0xD0840 + +#define mmMME_SHADOW_2_CIN_SCALE 0xD0844 + +#define mmMME_SHADOW_2_GEMMLOWP_ZP 0xD0848 + +#define mmMME_SHADOW_2_GEMMLOWP_EXPONENT 0xD084C + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_0 0xD0850 + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_1 0xD0854 + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_2 0xD0858 + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_3 0xD085C + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_4 0xD0860 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_0 0xD0864 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_1 0xD0868 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_2 0xD086C + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_3 0xD0870 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_4 0xD0874 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_0 0xD0878 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_1 0xD087C + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_2 0xD0880 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_3 0xD0884 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_4 0xD0888 + +#define mmMME_SHADOW_2_A_ROI_SIZE_0 0xD088C + +#define mmMME_SHADOW_2_A_ROI_SIZE_1 0xD0890 + +#define mmMME_SHADOW_2_A_ROI_SIZE_2 0xD0894 + +#define mmMME_SHADOW_2_A_ROI_SIZE_3 0xD0898 + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_0 0xD089C + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_1 0xD08A0 + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_2 0xD08A4 + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_3 0xD08A8 + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_0 0xD08AC + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_1 0xD08B0 + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_2 0xD08B4 + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_3 0xD08B8 + +#define mmMME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1 0xD08BC + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_0 0xD08C0 + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_1 0xD08C4 + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_2 0xD08C8 + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_3 0xD08CC + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_4 0xD08D0 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_0 0xD08D4 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_1 0xD08D8 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_2 0xD08DC + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_3 0xD08E0 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_4 0xD08E4 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_0 0xD08E8 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_1 0xD08EC + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_2 0xD08F0 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_3 0xD08F4 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_4 0xD08F8 + +#define mmMME_SHADOW_2_B_ROI_SIZE_0 0xD08FC + +#define mmMME_SHADOW_2_B_ROI_SIZE_1 0xD0900 + +#define mmMME_SHADOW_2_B_ROI_SIZE_2 0xD0904 + +#define mmMME_SHADOW_2_B_ROI_SIZE_3 0xD0908 + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_0 0xD090C + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_1 0xD0910 + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_2 0xD0914 + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_3 0xD0918 + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_0 0xD091C + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_1 0xD0920 + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_2 0xD0924 + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_3 0xD0928 + +#define mmMME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1 0xD092C + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_0 0xD0930 + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_1 0xD0934 + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_2 0xD0938 + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_3 0xD093C + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_4 0xD0940 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_0 0xD0944 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_1 0xD0948 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_2 0xD094C + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_3 0xD0950 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_4 0xD0954 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_0 0xD0958 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_1 0xD095C + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_2 0xD0960 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_3 0xD0964 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_4 0xD0968 + +#define mmMME_SHADOW_2_C_ROI_SIZE_0 0xD096C + +#define mmMME_SHADOW_2_C_ROI_SIZE_1 0xD0970 + +#define mmMME_SHADOW_2_C_ROI_SIZE_2 0xD0974 + +#define mmMME_SHADOW_2_C_ROI_SIZE_3 0xD0978 + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_0 0xD097C + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_1 0xD0980 + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_2 0xD0984 + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_3 0xD0988 + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_0 0xD098C + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_1 0xD0990 + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_2 0xD0994 + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_3 0xD0998 + +#define mmMME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1 0xD099C + +#define mmMME_SHADOW_2_SYNC_OBJECT_MESSAGE 0xD09A0 + +#define mmMME_SHADOW_2_E_PADDING_VALUE_A 0xD09A4 + +#define mmMME_SHADOW_2_E_NUM_ITERATION_MINUS_1 0xD09A8 + +#define mmMME_SHADOW_2_E_BUBBLES_PER_SPLIT 0xD09AC + +#define mmMME_SHADOW_3_STATUS 0xD0A00 + +#define mmMME_SHADOW_3_A_BASE_ADDR_HIGH 0xD0A08 + +#define mmMME_SHADOW_3_B_BASE_ADDR_HIGH 0xD0A0C + +#define mmMME_SHADOW_3_CIN_BASE_ADDR_HIGH 0xD0A10 + +#define mmMME_SHADOW_3_COUT_BASE_ADDR_HIGH 0xD0A14 + +#define mmMME_SHADOW_3_BIAS_BASE_ADDR_HIGH 0xD0A18 + +#define mmMME_SHADOW_3_A_BASE_ADDR_LOW 0xD0A1C + +#define mmMME_SHADOW_3_B_BASE_ADDR_LOW 0xD0A20 + +#define mmMME_SHADOW_3_CIN_BASE_ADDR_LOW 0xD0A24 + +#define mmMME_SHADOW_3_COUT_BASE_ADDR_LOW 0xD0A28 + +#define mmMME_SHADOW_3_BIAS_BASE_ADDR_LOW 0xD0A2C + +#define mmMME_SHADOW_3_HEADER 0xD0A30 + +#define mmMME_SHADOW_3_KERNEL_SIZE_MINUS_1 0xD0A34 + +#define mmMME_SHADOW_3_ASSOCIATED_DIMS_0 0xD0A38 + +#define mmMME_SHADOW_3_ASSOCIATED_DIMS_1 0xD0A3C + +#define mmMME_SHADOW_3_COUT_SCALE 0xD0A40 + +#define mmMME_SHADOW_3_CIN_SCALE 0xD0A44 + +#define mmMME_SHADOW_3_GEMMLOWP_ZP 0xD0A48 + +#define mmMME_SHADOW_3_GEMMLOWP_EXPONENT 0xD0A4C + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_0 0xD0A50 + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_1 0xD0A54 + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_2 0xD0A58 + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_3 0xD0A5C + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_4 0xD0A60 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_0 0xD0A64 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_1 0xD0A68 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_2 0xD0A6C + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_3 0xD0A70 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_4 0xD0A74 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_0 0xD0A78 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_1 0xD0A7C + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_2 0xD0A80 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_3 0xD0A84 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_4 0xD0A88 + +#define mmMME_SHADOW_3_A_ROI_SIZE_0 0xD0A8C + +#define mmMME_SHADOW_3_A_ROI_SIZE_1 0xD0A90 + +#define mmMME_SHADOW_3_A_ROI_SIZE_2 0xD0A94 + +#define mmMME_SHADOW_3_A_ROI_SIZE_3 0xD0A98 + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_0 0xD0A9C + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_1 0xD0AA0 + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_2 0xD0AA4 + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_3 0xD0AA8 + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_0 0xD0AAC + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_1 0xD0AB0 + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_2 0xD0AB4 + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_3 0xD0AB8 + +#define mmMME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1 0xD0ABC + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_0 0xD0AC0 + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_1 0xD0AC4 + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_2 0xD0AC8 + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_3 0xD0ACC + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_4 0xD0AD0 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_0 0xD0AD4 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_1 0xD0AD8 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_2 0xD0ADC + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_3 0xD0AE0 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_4 0xD0AE4 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_0 0xD0AE8 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_1 0xD0AEC + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_2 0xD0AF0 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_3 0xD0AF4 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_4 0xD0AF8 + +#define mmMME_SHADOW_3_B_ROI_SIZE_0 0xD0AFC + +#define mmMME_SHADOW_3_B_ROI_SIZE_1 0xD0B00 + +#define mmMME_SHADOW_3_B_ROI_SIZE_2 0xD0B04 + +#define mmMME_SHADOW_3_B_ROI_SIZE_3 0xD0B08 + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_0 0xD0B0C + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_1 0xD0B10 + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_2 0xD0B14 + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_3 0xD0B18 + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_0 0xD0B1C + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_1 0xD0B20 + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_2 0xD0B24 + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_3 0xD0B28 + +#define mmMME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1 0xD0B2C + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_0 0xD0B30 + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_1 0xD0B34 + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_2 0xD0B38 + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_3 0xD0B3C + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_4 0xD0B40 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_0 0xD0B44 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_1 0xD0B48 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_2 0xD0B4C + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_3 0xD0B50 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_4 0xD0B54 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_0 0xD0B58 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_1 0xD0B5C + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_2 0xD0B60 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_3 0xD0B64 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_4 0xD0B68 + +#define mmMME_SHADOW_3_C_ROI_SIZE_0 0xD0B6C + +#define mmMME_SHADOW_3_C_ROI_SIZE_1 0xD0B70 + +#define mmMME_SHADOW_3_C_ROI_SIZE_2 0xD0B74 + +#define mmMME_SHADOW_3_C_ROI_SIZE_3 0xD0B78 + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_0 0xD0B7C + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_1 0xD0B80 + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_2 0xD0B84 + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_3 0xD0B88 + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_0 0xD0B8C + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_1 0xD0B90 + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_2 0xD0B94 + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_3 0xD0B98 + +#define mmMME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1 0xD0B9C + +#define mmMME_SHADOW_3_SYNC_OBJECT_MESSAGE 0xD0BA0 + +#define mmMME_SHADOW_3_E_PADDING_VALUE_A 0xD0BA4 + +#define mmMME_SHADOW_3_E_NUM_ITERATION_MINUS_1 0xD0BA8 + +#define mmMME_SHADOW_3_E_BUBBLES_PER_SPLIT 0xD0BAC + +#endif /* ASIC_REG_MME_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h new file mode 100644 index 000000000000..3a78078d3c4c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MMU_MASKS_H_ +#define ASIC_REG_MMU_MASKS_H_ + +/* + ***************************************** + * MMU (Prototype: MMU) + ***************************************** + */ + +/* MMU_INPUT_FIFO_THRESHOLD */ +#define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0 +#define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7 +#define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT 4 +#define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70 +#define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT 8 +#define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700 +#define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT 12 +#define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000 +#define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT 16 +#define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000 +#define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT 20 +#define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000 +#define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT 24 +#define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000 + +/* MMU_MMU_ENABLE */ +#define MMU_MMU_ENABLE_R_SHIFT 0 +#define MMU_MMU_ENABLE_R_MASK 0x1 + +/* MMU_FORCE_ORDERING */ +#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT 0 +#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK 0x1 +#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT 1 +#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK 0x2 +#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT 2 +#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK 0x4 +#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT 3 +#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK 0x8 +#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT 4 +#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK 0x10 +#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT 5 +#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK 0x20 +#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT 6 +#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK 0x40 +#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT 8 +#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK 0x100 +#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT 9 +#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK 0x200 +#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT 10 +#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK 0x400 +#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT 11 +#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK 0x800 +#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT 12 +#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK 0x1000 +#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT 13 +#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK 0x2000 +#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT 14 +#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK 0x4000 + +/* MMU_FEATURE_ENABLE */ +#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 +#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 +#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 +#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 +#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 +#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 +#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 +#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 +#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 +#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 +#define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 +#define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 + +/* MMU_VA_ORDERING_MASK_31_7 */ +#define MMU_VA_ORDERING_MASK_31_7_R_SHIFT 0 +#define MMU_VA_ORDERING_MASK_31_7_R_MASK 0x1FFFFFF + +/* MMU_VA_ORDERING_MASK_49_32 */ +#define MMU_VA_ORDERING_MASK_49_32_R_SHIFT 0 +#define MMU_VA_ORDERING_MASK_49_32_R_MASK 0x3FFFF + +/* MMU_LOG2_DDR_SIZE */ +#define MMU_LOG2_DDR_SIZE_R_SHIFT 0 +#define MMU_LOG2_DDR_SIZE_R_MASK 0xFF + +/* MMU_SCRAMBLER */ +#define MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 +#define MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F +#define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 +#define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 +#define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 +#define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 + +/* MMU_MEM_INIT_BUSY */ +#define MMU_MEM_INIT_BUSY_DATA_SHIFT 0 +#define MMU_MEM_INIT_BUSY_DATA_MASK 0x3 +#define MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 +#define MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 +#define MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 +#define MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 + +/* MMU_SPI_MASK */ +#define MMU_SPI_MASK_R_SHIFT 0 +#define MMU_SPI_MASK_R_MASK 0xFF + +/* MMU_SPI_CAUSE */ +#define MMU_SPI_CAUSE_R_SHIFT 0 +#define MMU_SPI_CAUSE_R_MASK 0xFF + +/* MMU_PAGE_ERROR_CAPTURE */ +#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT 0 +#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18 +#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +/* MMU_PAGE_ERROR_CAPTURE_VA */ +#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +/* MMU_ACCESS_ERROR_CAPTURE */ +#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT 0 +#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18 +#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +/* MMU_ACCESS_ERROR_CAPTURE_VA */ +#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_MMU_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h new file mode 100644 index 000000000000..bec6c014135c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MMU_REGS_H_ +#define ASIC_REG_MMU_REGS_H_ + +/* + ***************************************** + * MMU (Prototype: MMU) + ***************************************** + */ + +#define mmMMU_INPUT_FIFO_THRESHOLD 0x480000 + +#define mmMMU_MMU_ENABLE 0x48000C + +#define mmMMU_FORCE_ORDERING 0x480010 + +#define mmMMU_FEATURE_ENABLE 0x480014 + +#define mmMMU_VA_ORDERING_MASK_31_7 0x480018 + +#define mmMMU_VA_ORDERING_MASK_49_32 0x48001C + +#define mmMMU_LOG2_DDR_SIZE 0x480020 + +#define mmMMU_SCRAMBLER 0x480024 + +#define mmMMU_MEM_INIT_BUSY 0x480028 + +#define mmMMU_SPI_MASK 0x48002C + +#define mmMMU_SPI_CAUSE 0x480030 + +#define mmMMU_PAGE_ERROR_CAPTURE 0x480034 + +#define mmMMU_PAGE_ERROR_CAPTURE_VA 0x480038 + +#define mmMMU_ACCESS_ERROR_CAPTURE 0x48003C + +#define mmMMU_ACCESS_ERROR_CAPTURE_VA 0x480040 + +#endif /* ASIC_REG_MMU_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h new file mode 100644 index 000000000000..209e41402a11 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCI_NRTR_MASKS_H_ +#define ASIC_REG_PCI_NRTR_MASKS_H_ + +/* + ***************************************** + * PCI_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +/* PCI_NRTR_HBW_MAX_CRED */ +#define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 +#define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F +#define PCI_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8 +#define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define PCI_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16 +#define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define PCI_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24 +#define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* PCI_NRTR_LBW_MAX_CRED */ +#define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 +#define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F +#define PCI_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8 +#define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define PCI_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16 +#define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define PCI_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24 +#define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* PCI_NRTR_DBG_E_ARB */ +#define PCI_NRTR_DBG_E_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_E_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_E_ARB_S_SHIFT 8 +#define PCI_NRTR_DBG_E_ARB_S_MASK 0x700 +#define PCI_NRTR_DBG_E_ARB_N_SHIFT 16 +#define PCI_NRTR_DBG_E_ARB_N_MASK 0x70000 +#define PCI_NRTR_DBG_E_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_E_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_W_ARB */ +#define PCI_NRTR_DBG_W_ARB_E_SHIFT 0 +#define PCI_NRTR_DBG_W_ARB_E_MASK 0x7 +#define PCI_NRTR_DBG_W_ARB_S_SHIFT 8 +#define PCI_NRTR_DBG_W_ARB_S_MASK 0x700 +#define PCI_NRTR_DBG_W_ARB_N_SHIFT 16 +#define PCI_NRTR_DBG_W_ARB_N_MASK 0x70000 +#define PCI_NRTR_DBG_W_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_W_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_N_ARB */ +#define PCI_NRTR_DBG_N_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_N_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_N_ARB_E_SHIFT 8 +#define PCI_NRTR_DBG_N_ARB_E_MASK 0x700 +#define PCI_NRTR_DBG_N_ARB_S_SHIFT 16 +#define PCI_NRTR_DBG_N_ARB_S_MASK 0x70000 +#define PCI_NRTR_DBG_N_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_N_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_S_ARB */ +#define PCI_NRTR_DBG_S_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_S_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_S_ARB_E_SHIFT 8 +#define PCI_NRTR_DBG_S_ARB_E_MASK 0x700 +#define PCI_NRTR_DBG_S_ARB_N_SHIFT 16 +#define PCI_NRTR_DBG_S_ARB_N_MASK 0x70000 +#define PCI_NRTR_DBG_S_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_S_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_L_ARB */ +#define PCI_NRTR_DBG_L_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_L_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_L_ARB_E_SHIFT 8 +#define PCI_NRTR_DBG_L_ARB_E_MASK 0x700 +#define PCI_NRTR_DBG_L_ARB_S_SHIFT 16 +#define PCI_NRTR_DBG_L_ARB_S_MASK 0x70000 +#define PCI_NRTR_DBG_L_ARB_N_SHIFT 24 +#define PCI_NRTR_DBG_L_ARB_N_MASK 0x7000000 + +/* PCI_NRTR_DBG_E_ARB_MAX */ +#define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_W_ARB_MAX */ +#define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_N_ARB_MAX */ +#define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_S_ARB_MAX */ +#define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_L_ARB_MAX */ +#define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_SPLIT_COEF */ +#define PCI_NRTR_SPLIT_COEF_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_CFG */ +#define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4 +#define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10 +#define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5 +#define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20 +#define PCI_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define PCI_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* PCI_NRTR_SPLIT_RD_SAT */ +#define PCI_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_RD_RST_TOKEN */ +#define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_RD_TIMEOUT */ +#define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_SPLIT_WR_SAT */ +#define PCI_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* PCI_NRTR_WPLIT_WR_TST_TOLEN */ +#define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_WR_TIMEOUT */ +#define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_HBW_RANGE_HIT */ +#define PCI_NRTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* PCI_NRTR_HBW_RANGE_MASK_L */ +#define PCI_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_HBW_RANGE_MASK_H */ +#define PCI_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* PCI_NRTR_HBW_RANGE_BASE_L */ +#define PCI_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_HBW_RANGE_BASE_H */ +#define PCI_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* PCI_NRTR_LBW_RANGE_HIT */ +#define PCI_NRTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define PCI_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* PCI_NRTR_LBW_RANGE_MASK */ +#define PCI_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define PCI_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* PCI_NRTR_LBW_RANGE_BASE */ +#define PCI_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define PCI_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* PCI_NRTR_RGLTR */ +#define PCI_NRTR_RGLTR_WR_EN_SHIFT 0 +#define PCI_NRTR_RGLTR_WR_EN_MASK 0x1 +#define PCI_NRTR_RGLTR_RD_EN_SHIFT 4 +#define PCI_NRTR_RGLTR_RD_EN_MASK 0x10 + +/* PCI_NRTR_RGLTR_WR_RESULT */ +#define PCI_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define PCI_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* PCI_NRTR_RGLTR_RD_RESULT */ +#define PCI_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define PCI_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* PCI_NRTR_SCRAMB_EN */ +#define PCI_NRTR_SCRAMB_EN_VAL_SHIFT 0 +#define PCI_NRTR_SCRAMB_EN_VAL_MASK 0x1 + +/* PCI_NRTR_NON_LIN_SCRAMB */ +#define PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define PCI_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_PCI_NRTR_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h new file mode 100644 index 000000000000..447e5d4e7dc8 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCI_NRTR_REGS_H_ +#define ASIC_REG_PCI_NRTR_REGS_H_ + +/* + ***************************************** + * PCI_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmPCI_NRTR_HBW_MAX_CRED 0x100 + +#define mmPCI_NRTR_LBW_MAX_CRED 0x120 + +#define mmPCI_NRTR_DBG_E_ARB 0x300 + +#define mmPCI_NRTR_DBG_W_ARB 0x304 + +#define mmPCI_NRTR_DBG_N_ARB 0x308 + +#define mmPCI_NRTR_DBG_S_ARB 0x30C + +#define mmPCI_NRTR_DBG_L_ARB 0x310 + +#define mmPCI_NRTR_DBG_E_ARB_MAX 0x320 + +#define mmPCI_NRTR_DBG_W_ARB_MAX 0x324 + +#define mmPCI_NRTR_DBG_N_ARB_MAX 0x328 + +#define mmPCI_NRTR_DBG_S_ARB_MAX 0x32C + +#define mmPCI_NRTR_DBG_L_ARB_MAX 0x330 + +#define mmPCI_NRTR_SPLIT_COEF_0 0x400 + +#define mmPCI_NRTR_SPLIT_COEF_1 0x404 + +#define mmPCI_NRTR_SPLIT_COEF_2 0x408 + +#define mmPCI_NRTR_SPLIT_COEF_3 0x40C + +#define mmPCI_NRTR_SPLIT_COEF_4 0x410 + +#define mmPCI_NRTR_SPLIT_COEF_5 0x414 + +#define mmPCI_NRTR_SPLIT_COEF_6 0x418 + +#define mmPCI_NRTR_SPLIT_COEF_7 0x41C + +#define mmPCI_NRTR_SPLIT_COEF_8 0x420 + +#define mmPCI_NRTR_SPLIT_COEF_9 0x424 + +#define mmPCI_NRTR_SPLIT_CFG 0x440 + +#define mmPCI_NRTR_SPLIT_RD_SAT 0x444 + +#define mmPCI_NRTR_SPLIT_RD_RST_TOKEN 0x448 + +#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_0 0x44C + +#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_1 0x450 + +#define mmPCI_NRTR_SPLIT_WR_SAT 0x454 + +#define mmPCI_NRTR_WPLIT_WR_TST_TOLEN 0x458 + +#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_0 0x45C + +#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_1 0x460 + +#define mmPCI_NRTR_HBW_RANGE_HIT 0x470 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_0 0x480 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_1 0x484 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_2 0x488 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_3 0x48C + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_4 0x490 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_5 0x494 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_6 0x498 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_7 0x49C + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_0 0x4A0 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_1 0x4A4 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_2 0x4A8 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_3 0x4AC + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_4 0x4B0 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_5 0x4B4 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_6 0x4B8 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_7 0x4BC + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_0 0x4C0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_1 0x4C4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_2 0x4C8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_3 0x4CC + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_4 0x4D0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_5 0x4D4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_6 0x4D8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_7 0x4DC + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_0 0x4E0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_1 0x4E4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_2 0x4E8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_3 0x4EC + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_4 0x4F0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_5 0x4F4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_6 0x4F8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_7 0x4FC + +#define mmPCI_NRTR_LBW_RANGE_HIT 0x500 + +#define mmPCI_NRTR_LBW_RANGE_MASK_0 0x510 + +#define mmPCI_NRTR_LBW_RANGE_MASK_1 0x514 + +#define mmPCI_NRTR_LBW_RANGE_MASK_2 0x518 + +#define mmPCI_NRTR_LBW_RANGE_MASK_3 0x51C + +#define mmPCI_NRTR_LBW_RANGE_MASK_4 0x520 + +#define mmPCI_NRTR_LBW_RANGE_MASK_5 0x524 + +#define mmPCI_NRTR_LBW_RANGE_MASK_6 0x528 + +#define mmPCI_NRTR_LBW_RANGE_MASK_7 0x52C + +#define mmPCI_NRTR_LBW_RANGE_MASK_8 0x530 + +#define mmPCI_NRTR_LBW_RANGE_MASK_9 0x534 + +#define mmPCI_NRTR_LBW_RANGE_MASK_10 0x538 + +#define mmPCI_NRTR_LBW_RANGE_MASK_11 0x53C + +#define mmPCI_NRTR_LBW_RANGE_MASK_12 0x540 + +#define mmPCI_NRTR_LBW_RANGE_MASK_13 0x544 + +#define mmPCI_NRTR_LBW_RANGE_MASK_14 0x548 + +#define mmPCI_NRTR_LBW_RANGE_MASK_15 0x54C + +#define mmPCI_NRTR_LBW_RANGE_BASE_0 0x550 + +#define mmPCI_NRTR_LBW_RANGE_BASE_1 0x554 + +#define mmPCI_NRTR_LBW_RANGE_BASE_2 0x558 + +#define mmPCI_NRTR_LBW_RANGE_BASE_3 0x55C + +#define mmPCI_NRTR_LBW_RANGE_BASE_4 0x560 + +#define mmPCI_NRTR_LBW_RANGE_BASE_5 0x564 + +#define mmPCI_NRTR_LBW_RANGE_BASE_6 0x568 + +#define mmPCI_NRTR_LBW_RANGE_BASE_7 0x56C + +#define mmPCI_NRTR_LBW_RANGE_BASE_8 0x570 + +#define mmPCI_NRTR_LBW_RANGE_BASE_9 0x574 + +#define mmPCI_NRTR_LBW_RANGE_BASE_10 0x578 + +#define mmPCI_NRTR_LBW_RANGE_BASE_11 0x57C + +#define mmPCI_NRTR_LBW_RANGE_BASE_12 0x580 + +#define mmPCI_NRTR_LBW_RANGE_BASE_13 0x584 + +#define mmPCI_NRTR_LBW_RANGE_BASE_14 0x588 + +#define mmPCI_NRTR_LBW_RANGE_BASE_15 0x58C + +#define mmPCI_NRTR_RGLTR 0x590 + +#define mmPCI_NRTR_RGLTR_WR_RESULT 0x594 + +#define mmPCI_NRTR_RGLTR_RD_RESULT 0x598 + +#define mmPCI_NRTR_SCRAMB_EN 0x600 + +#define mmPCI_NRTR_NON_LIN_SCRAMB 0x604 + +#endif /* ASIC_REG_PCI_NRTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h new file mode 100644 index 000000000000..daaf5d9079dc --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_AUX_REGS_H_ +#define ASIC_REG_PCIE_AUX_REGS_H_ + +/* + ***************************************** + * PCIE_AUX (Prototype: PCIE_AUX) + ***************************************** + */ + +#define mmPCIE_AUX_APB_TIMEOUT 0xC07004 + +#define mmPCIE_AUX_PHY_INIT 0xC07100 + +#define mmPCIE_AUX_LTR_MAX_LATENCY 0xC07138 + +#define mmPCIE_AUX_BAR0_START_L 0xC07160 + +#define mmPCIE_AUX_BAR0_START_H 0xC07164 + +#define mmPCIE_AUX_BAR1_START 0xC07168 + +#define mmPCIE_AUX_BAR2_START_L 0xC0716C + +#define mmPCIE_AUX_BAR2_START_H 0xC07170 + +#define mmPCIE_AUX_BAR3_START 0xC07174 + +#define mmPCIE_AUX_BAR4_START_L 0xC07178 + +#define mmPCIE_AUX_BAR4_START_H 0xC0717C + +#define mmPCIE_AUX_BAR5_START 0xC07180 + +#define mmPCIE_AUX_BAR0_LIMIT_L 0xC07184 + +#define mmPCIE_AUX_BAR0_LIMIT_H 0xC07188 + +#define mmPCIE_AUX_BAR1_LIMIT 0xC0718C + +#define mmPCIE_AUX_BAR2_LIMIT_L 0xC07190 + +#define mmPCIE_AUX_BAR2_LIMIT_H 0xC07194 + +#define mmPCIE_AUX_BAR3_LIMIT 0xC07198 + +#define mmPCIE_AUX_BAR4_LIMIT_L 0xC0719C + +#define mmPCIE_AUX_BAR4_LIMIT_H 0xC07200 + +#define mmPCIE_AUX_BAR5_LIMIT 0xC07204 + +#define mmPCIE_AUX_BUS_MASTER_EN 0xC07208 + +#define mmPCIE_AUX_MEM_SPACE_EN 0xC0720C + +#define mmPCIE_AUX_MAX_RD_REQ_SIZE 0xC07210 + +#define mmPCIE_AUX_MAX_PAYLOAD_SIZE 0xC07214 + +#define mmPCIE_AUX_EXT_TAG_EN 0xC07218 + +#define mmPCIE_AUX_RCB 0xC0721C + +#define mmPCIE_AUX_PM_NO_SOFT_RST 0xC07220 + +#define mmPCIE_AUX_PBUS_NUM 0xC07224 + +#define mmPCIE_AUX_PBUS_DEV_NUM 0xC07228 + +#define mmPCIE_AUX_NO_SNOOP_EN 0xC0722C + +#define mmPCIE_AUX_RELAX_ORDER_EN 0xC07230 + +#define mmPCIE_AUX_HP_SLOT_CTRL_ACCESS 0xC07234 + +#define mmPCIE_AUX_DLL_STATE_CHGED_EN 0xC07238 + +#define mmPCIE_AUX_CMP_CPLED_INT_EN 0xC0723C + +#define mmPCIE_AUX_HP_INT_EN 0xC07340 + +#define mmPCIE_AUX_PRE_DET_CHGEN_EN 0xC07344 + +#define mmPCIE_AUX_MRL_SENSOR_CHGED_EN 0xC07348 + +#define mmPCIE_AUX_PWR_FAULT_DET_EN 0xC0734C + +#define mmPCIE_AUX_ATTEN_BUTTON_PRESSED_EN 0xC07350 + +#define mmPCIE_AUX_PF_FLR_ACTIVE 0xC07360 + +#define mmPCIE_AUX_PF_FLR_DONE 0xC07364 + +#define mmPCIE_AUX_FLR_INT 0xC07390 + +#define mmPCIE_AUX_LTR_M_EN 0xC073B0 + +#define mmPCIE_AUX_LTSSM_EN 0xC07428 + +#define mmPCIE_AUX_SYS_INTR 0xC07440 + +#define mmPCIE_AUX_INT_DISABLE 0xC07444 + +#define mmPCIE_AUX_SMLH_LINK_UP 0xC07448 + +#define mmPCIE_AUX_PM_CURR_STATE 0xC07450 + +#define mmPCIE_AUX_RDLH_LINK_UP 0xC07458 + +#define mmPCIE_AUX_BRDG_SLV_XFER_PENDING 0xC0745C + +#define mmPCIE_AUX_BRDG_DBI_XFER_PENDING 0xC07460 + +#define mmPCIE_AUX_AUTO_SP_DIS 0xC07478 + +#define mmPCIE_AUX_DBI 0xC07490 + +#define mmPCIE_AUX_DBI_32 0xC07494 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_0 0xC074A4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_1 0xC074A8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_2 0xC074AC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_3 0xC074B0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_4 0xC074B4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_5 0xC074B8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_6 0xC074BC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_7 0xC074C0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_8 0xC074C4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_9 0xC074C8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_10 0xC074CC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_11 0xC074D0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_12 0xC074D4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_13 0xC074D8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_14 0xC074DC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_15 0xC074E0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_16 0xC074E4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_17 0xC074E8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_18 0xC074EC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_19 0xC074F0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_20 0xC074F4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_21 0xC074F8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_22 0xC074FC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_23 0xC07500 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_24 0xC07504 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_25 0xC07508 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_26 0xC0750C + +#define mmPCIE_AUX_DIAG_STATUS_BUS_27 0xC07510 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_28 0xC07514 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_0 0xC07640 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_1 0xC07644 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_2 0xC07648 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_3 0xC0764C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_4 0xC07650 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_5 0xC07654 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_6 0xC07658 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_7 0xC0765C + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_0 0xC07744 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_1 0xC07748 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_2 0xC0774C + +#define mmPCIE_AUX_APP_RAS_DES_TBA_CTRL 0xC07774 + +#define mmPCIE_AUX_PM_DSTATE 0xC07840 + +#define mmPCIE_AUX_PM_PME_EN 0xC07844 + +#define mmPCIE_AUX_PM_LINKST_IN_L0S 0xC07848 + +#define mmPCIE_AUX_PM_LINKST_IN_L1 0xC0784C + +#define mmPCIE_AUX_PM_LINKST_IN_L2 0xC07850 + +#define mmPCIE_AUX_PM_LINKST_L2_EXIT 0xC07854 + +#define mmPCIE_AUX_PM_STATUS 0xC07858 + +#define mmPCIE_AUX_APP_READY_ENTER_L23 0xC0785C + +#define mmPCIE_AUX_APP_XFER_PENDING 0xC07860 + +#define mmPCIE_AUX_APP_REQ_L1 0xC07930 + +#define mmPCIE_AUX_AUX_PM_EN 0xC07934 + +#define mmPCIE_AUX_APPS_PM_XMT_PME 0xC07938 + +#define mmPCIE_AUX_OUTBAND_PWRUP_CMD 0xC07940 + +#define mmPCIE_AUX_PERST 0xC079B8 + +#endif /* ASIC_REG_PCIE_AUX_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h new file mode 100644 index 000000000000..8eda4de58788 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_EMMC_PLL_REGS_H_ +#define ASIC_REG_PSOC_EMMC_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_EMMC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_EMMC_PLL_NR 0xC70100 + +#define mmPSOC_EMMC_PLL_NF 0xC70104 + +#define mmPSOC_EMMC_PLL_OD 0xC70108 + +#define mmPSOC_EMMC_PLL_NB 0xC7010C + +#define mmPSOC_EMMC_PLL_CFG 0xC70110 + +#define mmPSOC_EMMC_PLL_LOSE_MASK 0xC70120 + +#define mmPSOC_EMMC_PLL_LOCK_INTR 0xC70128 + +#define mmPSOC_EMMC_PLL_LOCK_BYPASS 0xC7012C + +#define mmPSOC_EMMC_PLL_DATA_CHNG 0xC70130 + +#define mmPSOC_EMMC_PLL_RST 0xC70134 + +#define mmPSOC_EMMC_PLL_SLIP_WD_CNTR 0xC70150 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_0 0xC70200 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_1 0xC70204 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_2 0xC70208 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_3 0xC7020C + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_0 0xC70220 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_1 0xC70224 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_2 0xC70228 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_3 0xC7022C + +#define mmPSOC_EMMC_PLL_DIV_SEL_0 0xC70280 + +#define mmPSOC_EMMC_PLL_DIV_SEL_1 0xC70284 + +#define mmPSOC_EMMC_PLL_DIV_SEL_2 0xC70288 + +#define mmPSOC_EMMC_PLL_DIV_SEL_3 0xC7028C + +#define mmPSOC_EMMC_PLL_DIV_EN_0 0xC702A0 + +#define mmPSOC_EMMC_PLL_DIV_EN_1 0xC702A4 + +#define mmPSOC_EMMC_PLL_DIV_EN_2 0xC702A8 + +#define mmPSOC_EMMC_PLL_DIV_EN_3 0xC702AC + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_0 0xC702C0 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_1 0xC702C4 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_2 0xC702C8 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_3 0xC702CC + +#define mmPSOC_EMMC_PLL_CLK_GATER 0xC70300 + +#define mmPSOC_EMMC_PLL_CLK_RLX_0 0xC70310 + +#define mmPSOC_EMMC_PLL_CLK_RLX_1 0xC70314 + +#define mmPSOC_EMMC_PLL_CLK_RLX_2 0xC70318 + +#define mmPSOC_EMMC_PLL_CLK_RLX_3 0xC7031C + +#define mmPSOC_EMMC_PLL_REF_CNTR_PERIOD 0xC70400 + +#define mmPSOC_EMMC_PLL_REF_LOW_THRESHOLD 0xC70410 + +#define mmPSOC_EMMC_PLL_REF_HIGH_THRESHOLD 0xC70420 + +#define mmPSOC_EMMC_PLL_PLL_NOT_STABLE 0xC70430 + +#define mmPSOC_EMMC_PLL_FREQ_CALC_EN 0xC70440 + +#endif /* ASIC_REG_PSOC_EMMC_PLL_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h new file mode 100644 index 000000000000..d4bf0e1db4df --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h @@ -0,0 +1,447 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BTM_FSM */ +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN */ +#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_EN */ +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 + +/* PSOC_GLOBAL_CONF_SCRATCHPAD */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SEMAPHORE */ +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_WARM_REBOOT */ +#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_UBOOT_MAGIC */ +#define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPL_SOURCE */ +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 + +/* PSOC_GLOBAL_CONF_I2C_SLV */ +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1 + +/* PSOC_GLOBAL_CONF_APP_STATUS */ +#define PSOC_GLOBAL_CONF_APP_STATUS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_APP_STATUS_IND_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_STS */ +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 + +/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TARGETID */ +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 12 +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFFF000 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 + +/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MII_ADDR */ +#define PSOC_GLOBAL_CONF_MII_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MII_ADDR_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_MII_SPEED */ +#define PSOC_GLOBAL_CONF_MII_SPEED_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MII_SPEED_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0xFE0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_SHIFT 12 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_MASK 0x3000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_SHIFT 14 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_MASK 0x1FC000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_SHIFT 21 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK 0x200000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_SHIFT 22 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_MASK 0x1C00000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_SHIFT 25 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_MASK 0x2000000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_SHIFT 26 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_MASK 0x1C000000 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MASK_REQ */ +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_WD_RST_CFG */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_UNIT_RST_N */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_PRSTN_MASK */ +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_MASK */ +#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_SRC */ +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */ +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7 + +/* PSOC_GLOBAL_CONF_BNK3V3_MS */ +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_SEL */ +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h new file mode 100644 index 000000000000..cfbdd2c9c5c7 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h @@ -0,0 +1,745 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0xC4B000 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0xC4B004 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0xC4B008 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0xC4B00C + +#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0xC4B020 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0xC4B024 + +#define mmPSOC_GLOBAL_CONF_BTM_FSM 0xC4B028 + +#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0xC4B030 + +#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0xC4B034 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0xC4B038 + +#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0xC4B040 + +#define mmPSOC_GLOBAL_CONF_PRSTN 0xC4B044 + +#define mmPSOC_GLOBAL_CONF_PCIE_EN 0xC4B048 + +#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0xC4B050 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0xC4B054 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0xC4B100 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0xC4B104 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0xC4B108 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0xC4B10C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0xC4B110 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0xC4B114 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0xC4B118 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0xC4B11C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0xC4B120 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0xC4B124 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0xC4B128 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0xC4B12C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0xC4B130 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0xC4B134 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0xC4B138 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0xC4B13C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0xC4B140 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0xC4B144 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0xC4B148 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0xC4B14C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0xC4B150 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0xC4B154 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0xC4B158 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0xC4B15C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0xC4B160 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0xC4B164 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0xC4B168 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0xC4B16C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0xC4B170 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0xC4B174 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0xC4B178 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0xC4B17C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0xC4B200 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0xC4B204 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0xC4B208 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0xC4B20C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0xC4B210 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0xC4B214 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0xC4B218 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0xC4B21C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0xC4B220 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0xC4B224 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0xC4B228 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0xC4B22C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0xC4B230 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0xC4B234 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0xC4B238 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0xC4B23C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0xC4B240 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0xC4B244 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0xC4B248 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0xC4B24C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0xC4B250 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0xC4B254 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0xC4B258 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0xC4B25C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0xC4B260 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0xC4B264 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0xC4B268 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0xC4B26C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0xC4B270 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0xC4B274 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0xC4B278 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0xC4B27C + +#define mmPSOC_GLOBAL_CONF_WARM_REBOOT 0xC4B300 + +#define mmPSOC_GLOBAL_CONF_UBOOT_MAGIC 0xC4B304 + +#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0xC4B308 + +#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0xC4B30C + +#define mmPSOC_GLOBAL_CONF_I2C_SLV 0xC4B310 + +#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0xC4B314 + +#define mmPSOC_GLOBAL_CONF_APP_STATUS 0xC4B320 + +#define mmPSOC_GLOBAL_CONF_BTL_STS 0xC4B340 + +#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0xC4B350 + +#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0xC4B354 + +#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0xC4B358 + +#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0xC4B35C + +#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0xC4B360 + +#define mmPSOC_GLOBAL_CONF_TARGETID 0xC4B400 + +#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0xC4B420 + +#define mmPSOC_GLOBAL_CONF_MII_ADDR 0xC4B424 + +#define mmPSOC_GLOBAL_CONF_MII_SPEED 0xC4B428 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS 0xC4B430 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0xC4B450 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0xC4B454 + +#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0xC4B458 + +#define mmPSOC_GLOBAL_CONF_MASK_REQ 0xC4B45C + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG 0xC4B470 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG 0xC4B474 + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG 0xC4B478 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG 0xC4B47C + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N 0xC4B480 + +#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0xC4B484 + +#define mmPSOC_GLOBAL_CONF_WD_MASK 0xC4B488 + +#define mmPSOC_GLOBAL_CONF_RST_SRC 0xC4B490 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0xC4B500 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0xC4B504 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0xC4B508 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0xC4B50C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0xC4B510 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0xC4B514 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0xC4B518 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0xC4B51C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0xC4B520 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0xC4B524 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0xC4B528 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0xC4B52C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0xC4B530 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0xC4B534 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0xC4B538 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0xC4B53C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0xC4B540 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0xC4B544 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0xC4B548 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0xC4B54C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0xC4B550 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0xC4B554 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0xC4B558 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0xC4B55C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0xC4B560 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0xC4B564 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0xC4B568 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0xC4B56C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0xC4B570 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0xC4B574 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0xC4B578 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0xC4B57C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0xC4B580 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0xC4B584 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0xC4B588 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0xC4B58C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0xC4B590 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0xC4B594 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0xC4B598 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0xC4B59C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0xC4B5A0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0xC4B5A4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0xC4B5A8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0xC4B5AC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0xC4B5B0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0xC4B5B4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0xC4B5B8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0xC4B5BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0xC4B5C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0xC4B5C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0xC4B5C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0xC4B5CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0xC4B5D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0xC4B5D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0xC4B5D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0xC4B5DC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0xC4B5E0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0xC4B5E4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0xC4B5E8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0xC4B5EC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0xC4B5F0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0xC4B5F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0xC4B5F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0xC4B5FC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0xC4B600 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0xC4B604 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0xC4B608 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0xC4B60C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0xC4B610 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0xC4B640 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0xC4B644 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0xC4B648 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0xC4B64C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0xC4B650 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0xC4B654 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0xC4B658 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0xC4B65C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0xC4B660 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0xC4B664 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0xC4B668 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0xC4B66C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0 0xC4B680 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1 0xC4B684 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2 0xC4B688 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3 0xC4B68C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4 0xC4B690 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5 0xC4B694 + +#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0xC4B6E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0xC4B700 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0xC4B704 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0xC4B708 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0xC4B70C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0xC4B710 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0xC4B714 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0xC4B718 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0xC4B71C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0xC4B720 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0xC4B724 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0xC4B728 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0xC4B72C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0xC4B730 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0xC4B734 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0xC4B738 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0xC4B73C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0xC4B740 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0xC4B744 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0xC4B748 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0xC4B74C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0xC4B750 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0xC4B754 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0xC4B758 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0xC4B75C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0xC4B760 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0xC4B764 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0xC4B768 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0xC4B76C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0xC4B770 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0xC4B774 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0xC4B778 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0xC4B77C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0xC4B780 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0xC4B784 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0xC4B788 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0xC4B78C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0xC4B790 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0xC4B794 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0xC4B798 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0xC4B79C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0xC4B7A0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0xC4B7A4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0xC4B7A8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0xC4B7AC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0xC4B7B0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0xC4B7B4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0xC4B7B8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0xC4B7BC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0xC4B7C0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0xC4B7C4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0xC4B7C8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0xC4B7CC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0xC4B7D0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0xC4B7D4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0xC4B7D8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0xC4B7DC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0xC4B7E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0xC4B7E4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0xC4B7E8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0xC4B7EC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0xC4B7F0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0xC4B7F4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0xC4B7F8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0xC4B7FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0xC4B800 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0xC4B804 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0xC4B808 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0xC4B80C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0xC4B810 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0xC4B814 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0xC4B818 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0xC4B81C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0xC4B820 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0xC4B824 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0xC4B828 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0xC4B82C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0xC4B830 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0xC4B834 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0xC4B838 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0xC4B83C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0xC4B840 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0xC4B844 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0xC4B900 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0xC4B904 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0xC4B908 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0xC4B90C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0xC4B910 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0xC4B914 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0xC4B918 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0xC4B91C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0xC4B920 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0xC4B924 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0xC4B928 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0xC4B92C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0xC4B930 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0xC4B934 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0xC4B938 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0xC4B93C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0xC4B940 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0xC4B944 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0xC4B948 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0xC4B94C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0xC4B950 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0xC4B954 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0xC4B958 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0xC4B95C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0xC4B960 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0xC4B964 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0xC4B968 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0xC4B96C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0xC4B970 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0xC4B974 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0xC4B978 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0xC4B97C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0xC4B980 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0xC4B984 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0xC4B988 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0xC4B98C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0xC4B990 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0xC4B994 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0xC4B998 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0xC4B99C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0xC4B9A0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0xC4B9A4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0xC4B9A8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0xC4B9AC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0xC4B9B0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0xC4B9B4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0xC4B9B8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0xC4B9BC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0xC4B9C0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0xC4B9C4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0xC4B9C8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0xC4B9CC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0xC4B9D0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0xC4B9D4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0xC4B9D8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0xC4B9DC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0xC4B9E0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0xC4B9E4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0xC4B9E8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0xC4B9EC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0xC4B9F0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0xC4B9F4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0xC4B9F8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0xC4B9FC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0xC4BA00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0xC4BA04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0xC4BA08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0xC4BA0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0xC4BA10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0xC4BA14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0xC4BA18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0xC4BA1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0xC4BA20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0xC4BA24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0xC4BA28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0xC4BA2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0xC4BA30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0xC4BA34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0xC4BA38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0xC4BA3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0xC4BA40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0xC4BA44 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h new file mode 100644 index 000000000000..6723d8f76f30 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_ +#define ASIC_REG_PSOC_MME_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_MME_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_MME_PLL_NR 0xC71100 + +#define mmPSOC_MME_PLL_NF 0xC71104 + +#define mmPSOC_MME_PLL_OD 0xC71108 + +#define mmPSOC_MME_PLL_NB 0xC7110C + +#define mmPSOC_MME_PLL_CFG 0xC71110 + +#define mmPSOC_MME_PLL_LOSE_MASK 0xC71120 + +#define mmPSOC_MME_PLL_LOCK_INTR 0xC71128 + +#define mmPSOC_MME_PLL_LOCK_BYPASS 0xC7112C + +#define mmPSOC_MME_PLL_DATA_CHNG 0xC71130 + +#define mmPSOC_MME_PLL_RST 0xC71134 + +#define mmPSOC_MME_PLL_SLIP_WD_CNTR 0xC71150 + +#define mmPSOC_MME_PLL_DIV_FACTOR_0 0xC71200 + +#define mmPSOC_MME_PLL_DIV_FACTOR_1 0xC71204 + +#define mmPSOC_MME_PLL_DIV_FACTOR_2 0xC71208 + +#define mmPSOC_MME_PLL_DIV_FACTOR_3 0xC7120C + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0 0xC71220 + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1 0xC71224 + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2 0xC71228 + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3 0xC7122C + +#define mmPSOC_MME_PLL_DIV_SEL_0 0xC71280 + +#define mmPSOC_MME_PLL_DIV_SEL_1 0xC71284 + +#define mmPSOC_MME_PLL_DIV_SEL_2 0xC71288 + +#define mmPSOC_MME_PLL_DIV_SEL_3 0xC7128C + +#define mmPSOC_MME_PLL_DIV_EN_0 0xC712A0 + +#define mmPSOC_MME_PLL_DIV_EN_1 0xC712A4 + +#define mmPSOC_MME_PLL_DIV_EN_2 0xC712A8 + +#define mmPSOC_MME_PLL_DIV_EN_3 0xC712AC + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0 0xC712C0 + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1 0xC712C4 + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2 0xC712C8 + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3 0xC712CC + +#define mmPSOC_MME_PLL_CLK_GATER 0xC71300 + +#define mmPSOC_MME_PLL_CLK_RLX_0 0xC71310 + +#define mmPSOC_MME_PLL_CLK_RLX_1 0xC71314 + +#define mmPSOC_MME_PLL_CLK_RLX_2 0xC71318 + +#define mmPSOC_MME_PLL_CLK_RLX_3 0xC7131C + +#define mmPSOC_MME_PLL_REF_CNTR_PERIOD 0xC71400 + +#define mmPSOC_MME_PLL_REF_LOW_THRESHOLD 0xC71410 + +#define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD 0xC71420 + +#define mmPSOC_MME_PLL_PLL_NOT_STABLE 0xC71430 + +#define mmPSOC_MME_PLL_FREQ_CALC_EN 0xC71440 + +#endif /* ASIC_REG_PSOC_MME_PLL_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h new file mode 100644 index 000000000000..abcded0531c9 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_ +#define ASIC_REG_PSOC_PCI_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_PCI_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_PCI_PLL_NR 0xC72100 + +#define mmPSOC_PCI_PLL_NF 0xC72104 + +#define mmPSOC_PCI_PLL_OD 0xC72108 + +#define mmPSOC_PCI_PLL_NB 0xC7210C + +#define mmPSOC_PCI_PLL_CFG 0xC72110 + +#define mmPSOC_PCI_PLL_LOSE_MASK 0xC72120 + +#define mmPSOC_PCI_PLL_LOCK_INTR 0xC72128 + +#define mmPSOC_PCI_PLL_LOCK_BYPASS 0xC7212C + +#define mmPSOC_PCI_PLL_DATA_CHNG 0xC72130 + +#define mmPSOC_PCI_PLL_RST 0xC72134 + +#define mmPSOC_PCI_PLL_SLIP_WD_CNTR 0xC72150 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_0 0xC72200 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_1 0xC72204 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_2 0xC72208 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_3 0xC7220C + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0 0xC72220 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1 0xC72224 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2 0xC72228 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3 0xC7222C + +#define mmPSOC_PCI_PLL_DIV_SEL_0 0xC72280 + +#define mmPSOC_PCI_PLL_DIV_SEL_1 0xC72284 + +#define mmPSOC_PCI_PLL_DIV_SEL_2 0xC72288 + +#define mmPSOC_PCI_PLL_DIV_SEL_3 0xC7228C + +#define mmPSOC_PCI_PLL_DIV_EN_0 0xC722A0 + +#define mmPSOC_PCI_PLL_DIV_EN_1 0xC722A4 + +#define mmPSOC_PCI_PLL_DIV_EN_2 0xC722A8 + +#define mmPSOC_PCI_PLL_DIV_EN_3 0xC722AC + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0 0xC722C0 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1 0xC722C4 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2 0xC722C8 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3 0xC722CC + +#define mmPSOC_PCI_PLL_CLK_GATER 0xC72300 + +#define mmPSOC_PCI_PLL_CLK_RLX_0 0xC72310 + +#define mmPSOC_PCI_PLL_CLK_RLX_1 0xC72314 + +#define mmPSOC_PCI_PLL_CLK_RLX_2 0xC72318 + +#define mmPSOC_PCI_PLL_CLK_RLX_3 0xC7231C + +#define mmPSOC_PCI_PLL_REF_CNTR_PERIOD 0xC72400 + +#define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD 0xC72410 + +#define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD 0xC72420 + +#define mmPSOC_PCI_PLL_PLL_NOT_STABLE 0xC72430 + +#define mmPSOC_PCI_PLL_FREQ_CALC_EN 0xC72440 + +#endif /* ASIC_REG_PSOC_PCI_PLL_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h new file mode 100644 index 000000000000..5925c7477c25 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_SPI_REGS_H_ +#define ASIC_REG_PSOC_SPI_REGS_H_ + +/* + ***************************************** + * PSOC_SPI (Prototype: SPI) + ***************************************** + */ + +#define mmPSOC_SPI_CTRLR0 0xC43000 + +#define mmPSOC_SPI_CTRLR1 0xC43004 + +#define mmPSOC_SPI_SSIENR 0xC43008 + +#define mmPSOC_SPI_MWCR 0xC4300C + +#define mmPSOC_SPI_SER 0xC43010 + +#define mmPSOC_SPI_BAUDR 0xC43014 + +#define mmPSOC_SPI_TXFTLR 0xC43018 + +#define mmPSOC_SPI_RXFTLR 0xC4301C + +#define mmPSOC_SPI_TXFLR 0xC43020 + +#define mmPSOC_SPI_RXFLR 0xC43024 + +#define mmPSOC_SPI_SR 0xC43028 + +#define mmPSOC_SPI_IMR 0xC4302C + +#define mmPSOC_SPI_ISR 0xC43030 + +#define mmPSOC_SPI_RISR 0xC43034 + +#define mmPSOC_SPI_TXOICR 0xC43038 + +#define mmPSOC_SPI_RXOICR 0xC4303C + +#define mmPSOC_SPI_RXUICR 0xC43040 + +#define mmPSOC_SPI_MSTICR 0xC43044 + +#define mmPSOC_SPI_ICR 0xC43048 + +#define mmPSOC_SPI_IDR 0xC43058 + +#define mmPSOC_SPI_SSI_VERSION_ID 0xC4305C + +#define mmPSOC_SPI_DR0 0xC43060 + +#define mmPSOC_SPI_DR1 0xC43064 + +#define mmPSOC_SPI_DR2 0xC43068 + +#define mmPSOC_SPI_DR3 0xC4306C + +#define mmPSOC_SPI_DR4 0xC43070 + +#define mmPSOC_SPI_DR5 0xC43074 + +#define mmPSOC_SPI_DR6 0xC43078 + +#define mmPSOC_SPI_DR7 0xC4307C + +#define mmPSOC_SPI_DR8 0xC43080 + +#define mmPSOC_SPI_DR9 0xC43084 + +#define mmPSOC_SPI_DR10 0xC43088 + +#define mmPSOC_SPI_DR11 0xC4308C + +#define mmPSOC_SPI_DR12 0xC43090 + +#define mmPSOC_SPI_DR13 0xC43094 + +#define mmPSOC_SPI_DR14 0xC43098 + +#define mmPSOC_SPI_DR15 0xC4309C + +#define mmPSOC_SPI_DR16 0xC430A0 + +#define mmPSOC_SPI_DR17 0xC430A4 + +#define mmPSOC_SPI_DR18 0xC430A8 + +#define mmPSOC_SPI_DR19 0xC430AC + +#define mmPSOC_SPI_DR20 0xC430B0 + +#define mmPSOC_SPI_DR21 0xC430B4 + +#define mmPSOC_SPI_DR22 0xC430B8 + +#define mmPSOC_SPI_DR23 0xC430BC + +#define mmPSOC_SPI_DR24 0xC430C0 + +#define mmPSOC_SPI_DR25 0xC430C4 + +#define mmPSOC_SPI_DR26 0xC430C8 + +#define mmPSOC_SPI_DR27 0xC430CC + +#define mmPSOC_SPI_DR28 0xC430D0 + +#define mmPSOC_SPI_DR29 0xC430D4 + +#define mmPSOC_SPI_DR30 0xC430D8 + +#define mmPSOC_SPI_DR31 0xC430DC + +#define mmPSOC_SPI_DR32 0xC430E0 + +#define mmPSOC_SPI_DR33 0xC430E4 + +#define mmPSOC_SPI_DR34 0xC430E8 + +#define mmPSOC_SPI_DR35 0xC430EC + +#define mmPSOC_SPI_RX_SAMPLE_DLY 0xC430F0 + +#define mmPSOC_SPI_RSVD_1 0xC430F8 + +#define mmPSOC_SPI_RSVD_2 0xC430FC + +#endif /* ASIC_REG_PSOC_SPI_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h new file mode 100644 index 000000000000..d56c9fa0e7ba --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X0_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_E_ARB 0x201100 + +#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_W_ARB 0x201104 + +#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB 0x201110 + +#define mmSRAM_Y0_X0_RTR_HBW_E_ARB_MAX 0x201120 + +#define mmSRAM_Y0_X0_RTR_HBW_W_ARB_MAX 0x201124 + +#define mmSRAM_Y0_X0_RTR_HBW_L_ARB_MAX 0x201130 + +#define mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB 0x201140 + +#define mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB 0x201144 + +#define mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB 0x201148 + +#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB 0x201160 + +#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB 0x201164 + +#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_L_ARB 0x201168 + +#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_E_ARB 0x201200 + +#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_W_ARB 0x201204 + +#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_L_ARB 0x201210 + +#define mmSRAM_Y0_X0_RTR_LBW_E_ARB_MAX 0x201220 + +#define mmSRAM_Y0_X0_RTR_LBW_W_ARB_MAX 0x201224 + +#define mmSRAM_Y0_X0_RTR_LBW_L_ARB_MAX 0x201230 + +#define mmSRAM_Y0_X0_RTR_LBW_DATA_E_ARB 0x201240 + +#define mmSRAM_Y0_X0_RTR_LBW_DATA_W_ARB 0x201244 + +#define mmSRAM_Y0_X0_RTR_LBW_DATA_L_ARB 0x201248 + +#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_E_ARB 0x201260 + +#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_W_ARB 0x201264 + +#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_L_ARB 0x201268 + +#define mmSRAM_Y0_X0_RTR_DBG_E_ARB 0x201300 + +#define mmSRAM_Y0_X0_RTR_DBG_W_ARB 0x201304 + +#define mmSRAM_Y0_X0_RTR_DBG_L_ARB 0x201310 + +#define mmSRAM_Y0_X0_RTR_DBG_E_ARB_MAX 0x201320 + +#define mmSRAM_Y0_X0_RTR_DBG_W_ARB_MAX 0x201324 + +#define mmSRAM_Y0_X0_RTR_DBG_L_ARB_MAX 0x201330 + +#endif /* ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h new file mode 100644 index 000000000000..5624544303ca --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X1_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_E_ARB 0x205100 + +#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_W_ARB 0x205104 + +#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB 0x205110 + +#define mmSRAM_Y0_X1_RTR_HBW_E_ARB_MAX 0x205120 + +#define mmSRAM_Y0_X1_RTR_HBW_W_ARB_MAX 0x205124 + +#define mmSRAM_Y0_X1_RTR_HBW_L_ARB_MAX 0x205130 + +#define mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB 0x205140 + +#define mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB 0x205144 + +#define mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB 0x205148 + +#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB 0x205160 + +#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB 0x205164 + +#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_L_ARB 0x205168 + +#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_E_ARB 0x205200 + +#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_W_ARB 0x205204 + +#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_L_ARB 0x205210 + +#define mmSRAM_Y0_X1_RTR_LBW_E_ARB_MAX 0x205220 + +#define mmSRAM_Y0_X1_RTR_LBW_W_ARB_MAX 0x205224 + +#define mmSRAM_Y0_X1_RTR_LBW_L_ARB_MAX 0x205230 + +#define mmSRAM_Y0_X1_RTR_LBW_DATA_E_ARB 0x205240 + +#define mmSRAM_Y0_X1_RTR_LBW_DATA_W_ARB 0x205244 + +#define mmSRAM_Y0_X1_RTR_LBW_DATA_L_ARB 0x205248 + +#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_E_ARB 0x205260 + +#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_W_ARB 0x205264 + +#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_L_ARB 0x205268 + +#define mmSRAM_Y0_X1_RTR_DBG_E_ARB 0x205300 + +#define mmSRAM_Y0_X1_RTR_DBG_W_ARB 0x205304 + +#define mmSRAM_Y0_X1_RTR_DBG_L_ARB 0x205310 + +#define mmSRAM_Y0_X1_RTR_DBG_E_ARB_MAX 0x205320 + +#define mmSRAM_Y0_X1_RTR_DBG_W_ARB_MAX 0x205324 + +#define mmSRAM_Y0_X1_RTR_DBG_L_ARB_MAX 0x205330 + +#endif /* ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h new file mode 100644 index 000000000000..3322bc0bd1df --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X2_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_E_ARB 0x209100 + +#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_W_ARB 0x209104 + +#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB 0x209110 + +#define mmSRAM_Y0_X2_RTR_HBW_E_ARB_MAX 0x209120 + +#define mmSRAM_Y0_X2_RTR_HBW_W_ARB_MAX 0x209124 + +#define mmSRAM_Y0_X2_RTR_HBW_L_ARB_MAX 0x209130 + +#define mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB 0x209140 + +#define mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB 0x209144 + +#define mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB 0x209148 + +#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB 0x209160 + +#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB 0x209164 + +#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_L_ARB 0x209168 + +#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_E_ARB 0x209200 + +#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_W_ARB 0x209204 + +#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_L_ARB 0x209210 + +#define mmSRAM_Y0_X2_RTR_LBW_E_ARB_MAX 0x209220 + +#define mmSRAM_Y0_X2_RTR_LBW_W_ARB_MAX 0x209224 + +#define mmSRAM_Y0_X2_RTR_LBW_L_ARB_MAX 0x209230 + +#define mmSRAM_Y0_X2_RTR_LBW_DATA_E_ARB 0x209240 + +#define mmSRAM_Y0_X2_RTR_LBW_DATA_W_ARB 0x209244 + +#define mmSRAM_Y0_X2_RTR_LBW_DATA_L_ARB 0x209248 + +#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_E_ARB 0x209260 + +#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_W_ARB 0x209264 + +#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_L_ARB 0x209268 + +#define mmSRAM_Y0_X2_RTR_DBG_E_ARB 0x209300 + +#define mmSRAM_Y0_X2_RTR_DBG_W_ARB 0x209304 + +#define mmSRAM_Y0_X2_RTR_DBG_L_ARB 0x209310 + +#define mmSRAM_Y0_X2_RTR_DBG_E_ARB_MAX 0x209320 + +#define mmSRAM_Y0_X2_RTR_DBG_W_ARB_MAX 0x209324 + +#define mmSRAM_Y0_X2_RTR_DBG_L_ARB_MAX 0x209330 + +#endif /* ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h new file mode 100644 index 000000000000..81e393db2027 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X3_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_E_ARB 0x20D100 + +#define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_W_ARB 0x20D104 + +#define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB 0x20D110 + +#define mmSRAM_Y0_X3_RTR_HBW_E_ARB_MAX 0x20D120 + +#define mmSRAM_Y0_X3_RTR_HBW_W_ARB_MAX 0x20D124 + +#define mmSRAM_Y0_X3_RTR_HBW_L_ARB_MAX 0x20D130 + +#define mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB 0x20D140 + +#define mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB 0x20D144 + +#define mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB 0x20D148 + +#define mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB 0x20D160 + +#define mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB 0x20D164 + +#define mmSRAM_Y0_X3_RTR_HBW_WR_RS_L_ARB 0x20D168 + +#define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_E_ARB 0x20D200 + +#define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_W_ARB 0x20D204 + +#define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_L_ARB 0x20D210 + +#define mmSRAM_Y0_X3_RTR_LBW_E_ARB_MAX 0x20D220 + +#define mmSRAM_Y0_X3_RTR_LBW_W_ARB_MAX 0x20D224 + +#define mmSRAM_Y0_X3_RTR_LBW_L_ARB_MAX 0x20D230 + +#define mmSRAM_Y0_X3_RTR_LBW_DATA_E_ARB 0x20D240 + +#define mmSRAM_Y0_X3_RTR_LBW_DATA_W_ARB 0x20D244 + +#define mmSRAM_Y0_X3_RTR_LBW_DATA_L_ARB 0x20D248 + +#define mmSRAM_Y0_X3_RTR_LBW_WR_RS_E_ARB 0x20D260 + +#define mmSRAM_Y0_X3_RTR_LBW_WR_RS_W_ARB 0x20D264 + +#define mmSRAM_Y0_X3_RTR_LBW_WR_RS_L_ARB 0x20D268 + +#define mmSRAM_Y0_X3_RTR_DBG_E_ARB 0x20D300 + +#define mmSRAM_Y0_X3_RTR_DBG_W_ARB 0x20D304 + +#define mmSRAM_Y0_X3_RTR_DBG_L_ARB 0x20D310 + +#define mmSRAM_Y0_X3_RTR_DBG_E_ARB_MAX 0x20D320 + +#define mmSRAM_Y0_X3_RTR_DBG_W_ARB_MAX 0x20D324 + +#define mmSRAM_Y0_X3_RTR_DBG_L_ARB_MAX 0x20D330 + +#endif /* ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h new file mode 100644 index 000000000000..b2e11b1de385 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X4_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_E_ARB 0x211100 + +#define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_W_ARB 0x211104 + +#define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB 0x211110 + +#define mmSRAM_Y0_X4_RTR_HBW_E_ARB_MAX 0x211120 + +#define mmSRAM_Y0_X4_RTR_HBW_W_ARB_MAX 0x211124 + +#define mmSRAM_Y0_X4_RTR_HBW_L_ARB_MAX 0x211130 + +#define mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB 0x211140 + +#define mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB 0x211144 + +#define mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB 0x211148 + +#define mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB 0x211160 + +#define mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB 0x211164 + +#define mmSRAM_Y0_X4_RTR_HBW_WR_RS_L_ARB 0x211168 + +#define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_E_ARB 0x211200 + +#define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_W_ARB 0x211204 + +#define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_L_ARB 0x211210 + +#define mmSRAM_Y0_X4_RTR_LBW_E_ARB_MAX 0x211220 + +#define mmSRAM_Y0_X4_RTR_LBW_W_ARB_MAX 0x211224 + +#define mmSRAM_Y0_X4_RTR_LBW_L_ARB_MAX 0x211230 + +#define mmSRAM_Y0_X4_RTR_LBW_DATA_E_ARB 0x211240 + +#define mmSRAM_Y0_X4_RTR_LBW_DATA_W_ARB 0x211244 + +#define mmSRAM_Y0_X4_RTR_LBW_DATA_L_ARB 0x211248 + +#define mmSRAM_Y0_X4_RTR_LBW_WR_RS_E_ARB 0x211260 + +#define mmSRAM_Y0_X4_RTR_LBW_WR_RS_W_ARB 0x211264 + +#define mmSRAM_Y0_X4_RTR_LBW_WR_RS_L_ARB 0x211268 + +#define mmSRAM_Y0_X4_RTR_DBG_E_ARB 0x211300 + +#define mmSRAM_Y0_X4_RTR_DBG_W_ARB 0x211304 + +#define mmSRAM_Y0_X4_RTR_DBG_L_ARB 0x211310 + +#define mmSRAM_Y0_X4_RTR_DBG_E_ARB_MAX 0x211320 + +#define mmSRAM_Y0_X4_RTR_DBG_W_ARB_MAX 0x211324 + +#define mmSRAM_Y0_X4_RTR_DBG_L_ARB_MAX 0x211330 + +#endif /* ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h new file mode 100644 index 000000000000..b4ea8cae2757 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_MASKS_H_ +#define ASIC_REG_STLB_MASKS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +/* STLB_CACHE_INV */ +#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +/* STLB_CACHE_INV_BASE_39_8 */ +#define STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 +#define STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF + +/* STLB_CACHE_INV_BASE_49_40 */ +#define STLB_CACHE_INV_BASE_49_40_PA_SHIFT 0 +#define STLB_CACHE_INV_BASE_49_40_PA_MASK 0x3FF + +/* STLB_STLB_FEATURE_EN */ +#define STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 +#define STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 +#define STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 +#define STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 +#define STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 +#define STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 +#define STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 +#define STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 +#define STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 +#define STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 +#define STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 +#define STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 +#define STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 +#define STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 +#define STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 +#define STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0xF80 + +/* STLB_STLB_AXI_CACHE */ +#define STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 +#define STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF +#define STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 +#define STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 +#define STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 +#define STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 + +/* STLB_HOP_CONFIGURATION */ +#define STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 +#define STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 +#define STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SHIFT 4 +#define STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_MASK 0x70 +#define STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 8 +#define STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x700 + +/* STLB_LINK_LIST_LOOKUP_MASK_49_32 */ +#define STLB_LINK_LIST_LOOKUP_MASK_49_32_R_SHIFT 0 +#define STLB_LINK_LIST_LOOKUP_MASK_49_32_R_MASK 0x3FFFF + +/* STLB_LINK_LIST_LOOKUP_MASK_31_0 */ +#define STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 +#define STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF + +/* STLB_LINK_LIST */ +#define STLB_LINK_LIST_CLEAR_SHIFT 0 +#define STLB_LINK_LIST_CLEAR_MASK 0x1 +#define STLB_LINK_LIST_EN_SHIFT 1 +#define STLB_LINK_LIST_EN_MASK 0x2 + +/* STLB_INV_ALL_START */ +#define STLB_INV_ALL_START_R_SHIFT 0 +#define STLB_INV_ALL_START_R_MASK 0x1 + +/* STLB_INV_ALL_SET */ +#define STLB_INV_ALL_SET_R_SHIFT 0 +#define STLB_INV_ALL_SET_R_MASK 0xFF + +/* STLB_INV_PS */ +#define STLB_INV_PS_R_SHIFT 0 +#define STLB_INV_PS_R_MASK 0x3 + +/* STLB_INV_CONSUMER_INDEX */ +#define STLB_INV_CONSUMER_INDEX_R_SHIFT 0 +#define STLB_INV_CONSUMER_INDEX_R_MASK 0xFF + +/* STLB_INV_HIT_COUNT */ +#define STLB_INV_HIT_COUNT_R_SHIFT 0 +#define STLB_INV_HIT_COUNT_R_MASK 0x7FF + +/* STLB_INV_SET */ +#define STLB_INV_SET_R_SHIFT 0 +#define STLB_INV_SET_R_MASK 0xFF + +/* STLB_SRAM_INIT */ +#define STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 +#define STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 +#define STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 +#define STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC +#define STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 +#define STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 + +#endif /* ASIC_REG_STLB_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h new file mode 100644 index 000000000000..0f5281d3e65b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_REGS_H_ +#define ASIC_REG_STLB_REGS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +#define mmSTLB_CACHE_INV 0x490010 + +#define mmSTLB_CACHE_INV_BASE_39_8 0x490014 + +#define mmSTLB_CACHE_INV_BASE_49_40 0x490018 + +#define mmSTLB_STLB_FEATURE_EN 0x49001C + +#define mmSTLB_STLB_AXI_CACHE 0x490020 + +#define mmSTLB_HOP_CONFIGURATION 0x490024 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32 0x490028 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0 0x49002C + +#define mmSTLB_LINK_LIST 0x490030 + +#define mmSTLB_INV_ALL_START 0x490034 + +#define mmSTLB_INV_ALL_SET 0x490038 + +#define mmSTLB_INV_PS 0x49003C + +#define mmSTLB_INV_CONSUMER_INDEX 0x490040 + +#define mmSTLB_INV_HIT_COUNT 0x490044 + +#define mmSTLB_INV_SET 0x490048 + +#define mmSTLB_SRAM_INIT 0x49004C + +#endif /* ASIC_REG_STLB_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h new file mode 100644 index 000000000000..e5587b49eecd --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h @@ -0,0 +1,1607 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_MASKS_H_ +#define ASIC_REG_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_SRF */ +#define TPC0_CFG_KERNEL_SRF_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_CONFIG */ +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 8 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0x3F00 + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* TPC0_CFG_RESERVED_DESC_END */ +#define TPC0_CFG_RESERVED_DESC_END_V_SHIFT 0 +#define TPC0_CFG_RESERVED_DESC_END_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ROUND_CSR */ +#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* TPC0_CFG_TBUF_BASE_ADDR_LOW */ +#define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TBUF_BASE_ADDR_HIGH */ +#define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SEMAPHORE */ +#define TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_VFLAGS */ +#define TPC0_CFG_VFLAGS_V_SHIFT 0 +#define TPC0_CFG_VFLAGS_V_MASK 0xF + +/* TPC0_CFG_SFLAGS */ +#define TPC0_CFG_SFLAGS_V_SHIFT 0 +#define TPC0_CFG_SFLAGS_V_MASK 0xF + +/* TPC0_CFG_LFSR_POLYNOM */ +#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_STATUS */ +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_SHIFT 4 +#define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK 0x10 + +/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SM_BASE_ADDRESS_LOW */ +#define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TPC_CMD */ +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* TPC0_CFG_TPC_EXECUTE */ +#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* TPC0_CFG_TPC_STALL */ +#define TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_MSS_CONFIG */ +#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 + +/* TPC0_CFG_TPC_INTR_CAUSE */ +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF + +/* TPC0_CFG_TPC_INTR_MASK */ +#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF + +/* TPC0_CFG_TSB_CONFIG */ +#define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_SHIFT 0 +#define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_MASK 0x1F +#define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_SHIFT 5 +#define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_MASK 0x3E0 +#define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_SHIFT 10 +#define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_MASK 0xFFC00 +#define TPC0_CFG_TSB_CONFIG_MAX_SIZE_SHIFT 20 +#define TPC0_CFG_TSB_CONFIG_MAX_SIZE_MASK 0x3FF00000 + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_0 */ +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_0 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_1 */ +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_1 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_2 */ +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_2 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_3 */ +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_3 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_4 */ +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_4 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_SRF */ +#define TPC0_CFG_QM_SRF_V_SHIFT 0 +#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_CONFIG */ +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 8 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0x3F00 + +/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* TPC0_CFG_ARUSER */ +#define TPC0_CFG_ARUSER_ASID_SHIFT 0 +#define TPC0_CFG_ARUSER_ASID_MASK 0x3FF +#define TPC0_CFG_ARUSER_MMBP_SHIFT 10 +#define TPC0_CFG_ARUSER_MMBP_MASK 0x400 +#define TPC0_CFG_ARUSER_V_SHIFT 11 +#define TPC0_CFG_ARUSER_V_MASK 0xFFFFF800 + +/* TPC0_CFG_AWUSER */ +#define TPC0_CFG_AWUSER_ASID_SHIFT 0 +#define TPC0_CFG_AWUSER_ASID_MASK 0x3FF +#define TPC0_CFG_AWUSER_MMBP_SHIFT 10 +#define TPC0_CFG_AWUSER_MMBP_MASK 0x400 +#define TPC0_CFG_AWUSER_V_SHIFT 11 +#define TPC0_CFG_AWUSER_V_MASK 0xFFFFF800 + +/* TPC0_CFG_FUNC_MBIST_CNTRL */ +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x4 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF0000 + +/* TPC0_CFG_FUNC_MBIST_PAT */ +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x3 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 4 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x30 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 6 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 8 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x300 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 10 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC00 + +/* TPC0_CFG_FUNC_MBIST_MEM */ +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 12 +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x7000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF0000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 28 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x70000000 + +#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h new file mode 100644 index 000000000000..2be28a63c50a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_REGS_H_ +#define ASIC_REG_TPC0_CFG_REGS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE06418 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE0641C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE06420 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE06424 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06428 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE0642C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE06430 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06434 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE06438 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE0643C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06440 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06444 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE06448 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE0644C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE06450 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06454 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06458 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE0645C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE06460 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE06464 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06468 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE0646C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE06470 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06474 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE06478 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE0647C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06480 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06484 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE06488 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE0648C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE06490 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE06494 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06498 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE0649C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE064A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE064A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE064A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE064AC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE064B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE064B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE064B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE064BC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE064C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE064C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE064C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE064CC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE064D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE064D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064DC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE064E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064EC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE064FC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE06500 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE06504 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE06508 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE0650C + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE06510 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE06514 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE06518 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE0651C + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE06520 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE06524 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE06528 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE0652C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE06530 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE06534 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE06538 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE0653C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE06540 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE06544 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE06548 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE0654C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE06550 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE06554 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06558 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE0655C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE06560 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06564 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE06568 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE0656C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06570 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06574 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE06578 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE0657C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE06580 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06584 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06588 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE0658C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE06590 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE06594 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06598 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE0659C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE065A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE065A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE065A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE065AC + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE065B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE065B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE065B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE065BC + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE065C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE065C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE065C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE065CC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE065D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE065D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE065D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE065DC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE065E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE065E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE065E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE065EC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE065F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE065F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE065F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE065FC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE06600 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE06604 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06608 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE0660C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE06610 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06614 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE06618 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE0661C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06620 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06624 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE06628 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE0662C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE06630 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE06634 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE06638 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE0663C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE06640 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE06644 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE06648 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE0664C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE06650 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE06654 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE06658 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE0665C + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06660 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE06664 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06668 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE0666C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06670 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE06674 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE06678 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE0667C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE06680 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE06684 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE06688 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE0668C + +#define mmTPC0_CFG_KERNEL_SRF_0 0xE06690 + +#define mmTPC0_CFG_KERNEL_SRF_1 0xE06694 + +#define mmTPC0_CFG_KERNEL_SRF_2 0xE06698 + +#define mmTPC0_CFG_KERNEL_SRF_3 0xE0669C + +#define mmTPC0_CFG_KERNEL_SRF_4 0xE066A0 + +#define mmTPC0_CFG_KERNEL_SRF_5 0xE066A4 + +#define mmTPC0_CFG_KERNEL_SRF_6 0xE066A8 + +#define mmTPC0_CFG_KERNEL_SRF_7 0xE066AC + +#define mmTPC0_CFG_KERNEL_SRF_8 0xE066B0 + +#define mmTPC0_CFG_KERNEL_SRF_9 0xE066B4 + +#define mmTPC0_CFG_KERNEL_SRF_10 0xE066B8 + +#define mmTPC0_CFG_KERNEL_SRF_11 0xE066BC + +#define mmTPC0_CFG_KERNEL_SRF_12 0xE066C0 + +#define mmTPC0_CFG_KERNEL_SRF_13 0xE066C4 + +#define mmTPC0_CFG_KERNEL_SRF_14 0xE066C8 + +#define mmTPC0_CFG_KERNEL_SRF_15 0xE066CC + +#define mmTPC0_CFG_KERNEL_SRF_16 0xE066D0 + +#define mmTPC0_CFG_KERNEL_SRF_17 0xE066D4 + +#define mmTPC0_CFG_KERNEL_SRF_18 0xE066D8 + +#define mmTPC0_CFG_KERNEL_SRF_19 0xE066DC + +#define mmTPC0_CFG_KERNEL_SRF_20 0xE066E0 + +#define mmTPC0_CFG_KERNEL_SRF_21 0xE066E4 + +#define mmTPC0_CFG_KERNEL_SRF_22 0xE066E8 + +#define mmTPC0_CFG_KERNEL_SRF_23 0xE066EC + +#define mmTPC0_CFG_KERNEL_SRF_24 0xE066F0 + +#define mmTPC0_CFG_KERNEL_SRF_25 0xE066F4 + +#define mmTPC0_CFG_KERNEL_SRF_26 0xE066F8 + +#define mmTPC0_CFG_KERNEL_SRF_27 0xE066FC + +#define mmTPC0_CFG_KERNEL_SRF_28 0xE06700 + +#define mmTPC0_CFG_KERNEL_SRF_29 0xE06704 + +#define mmTPC0_CFG_KERNEL_SRF_30 0xE06708 + +#define mmTPC0_CFG_KERNEL_SRF_31 0xE0670C + +#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE06710 + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06714 + +#define mmTPC0_CFG_RESERVED_DESC_END 0xE06738 + +#define mmTPC0_CFG_ROUND_CSR 0xE067FC + +#define mmTPC0_CFG_TBUF_BASE_ADDR_LOW 0xE06800 + +#define mmTPC0_CFG_TBUF_BASE_ADDR_HIGH 0xE06804 + +#define mmTPC0_CFG_SEMAPHORE 0xE06808 + +#define mmTPC0_CFG_VFLAGS 0xE0680C + +#define mmTPC0_CFG_SFLAGS 0xE06810 + +#define mmTPC0_CFG_LFSR_POLYNOM 0xE06818 + +#define mmTPC0_CFG_STATUS 0xE0681C + +#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06820 + +#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06824 + +#define mmTPC0_CFG_SM_BASE_ADDRESS_LOW 0xE06828 + +#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0682C + +#define mmTPC0_CFG_TPC_CMD 0xE06830 + +#define mmTPC0_CFG_TPC_EXECUTE 0xE06838 + +#define mmTPC0_CFG_TPC_STALL 0xE0683C + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06840 + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06844 + +#define mmTPC0_CFG_MSS_CONFIG 0xE06854 + +#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06858 + +#define mmTPC0_CFG_TPC_INTR_MASK 0xE0685C + +#define mmTPC0_CFG_TSB_CONFIG 0xE06860 + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00 + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04 + +#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08 + +#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE06A18 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A1C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A20 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE06A24 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A28 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A2C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE06A30 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A34 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A38 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE06A3C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A40 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A44 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE06A48 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A4C + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A50 + +#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A54 + +#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A58 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A5C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A60 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE06A64 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A68 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A6C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE06A70 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A74 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A78 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE06A7C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A80 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A84 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE06A88 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A8C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A90 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE06A94 + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A98 + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A9C + +#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06AA0 + +#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06AA4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06AA8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06AAC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE06AB0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06AB4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06AB8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE06ABC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06AC0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06AC4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE06AC8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06ACC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06AD0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE06AD4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AD8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06ADC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE06AE0 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AE4 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AE8 + +#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AEC + +#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AF0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AF4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06AF8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE06AFC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06B00 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06B04 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE06B08 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06B0C + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06B10 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE06B14 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06B18 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06B1C + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE06B20 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06B24 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06B28 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE06B2C + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06B30 + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06B34 + +#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06B38 + +#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06B3C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06B40 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06B44 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE06B48 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06B4C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06B50 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE06B54 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B58 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B5C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE06B60 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B64 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B68 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE06B6C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B70 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B74 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE06B78 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B7C + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B80 + +#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B84 + +#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B88 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B8C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B90 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE06B94 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B98 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B9C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE06BA0 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06BA4 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06BA8 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE06BAC + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06BB0 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06BB4 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE06BB8 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06BBC + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06BC0 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE06BC4 + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06BC8 + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06BCC + +#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06BD0 + +#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06BD4 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06BD8 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06BDC + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE06BE0 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06BE4 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06BE8 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE06BEC + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06BF0 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06BF4 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE06BF8 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06BFC + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06C00 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE06C04 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06C08 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06C0C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE06C10 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06C14 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06C18 + +#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06C1C + +#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06C20 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06C24 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06C28 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE06C2C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06C30 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06C34 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE06C38 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06C3C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06C40 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE06C44 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06C48 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06C4C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE06C50 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06C54 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06C58 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE06C5C + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06C60 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06C64 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06C68 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06C6C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06C70 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06C74 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06C78 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06C7C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06C80 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06C84 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06C88 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06C8C + +#define mmTPC0_CFG_QM_SRF_0 0xE06C90 + +#define mmTPC0_CFG_QM_SRF_1 0xE06C94 + +#define mmTPC0_CFG_QM_SRF_2 0xE06C98 + +#define mmTPC0_CFG_QM_SRF_3 0xE06C9C + +#define mmTPC0_CFG_QM_SRF_4 0xE06CA0 + +#define mmTPC0_CFG_QM_SRF_5 0xE06CA4 + +#define mmTPC0_CFG_QM_SRF_6 0xE06CA8 + +#define mmTPC0_CFG_QM_SRF_7 0xE06CAC + +#define mmTPC0_CFG_QM_SRF_8 0xE06CB0 + +#define mmTPC0_CFG_QM_SRF_9 0xE06CB4 + +#define mmTPC0_CFG_QM_SRF_10 0xE06CB8 + +#define mmTPC0_CFG_QM_SRF_11 0xE06CBC + +#define mmTPC0_CFG_QM_SRF_12 0xE06CC0 + +#define mmTPC0_CFG_QM_SRF_13 0xE06CC4 + +#define mmTPC0_CFG_QM_SRF_14 0xE06CC8 + +#define mmTPC0_CFG_QM_SRF_15 0xE06CCC + +#define mmTPC0_CFG_QM_SRF_16 0xE06CD0 + +#define mmTPC0_CFG_QM_SRF_17 0xE06CD4 + +#define mmTPC0_CFG_QM_SRF_18 0xE06CD8 + +#define mmTPC0_CFG_QM_SRF_19 0xE06CDC + +#define mmTPC0_CFG_QM_SRF_20 0xE06CE0 + +#define mmTPC0_CFG_QM_SRF_21 0xE06CE4 + +#define mmTPC0_CFG_QM_SRF_22 0xE06CE8 + +#define mmTPC0_CFG_QM_SRF_23 0xE06CEC + +#define mmTPC0_CFG_QM_SRF_24 0xE06CF0 + +#define mmTPC0_CFG_QM_SRF_25 0xE06CF4 + +#define mmTPC0_CFG_QM_SRF_26 0xE06CF8 + +#define mmTPC0_CFG_QM_SRF_27 0xE06CFC + +#define mmTPC0_CFG_QM_SRF_28 0xE06D00 + +#define mmTPC0_CFG_QM_SRF_29 0xE06D04 + +#define mmTPC0_CFG_QM_SRF_30 0xE06D08 + +#define mmTPC0_CFG_QM_SRF_31 0xE06D0C + +#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06D10 + +#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D14 + +#define mmTPC0_CFG_ARUSER 0xE06D18 + +#define mmTPC0_CFG_AWUSER 0xE06D1C + +#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE06E00 + +#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE06E04 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE06E08 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE06E0C + +#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE06E10 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE06E14 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE06E18 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE06E1C + +#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE06E20 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE06E24 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE06E28 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE06E2C + +#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h new file mode 100644 index 000000000000..9aa2d8b53207 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CMDQ_MASKS_H_ +#define ASIC_REG_TPC0_CMDQ_MASKS_H_ + +/* + ***************************************** + * TPC0_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +/* TPC0_CMDQ_GLBL_CFG0 */ +#define TPC0_CMDQ_GLBL_CFG0_PQF_EN_SHIFT 0 +#define TPC0_CMDQ_GLBL_CFG0_PQF_EN_MASK 0x1 +#define TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT 1 +#define TPC0_CMDQ_GLBL_CFG0_CQF_EN_MASK 0x2 +#define TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT 2 +#define TPC0_CMDQ_GLBL_CFG0_CP_EN_MASK 0x4 +#define TPC0_CMDQ_GLBL_CFG0_DMA_EN_SHIFT 3 +#define TPC0_CMDQ_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* TPC0_CMDQ_GLBL_CFG1 */ +#define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT 2 +#define TPC0_CMDQ_GLBL_CFG1_CP_STOP_MASK 0x4 +#define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* TPC0_CMDQ_GLBL_PROT */ +#define TPC0_CMDQ_GLBL_PROT_PQF_PROT_SHIFT 0 +#define TPC0_CMDQ_GLBL_PROT_PQF_PROT_MASK 0x1 +#define TPC0_CMDQ_GLBL_PROT_CQF_PROT_SHIFT 1 +#define TPC0_CMDQ_GLBL_PROT_CQF_PROT_MASK 0x2 +#define TPC0_CMDQ_GLBL_PROT_CP_PROT_SHIFT 2 +#define TPC0_CMDQ_GLBL_PROT_CP_PROT_MASK 0x4 +#define TPC0_CMDQ_GLBL_PROT_DMA_PROT_SHIFT 3 +#define TPC0_CMDQ_GLBL_PROT_DMA_PROT_MASK 0x8 +#define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* TPC0_CMDQ_GLBL_ERR_CFG */ +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* TPC0_CMDQ_GLBL_ERR_ADDR_LO */ +#define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_GLBL_ERR_ADDR_HI */ +#define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_GLBL_ERR_WDATA */ +#define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_GLBL_SECURE_PROPS */ +#define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_CMDQ_GLBL_NON_SECURE_PROPS */ +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_CMDQ_GLBL_STS0 */ +#define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define TPC0_CMDQ_GLBL_STS0_CP_IDLE_SHIFT 2 +#define TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK 0x4 +#define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* TPC0_CMDQ_GLBL_STS1 */ +#define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* TPC0_CMDQ_CQ_CFG0 */ +#define TPC0_CMDQ_CQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_CMDQ_CQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_CMDQ_CQ_CFG1 */ +#define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_ARUSER */ +#define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define TPC0_CMDQ_CQ_ARUSER_WORD_SHIFT 1 +#define TPC0_CMDQ_CQ_ARUSER_WORD_MASK 0x2 + +/* TPC0_CMDQ_CQ_PTR_LO */ +#define TPC0_CMDQ_CQ_PTR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_PTR_HI */ +#define TPC0_CMDQ_CQ_PTR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_TSIZE */ +#define TPC0_CMDQ_CQ_TSIZE_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_CTL */ +#define TPC0_CMDQ_CQ_CTL_RPT_SHIFT 0 +#define TPC0_CMDQ_CQ_CTL_RPT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_CTL_CTL_SHIFT 16 +#define TPC0_CMDQ_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_PTR_LO_STS */ +#define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_PTR_HI_STS */ +#define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_TSIZE_STS */ +#define TPC0_CMDQ_CQ_TSIZE_STS_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_CTL_STS */ +#define TPC0_CMDQ_CQ_CTL_STS_RPT_SHIFT 0 +#define TPC0_CMDQ_CQ_CTL_STS_RPT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_CTL_STS_CTL_SHIFT 16 +#define TPC0_CMDQ_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_STS0 */ +#define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_STS1 */ +#define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_CMDQ_CQ_STS1_CQ_BUSY_SHIFT 31 +#define TPC0_CMDQ_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_EN */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_SAT */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* TPC0_CMDQ_CQ_IFIFO_CNT */ +#define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_FENCE0_RDATA */ +#define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE1_RDATA */ +#define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE2_RDATA */ +#define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE3_RDATA */ +#define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE0_CNT */ +#define TPC0_CMDQ_CP_FENCE0_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_FENCE1_CNT */ +#define TPC0_CMDQ_CP_FENCE1_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_FENCE2_CNT */ +#define TPC0_CMDQ_CP_FENCE2_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_FENCE3_CNT */ +#define TPC0_CMDQ_CP_FENCE3_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_STS */ +#define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_CMDQ_CP_STS_ERDY_SHIFT 16 +#define TPC0_CMDQ_CP_STS_ERDY_MASK 0x10000 +#define TPC0_CMDQ_CP_STS_RRDY_SHIFT 17 +#define TPC0_CMDQ_CP_STS_RRDY_MASK 0x20000 +#define TPC0_CMDQ_CP_STS_MRDY_SHIFT 18 +#define TPC0_CMDQ_CP_STS_MRDY_MASK 0x40000 +#define TPC0_CMDQ_CP_STS_SW_STOP_SHIFT 19 +#define TPC0_CMDQ_CP_STS_SW_STOP_MASK 0x80000 +#define TPC0_CMDQ_CP_STS_FENCE_ID_SHIFT 20 +#define TPC0_CMDQ_CP_STS_FENCE_ID_MASK 0x300000 +#define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* TPC0_CMDQ_CP_CURRENT_INST_LO */ +#define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_CURRENT_INST_HI */ +#define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_BARRIER_CFG */ +#define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* TPC0_CMDQ_CP_DBG_0 */ +#define TPC0_CMDQ_CP_DBG_0_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_DBG_0_VAL_MASK 0xFF + +/* TPC0_CMDQ_CQ_BUF_ADDR */ +#define TPC0_CMDQ_CQ_BUF_ADDR_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_BUF_RDATA */ +#define TPC0_CMDQ_CQ_BUF_RDATA_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_TPC0_CMDQ_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h new file mode 100644 index 000000000000..3572752ba66e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CMDQ_REGS_H_ +#define ASIC_REG_TPC0_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC0_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC0_CMDQ_GLBL_CFG0 0xE09000 + +#define mmTPC0_CMDQ_GLBL_CFG1 0xE09004 + +#define mmTPC0_CMDQ_GLBL_PROT 0xE09008 + +#define mmTPC0_CMDQ_GLBL_ERR_CFG 0xE0900C + +#define mmTPC0_CMDQ_GLBL_ERR_ADDR_LO 0xE09010 + +#define mmTPC0_CMDQ_GLBL_ERR_ADDR_HI 0xE09014 + +#define mmTPC0_CMDQ_GLBL_ERR_WDATA 0xE09018 + +#define mmTPC0_CMDQ_GLBL_SECURE_PROPS 0xE0901C + +#define mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS 0xE09020 + +#define mmTPC0_CMDQ_GLBL_STS0 0xE09024 + +#define mmTPC0_CMDQ_GLBL_STS1 0xE09028 + +#define mmTPC0_CMDQ_CQ_CFG0 0xE090B0 + +#define mmTPC0_CMDQ_CQ_CFG1 0xE090B4 + +#define mmTPC0_CMDQ_CQ_ARUSER 0xE090B8 + +#define mmTPC0_CMDQ_CQ_PTR_LO 0xE090C0 + +#define mmTPC0_CMDQ_CQ_PTR_HI 0xE090C4 + +#define mmTPC0_CMDQ_CQ_TSIZE 0xE090C8 + +#define mmTPC0_CMDQ_CQ_CTL 0xE090CC + +#define mmTPC0_CMDQ_CQ_PTR_LO_STS 0xE090D4 + +#define mmTPC0_CMDQ_CQ_PTR_HI_STS 0xE090D8 + +#define mmTPC0_CMDQ_CQ_TSIZE_STS 0xE090DC + +#define mmTPC0_CMDQ_CQ_CTL_STS 0xE090E0 + +#define mmTPC0_CMDQ_CQ_STS0 0xE090E4 + +#define mmTPC0_CMDQ_CQ_STS1 0xE090E8 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN 0xE090F0 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE090F4 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT 0xE090F8 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE090FC + +#define mmTPC0_CMDQ_CQ_IFIFO_CNT 0xE09108 + +#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE09120 + +#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE09124 + +#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE09128 + +#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE0912C + +#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE09130 + +#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE09134 + +#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE09138 + +#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE0913C + +#define mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE09140 + +#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE09144 + +#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE09148 + +#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE0914C + +#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE09150 + +#define mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE09154 + +#define mmTPC0_CMDQ_CP_FENCE0_RDATA 0xE09158 + +#define mmTPC0_CMDQ_CP_FENCE1_RDATA 0xE0915C + +#define mmTPC0_CMDQ_CP_FENCE2_RDATA 0xE09160 + +#define mmTPC0_CMDQ_CP_FENCE3_RDATA 0xE09164 + +#define mmTPC0_CMDQ_CP_FENCE0_CNT 0xE09168 + +#define mmTPC0_CMDQ_CP_FENCE1_CNT 0xE0916C + +#define mmTPC0_CMDQ_CP_FENCE2_CNT 0xE09170 + +#define mmTPC0_CMDQ_CP_FENCE3_CNT 0xE09174 + +#define mmTPC0_CMDQ_CP_STS 0xE09178 + +#define mmTPC0_CMDQ_CP_CURRENT_INST_LO 0xE0917C + +#define mmTPC0_CMDQ_CP_CURRENT_INST_HI 0xE09180 + +#define mmTPC0_CMDQ_CP_BARRIER_CFG 0xE09184 + +#define mmTPC0_CMDQ_CP_DBG_0 0xE09188 + +#define mmTPC0_CMDQ_CQ_BUF_ADDR 0xE09308 + +#define mmTPC0_CMDQ_CQ_BUF_RDATA 0xE0930C + +#endif /* ASIC_REG_TPC0_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h new file mode 100644 index 000000000000..ed866d93c440 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h @@ -0,0 +1,347 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_EML_CFG_MASKS_H_ +#define ASIC_REG_TPC0_EML_CFG_MASKS_H_ + +/* + ***************************************** + * TPC0_EML_CFG (Prototype: TPC_EML_CFG) + ***************************************** + */ + +/* TPC0_EML_CFG_DBG_CNT */ +#define TPC0_EML_CFG_DBG_CNT_DBG_ENTER_SHIFT 0 +#define TPC0_EML_CFG_DBG_CNT_DBG_ENTER_MASK 0x1 +#define TPC0_EML_CFG_DBG_CNT_DBG_EN_SHIFT 1 +#define TPC0_EML_CFG_DBG_CNT_DBG_EN_MASK 0x2 +#define TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT 2 +#define TPC0_EML_CFG_DBG_CNT_CORE_RST_MASK 0x4 +#define TPC0_EML_CFG_DBG_CNT_DCACHE_INV_SHIFT 4 +#define TPC0_EML_CFG_DBG_CNT_DCACHE_INV_MASK 0x10 +#define TPC0_EML_CFG_DBG_CNT_ICACHE_INV_SHIFT 5 +#define TPC0_EML_CFG_DBG_CNT_ICACHE_INV_MASK 0x20 +#define TPC0_EML_CFG_DBG_CNT_DBG_EXIT_SHIFT 6 +#define TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40 +#define TPC0_EML_CFG_DBG_CNT_SNG_STEP_SHIFT 7 +#define TPC0_EML_CFG_DBG_CNT_SNG_STEP_MASK 0x80 +#define TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_SHIFT 16 +#define TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_MASK 0x10000 + +/* TPC0_EML_CFG_DBG_STS */ +#define TPC0_EML_CFG_DBG_STS_DBG_MODE_SHIFT 0 +#define TPC0_EML_CFG_DBG_STS_DBG_MODE_MASK 0x1 +#define TPC0_EML_CFG_DBG_STS_CORE_READY_SHIFT 1 +#define TPC0_EML_CFG_DBG_STS_CORE_READY_MASK 0x2 +#define TPC0_EML_CFG_DBG_STS_DURING_KERNEL_SHIFT 2 +#define TPC0_EML_CFG_DBG_STS_DURING_KERNEL_MASK 0x4 +#define TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_SHIFT 3 +#define TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_MASK 0x8 +#define TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_SHIFT 4 +#define TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_MASK 0x10 +#define TPC0_EML_CFG_DBG_STS_QM_IDLE_SHIFT 5 +#define TPC0_EML_CFG_DBG_STS_QM_IDLE_MASK 0x20 +#define TPC0_EML_CFG_DBG_STS_WQ_IDLE_SHIFT 6 +#define TPC0_EML_CFG_DBG_STS_WQ_IDLE_MASK 0x40 +#define TPC0_EML_CFG_DBG_STS_MSS_IDLE_SHIFT 7 +#define TPC0_EML_CFG_DBG_STS_MSS_IDLE_MASK 0x80 +#define TPC0_EML_CFG_DBG_STS_DBG_CAUSE_SHIFT 8 +#define TPC0_EML_CFG_DBG_STS_DBG_CAUSE_MASK 0xFFFFFF00 + +/* TPC0_EML_CFG_DBG_PADD */ +#define TPC0_EML_CFG_DBG_PADD_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_PADD_COUNT */ +#define TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_PADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_PADD_EN */ +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_SHIFT 2 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_MASK 0x4 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_SHIFT 3 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_MASK 0x8 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_SHIFT 4 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_MASK 0x10 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_SHIFT 5 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_MASK 0x20 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_SHIFT 6 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_MASK 0x40 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_SHIFT 7 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_MASK 0x80 + +/* TPC0_EML_CFG_DBG_VPADD_HIGH */ +#define TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_MASK 0x1FF + +/* TPC0_EML_CFG_DBG_VPADD_LOW */ +#define TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_MASK 0x1FF + +/* TPC0_EML_CFG_DBG_VPADD_COUNT */ +#define TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_VPADD_EN */ +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_SPADD_HIGH */ +#define TPC0_EML_CFG_DBG_SPADD_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_HIGH_ADDRESS_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_LOW */ +#define TPC0_EML_CFG_DBG_SPADD_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_LOW_ADDRESS_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_COUNT */ +#define TPC0_EML_CFG_DBG_SPADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_EN */ +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH */ +#define TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_MSB_LOW */ +#define TPC0_EML_CFG_DBG_AGUADD_MSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_MSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH */ +#define TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_LSB_LOW */ +#define TPC0_EML_CFG_DBG_AGUADD_LSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_LSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_COUNT */ +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AGUADD_EN */ +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_COUNT */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_EN */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW */ +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW */ +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_COUNT */ +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_EN */ +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_SPDATA */ +#define TPC0_EML_CFG_DBG_SPDATA_DATA_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_DATA_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_SPDATA_COUNT */ +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPDATA_EN */ +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AXIHBWDATA */ +#define TPC0_EML_CFG_DBG_AXIHBWDATA_DATA_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_DATA_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT */ +#define TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWDATA_EN */ +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_ENABLE_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_ENABLE_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_RW_N_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_RW_N_MASK 0x2 + +/* TPC0_EML_CFG_DBG_AXILBWDATA */ +#define TPC0_EML_CFG_DBG_AXILBWDATA_DATA_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDATA_DATA_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWDATA_COUNT */ +#define TPC0_EML_CFG_DBG_AXILBWDATA_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDATA_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWDATA_EN */ +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_ENABLE_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_ENABLE_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_RW_N_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_RW_N_MASK 0x2 + +/* TPC0_EML_CFG_DBG_D0_PC */ +#define TPC0_EML_CFG_DBG_D0_PC_PC_SHIFT 0 +#define TPC0_EML_CFG_DBG_D0_PC_PC_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_RTTCONFIG */ +#define TPC0_EML_CFG_RTTCONFIG_TR_EN_SHIFT 0 +#define TPC0_EML_CFG_RTTCONFIG_TR_EN_MASK 0x1 +#define TPC0_EML_CFG_RTTCONFIG_PRIO_SHIFT 1 +#define TPC0_EML_CFG_RTTCONFIG_PRIO_MASK 0x2 + +/* TPC0_EML_CFG_RTTPREDICATE */ +#define TPC0_EML_CFG_RTTPREDICATE_TR_EN_SHIFT 0 +#define TPC0_EML_CFG_RTTPREDICATE_TR_EN_MASK 0x1 +#define TPC0_EML_CFG_RTTPREDICATE_GEN_SHIFT 1 +#define TPC0_EML_CFG_RTTPREDICATE_GEN_MASK 0x2 +#define TPC0_EML_CFG_RTTPREDICATE_USE_INTERVAL_SHIFT 2 +#define TPC0_EML_CFG_RTTPREDICATE_USE_INTERVAL_MASK 0x4 +#define TPC0_EML_CFG_RTTPREDICATE_SPRF_MASK_SHIFT 16 +#define TPC0_EML_CFG_RTTPREDICATE_SPRF_MASK_MASK 0xFFFF0000 + +/* TPC0_EML_CFG_RTTPREDICATE_INTV */ +#define TPC0_EML_CFG_RTTPREDICATE_INTV_INTERVAL_SHIFT 0 +#define TPC0_EML_CFG_RTTPREDICATE_INTV_INTERVAL_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_RTTTS */ +#define TPC0_EML_CFG_RTTTS_TR_EN_SHIFT 0 +#define TPC0_EML_CFG_RTTTS_TR_EN_MASK 0x1 +#define TPC0_EML_CFG_RTTTS_GEN_SHIFT 1 +#define TPC0_EML_CFG_RTTTS_GEN_MASK 0x2 +#define TPC0_EML_CFG_RTTTS_COMPRESS_EN_SHIFT 2 +#define TPC0_EML_CFG_RTTTS_COMPRESS_EN_MASK 0x4 + +/* TPC0_EML_CFG_RTTTS_INTV */ +#define TPC0_EML_CFG_RTTTS_INTV_INTERVAL_SHIFT 0 +#define TPC0_EML_CFG_RTTTS_INTV_INTERVAL_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_INST_INSERT */ +#define TPC0_EML_CFG_DBG_INST_INSERT_INST_SHIFT 0 +#define TPC0_EML_CFG_DBG_INST_INSERT_INST_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_INST_INSERT_CTL */ +#define TPC0_EML_CFG_DBG_INST_INSERT_CTL_INSERT_SHIFT 0 +#define TPC0_EML_CFG_DBG_INST_INSERT_CTL_INSERT_MASK 0x1 + +#endif /* ASIC_REG_TPC0_EML_CFG_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h new file mode 100644 index 000000000000..f1a1b4fa4841 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_EML_CFG_REGS_H_ +#define ASIC_REG_TPC0_EML_CFG_REGS_H_ + +/* + ***************************************** + * TPC0_EML_CFG (Prototype: TPC_EML_CFG) + ***************************************** + */ + +#define mmTPC0_EML_CFG_DBG_CNT 0x3040000 + +#define mmTPC0_EML_CFG_DBG_STS 0x3040004 + +#define mmTPC0_EML_CFG_DBG_PADD_0 0x3040008 + +#define mmTPC0_EML_CFG_DBG_PADD_1 0x304000C + +#define mmTPC0_EML_CFG_DBG_PADD_2 0x3040010 + +#define mmTPC0_EML_CFG_DBG_PADD_3 0x3040014 + +#define mmTPC0_EML_CFG_DBG_PADD_4 0x3040018 + +#define mmTPC0_EML_CFG_DBG_PADD_5 0x304001C + +#define mmTPC0_EML_CFG_DBG_PADD_6 0x3040020 + +#define mmTPC0_EML_CFG_DBG_PADD_7 0x3040024 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_0 0x3040028 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_1 0x304002C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_2 0x3040030 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_3 0x3040034 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_4 0x3040038 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_5 0x304003C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_6 0x3040040 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_7 0x3040044 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_0 0x3040048 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_1 0x304004C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_2 0x3040050 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_3 0x3040054 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_4 0x3040058 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_5 0x304005C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_6 0x3040060 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_7 0x3040064 + +#define mmTPC0_EML_CFG_DBG_PADD_EN 0x3040068 + +#define mmTPC0_EML_CFG_DBG_VPADD_HIGH_0 0x304006C + +#define mmTPC0_EML_CFG_DBG_VPADD_HIGH_1 0x3040070 + +#define mmTPC0_EML_CFG_DBG_VPADD_LOW_0 0x3040074 + +#define mmTPC0_EML_CFG_DBG_VPADD_LOW_1 0x3040078 + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_0 0x304007C + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_1 0x3040080 + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_0 0x3040084 + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_1 0x3040088 + +#define mmTPC0_EML_CFG_DBG_VPADD_EN 0x304008C + +#define mmTPC0_EML_CFG_DBG_SPADD_HIGH_0 0x3040090 + +#define mmTPC0_EML_CFG_DBG_SPADD_HIGH_1 0x3040094 + +#define mmTPC0_EML_CFG_DBG_SPADD_LOW_0 0x3040098 + +#define mmTPC0_EML_CFG_DBG_SPADD_LOW_1 0x304009C + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_0 0x30400A0 + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_1 0x30400A4 + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_0 0x30400A8 + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_1 0x30400AC + +#define mmTPC0_EML_CFG_DBG_SPADD_EN 0x30400B0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_0 0x30400B4 + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_1 0x30400B8 + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_0 0x30400BC + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_1 0x30400C0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_0 0x30400C4 + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_1 0x30400C8 + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_0 0x30400CC + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_1 0x30400D0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_0 0x30400D4 + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_1 0x30400D8 + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_0 0x30400DC + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_1 0x30400E0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_EN 0x30400E4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_0 0x30400E8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_1 0x30400EC + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_0 0x30400F0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_1 0x30400F4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_0 0x30400F8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_1 0x30400FC + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_0 0x3040100 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_1 0x3040104 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_0 0x3040108 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_1 0x304010C + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_0 0x3040110 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_1 0x3040114 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_EN 0x3040118 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_0 0x304011C + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_1 0x3040120 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_0 0x3040124 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_1 0x3040128 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_0 0x304012C + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_1 0x3040130 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_0 0x3040134 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_1 0x3040138 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_0 0x304013C + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_1 0x3040140 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_0 0x3040144 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_1 0x3040148 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_EN 0x304014C + +#define mmTPC0_EML_CFG_DBG_SPDATA_0 0x3040150 + +#define mmTPC0_EML_CFG_DBG_SPDATA_1 0x3040154 + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_0 0x3040158 + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_1 0x304015C + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_0 0x3040160 + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_1 0x3040164 + +#define mmTPC0_EML_CFG_DBG_SPDATA_EN 0x3040168 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_0 0x304016C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_1 0x3040170 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_2 0x3040174 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_3 0x3040178 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_4 0x304017C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_5 0x3040180 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_6 0x3040184 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_7 0x3040188 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_8 0x304018C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_9 0x3040190 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_10 0x3040194 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_11 0x3040198 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_12 0x304019C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_13 0x30401A0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_14 0x30401A4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_15 0x30401A8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_16 0x30401AC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_17 0x30401B0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_18 0x30401B4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_19 0x30401B8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_20 0x30401BC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_21 0x30401C0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_22 0x30401C4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_23 0x30401C8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_24 0x30401CC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_25 0x30401D0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_26 0x30401D4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_27 0x30401D8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_28 0x30401DC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_29 0x30401E0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_30 0x30401E4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_31 0x30401E8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_COUNT 0x30401EC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH 0x30401F0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_EN 0x30401F4 + +#define mmTPC0_EML_CFG_DBG_AXILBWDATA 0x30401F8 + +#define mmTPC0_EML_CFG_DBG_AXILBWDATA_COUNT 0x30401FC + +#define mmTPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH 0x3040200 + +#define mmTPC0_EML_CFG_DBG_AXILBWDATA_EN 0x3040204 + +#define mmTPC0_EML_CFG_DBG_D0_PC 0x3040208 + +#define mmTPC0_EML_CFG_RTTCONFIG 0x3040300 + +#define mmTPC0_EML_CFG_RTTPREDICATE 0x3040304 + +#define mmTPC0_EML_CFG_RTTPREDICATE_INTV 0x3040308 + +#define mmTPC0_EML_CFG_RTTTS 0x304030C + +#define mmTPC0_EML_CFG_RTTTS_INTV 0x3040310 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_0 0x3040314 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_1 0x3040318 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_2 0x304031C + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_3 0x3040320 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_4 0x3040324 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_5 0x3040328 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_6 0x304032C + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_7 0x3040330 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_CTL 0x3040334 + +#endif /* ASIC_REG_TPC0_EML_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h new file mode 100644 index 000000000000..7f86621179a5 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_NRTR_MASKS_H_ +#define ASIC_REG_TPC0_NRTR_MASKS_H_ + +/* + ***************************************** + * TPC0_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +/* TPC0_NRTR_HBW_MAX_CRED */ +#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 +#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F +#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8 +#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* TPC0_NRTR_LBW_MAX_CRED */ +#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 +#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F +#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8 +#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* TPC0_NRTR_DBG_E_ARB */ +#define TPC0_NRTR_DBG_E_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_E_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_E_ARB_S_SHIFT 8 +#define TPC0_NRTR_DBG_E_ARB_S_MASK 0x700 +#define TPC0_NRTR_DBG_E_ARB_N_SHIFT 16 +#define TPC0_NRTR_DBG_E_ARB_N_MASK 0x70000 +#define TPC0_NRTR_DBG_E_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_E_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_W_ARB */ +#define TPC0_NRTR_DBG_W_ARB_E_SHIFT 0 +#define TPC0_NRTR_DBG_W_ARB_E_MASK 0x7 +#define TPC0_NRTR_DBG_W_ARB_S_SHIFT 8 +#define TPC0_NRTR_DBG_W_ARB_S_MASK 0x700 +#define TPC0_NRTR_DBG_W_ARB_N_SHIFT 16 +#define TPC0_NRTR_DBG_W_ARB_N_MASK 0x70000 +#define TPC0_NRTR_DBG_W_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_W_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_N_ARB */ +#define TPC0_NRTR_DBG_N_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_N_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_N_ARB_E_SHIFT 8 +#define TPC0_NRTR_DBG_N_ARB_E_MASK 0x700 +#define TPC0_NRTR_DBG_N_ARB_S_SHIFT 16 +#define TPC0_NRTR_DBG_N_ARB_S_MASK 0x70000 +#define TPC0_NRTR_DBG_N_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_N_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_S_ARB */ +#define TPC0_NRTR_DBG_S_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_S_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_S_ARB_E_SHIFT 8 +#define TPC0_NRTR_DBG_S_ARB_E_MASK 0x700 +#define TPC0_NRTR_DBG_S_ARB_N_SHIFT 16 +#define TPC0_NRTR_DBG_S_ARB_N_MASK 0x70000 +#define TPC0_NRTR_DBG_S_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_S_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_L_ARB */ +#define TPC0_NRTR_DBG_L_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_L_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_L_ARB_E_SHIFT 8 +#define TPC0_NRTR_DBG_L_ARB_E_MASK 0x700 +#define TPC0_NRTR_DBG_L_ARB_S_SHIFT 16 +#define TPC0_NRTR_DBG_L_ARB_S_MASK 0x70000 +#define TPC0_NRTR_DBG_L_ARB_N_SHIFT 24 +#define TPC0_NRTR_DBG_L_ARB_N_MASK 0x7000000 + +/* TPC0_NRTR_DBG_E_ARB_MAX */ +#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_W_ARB_MAX */ +#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_N_ARB_MAX */ +#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_S_ARB_MAX */ +#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_L_ARB_MAX */ +#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_SPLIT_COEF */ +#define TPC0_NRTR_SPLIT_COEF_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_CFG */ +#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4 +#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10 +#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5 +#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20 +#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* TPC0_NRTR_SPLIT_RD_SAT */ +#define TPC0_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_RD_RST_TOKEN */ +#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_RD_TIMEOUT */ +#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_SPLIT_WR_SAT */ +#define TPC0_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* TPC0_NRTR_WPLIT_WR_TST_TOLEN */ +#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_WR_TIMEOUT */ +#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_HBW_RANGE_HIT */ +#define TPC0_NRTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* TPC0_NRTR_HBW_RANGE_MASK_L */ +#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_HBW_RANGE_MASK_H */ +#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* TPC0_NRTR_HBW_RANGE_BASE_L */ +#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_HBW_RANGE_BASE_H */ +#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* TPC0_NRTR_LBW_RANGE_HIT */ +#define TPC0_NRTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define TPC0_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* TPC0_NRTR_LBW_RANGE_MASK */ +#define TPC0_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define TPC0_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* TPC0_NRTR_LBW_RANGE_BASE */ +#define TPC0_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define TPC0_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* TPC0_NRTR_RGLTR */ +#define TPC0_NRTR_RGLTR_WR_EN_SHIFT 0 +#define TPC0_NRTR_RGLTR_WR_EN_MASK 0x1 +#define TPC0_NRTR_RGLTR_RD_EN_SHIFT 4 +#define TPC0_NRTR_RGLTR_RD_EN_MASK 0x10 + +/* TPC0_NRTR_RGLTR_WR_RESULT */ +#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* TPC0_NRTR_RGLTR_RD_RESULT */ +#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* TPC0_NRTR_SCRAMB_EN */ +#define TPC0_NRTR_SCRAMB_EN_VAL_SHIFT 0 +#define TPC0_NRTR_SCRAMB_EN_VAL_MASK 0x1 + +/* TPC0_NRTR_NON_LIN_SCRAMB */ +#define TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define TPC0_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_TPC0_NRTR_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h new file mode 100644 index 000000000000..dc280f4e6608 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_NRTR_REGS_H_ +#define ASIC_REG_TPC0_NRTR_REGS_H_ + +/* + ***************************************** + * TPC0_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmTPC0_NRTR_HBW_MAX_CRED 0xE00100 + +#define mmTPC0_NRTR_LBW_MAX_CRED 0xE00120 + +#define mmTPC0_NRTR_DBG_E_ARB 0xE00300 + +#define mmTPC0_NRTR_DBG_W_ARB 0xE00304 + +#define mmTPC0_NRTR_DBG_N_ARB 0xE00308 + +#define mmTPC0_NRTR_DBG_S_ARB 0xE0030C + +#define mmTPC0_NRTR_DBG_L_ARB 0xE00310 + +#define mmTPC0_NRTR_DBG_E_ARB_MAX 0xE00320 + +#define mmTPC0_NRTR_DBG_W_ARB_MAX 0xE00324 + +#define mmTPC0_NRTR_DBG_N_ARB_MAX 0xE00328 + +#define mmTPC0_NRTR_DBG_S_ARB_MAX 0xE0032C + +#define mmTPC0_NRTR_DBG_L_ARB_MAX 0xE00330 + +#define mmTPC0_NRTR_SPLIT_COEF_0 0xE00400 + +#define mmTPC0_NRTR_SPLIT_COEF_1 0xE00404 + +#define mmTPC0_NRTR_SPLIT_COEF_2 0xE00408 + +#define mmTPC0_NRTR_SPLIT_COEF_3 0xE0040C + +#define mmTPC0_NRTR_SPLIT_COEF_4 0xE00410 + +#define mmTPC0_NRTR_SPLIT_COEF_5 0xE00414 + +#define mmTPC0_NRTR_SPLIT_COEF_6 0xE00418 + +#define mmTPC0_NRTR_SPLIT_COEF_7 0xE0041C + +#define mmTPC0_NRTR_SPLIT_COEF_8 0xE00420 + +#define mmTPC0_NRTR_SPLIT_COEF_9 0xE00424 + +#define mmTPC0_NRTR_SPLIT_CFG 0xE00440 + +#define mmTPC0_NRTR_SPLIT_RD_SAT 0xE00444 + +#define mmTPC0_NRTR_SPLIT_RD_RST_TOKEN 0xE00448 + +#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_0 0xE0044C + +#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_1 0xE00450 + +#define mmTPC0_NRTR_SPLIT_WR_SAT 0xE00454 + +#define mmTPC0_NRTR_WPLIT_WR_TST_TOLEN 0xE00458 + +#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_0 0xE0045C + +#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_1 0xE00460 + +#define mmTPC0_NRTR_HBW_RANGE_HIT 0xE00470 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_0 0xE00480 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_1 0xE00484 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_2 0xE00488 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_3 0xE0048C + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_4 0xE00490 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_5 0xE00494 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_6 0xE00498 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_7 0xE0049C + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_0 0xE004A0 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_1 0xE004A4 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_2 0xE004A8 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_3 0xE004AC + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_4 0xE004B0 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_5 0xE004B4 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_6 0xE004B8 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_7 0xE004BC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_0 0xE004C0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_1 0xE004C4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_2 0xE004C8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_3 0xE004CC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_4 0xE004D0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_5 0xE004D4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_6 0xE004D8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_7 0xE004DC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_0 0xE004E0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_1 0xE004E4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_2 0xE004E8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_3 0xE004EC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_4 0xE004F0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_5 0xE004F4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_6 0xE004F8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_7 0xE004FC + +#define mmTPC0_NRTR_LBW_RANGE_HIT 0xE00500 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_0 0xE00510 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_1 0xE00514 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_2 0xE00518 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_3 0xE0051C + +#define mmTPC0_NRTR_LBW_RANGE_MASK_4 0xE00520 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_5 0xE00524 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_6 0xE00528 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_7 0xE0052C + +#define mmTPC0_NRTR_LBW_RANGE_MASK_8 0xE00530 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_9 0xE00534 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_10 0xE00538 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_11 0xE0053C + +#define mmTPC0_NRTR_LBW_RANGE_MASK_12 0xE00540 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_13 0xE00544 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_14 0xE00548 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_15 0xE0054C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_0 0xE00550 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_1 0xE00554 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_2 0xE00558 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_3 0xE0055C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_4 0xE00560 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_5 0xE00564 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_6 0xE00568 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_7 0xE0056C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_8 0xE00570 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_9 0xE00574 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_10 0xE00578 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_11 0xE0057C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_12 0xE00580 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_13 0xE00584 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_14 0xE00588 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_15 0xE0058C + +#define mmTPC0_NRTR_RGLTR 0xE00590 + +#define mmTPC0_NRTR_RGLTR_WR_RESULT 0xE00594 + +#define mmTPC0_NRTR_RGLTR_RD_RESULT 0xE00598 + +#define mmTPC0_NRTR_SCRAMB_EN 0xE00600 + +#define mmTPC0_NRTR_NON_LIN_SCRAMB 0xE00604 + +#endif /* ASIC_REG_TPC0_NRTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h new file mode 100644 index 000000000000..80d97ee3d8d6 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h @@ -0,0 +1,465 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_MASKS_H_ +#define ASIC_REG_TPC0_QM_MASKS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +/* TPC0_QM_GLBL_CFG0 */ +#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x1 +#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 1 +#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x2 +#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 2 +#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x4 +#define TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT 3 +#define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* TPC0_QM_GLBL_CFG1 */ +#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 2 +#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x4 +#define TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* TPC0_QM_GLBL_PROT */ +#define TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT 0 +#define TPC0_QM_GLBL_PROT_PQF_PROT_MASK 0x1 +#define TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT 1 +#define TPC0_QM_GLBL_PROT_CQF_PROT_MASK 0x2 +#define TPC0_QM_GLBL_PROT_CP_PROT_SHIFT 2 +#define TPC0_QM_GLBL_PROT_CP_PROT_MASK 0x4 +#define TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT 3 +#define TPC0_QM_GLBL_PROT_DMA_PROT_MASK 0x8 +#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* TPC0_QM_GLBL_ERR_CFG */ +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* TPC0_QM_GLBL_ERR_ADDR_LO */ +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_ADDR_HI */ +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_WDATA */ +#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_SECURE_PROPS */ +#define TPC0_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_NON_SECURE_PROPS */ +#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_STS0 */ +#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 2 +#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x4 +#define TPC0_QM_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define TPC0_QM_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* TPC0_QM_GLBL_STS1 */ +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* TPC0_QM_PQ_BASE_LO */ +#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_BASE_HI */ +#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_SIZE */ +#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 +#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PI */ +#define TPC0_QM_PQ_PI_VAL_SHIFT 0 +#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CI */ +#define TPC0_QM_PQ_CI_VAL_SHIFT 0 +#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CFG0 */ +#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_PQ_CFG1 */ +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_ARUSER */ +#define TPC0_QM_PQ_ARUSER_NOSNOOP_SHIFT 0 +#define TPC0_QM_PQ_ARUSER_NOSNOOP_MASK 0x1 +#define TPC0_QM_PQ_ARUSER_WORD_SHIFT 1 +#define TPC0_QM_PQ_ARUSER_WORD_MASK 0x2 + +/* TPC0_QM_PQ_PUSH0 */ +#define TPC0_QM_PQ_PUSH0_PTR_LO_SHIFT 0 +#define TPC0_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PUSH1 */ +#define TPC0_QM_PQ_PUSH1_PTR_HI_SHIFT 0 +#define TPC0_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PUSH2 */ +#define TPC0_QM_PQ_PUSH2_TSIZE_SHIFT 0 +#define TPC0_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PUSH3 */ +#define TPC0_QM_PQ_PUSH3_RPT_SHIFT 0 +#define TPC0_QM_PQ_PUSH3_RPT_MASK 0xFFFF +#define TPC0_QM_PQ_PUSH3_CTL_SHIFT 16 +#define TPC0_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_STS0 */ +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_STS1 */ +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_PQ_RD_RATE_LIM_EN */ +#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN */ +#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_QM_PQ_RD_RATE_LIM_SAT */ +#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* TPC0_QM_PQ_RD_RATE_LIM_TOUT */ +#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* TPC0_QM_CQ_CFG0 */ +#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_CQ_CFG1 */ +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_ARUSER */ +#define TPC0_QM_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define TPC0_QM_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define TPC0_QM_CQ_ARUSER_WORD_SHIFT 1 +#define TPC0_QM_CQ_ARUSER_WORD_MASK 0x2 + +/* TPC0_QM_CQ_PTR_LO */ +#define TPC0_QM_CQ_PTR_LO_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI */ +#define TPC0_QM_CQ_PTR_HI_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE */ +#define TPC0_QM_CQ_TSIZE_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL */ +#define TPC0_QM_CQ_CTL_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_STS */ +#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_STS */ +#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_STS */ +#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_STS */ +#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_STS0 */ +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_STS1 */ +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_RD_RATE_LIM_EN */ +#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN */ +#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_QM_CQ_RD_RATE_LIM_SAT */ +#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* TPC0_QM_CQ_RD_RATE_LIM_TOUT */ +#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* TPC0_QM_CQ_IFIFO_CNT */ +#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET */ +#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_COMMIT_OFFSET */ +#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_FENCE0_RDATA */ +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE1_RDATA */ +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE2_RDATA */ +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE3_RDATA */ +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE0_CNT */ +#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_FENCE1_CNT */ +#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_FENCE2_CNT */ +#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_FENCE3_CNT */ +#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_STS */ +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CP_STS_ERDY_SHIFT 16 +#define TPC0_QM_CP_STS_ERDY_MASK 0x10000 +#define TPC0_QM_CP_STS_RRDY_SHIFT 17 +#define TPC0_QM_CP_STS_RRDY_MASK 0x20000 +#define TPC0_QM_CP_STS_MRDY_SHIFT 18 +#define TPC0_QM_CP_STS_MRDY_MASK 0x40000 +#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 +#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* TPC0_QM_CP_CURRENT_INST_LO */ +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_CURRENT_INST_HI */ +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_BARRIER_CFG */ +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* TPC0_QM_CP_DBG_0 */ +#define TPC0_QM_CP_DBG_0_VAL_SHIFT 0 +#define TPC0_QM_CP_DBG_0_VAL_MASK 0xFF + +/* TPC0_QM_PQ_BUF_ADDR */ +#define TPC0_QM_PQ_BUF_ADDR_VAL_SHIFT 0 +#define TPC0_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_BUF_RDATA */ +#define TPC0_QM_PQ_BUF_RDATA_VAL_SHIFT 0 +#define TPC0_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_BUF_ADDR */ +#define TPC0_QM_CQ_BUF_ADDR_VAL_SHIFT 0 +#define TPC0_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_BUF_RDATA */ +#define TPC0_QM_CQ_BUF_RDATA_VAL_SHIFT 0 +#define TPC0_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h new file mode 100644 index 000000000000..7552d4ba61fe --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_REGS_H_ +#define ASIC_REG_TPC0_QM_REGS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC0_QM_GLBL_CFG0 0xE08000 + +#define mmTPC0_QM_GLBL_CFG1 0xE08004 + +#define mmTPC0_QM_GLBL_PROT 0xE08008 + +#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C + +#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08010 + +#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08014 + +#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08018 + +#define mmTPC0_QM_GLBL_SECURE_PROPS 0xE0801C + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS 0xE08020 + +#define mmTPC0_QM_GLBL_STS0 0xE08024 + +#define mmTPC0_QM_GLBL_STS1 0xE08028 + +#define mmTPC0_QM_PQ_BASE_LO 0xE08060 + +#define mmTPC0_QM_PQ_BASE_HI 0xE08064 + +#define mmTPC0_QM_PQ_SIZE 0xE08068 + +#define mmTPC0_QM_PQ_PI 0xE0806C + +#define mmTPC0_QM_PQ_CI 0xE08070 + +#define mmTPC0_QM_PQ_CFG0 0xE08074 + +#define mmTPC0_QM_PQ_CFG1 0xE08078 + +#define mmTPC0_QM_PQ_ARUSER 0xE0807C + +#define mmTPC0_QM_PQ_PUSH0 0xE08080 + +#define mmTPC0_QM_PQ_PUSH1 0xE08084 + +#define mmTPC0_QM_PQ_PUSH2 0xE08088 + +#define mmTPC0_QM_PQ_PUSH3 0xE0808C + +#define mmTPC0_QM_PQ_STS0 0xE08090 + +#define mmTPC0_QM_PQ_STS1 0xE08094 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_EN 0xE080A0 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE080A4 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_SAT 0xE080A8 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_TOUT 0xE080AC + +#define mmTPC0_QM_CQ_CFG0 0xE080B0 + +#define mmTPC0_QM_CQ_CFG1 0xE080B4 + +#define mmTPC0_QM_CQ_ARUSER 0xE080B8 + +#define mmTPC0_QM_CQ_PTR_LO 0xE080C0 + +#define mmTPC0_QM_CQ_PTR_HI 0xE080C4 + +#define mmTPC0_QM_CQ_TSIZE 0xE080C8 + +#define mmTPC0_QM_CQ_CTL 0xE080CC + +#define mmTPC0_QM_CQ_PTR_LO_STS 0xE080D4 + +#define mmTPC0_QM_CQ_PTR_HI_STS 0xE080D8 + +#define mmTPC0_QM_CQ_TSIZE_STS 0xE080DC + +#define mmTPC0_QM_CQ_CTL_STS 0xE080E0 + +#define mmTPC0_QM_CQ_STS0 0xE080E4 + +#define mmTPC0_QM_CQ_STS1 0xE080E8 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_EN 0xE080F0 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE080F4 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_SAT 0xE080F8 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_TOUT 0xE080FC + +#define mmTPC0_QM_CQ_IFIFO_CNT 0xE08108 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO 0xE08120 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI 0xE08124 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO 0xE08128 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI 0xE0812C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO 0xE08130 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI 0xE08134 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO 0xE08138 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI 0xE0813C + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET 0xE08140 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE08144 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE08148 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE0814C + +#define mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE08150 + +#define mmTPC0_QM_CP_LDMA_COMMIT_OFFSET 0xE08154 + +#define mmTPC0_QM_CP_FENCE0_RDATA 0xE08158 + +#define mmTPC0_QM_CP_FENCE1_RDATA 0xE0815C + +#define mmTPC0_QM_CP_FENCE2_RDATA 0xE08160 + +#define mmTPC0_QM_CP_FENCE3_RDATA 0xE08164 + +#define mmTPC0_QM_CP_FENCE0_CNT 0xE08168 + +#define mmTPC0_QM_CP_FENCE1_CNT 0xE0816C + +#define mmTPC0_QM_CP_FENCE2_CNT 0xE08170 + +#define mmTPC0_QM_CP_FENCE3_CNT 0xE08174 + +#define mmTPC0_QM_CP_STS 0xE08178 + +#define mmTPC0_QM_CP_CURRENT_INST_LO 0xE0817C + +#define mmTPC0_QM_CP_CURRENT_INST_HI 0xE08180 + +#define mmTPC0_QM_CP_BARRIER_CFG 0xE08184 + +#define mmTPC0_QM_CP_DBG_0 0xE08188 + +#define mmTPC0_QM_PQ_BUF_ADDR 0xE08300 + +#define mmTPC0_QM_PQ_BUF_RDATA 0xE08304 + +#define mmTPC0_QM_CQ_BUF_ADDR 0xE08308 + +#define mmTPC0_QM_CQ_BUF_RDATA 0xE0830C + +#endif /* ASIC_REG_TPC0_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h new file mode 100644 index 000000000000..19894413474a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_CFG_REGS_H_ +#define ASIC_REG_TPC1_CFG_REGS_H_ + +/* + ***************************************** + * TPC1_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE46418 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE4641C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE46420 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE46424 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46428 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE4642C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE46430 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46434 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE46438 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE4643C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46440 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46444 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE46448 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE4644C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE46450 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46454 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46458 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE4645C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE46460 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE46464 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46468 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE4646C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE46470 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46474 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE46478 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE4647C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46480 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46484 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE46488 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE4648C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE46490 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE46494 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46498 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE4649C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE464A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE464A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE464A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE464AC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE464B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE464B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE464B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE464BC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE464C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE464C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE464C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE464CC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE464D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE464D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464DC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE464E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464EC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE464FC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE46500 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE46504 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE46508 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE4650C + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE46510 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE46514 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE46518 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE4651C + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE46520 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE46524 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE46528 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE4652C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE46530 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE46534 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE46538 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE4653C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE46540 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE46544 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE46548 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE4654C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE46550 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE46554 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46558 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE4655C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE46560 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46564 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE46568 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE4656C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46570 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46574 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE46578 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE4657C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE46580 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46584 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46588 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE4658C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE46590 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE46594 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46598 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE4659C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE465A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE465A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE465A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE465AC + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE465B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE465B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE465B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE465BC + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE465C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE465C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE465C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE465CC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE465D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE465D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE465D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE465DC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE465E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE465E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE465E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE465EC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE465F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE465F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE465F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE465FC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE46600 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE46604 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46608 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE4660C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE46610 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46614 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE46618 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE4661C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46620 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46624 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE46628 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE4662C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE46630 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE46634 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE46638 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE4663C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE46640 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE46644 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE46648 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE4664C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE46650 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE46654 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE46658 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE4665C + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46660 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE46664 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46668 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE4666C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46670 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE46674 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE46678 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE4667C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE46680 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE46684 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE46688 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE4668C + +#define mmTPC1_CFG_KERNEL_SRF_0 0xE46690 + +#define mmTPC1_CFG_KERNEL_SRF_1 0xE46694 + +#define mmTPC1_CFG_KERNEL_SRF_2 0xE46698 + +#define mmTPC1_CFG_KERNEL_SRF_3 0xE4669C + +#define mmTPC1_CFG_KERNEL_SRF_4 0xE466A0 + +#define mmTPC1_CFG_KERNEL_SRF_5 0xE466A4 + +#define mmTPC1_CFG_KERNEL_SRF_6 0xE466A8 + +#define mmTPC1_CFG_KERNEL_SRF_7 0xE466AC + +#define mmTPC1_CFG_KERNEL_SRF_8 0xE466B0 + +#define mmTPC1_CFG_KERNEL_SRF_9 0xE466B4 + +#define mmTPC1_CFG_KERNEL_SRF_10 0xE466B8 + +#define mmTPC1_CFG_KERNEL_SRF_11 0xE466BC + +#define mmTPC1_CFG_KERNEL_SRF_12 0xE466C0 + +#define mmTPC1_CFG_KERNEL_SRF_13 0xE466C4 + +#define mmTPC1_CFG_KERNEL_SRF_14 0xE466C8 + +#define mmTPC1_CFG_KERNEL_SRF_15 0xE466CC + +#define mmTPC1_CFG_KERNEL_SRF_16 0xE466D0 + +#define mmTPC1_CFG_KERNEL_SRF_17 0xE466D4 + +#define mmTPC1_CFG_KERNEL_SRF_18 0xE466D8 + +#define mmTPC1_CFG_KERNEL_SRF_19 0xE466DC + +#define mmTPC1_CFG_KERNEL_SRF_20 0xE466E0 + +#define mmTPC1_CFG_KERNEL_SRF_21 0xE466E4 + +#define mmTPC1_CFG_KERNEL_SRF_22 0xE466E8 + +#define mmTPC1_CFG_KERNEL_SRF_23 0xE466EC + +#define mmTPC1_CFG_KERNEL_SRF_24 0xE466F0 + +#define mmTPC1_CFG_KERNEL_SRF_25 0xE466F4 + +#define mmTPC1_CFG_KERNEL_SRF_26 0xE466F8 + +#define mmTPC1_CFG_KERNEL_SRF_27 0xE466FC + +#define mmTPC1_CFG_KERNEL_SRF_28 0xE46700 + +#define mmTPC1_CFG_KERNEL_SRF_29 0xE46704 + +#define mmTPC1_CFG_KERNEL_SRF_30 0xE46708 + +#define mmTPC1_CFG_KERNEL_SRF_31 0xE4670C + +#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE46710 + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46714 + +#define mmTPC1_CFG_RESERVED_DESC_END 0xE46738 + +#define mmTPC1_CFG_ROUND_CSR 0xE467FC + +#define mmTPC1_CFG_TBUF_BASE_ADDR_LOW 0xE46800 + +#define mmTPC1_CFG_TBUF_BASE_ADDR_HIGH 0xE46804 + +#define mmTPC1_CFG_SEMAPHORE 0xE46808 + +#define mmTPC1_CFG_VFLAGS 0xE4680C + +#define mmTPC1_CFG_SFLAGS 0xE46810 + +#define mmTPC1_CFG_LFSR_POLYNOM 0xE46818 + +#define mmTPC1_CFG_STATUS 0xE4681C + +#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46820 + +#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46824 + +#define mmTPC1_CFG_SM_BASE_ADDRESS_LOW 0xE46828 + +#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4682C + +#define mmTPC1_CFG_TPC_CMD 0xE46830 + +#define mmTPC1_CFG_TPC_EXECUTE 0xE46838 + +#define mmTPC1_CFG_TPC_STALL 0xE4683C + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46840 + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46844 + +#define mmTPC1_CFG_MSS_CONFIG 0xE46854 + +#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46858 + +#define mmTPC1_CFG_TPC_INTR_MASK 0xE4685C + +#define mmTPC1_CFG_TSB_CONFIG 0xE46860 + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00 + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04 + +#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08 + +#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE46A18 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A1C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A20 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE46A24 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A28 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A2C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE46A30 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A34 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A38 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE46A3C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A40 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A44 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE46A48 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A4C + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A50 + +#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A54 + +#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A58 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A5C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A60 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE46A64 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A68 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A6C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE46A70 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A74 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A78 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE46A7C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A80 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A84 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE46A88 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A8C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A90 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE46A94 + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A98 + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A9C + +#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46AA0 + +#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46AA4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46AA8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46AAC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE46AB0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46AB4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46AB8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE46ABC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46AC0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46AC4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE46AC8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46ACC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46AD0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE46AD4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AD8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46ADC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE46AE0 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AE4 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AE8 + +#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AEC + +#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AF0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AF4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46AF8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE46AFC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46B00 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46B04 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE46B08 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46B0C + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46B10 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE46B14 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46B18 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46B1C + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE46B20 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46B24 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46B28 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE46B2C + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46B30 + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46B34 + +#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46B38 + +#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46B3C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46B40 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46B44 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE46B48 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46B4C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46B50 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE46B54 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B58 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B5C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE46B60 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B64 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B68 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE46B6C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B70 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B74 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE46B78 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B7C + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B80 + +#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B84 + +#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B88 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B8C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B90 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE46B94 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B98 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B9C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE46BA0 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46BA4 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46BA8 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE46BAC + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46BB0 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46BB4 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE46BB8 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46BBC + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46BC0 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE46BC4 + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46BC8 + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46BCC + +#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46BD0 + +#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46BD4 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46BD8 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46BDC + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE46BE0 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46BE4 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46BE8 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE46BEC + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46BF0 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46BF4 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE46BF8 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46BFC + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46C00 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE46C04 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46C08 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46C0C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE46C10 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46C14 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46C18 + +#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46C1C + +#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46C20 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46C24 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46C28 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE46C2C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46C30 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46C34 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE46C38 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46C3C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46C40 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE46C44 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46C48 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46C4C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE46C50 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46C54 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46C58 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE46C5C + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46C60 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46C64 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46C68 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46C6C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46C70 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46C74 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46C78 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46C7C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46C80 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46C84 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46C88 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46C8C + +#define mmTPC1_CFG_QM_SRF_0 0xE46C90 + +#define mmTPC1_CFG_QM_SRF_1 0xE46C94 + +#define mmTPC1_CFG_QM_SRF_2 0xE46C98 + +#define mmTPC1_CFG_QM_SRF_3 0xE46C9C + +#define mmTPC1_CFG_QM_SRF_4 0xE46CA0 + +#define mmTPC1_CFG_QM_SRF_5 0xE46CA4 + +#define mmTPC1_CFG_QM_SRF_6 0xE46CA8 + +#define mmTPC1_CFG_QM_SRF_7 0xE46CAC + +#define mmTPC1_CFG_QM_SRF_8 0xE46CB0 + +#define mmTPC1_CFG_QM_SRF_9 0xE46CB4 + +#define mmTPC1_CFG_QM_SRF_10 0xE46CB8 + +#define mmTPC1_CFG_QM_SRF_11 0xE46CBC + +#define mmTPC1_CFG_QM_SRF_12 0xE46CC0 + +#define mmTPC1_CFG_QM_SRF_13 0xE46CC4 + +#define mmTPC1_CFG_QM_SRF_14 0xE46CC8 + +#define mmTPC1_CFG_QM_SRF_15 0xE46CCC + +#define mmTPC1_CFG_QM_SRF_16 0xE46CD0 + +#define mmTPC1_CFG_QM_SRF_17 0xE46CD4 + +#define mmTPC1_CFG_QM_SRF_18 0xE46CD8 + +#define mmTPC1_CFG_QM_SRF_19 0xE46CDC + +#define mmTPC1_CFG_QM_SRF_20 0xE46CE0 + +#define mmTPC1_CFG_QM_SRF_21 0xE46CE4 + +#define mmTPC1_CFG_QM_SRF_22 0xE46CE8 + +#define mmTPC1_CFG_QM_SRF_23 0xE46CEC + +#define mmTPC1_CFG_QM_SRF_24 0xE46CF0 + +#define mmTPC1_CFG_QM_SRF_25 0xE46CF4 + +#define mmTPC1_CFG_QM_SRF_26 0xE46CF8 + +#define mmTPC1_CFG_QM_SRF_27 0xE46CFC + +#define mmTPC1_CFG_QM_SRF_28 0xE46D00 + +#define mmTPC1_CFG_QM_SRF_29 0xE46D04 + +#define mmTPC1_CFG_QM_SRF_30 0xE46D08 + +#define mmTPC1_CFG_QM_SRF_31 0xE46D0C + +#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46D10 + +#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D14 + +#define mmTPC1_CFG_ARUSER 0xE46D18 + +#define mmTPC1_CFG_AWUSER 0xE46D1C + +#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE46E00 + +#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE46E04 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE46E08 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE46E0C + +#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE46E10 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE46E14 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE46E18 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE46E1C + +#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE46E20 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE46E24 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE46E28 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE46E2C + +#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h new file mode 100644 index 000000000000..9099ebd7ab23 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_CMDQ_REGS_H_ +#define ASIC_REG_TPC1_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC1_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC1_CMDQ_GLBL_CFG0 0xE49000 + +#define mmTPC1_CMDQ_GLBL_CFG1 0xE49004 + +#define mmTPC1_CMDQ_GLBL_PROT 0xE49008 + +#define mmTPC1_CMDQ_GLBL_ERR_CFG 0xE4900C + +#define mmTPC1_CMDQ_GLBL_ERR_ADDR_LO 0xE49010 + +#define mmTPC1_CMDQ_GLBL_ERR_ADDR_HI 0xE49014 + +#define mmTPC1_CMDQ_GLBL_ERR_WDATA 0xE49018 + +#define mmTPC1_CMDQ_GLBL_SECURE_PROPS 0xE4901C + +#define mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS 0xE49020 + +#define mmTPC1_CMDQ_GLBL_STS0 0xE49024 + +#define mmTPC1_CMDQ_GLBL_STS1 0xE49028 + +#define mmTPC1_CMDQ_CQ_CFG0 0xE490B0 + +#define mmTPC1_CMDQ_CQ_CFG1 0xE490B4 + +#define mmTPC1_CMDQ_CQ_ARUSER 0xE490B8 + +#define mmTPC1_CMDQ_CQ_PTR_LO 0xE490C0 + +#define mmTPC1_CMDQ_CQ_PTR_HI 0xE490C4 + +#define mmTPC1_CMDQ_CQ_TSIZE 0xE490C8 + +#define mmTPC1_CMDQ_CQ_CTL 0xE490CC + +#define mmTPC1_CMDQ_CQ_PTR_LO_STS 0xE490D4 + +#define mmTPC1_CMDQ_CQ_PTR_HI_STS 0xE490D8 + +#define mmTPC1_CMDQ_CQ_TSIZE_STS 0xE490DC + +#define mmTPC1_CMDQ_CQ_CTL_STS 0xE490E0 + +#define mmTPC1_CMDQ_CQ_STS0 0xE490E4 + +#define mmTPC1_CMDQ_CQ_STS1 0xE490E8 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN 0xE490F0 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE490F4 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT 0xE490F8 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE490FC + +#define mmTPC1_CMDQ_CQ_IFIFO_CNT 0xE49108 + +#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE49120 + +#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE49124 + +#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE49128 + +#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE4912C + +#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE49130 + +#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE49134 + +#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE49138 + +#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE4913C + +#define mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE49140 + +#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE49144 + +#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE49148 + +#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE4914C + +#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE49150 + +#define mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE49154 + +#define mmTPC1_CMDQ_CP_FENCE0_RDATA 0xE49158 + +#define mmTPC1_CMDQ_CP_FENCE1_RDATA 0xE4915C + +#define mmTPC1_CMDQ_CP_FENCE2_RDATA 0xE49160 + +#define mmTPC1_CMDQ_CP_FENCE3_RDATA 0xE49164 + +#define mmTPC1_CMDQ_CP_FENCE0_CNT 0xE49168 + +#define mmTPC1_CMDQ_CP_FENCE1_CNT 0xE4916C + +#define mmTPC1_CMDQ_CP_FENCE2_CNT 0xE49170 + +#define mmTPC1_CMDQ_CP_FENCE3_CNT 0xE49174 + +#define mmTPC1_CMDQ_CP_STS 0xE49178 + +#define mmTPC1_CMDQ_CP_CURRENT_INST_LO 0xE4917C + +#define mmTPC1_CMDQ_CP_CURRENT_INST_HI 0xE49180 + +#define mmTPC1_CMDQ_CP_BARRIER_CFG 0xE49184 + +#define mmTPC1_CMDQ_CP_DBG_0 0xE49188 + +#define mmTPC1_CMDQ_CQ_BUF_ADDR 0xE49308 + +#define mmTPC1_CMDQ_CQ_BUF_RDATA 0xE4930C + +#endif /* ASIC_REG_TPC1_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h new file mode 100644 index 000000000000..bc8b9a10391f --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_QM_REGS_H_ +#define ASIC_REG_TPC1_QM_REGS_H_ + +/* + ***************************************** + * TPC1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC1_QM_GLBL_CFG0 0xE48000 + +#define mmTPC1_QM_GLBL_CFG1 0xE48004 + +#define mmTPC1_QM_GLBL_PROT 0xE48008 + +#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C + +#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48010 + +#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48014 + +#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48018 + +#define mmTPC1_QM_GLBL_SECURE_PROPS 0xE4801C + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS 0xE48020 + +#define mmTPC1_QM_GLBL_STS0 0xE48024 + +#define mmTPC1_QM_GLBL_STS1 0xE48028 + +#define mmTPC1_QM_PQ_BASE_LO 0xE48060 + +#define mmTPC1_QM_PQ_BASE_HI 0xE48064 + +#define mmTPC1_QM_PQ_SIZE 0xE48068 + +#define mmTPC1_QM_PQ_PI 0xE4806C + +#define mmTPC1_QM_PQ_CI 0xE48070 + +#define mmTPC1_QM_PQ_CFG0 0xE48074 + +#define mmTPC1_QM_PQ_CFG1 0xE48078 + +#define mmTPC1_QM_PQ_ARUSER 0xE4807C + +#define mmTPC1_QM_PQ_PUSH0 0xE48080 + +#define mmTPC1_QM_PQ_PUSH1 0xE48084 + +#define mmTPC1_QM_PQ_PUSH2 0xE48088 + +#define mmTPC1_QM_PQ_PUSH3 0xE4808C + +#define mmTPC1_QM_PQ_STS0 0xE48090 + +#define mmTPC1_QM_PQ_STS1 0xE48094 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_EN 0xE480A0 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE480A4 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_SAT 0xE480A8 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_TOUT 0xE480AC + +#define mmTPC1_QM_CQ_CFG0 0xE480B0 + +#define mmTPC1_QM_CQ_CFG1 0xE480B4 + +#define mmTPC1_QM_CQ_ARUSER 0xE480B8 + +#define mmTPC1_QM_CQ_PTR_LO 0xE480C0 + +#define mmTPC1_QM_CQ_PTR_HI 0xE480C4 + +#define mmTPC1_QM_CQ_TSIZE 0xE480C8 + +#define mmTPC1_QM_CQ_CTL 0xE480CC + +#define mmTPC1_QM_CQ_PTR_LO_STS 0xE480D4 + +#define mmTPC1_QM_CQ_PTR_HI_STS 0xE480D8 + +#define mmTPC1_QM_CQ_TSIZE_STS 0xE480DC + +#define mmTPC1_QM_CQ_CTL_STS 0xE480E0 + +#define mmTPC1_QM_CQ_STS0 0xE480E4 + +#define mmTPC1_QM_CQ_STS1 0xE480E8 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_EN 0xE480F0 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE480F4 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_SAT 0xE480F8 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_TOUT 0xE480FC + +#define mmTPC1_QM_CQ_IFIFO_CNT 0xE48108 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO 0xE48120 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI 0xE48124 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO 0xE48128 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI 0xE4812C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO 0xE48130 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI 0xE48134 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO 0xE48138 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI 0xE4813C + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET 0xE48140 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE48144 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE48148 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE4814C + +#define mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE48150 + +#define mmTPC1_QM_CP_LDMA_COMMIT_OFFSET 0xE48154 + +#define mmTPC1_QM_CP_FENCE0_RDATA 0xE48158 + +#define mmTPC1_QM_CP_FENCE1_RDATA 0xE4815C + +#define mmTPC1_QM_CP_FENCE2_RDATA 0xE48160 + +#define mmTPC1_QM_CP_FENCE3_RDATA 0xE48164 + +#define mmTPC1_QM_CP_FENCE0_CNT 0xE48168 + +#define mmTPC1_QM_CP_FENCE1_CNT 0xE4816C + +#define mmTPC1_QM_CP_FENCE2_CNT 0xE48170 + +#define mmTPC1_QM_CP_FENCE3_CNT 0xE48174 + +#define mmTPC1_QM_CP_STS 0xE48178 + +#define mmTPC1_QM_CP_CURRENT_INST_LO 0xE4817C + +#define mmTPC1_QM_CP_CURRENT_INST_HI 0xE48180 + +#define mmTPC1_QM_CP_BARRIER_CFG 0xE48184 + +#define mmTPC1_QM_CP_DBG_0 0xE48188 + +#define mmTPC1_QM_PQ_BUF_ADDR 0xE48300 + +#define mmTPC1_QM_PQ_BUF_RDATA 0xE48304 + +#define mmTPC1_QM_CQ_BUF_ADDR 0xE48308 + +#define mmTPC1_QM_CQ_BUF_RDATA 0xE4830C + +#endif /* ASIC_REG_TPC1_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h new file mode 100644 index 000000000000..ae267f8f457e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_RTR_REGS_H_ +#define ASIC_REG_TPC1_RTR_REGS_H_ + +/* + ***************************************** + * TPC1_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC1_RTR_HBW_RD_RQ_E_ARB 0xE40100 + +#define mmTPC1_RTR_HBW_RD_RQ_W_ARB 0xE40104 + +#define mmTPC1_RTR_HBW_RD_RQ_N_ARB 0xE40108 + +#define mmTPC1_RTR_HBW_RD_RQ_S_ARB 0xE4010C + +#define mmTPC1_RTR_HBW_RD_RQ_L_ARB 0xE40110 + +#define mmTPC1_RTR_HBW_E_ARB_MAX 0xE40120 + +#define mmTPC1_RTR_HBW_W_ARB_MAX 0xE40124 + +#define mmTPC1_RTR_HBW_N_ARB_MAX 0xE40128 + +#define mmTPC1_RTR_HBW_S_ARB_MAX 0xE4012C + +#define mmTPC1_RTR_HBW_L_ARB_MAX 0xE40130 + +#define mmTPC1_RTR_HBW_RD_RS_E_ARB 0xE40140 + +#define mmTPC1_RTR_HBW_RD_RS_W_ARB 0xE40144 + +#define mmTPC1_RTR_HBW_RD_RS_N_ARB 0xE40148 + +#define mmTPC1_RTR_HBW_RD_RS_S_ARB 0xE4014C + +#define mmTPC1_RTR_HBW_RD_RS_L_ARB 0xE40150 + +#define mmTPC1_RTR_HBW_WR_RQ_E_ARB 0xE40170 + +#define mmTPC1_RTR_HBW_WR_RQ_W_ARB 0xE40174 + +#define mmTPC1_RTR_HBW_WR_RQ_N_ARB 0xE40178 + +#define mmTPC1_RTR_HBW_WR_RQ_S_ARB 0xE4017C + +#define mmTPC1_RTR_HBW_WR_RQ_L_ARB 0xE40180 + +#define mmTPC1_RTR_HBW_WR_RS_E_ARB 0xE40190 + +#define mmTPC1_RTR_HBW_WR_RS_W_ARB 0xE40194 + +#define mmTPC1_RTR_HBW_WR_RS_N_ARB 0xE40198 + +#define mmTPC1_RTR_HBW_WR_RS_S_ARB 0xE4019C + +#define mmTPC1_RTR_HBW_WR_RS_L_ARB 0xE401A0 + +#define mmTPC1_RTR_LBW_RD_RQ_E_ARB 0xE40200 + +#define mmTPC1_RTR_LBW_RD_RQ_W_ARB 0xE40204 + +#define mmTPC1_RTR_LBW_RD_RQ_N_ARB 0xE40208 + +#define mmTPC1_RTR_LBW_RD_RQ_S_ARB 0xE4020C + +#define mmTPC1_RTR_LBW_RD_RQ_L_ARB 0xE40210 + +#define mmTPC1_RTR_LBW_E_ARB_MAX 0xE40220 + +#define mmTPC1_RTR_LBW_W_ARB_MAX 0xE40224 + +#define mmTPC1_RTR_LBW_N_ARB_MAX 0xE40228 + +#define mmTPC1_RTR_LBW_S_ARB_MAX 0xE4022C + +#define mmTPC1_RTR_LBW_L_ARB_MAX 0xE40230 + +#define mmTPC1_RTR_LBW_RD_RS_E_ARB 0xE40250 + +#define mmTPC1_RTR_LBW_RD_RS_W_ARB 0xE40254 + +#define mmTPC1_RTR_LBW_RD_RS_N_ARB 0xE40258 + +#define mmTPC1_RTR_LBW_RD_RS_S_ARB 0xE4025C + +#define mmTPC1_RTR_LBW_RD_RS_L_ARB 0xE40260 + +#define mmTPC1_RTR_LBW_WR_RQ_E_ARB 0xE40270 + +#define mmTPC1_RTR_LBW_WR_RQ_W_ARB 0xE40274 + +#define mmTPC1_RTR_LBW_WR_RQ_N_ARB 0xE40278 + +#define mmTPC1_RTR_LBW_WR_RQ_S_ARB 0xE4027C + +#define mmTPC1_RTR_LBW_WR_RQ_L_ARB 0xE40280 + +#define mmTPC1_RTR_LBW_WR_RS_E_ARB 0xE40290 + +#define mmTPC1_RTR_LBW_WR_RS_W_ARB 0xE40294 + +#define mmTPC1_RTR_LBW_WR_RS_N_ARB 0xE40298 + +#define mmTPC1_RTR_LBW_WR_RS_S_ARB 0xE4029C + +#define mmTPC1_RTR_LBW_WR_RS_L_ARB 0xE402A0 + +#define mmTPC1_RTR_DBG_E_ARB 0xE40300 + +#define mmTPC1_RTR_DBG_W_ARB 0xE40304 + +#define mmTPC1_RTR_DBG_N_ARB 0xE40308 + +#define mmTPC1_RTR_DBG_S_ARB 0xE4030C + +#define mmTPC1_RTR_DBG_L_ARB 0xE40310 + +#define mmTPC1_RTR_DBG_E_ARB_MAX 0xE40320 + +#define mmTPC1_RTR_DBG_W_ARB_MAX 0xE40324 + +#define mmTPC1_RTR_DBG_N_ARB_MAX 0xE40328 + +#define mmTPC1_RTR_DBG_S_ARB_MAX 0xE4032C + +#define mmTPC1_RTR_DBG_L_ARB_MAX 0xE40330 + +#define mmTPC1_RTR_SPLIT_COEF_0 0xE40400 + +#define mmTPC1_RTR_SPLIT_COEF_1 0xE40404 + +#define mmTPC1_RTR_SPLIT_COEF_2 0xE40408 + +#define mmTPC1_RTR_SPLIT_COEF_3 0xE4040C + +#define mmTPC1_RTR_SPLIT_COEF_4 0xE40410 + +#define mmTPC1_RTR_SPLIT_COEF_5 0xE40414 + +#define mmTPC1_RTR_SPLIT_COEF_6 0xE40418 + +#define mmTPC1_RTR_SPLIT_COEF_7 0xE4041C + +#define mmTPC1_RTR_SPLIT_COEF_8 0xE40420 + +#define mmTPC1_RTR_SPLIT_COEF_9 0xE40424 + +#define mmTPC1_RTR_SPLIT_CFG 0xE40440 + +#define mmTPC1_RTR_SPLIT_RD_SAT 0xE40444 + +#define mmTPC1_RTR_SPLIT_RD_RST_TOKEN 0xE40448 + +#define mmTPC1_RTR_SPLIT_RD_TIMEOUT_0 0xE4044C + +#define mmTPC1_RTR_SPLIT_RD_TIMEOUT_1 0xE40450 + +#define mmTPC1_RTR_SPLIT_WR_SAT 0xE40454 + +#define mmTPC1_RTR_WPLIT_WR_TST_TOLEN 0xE40458 + +#define mmTPC1_RTR_SPLIT_WR_TIMEOUT_0 0xE4045C + +#define mmTPC1_RTR_SPLIT_WR_TIMEOUT_1 0xE40460 + +#define mmTPC1_RTR_HBW_RANGE_HIT 0xE40470 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_0 0xE40480 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_1 0xE40484 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_2 0xE40488 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_3 0xE4048C + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_4 0xE40490 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_5 0xE40494 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_6 0xE40498 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_7 0xE4049C + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_0 0xE404A0 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_1 0xE404A4 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_2 0xE404A8 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_3 0xE404AC + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_4 0xE404B0 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_5 0xE404B4 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_6 0xE404B8 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_7 0xE404BC + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_0 0xE404C0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_1 0xE404C4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_2 0xE404C8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_3 0xE404CC + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_4 0xE404D0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_5 0xE404D4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_6 0xE404D8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_7 0xE404DC + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_0 0xE404E0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_1 0xE404E4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_2 0xE404E8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_3 0xE404EC + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_4 0xE404F0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_5 0xE404F4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_6 0xE404F8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_7 0xE404FC + +#define mmTPC1_RTR_LBW_RANGE_HIT 0xE40500 + +#define mmTPC1_RTR_LBW_RANGE_MASK_0 0xE40510 + +#define mmTPC1_RTR_LBW_RANGE_MASK_1 0xE40514 + +#define mmTPC1_RTR_LBW_RANGE_MASK_2 0xE40518 + +#define mmTPC1_RTR_LBW_RANGE_MASK_3 0xE4051C + +#define mmTPC1_RTR_LBW_RANGE_MASK_4 0xE40520 + +#define mmTPC1_RTR_LBW_RANGE_MASK_5 0xE40524 + +#define mmTPC1_RTR_LBW_RANGE_MASK_6 0xE40528 + +#define mmTPC1_RTR_LBW_RANGE_MASK_7 0xE4052C + +#define mmTPC1_RTR_LBW_RANGE_MASK_8 0xE40530 + +#define mmTPC1_RTR_LBW_RANGE_MASK_9 0xE40534 + +#define mmTPC1_RTR_LBW_RANGE_MASK_10 0xE40538 + +#define mmTPC1_RTR_LBW_RANGE_MASK_11 0xE4053C + +#define mmTPC1_RTR_LBW_RANGE_MASK_12 0xE40540 + +#define mmTPC1_RTR_LBW_RANGE_MASK_13 0xE40544 + +#define mmTPC1_RTR_LBW_RANGE_MASK_14 0xE40548 + +#define mmTPC1_RTR_LBW_RANGE_MASK_15 0xE4054C + +#define mmTPC1_RTR_LBW_RANGE_BASE_0 0xE40550 + +#define mmTPC1_RTR_LBW_RANGE_BASE_1 0xE40554 + +#define mmTPC1_RTR_LBW_RANGE_BASE_2 0xE40558 + +#define mmTPC1_RTR_LBW_RANGE_BASE_3 0xE4055C + +#define mmTPC1_RTR_LBW_RANGE_BASE_4 0xE40560 + +#define mmTPC1_RTR_LBW_RANGE_BASE_5 0xE40564 + +#define mmTPC1_RTR_LBW_RANGE_BASE_6 0xE40568 + +#define mmTPC1_RTR_LBW_RANGE_BASE_7 0xE4056C + +#define mmTPC1_RTR_LBW_RANGE_BASE_8 0xE40570 + +#define mmTPC1_RTR_LBW_RANGE_BASE_9 0xE40574 + +#define mmTPC1_RTR_LBW_RANGE_BASE_10 0xE40578 + +#define mmTPC1_RTR_LBW_RANGE_BASE_11 0xE4057C + +#define mmTPC1_RTR_LBW_RANGE_BASE_12 0xE40580 + +#define mmTPC1_RTR_LBW_RANGE_BASE_13 0xE40584 + +#define mmTPC1_RTR_LBW_RANGE_BASE_14 0xE40588 + +#define mmTPC1_RTR_LBW_RANGE_BASE_15 0xE4058C + +#define mmTPC1_RTR_RGLTR 0xE40590 + +#define mmTPC1_RTR_RGLTR_WR_RESULT 0xE40594 + +#define mmTPC1_RTR_RGLTR_RD_RESULT 0xE40598 + +#define mmTPC1_RTR_SCRAMB_EN 0xE40600 + +#define mmTPC1_RTR_NON_LIN_SCRAMB 0xE40604 + +#endif /* ASIC_REG_TPC1_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h new file mode 100644 index 000000000000..9c33fc039036 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CFG_REGS_H_ +#define ASIC_REG_TPC2_CFG_REGS_H_ + +/* + ***************************************** + * TPC2_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE86418 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE8641C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE86420 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE86424 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86428 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE8642C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE86430 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86434 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE86438 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE8643C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86440 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86444 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE86448 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE8644C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE86450 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86454 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86458 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE8645C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE86460 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE86464 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86468 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE8646C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE86470 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86474 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE86478 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE8647C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86480 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86484 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE86488 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE8648C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE86490 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE86494 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86498 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE8649C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE864A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE864A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE864A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE864AC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE864B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE864B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE864B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE864BC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE864C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE864C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE864C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE864CC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE864D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE864D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864DC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE864E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864EC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE864FC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE86500 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE86504 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE86508 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE8650C + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE86510 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE86514 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE86518 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE8651C + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE86520 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE86524 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE86528 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE8652C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE86530 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE86534 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE86538 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE8653C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE86540 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE86544 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE86548 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE8654C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE86550 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE86554 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86558 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE8655C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE86560 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86564 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE86568 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE8656C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86570 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86574 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE86578 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE8657C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE86580 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86584 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86588 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE8658C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE86590 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE86594 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86598 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE8659C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE865A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE865A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE865A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE865AC + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE865B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE865B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE865B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE865BC + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE865C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE865C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE865C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE865CC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE865D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE865D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE865D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE865DC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE865E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE865E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE865E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE865EC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE865F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE865F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE865F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE865FC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE86600 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE86604 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86608 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE8660C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE86610 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86614 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE86618 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE8661C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86620 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86624 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE86628 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE8662C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE86630 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE86634 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE86638 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE8663C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE86640 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE86644 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE86648 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE8664C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE86650 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE86654 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE86658 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE8665C + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86660 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE86664 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86668 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE8666C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86670 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE86674 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE86678 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE8667C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE86680 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE86684 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE86688 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE8668C + +#define mmTPC2_CFG_KERNEL_SRF_0 0xE86690 + +#define mmTPC2_CFG_KERNEL_SRF_1 0xE86694 + +#define mmTPC2_CFG_KERNEL_SRF_2 0xE86698 + +#define mmTPC2_CFG_KERNEL_SRF_3 0xE8669C + +#define mmTPC2_CFG_KERNEL_SRF_4 0xE866A0 + +#define mmTPC2_CFG_KERNEL_SRF_5 0xE866A4 + +#define mmTPC2_CFG_KERNEL_SRF_6 0xE866A8 + +#define mmTPC2_CFG_KERNEL_SRF_7 0xE866AC + +#define mmTPC2_CFG_KERNEL_SRF_8 0xE866B0 + +#define mmTPC2_CFG_KERNEL_SRF_9 0xE866B4 + +#define mmTPC2_CFG_KERNEL_SRF_10 0xE866B8 + +#define mmTPC2_CFG_KERNEL_SRF_11 0xE866BC + +#define mmTPC2_CFG_KERNEL_SRF_12 0xE866C0 + +#define mmTPC2_CFG_KERNEL_SRF_13 0xE866C4 + +#define mmTPC2_CFG_KERNEL_SRF_14 0xE866C8 + +#define mmTPC2_CFG_KERNEL_SRF_15 0xE866CC + +#define mmTPC2_CFG_KERNEL_SRF_16 0xE866D0 + +#define mmTPC2_CFG_KERNEL_SRF_17 0xE866D4 + +#define mmTPC2_CFG_KERNEL_SRF_18 0xE866D8 + +#define mmTPC2_CFG_KERNEL_SRF_19 0xE866DC + +#define mmTPC2_CFG_KERNEL_SRF_20 0xE866E0 + +#define mmTPC2_CFG_KERNEL_SRF_21 0xE866E4 + +#define mmTPC2_CFG_KERNEL_SRF_22 0xE866E8 + +#define mmTPC2_CFG_KERNEL_SRF_23 0xE866EC + +#define mmTPC2_CFG_KERNEL_SRF_24 0xE866F0 + +#define mmTPC2_CFG_KERNEL_SRF_25 0xE866F4 + +#define mmTPC2_CFG_KERNEL_SRF_26 0xE866F8 + +#define mmTPC2_CFG_KERNEL_SRF_27 0xE866FC + +#define mmTPC2_CFG_KERNEL_SRF_28 0xE86700 + +#define mmTPC2_CFG_KERNEL_SRF_29 0xE86704 + +#define mmTPC2_CFG_KERNEL_SRF_30 0xE86708 + +#define mmTPC2_CFG_KERNEL_SRF_31 0xE8670C + +#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE86710 + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86714 + +#define mmTPC2_CFG_RESERVED_DESC_END 0xE86738 + +#define mmTPC2_CFG_ROUND_CSR 0xE867FC + +#define mmTPC2_CFG_TBUF_BASE_ADDR_LOW 0xE86800 + +#define mmTPC2_CFG_TBUF_BASE_ADDR_HIGH 0xE86804 + +#define mmTPC2_CFG_SEMAPHORE 0xE86808 + +#define mmTPC2_CFG_VFLAGS 0xE8680C + +#define mmTPC2_CFG_SFLAGS 0xE86810 + +#define mmTPC2_CFG_LFSR_POLYNOM 0xE86818 + +#define mmTPC2_CFG_STATUS 0xE8681C + +#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86820 + +#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86824 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_LOW 0xE86828 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8682C + +#define mmTPC2_CFG_TPC_CMD 0xE86830 + +#define mmTPC2_CFG_TPC_EXECUTE 0xE86838 + +#define mmTPC2_CFG_TPC_STALL 0xE8683C + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86840 + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86844 + +#define mmTPC2_CFG_MSS_CONFIG 0xE86854 + +#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86858 + +#define mmTPC2_CFG_TPC_INTR_MASK 0xE8685C + +#define mmTPC2_CFG_TSB_CONFIG 0xE86860 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04 + +#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08 + +#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE86A18 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A1C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A20 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE86A24 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A28 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A2C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE86A30 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A34 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A38 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE86A3C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A40 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A44 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE86A48 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A4C + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A50 + +#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A54 + +#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A58 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A5C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A60 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE86A64 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A68 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A6C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE86A70 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A74 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A78 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE86A7C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A80 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A84 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE86A88 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A8C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A90 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE86A94 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A98 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A9C + +#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86AA0 + +#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86AA4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86AA8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86AAC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE86AB0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86AB4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86AB8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE86ABC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86AC0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86AC4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE86AC8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86ACC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86AD0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE86AD4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AD8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86ADC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE86AE0 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AE4 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AE8 + +#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AEC + +#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AF0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AF4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86AF8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE86AFC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86B00 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86B04 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE86B08 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86B0C + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86B10 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE86B14 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86B18 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86B1C + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE86B20 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86B24 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86B28 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE86B2C + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86B30 + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86B34 + +#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86B38 + +#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86B3C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86B40 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86B44 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE86B48 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86B4C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86B50 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE86B54 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B58 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B5C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE86B60 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B64 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B68 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE86B6C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B70 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B74 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE86B78 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B7C + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B80 + +#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B84 + +#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B88 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B8C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B90 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE86B94 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B98 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B9C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE86BA0 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86BA4 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86BA8 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE86BAC + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86BB0 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86BB4 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE86BB8 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86BBC + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86BC0 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE86BC4 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86BC8 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86BCC + +#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86BD0 + +#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86BD4 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86BD8 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86BDC + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE86BE0 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86BE4 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86BE8 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE86BEC + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86BF0 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86BF4 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE86BF8 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86BFC + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86C00 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE86C04 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86C08 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86C0C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE86C10 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86C14 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86C18 + +#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86C1C + +#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86C20 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86C24 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86C28 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE86C2C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86C30 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86C34 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE86C38 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86C3C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86C40 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE86C44 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86C48 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86C4C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE86C50 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86C54 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86C58 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE86C5C + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86C60 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86C64 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86C68 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86C6C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86C70 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86C74 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86C78 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86C7C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86C80 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86C84 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86C88 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86C8C + +#define mmTPC2_CFG_QM_SRF_0 0xE86C90 + +#define mmTPC2_CFG_QM_SRF_1 0xE86C94 + +#define mmTPC2_CFG_QM_SRF_2 0xE86C98 + +#define mmTPC2_CFG_QM_SRF_3 0xE86C9C + +#define mmTPC2_CFG_QM_SRF_4 0xE86CA0 + +#define mmTPC2_CFG_QM_SRF_5 0xE86CA4 + +#define mmTPC2_CFG_QM_SRF_6 0xE86CA8 + +#define mmTPC2_CFG_QM_SRF_7 0xE86CAC + +#define mmTPC2_CFG_QM_SRF_8 0xE86CB0 + +#define mmTPC2_CFG_QM_SRF_9 0xE86CB4 + +#define mmTPC2_CFG_QM_SRF_10 0xE86CB8 + +#define mmTPC2_CFG_QM_SRF_11 0xE86CBC + +#define mmTPC2_CFG_QM_SRF_12 0xE86CC0 + +#define mmTPC2_CFG_QM_SRF_13 0xE86CC4 + +#define mmTPC2_CFG_QM_SRF_14 0xE86CC8 + +#define mmTPC2_CFG_QM_SRF_15 0xE86CCC + +#define mmTPC2_CFG_QM_SRF_16 0xE86CD0 + +#define mmTPC2_CFG_QM_SRF_17 0xE86CD4 + +#define mmTPC2_CFG_QM_SRF_18 0xE86CD8 + +#define mmTPC2_CFG_QM_SRF_19 0xE86CDC + +#define mmTPC2_CFG_QM_SRF_20 0xE86CE0 + +#define mmTPC2_CFG_QM_SRF_21 0xE86CE4 + +#define mmTPC2_CFG_QM_SRF_22 0xE86CE8 + +#define mmTPC2_CFG_QM_SRF_23 0xE86CEC + +#define mmTPC2_CFG_QM_SRF_24 0xE86CF0 + +#define mmTPC2_CFG_QM_SRF_25 0xE86CF4 + +#define mmTPC2_CFG_QM_SRF_26 0xE86CF8 + +#define mmTPC2_CFG_QM_SRF_27 0xE86CFC + +#define mmTPC2_CFG_QM_SRF_28 0xE86D00 + +#define mmTPC2_CFG_QM_SRF_29 0xE86D04 + +#define mmTPC2_CFG_QM_SRF_30 0xE86D08 + +#define mmTPC2_CFG_QM_SRF_31 0xE86D0C + +#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86D10 + +#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D14 + +#define mmTPC2_CFG_ARUSER 0xE86D18 + +#define mmTPC2_CFG_AWUSER 0xE86D1C + +#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE86E00 + +#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE86E04 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE86E08 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE86E0C + +#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE86E10 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE86E14 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE86E18 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE86E1C + +#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE86E20 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE86E24 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE86E28 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE86E2C + +#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h new file mode 100644 index 000000000000..7a643887d6e1 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CMDQ_REGS_H_ +#define ASIC_REG_TPC2_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC2_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC2_CMDQ_GLBL_CFG0 0xE89000 + +#define mmTPC2_CMDQ_GLBL_CFG1 0xE89004 + +#define mmTPC2_CMDQ_GLBL_PROT 0xE89008 + +#define mmTPC2_CMDQ_GLBL_ERR_CFG 0xE8900C + +#define mmTPC2_CMDQ_GLBL_ERR_ADDR_LO 0xE89010 + +#define mmTPC2_CMDQ_GLBL_ERR_ADDR_HI 0xE89014 + +#define mmTPC2_CMDQ_GLBL_ERR_WDATA 0xE89018 + +#define mmTPC2_CMDQ_GLBL_SECURE_PROPS 0xE8901C + +#define mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS 0xE89020 + +#define mmTPC2_CMDQ_GLBL_STS0 0xE89024 + +#define mmTPC2_CMDQ_GLBL_STS1 0xE89028 + +#define mmTPC2_CMDQ_CQ_CFG0 0xE890B0 + +#define mmTPC2_CMDQ_CQ_CFG1 0xE890B4 + +#define mmTPC2_CMDQ_CQ_ARUSER 0xE890B8 + +#define mmTPC2_CMDQ_CQ_PTR_LO 0xE890C0 + +#define mmTPC2_CMDQ_CQ_PTR_HI 0xE890C4 + +#define mmTPC2_CMDQ_CQ_TSIZE 0xE890C8 + +#define mmTPC2_CMDQ_CQ_CTL 0xE890CC + +#define mmTPC2_CMDQ_CQ_PTR_LO_STS 0xE890D4 + +#define mmTPC2_CMDQ_CQ_PTR_HI_STS 0xE890D8 + +#define mmTPC2_CMDQ_CQ_TSIZE_STS 0xE890DC + +#define mmTPC2_CMDQ_CQ_CTL_STS 0xE890E0 + +#define mmTPC2_CMDQ_CQ_STS0 0xE890E4 + +#define mmTPC2_CMDQ_CQ_STS1 0xE890E8 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN 0xE890F0 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE890F4 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT 0xE890F8 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE890FC + +#define mmTPC2_CMDQ_CQ_IFIFO_CNT 0xE89108 + +#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE89120 + +#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE89124 + +#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE89128 + +#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE8912C + +#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE89130 + +#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE89134 + +#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE89138 + +#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE8913C + +#define mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE89140 + +#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE89144 + +#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE89148 + +#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE8914C + +#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE89150 + +#define mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE89154 + +#define mmTPC2_CMDQ_CP_FENCE0_RDATA 0xE89158 + +#define mmTPC2_CMDQ_CP_FENCE1_RDATA 0xE8915C + +#define mmTPC2_CMDQ_CP_FENCE2_RDATA 0xE89160 + +#define mmTPC2_CMDQ_CP_FENCE3_RDATA 0xE89164 + +#define mmTPC2_CMDQ_CP_FENCE0_CNT 0xE89168 + +#define mmTPC2_CMDQ_CP_FENCE1_CNT 0xE8916C + +#define mmTPC2_CMDQ_CP_FENCE2_CNT 0xE89170 + +#define mmTPC2_CMDQ_CP_FENCE3_CNT 0xE89174 + +#define mmTPC2_CMDQ_CP_STS 0xE89178 + +#define mmTPC2_CMDQ_CP_CURRENT_INST_LO 0xE8917C + +#define mmTPC2_CMDQ_CP_CURRENT_INST_HI 0xE89180 + +#define mmTPC2_CMDQ_CP_BARRIER_CFG 0xE89184 + +#define mmTPC2_CMDQ_CP_DBG_0 0xE89188 + +#define mmTPC2_CMDQ_CQ_BUF_ADDR 0xE89308 + +#define mmTPC2_CMDQ_CQ_BUF_RDATA 0xE8930C + +#endif /* ASIC_REG_TPC2_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h new file mode 100644 index 000000000000..f3e32c018064 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_QM_REGS_H_ +#define ASIC_REG_TPC2_QM_REGS_H_ + +/* + ***************************************** + * TPC2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC2_QM_GLBL_CFG0 0xE88000 + +#define mmTPC2_QM_GLBL_CFG1 0xE88004 + +#define mmTPC2_QM_GLBL_PROT 0xE88008 + +#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C + +#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88010 + +#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88014 + +#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88018 + +#define mmTPC2_QM_GLBL_SECURE_PROPS 0xE8801C + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS 0xE88020 + +#define mmTPC2_QM_GLBL_STS0 0xE88024 + +#define mmTPC2_QM_GLBL_STS1 0xE88028 + +#define mmTPC2_QM_PQ_BASE_LO 0xE88060 + +#define mmTPC2_QM_PQ_BASE_HI 0xE88064 + +#define mmTPC2_QM_PQ_SIZE 0xE88068 + +#define mmTPC2_QM_PQ_PI 0xE8806C + +#define mmTPC2_QM_PQ_CI 0xE88070 + +#define mmTPC2_QM_PQ_CFG0 0xE88074 + +#define mmTPC2_QM_PQ_CFG1 0xE88078 + +#define mmTPC2_QM_PQ_ARUSER 0xE8807C + +#define mmTPC2_QM_PQ_PUSH0 0xE88080 + +#define mmTPC2_QM_PQ_PUSH1 0xE88084 + +#define mmTPC2_QM_PQ_PUSH2 0xE88088 + +#define mmTPC2_QM_PQ_PUSH3 0xE8808C + +#define mmTPC2_QM_PQ_STS0 0xE88090 + +#define mmTPC2_QM_PQ_STS1 0xE88094 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_EN 0xE880A0 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE880A4 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_SAT 0xE880A8 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_TOUT 0xE880AC + +#define mmTPC2_QM_CQ_CFG0 0xE880B0 + +#define mmTPC2_QM_CQ_CFG1 0xE880B4 + +#define mmTPC2_QM_CQ_ARUSER 0xE880B8 + +#define mmTPC2_QM_CQ_PTR_LO 0xE880C0 + +#define mmTPC2_QM_CQ_PTR_HI 0xE880C4 + +#define mmTPC2_QM_CQ_TSIZE 0xE880C8 + +#define mmTPC2_QM_CQ_CTL 0xE880CC + +#define mmTPC2_QM_CQ_PTR_LO_STS 0xE880D4 + +#define mmTPC2_QM_CQ_PTR_HI_STS 0xE880D8 + +#define mmTPC2_QM_CQ_TSIZE_STS 0xE880DC + +#define mmTPC2_QM_CQ_CTL_STS 0xE880E0 + +#define mmTPC2_QM_CQ_STS0 0xE880E4 + +#define mmTPC2_QM_CQ_STS1 0xE880E8 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_EN 0xE880F0 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE880F4 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_SAT 0xE880F8 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_TOUT 0xE880FC + +#define mmTPC2_QM_CQ_IFIFO_CNT 0xE88108 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO 0xE88120 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI 0xE88124 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO 0xE88128 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI 0xE8812C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO 0xE88130 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI 0xE88134 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO 0xE88138 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI 0xE8813C + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET 0xE88140 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE88144 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE88148 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE8814C + +#define mmTPC2_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE88150 + +#define mmTPC2_QM_CP_LDMA_COMMIT_OFFSET 0xE88154 + +#define mmTPC2_QM_CP_FENCE0_RDATA 0xE88158 + +#define mmTPC2_QM_CP_FENCE1_RDATA 0xE8815C + +#define mmTPC2_QM_CP_FENCE2_RDATA 0xE88160 + +#define mmTPC2_QM_CP_FENCE3_RDATA 0xE88164 + +#define mmTPC2_QM_CP_FENCE0_CNT 0xE88168 + +#define mmTPC2_QM_CP_FENCE1_CNT 0xE8816C + +#define mmTPC2_QM_CP_FENCE2_CNT 0xE88170 + +#define mmTPC2_QM_CP_FENCE3_CNT 0xE88174 + +#define mmTPC2_QM_CP_STS 0xE88178 + +#define mmTPC2_QM_CP_CURRENT_INST_LO 0xE8817C + +#define mmTPC2_QM_CP_CURRENT_INST_HI 0xE88180 + +#define mmTPC2_QM_CP_BARRIER_CFG 0xE88184 + +#define mmTPC2_QM_CP_DBG_0 0xE88188 + +#define mmTPC2_QM_PQ_BUF_ADDR 0xE88300 + +#define mmTPC2_QM_PQ_BUF_RDATA 0xE88304 + +#define mmTPC2_QM_CQ_BUF_ADDR 0xE88308 + +#define mmTPC2_QM_CQ_BUF_RDATA 0xE8830C + +#endif /* ASIC_REG_TPC2_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h new file mode 100644 index 000000000000..0eb0cd1fbd19 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_RTR_REGS_H_ +#define ASIC_REG_TPC2_RTR_REGS_H_ + +/* + ***************************************** + * TPC2_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC2_RTR_HBW_RD_RQ_E_ARB 0xE80100 + +#define mmTPC2_RTR_HBW_RD_RQ_W_ARB 0xE80104 + +#define mmTPC2_RTR_HBW_RD_RQ_N_ARB 0xE80108 + +#define mmTPC2_RTR_HBW_RD_RQ_S_ARB 0xE8010C + +#define mmTPC2_RTR_HBW_RD_RQ_L_ARB 0xE80110 + +#define mmTPC2_RTR_HBW_E_ARB_MAX 0xE80120 + +#define mmTPC2_RTR_HBW_W_ARB_MAX 0xE80124 + +#define mmTPC2_RTR_HBW_N_ARB_MAX 0xE80128 + +#define mmTPC2_RTR_HBW_S_ARB_MAX 0xE8012C + +#define mmTPC2_RTR_HBW_L_ARB_MAX 0xE80130 + +#define mmTPC2_RTR_HBW_RD_RS_E_ARB 0xE80140 + +#define mmTPC2_RTR_HBW_RD_RS_W_ARB 0xE80144 + +#define mmTPC2_RTR_HBW_RD_RS_N_ARB 0xE80148 + +#define mmTPC2_RTR_HBW_RD_RS_S_ARB 0xE8014C + +#define mmTPC2_RTR_HBW_RD_RS_L_ARB 0xE80150 + +#define mmTPC2_RTR_HBW_WR_RQ_E_ARB 0xE80170 + +#define mmTPC2_RTR_HBW_WR_RQ_W_ARB 0xE80174 + +#define mmTPC2_RTR_HBW_WR_RQ_N_ARB 0xE80178 + +#define mmTPC2_RTR_HBW_WR_RQ_S_ARB 0xE8017C + +#define mmTPC2_RTR_HBW_WR_RQ_L_ARB 0xE80180 + +#define mmTPC2_RTR_HBW_WR_RS_E_ARB 0xE80190 + +#define mmTPC2_RTR_HBW_WR_RS_W_ARB 0xE80194 + +#define mmTPC2_RTR_HBW_WR_RS_N_ARB 0xE80198 + +#define mmTPC2_RTR_HBW_WR_RS_S_ARB 0xE8019C + +#define mmTPC2_RTR_HBW_WR_RS_L_ARB 0xE801A0 + +#define mmTPC2_RTR_LBW_RD_RQ_E_ARB 0xE80200 + +#define mmTPC2_RTR_LBW_RD_RQ_W_ARB 0xE80204 + +#define mmTPC2_RTR_LBW_RD_RQ_N_ARB 0xE80208 + +#define mmTPC2_RTR_LBW_RD_RQ_S_ARB 0xE8020C + +#define mmTPC2_RTR_LBW_RD_RQ_L_ARB 0xE80210 + +#define mmTPC2_RTR_LBW_E_ARB_MAX 0xE80220 + +#define mmTPC2_RTR_LBW_W_ARB_MAX 0xE80224 + +#define mmTPC2_RTR_LBW_N_ARB_MAX 0xE80228 + +#define mmTPC2_RTR_LBW_S_ARB_MAX 0xE8022C + +#define mmTPC2_RTR_LBW_L_ARB_MAX 0xE80230 + +#define mmTPC2_RTR_LBW_RD_RS_E_ARB 0xE80250 + +#define mmTPC2_RTR_LBW_RD_RS_W_ARB 0xE80254 + +#define mmTPC2_RTR_LBW_RD_RS_N_ARB 0xE80258 + +#define mmTPC2_RTR_LBW_RD_RS_S_ARB 0xE8025C + +#define mmTPC2_RTR_LBW_RD_RS_L_ARB 0xE80260 + +#define mmTPC2_RTR_LBW_WR_RQ_E_ARB 0xE80270 + +#define mmTPC2_RTR_LBW_WR_RQ_W_ARB 0xE80274 + +#define mmTPC2_RTR_LBW_WR_RQ_N_ARB 0xE80278 + +#define mmTPC2_RTR_LBW_WR_RQ_S_ARB 0xE8027C + +#define mmTPC2_RTR_LBW_WR_RQ_L_ARB 0xE80280 + +#define mmTPC2_RTR_LBW_WR_RS_E_ARB 0xE80290 + +#define mmTPC2_RTR_LBW_WR_RS_W_ARB 0xE80294 + +#define mmTPC2_RTR_LBW_WR_RS_N_ARB 0xE80298 + +#define mmTPC2_RTR_LBW_WR_RS_S_ARB 0xE8029C + +#define mmTPC2_RTR_LBW_WR_RS_L_ARB 0xE802A0 + +#define mmTPC2_RTR_DBG_E_ARB 0xE80300 + +#define mmTPC2_RTR_DBG_W_ARB 0xE80304 + +#define mmTPC2_RTR_DBG_N_ARB 0xE80308 + +#define mmTPC2_RTR_DBG_S_ARB 0xE8030C + +#define mmTPC2_RTR_DBG_L_ARB 0xE80310 + +#define mmTPC2_RTR_DBG_E_ARB_MAX 0xE80320 + +#define mmTPC2_RTR_DBG_W_ARB_MAX 0xE80324 + +#define mmTPC2_RTR_DBG_N_ARB_MAX 0xE80328 + +#define mmTPC2_RTR_DBG_S_ARB_MAX 0xE8032C + +#define mmTPC2_RTR_DBG_L_ARB_MAX 0xE80330 + +#define mmTPC2_RTR_SPLIT_COEF_0 0xE80400 + +#define mmTPC2_RTR_SPLIT_COEF_1 0xE80404 + +#define mmTPC2_RTR_SPLIT_COEF_2 0xE80408 + +#define mmTPC2_RTR_SPLIT_COEF_3 0xE8040C + +#define mmTPC2_RTR_SPLIT_COEF_4 0xE80410 + +#define mmTPC2_RTR_SPLIT_COEF_5 0xE80414 + +#define mmTPC2_RTR_SPLIT_COEF_6 0xE80418 + +#define mmTPC2_RTR_SPLIT_COEF_7 0xE8041C + +#define mmTPC2_RTR_SPLIT_COEF_8 0xE80420 + +#define mmTPC2_RTR_SPLIT_COEF_9 0xE80424 + +#define mmTPC2_RTR_SPLIT_CFG 0xE80440 + +#define mmTPC2_RTR_SPLIT_RD_SAT 0xE80444 + +#define mmTPC2_RTR_SPLIT_RD_RST_TOKEN 0xE80448 + +#define mmTPC2_RTR_SPLIT_RD_TIMEOUT_0 0xE8044C + +#define mmTPC2_RTR_SPLIT_RD_TIMEOUT_1 0xE80450 + +#define mmTPC2_RTR_SPLIT_WR_SAT 0xE80454 + +#define mmTPC2_RTR_WPLIT_WR_TST_TOLEN 0xE80458 + +#define mmTPC2_RTR_SPLIT_WR_TIMEOUT_0 0xE8045C + +#define mmTPC2_RTR_SPLIT_WR_TIMEOUT_1 0xE80460 + +#define mmTPC2_RTR_HBW_RANGE_HIT 0xE80470 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_0 0xE80480 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_1 0xE80484 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_2 0xE80488 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_3 0xE8048C + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_4 0xE80490 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_5 0xE80494 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_6 0xE80498 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_7 0xE8049C + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_0 0xE804A0 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_1 0xE804A4 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_2 0xE804A8 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_3 0xE804AC + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_4 0xE804B0 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_5 0xE804B4 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_6 0xE804B8 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_7 0xE804BC + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_0 0xE804C0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_1 0xE804C4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_2 0xE804C8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_3 0xE804CC + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_4 0xE804D0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_5 0xE804D4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_6 0xE804D8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_7 0xE804DC + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_0 0xE804E0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_1 0xE804E4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_2 0xE804E8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_3 0xE804EC + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_4 0xE804F0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_5 0xE804F4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_6 0xE804F8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_7 0xE804FC + +#define mmTPC2_RTR_LBW_RANGE_HIT 0xE80500 + +#define mmTPC2_RTR_LBW_RANGE_MASK_0 0xE80510 + +#define mmTPC2_RTR_LBW_RANGE_MASK_1 0xE80514 + +#define mmTPC2_RTR_LBW_RANGE_MASK_2 0xE80518 + +#define mmTPC2_RTR_LBW_RANGE_MASK_3 0xE8051C + +#define mmTPC2_RTR_LBW_RANGE_MASK_4 0xE80520 + +#define mmTPC2_RTR_LBW_RANGE_MASK_5 0xE80524 + +#define mmTPC2_RTR_LBW_RANGE_MASK_6 0xE80528 + +#define mmTPC2_RTR_LBW_RANGE_MASK_7 0xE8052C + +#define mmTPC2_RTR_LBW_RANGE_MASK_8 0xE80530 + +#define mmTPC2_RTR_LBW_RANGE_MASK_9 0xE80534 + +#define mmTPC2_RTR_LBW_RANGE_MASK_10 0xE80538 + +#define mmTPC2_RTR_LBW_RANGE_MASK_11 0xE8053C + +#define mmTPC2_RTR_LBW_RANGE_MASK_12 0xE80540 + +#define mmTPC2_RTR_LBW_RANGE_MASK_13 0xE80544 + +#define mmTPC2_RTR_LBW_RANGE_MASK_14 0xE80548 + +#define mmTPC2_RTR_LBW_RANGE_MASK_15 0xE8054C + +#define mmTPC2_RTR_LBW_RANGE_BASE_0 0xE80550 + +#define mmTPC2_RTR_LBW_RANGE_BASE_1 0xE80554 + +#define mmTPC2_RTR_LBW_RANGE_BASE_2 0xE80558 + +#define mmTPC2_RTR_LBW_RANGE_BASE_3 0xE8055C + +#define mmTPC2_RTR_LBW_RANGE_BASE_4 0xE80560 + +#define mmTPC2_RTR_LBW_RANGE_BASE_5 0xE80564 + +#define mmTPC2_RTR_LBW_RANGE_BASE_6 0xE80568 + +#define mmTPC2_RTR_LBW_RANGE_BASE_7 0xE8056C + +#define mmTPC2_RTR_LBW_RANGE_BASE_8 0xE80570 + +#define mmTPC2_RTR_LBW_RANGE_BASE_9 0xE80574 + +#define mmTPC2_RTR_LBW_RANGE_BASE_10 0xE80578 + +#define mmTPC2_RTR_LBW_RANGE_BASE_11 0xE8057C + +#define mmTPC2_RTR_LBW_RANGE_BASE_12 0xE80580 + +#define mmTPC2_RTR_LBW_RANGE_BASE_13 0xE80584 + +#define mmTPC2_RTR_LBW_RANGE_BASE_14 0xE80588 + +#define mmTPC2_RTR_LBW_RANGE_BASE_15 0xE8058C + +#define mmTPC2_RTR_RGLTR 0xE80590 + +#define mmTPC2_RTR_RGLTR_WR_RESULT 0xE80594 + +#define mmTPC2_RTR_RGLTR_RD_RESULT 0xE80598 + +#define mmTPC2_RTR_SCRAMB_EN 0xE80600 + +#define mmTPC2_RTR_NON_LIN_SCRAMB 0xE80604 + +#endif /* ASIC_REG_TPC2_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h new file mode 100644 index 000000000000..0baf63c69b25 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_CFG_REGS_H_ +#define ASIC_REG_TPC3_CFG_REGS_H_ + +/* + ***************************************** + * TPC3_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xEC6418 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC641C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC6420 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xEC6424 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6428 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC642C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xEC6430 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6434 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC6438 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xEC643C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6440 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6444 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xEC6448 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC644C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC6450 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6454 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6458 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC645C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC6460 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xEC6464 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6468 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC646C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xEC6470 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6474 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC6478 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xEC647C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6480 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6484 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xEC6488 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC648C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC6490 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xEC6494 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6498 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC649C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC64A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC64A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC64A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC64AC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xEC64B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC64B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC64B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xEC64BC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC64C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC64C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xEC64C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC64CC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC64D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xEC64D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64DC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xEC64E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64EC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xEC64FC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC6500 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC6504 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xEC6508 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC650C + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC6510 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xEC6514 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC6518 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC651C + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xEC6520 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC6524 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC6528 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xEC652C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC6530 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC6534 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC6538 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC653C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC6540 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC6544 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xEC6548 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC654C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC6550 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xEC6554 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6558 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC655C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xEC6560 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6564 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC6568 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xEC656C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6570 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6574 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xEC6578 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC657C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC6580 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6584 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6588 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC658C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC6590 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xEC6594 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6598 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC659C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xEC65A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC65A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC65A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xEC65AC + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC65B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC65B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xEC65B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC65BC + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC65C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xEC65C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC65C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC65CC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC65D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC65D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC65D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC65DC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xEC65E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC65E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC65E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xEC65EC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC65F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC65F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xEC65F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC65FC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC6600 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xEC6604 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6608 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC660C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xEC6610 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6614 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC6618 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC661C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6620 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6624 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC6628 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xEC662C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC6630 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC6634 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xEC6638 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC663C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC6640 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xEC6644 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC6648 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC664C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xEC6650 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC6654 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC6658 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xEC665C + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6660 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC6664 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6668 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC666C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6670 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC6674 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC6678 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC667C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC6680 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC6684 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC6688 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC668C + +#define mmTPC3_CFG_KERNEL_SRF_0 0xEC6690 + +#define mmTPC3_CFG_KERNEL_SRF_1 0xEC6694 + +#define mmTPC3_CFG_KERNEL_SRF_2 0xEC6698 + +#define mmTPC3_CFG_KERNEL_SRF_3 0xEC669C + +#define mmTPC3_CFG_KERNEL_SRF_4 0xEC66A0 + +#define mmTPC3_CFG_KERNEL_SRF_5 0xEC66A4 + +#define mmTPC3_CFG_KERNEL_SRF_6 0xEC66A8 + +#define mmTPC3_CFG_KERNEL_SRF_7 0xEC66AC + +#define mmTPC3_CFG_KERNEL_SRF_8 0xEC66B0 + +#define mmTPC3_CFG_KERNEL_SRF_9 0xEC66B4 + +#define mmTPC3_CFG_KERNEL_SRF_10 0xEC66B8 + +#define mmTPC3_CFG_KERNEL_SRF_11 0xEC66BC + +#define mmTPC3_CFG_KERNEL_SRF_12 0xEC66C0 + +#define mmTPC3_CFG_KERNEL_SRF_13 0xEC66C4 + +#define mmTPC3_CFG_KERNEL_SRF_14 0xEC66C8 + +#define mmTPC3_CFG_KERNEL_SRF_15 0xEC66CC + +#define mmTPC3_CFG_KERNEL_SRF_16 0xEC66D0 + +#define mmTPC3_CFG_KERNEL_SRF_17 0xEC66D4 + +#define mmTPC3_CFG_KERNEL_SRF_18 0xEC66D8 + +#define mmTPC3_CFG_KERNEL_SRF_19 0xEC66DC + +#define mmTPC3_CFG_KERNEL_SRF_20 0xEC66E0 + +#define mmTPC3_CFG_KERNEL_SRF_21 0xEC66E4 + +#define mmTPC3_CFG_KERNEL_SRF_22 0xEC66E8 + +#define mmTPC3_CFG_KERNEL_SRF_23 0xEC66EC + +#define mmTPC3_CFG_KERNEL_SRF_24 0xEC66F0 + +#define mmTPC3_CFG_KERNEL_SRF_25 0xEC66F4 + +#define mmTPC3_CFG_KERNEL_SRF_26 0xEC66F8 + +#define mmTPC3_CFG_KERNEL_SRF_27 0xEC66FC + +#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6700 + +#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6704 + +#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6708 + +#define mmTPC3_CFG_KERNEL_SRF_31 0xEC670C + +#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC6710 + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6714 + +#define mmTPC3_CFG_RESERVED_DESC_END 0xEC6738 + +#define mmTPC3_CFG_ROUND_CSR 0xEC67FC + +#define mmTPC3_CFG_TBUF_BASE_ADDR_LOW 0xEC6800 + +#define mmTPC3_CFG_TBUF_BASE_ADDR_HIGH 0xEC6804 + +#define mmTPC3_CFG_SEMAPHORE 0xEC6808 + +#define mmTPC3_CFG_VFLAGS 0xEC680C + +#define mmTPC3_CFG_SFLAGS 0xEC6810 + +#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6818 + +#define mmTPC3_CFG_STATUS 0xEC681C + +#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6820 + +#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6824 + +#define mmTPC3_CFG_SM_BASE_ADDRESS_LOW 0xEC6828 + +#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC682C + +#define mmTPC3_CFG_TPC_CMD 0xEC6830 + +#define mmTPC3_CFG_TPC_EXECUTE 0xEC6838 + +#define mmTPC3_CFG_TPC_STALL 0xEC683C + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6840 + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6844 + +#define mmTPC3_CFG_MSS_CONFIG 0xEC6854 + +#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6858 + +#define mmTPC3_CFG_TPC_INTR_MASK 0xEC685C + +#define mmTPC3_CFG_TSB_CONFIG 0xEC6860 + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00 + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04 + +#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08 + +#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xEC6A18 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A1C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A20 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xEC6A24 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A28 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A2C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xEC6A30 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A34 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A38 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xEC6A3C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A40 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A44 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xEC6A48 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A4C + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A50 + +#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A54 + +#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A58 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A5C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A60 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xEC6A64 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A68 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A6C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xEC6A70 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A74 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A78 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xEC6A7C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A80 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A84 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xEC6A88 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A8C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A90 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xEC6A94 + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A98 + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A9C + +#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6AA0 + +#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6AA4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6AA8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6AAC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xEC6AB0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6AB4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6AB8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xEC6ABC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6AC0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6AC4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xEC6AC8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6ACC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6AD0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xEC6AD4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AD8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6ADC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xEC6AE0 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AE4 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AE8 + +#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AEC + +#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AF0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AF4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6AF8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xEC6AFC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6B00 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6B04 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xEC6B08 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6B0C + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6B10 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xEC6B14 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6B18 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6B1C + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xEC6B20 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6B24 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6B28 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xEC6B2C + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6B30 + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6B34 + +#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6B38 + +#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6B3C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6B40 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6B44 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xEC6B48 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6B4C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6B50 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xEC6B54 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B58 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B5C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xEC6B60 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B64 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B68 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xEC6B6C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B70 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B74 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xEC6B78 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B7C + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B80 + +#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B84 + +#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B88 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B8C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B90 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xEC6B94 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B98 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B9C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xEC6BA0 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6BA4 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6BA8 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xEC6BAC + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6BB0 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6BB4 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xEC6BB8 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6BBC + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6BC0 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xEC6BC4 + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6BC8 + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6BCC + +#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6BD0 + +#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6BD4 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6BD8 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6BDC + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xEC6BE0 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6BE4 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6BE8 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xEC6BEC + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6BF0 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6BF4 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xEC6BF8 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6BFC + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6C00 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xEC6C04 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6C08 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6C0C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xEC6C10 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6C14 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6C18 + +#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6C1C + +#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6C20 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6C24 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6C28 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xEC6C2C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6C30 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6C34 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xEC6C38 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6C3C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6C40 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xEC6C44 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6C48 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6C4C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xEC6C50 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6C54 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6C58 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xEC6C5C + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6C60 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6C64 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6C68 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6C6C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6C70 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6C74 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6C78 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6C7C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6C80 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6C84 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6C88 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6C8C + +#define mmTPC3_CFG_QM_SRF_0 0xEC6C90 + +#define mmTPC3_CFG_QM_SRF_1 0xEC6C94 + +#define mmTPC3_CFG_QM_SRF_2 0xEC6C98 + +#define mmTPC3_CFG_QM_SRF_3 0xEC6C9C + +#define mmTPC3_CFG_QM_SRF_4 0xEC6CA0 + +#define mmTPC3_CFG_QM_SRF_5 0xEC6CA4 + +#define mmTPC3_CFG_QM_SRF_6 0xEC6CA8 + +#define mmTPC3_CFG_QM_SRF_7 0xEC6CAC + +#define mmTPC3_CFG_QM_SRF_8 0xEC6CB0 + +#define mmTPC3_CFG_QM_SRF_9 0xEC6CB4 + +#define mmTPC3_CFG_QM_SRF_10 0xEC6CB8 + +#define mmTPC3_CFG_QM_SRF_11 0xEC6CBC + +#define mmTPC3_CFG_QM_SRF_12 0xEC6CC0 + +#define mmTPC3_CFG_QM_SRF_13 0xEC6CC4 + +#define mmTPC3_CFG_QM_SRF_14 0xEC6CC8 + +#define mmTPC3_CFG_QM_SRF_15 0xEC6CCC + +#define mmTPC3_CFG_QM_SRF_16 0xEC6CD0 + +#define mmTPC3_CFG_QM_SRF_17 0xEC6CD4 + +#define mmTPC3_CFG_QM_SRF_18 0xEC6CD8 + +#define mmTPC3_CFG_QM_SRF_19 0xEC6CDC + +#define mmTPC3_CFG_QM_SRF_20 0xEC6CE0 + +#define mmTPC3_CFG_QM_SRF_21 0xEC6CE4 + +#define mmTPC3_CFG_QM_SRF_22 0xEC6CE8 + +#define mmTPC3_CFG_QM_SRF_23 0xEC6CEC + +#define mmTPC3_CFG_QM_SRF_24 0xEC6CF0 + +#define mmTPC3_CFG_QM_SRF_25 0xEC6CF4 + +#define mmTPC3_CFG_QM_SRF_26 0xEC6CF8 + +#define mmTPC3_CFG_QM_SRF_27 0xEC6CFC + +#define mmTPC3_CFG_QM_SRF_28 0xEC6D00 + +#define mmTPC3_CFG_QM_SRF_29 0xEC6D04 + +#define mmTPC3_CFG_QM_SRF_30 0xEC6D08 + +#define mmTPC3_CFG_QM_SRF_31 0xEC6D0C + +#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6D10 + +#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D14 + +#define mmTPC3_CFG_ARUSER 0xEC6D18 + +#define mmTPC3_CFG_AWUSER 0xEC6D1C + +#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC6E00 + +#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC6E04 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC6E08 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC6E0C + +#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC6E10 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC6E14 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC6E18 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC6E1C + +#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC6E20 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC6E24 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC6E28 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC6E2C + +#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h new file mode 100644 index 000000000000..82a5261e852f --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_CMDQ_REGS_H_ +#define ASIC_REG_TPC3_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC3_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC3_CMDQ_GLBL_CFG0 0xEC9000 + +#define mmTPC3_CMDQ_GLBL_CFG1 0xEC9004 + +#define mmTPC3_CMDQ_GLBL_PROT 0xEC9008 + +#define mmTPC3_CMDQ_GLBL_ERR_CFG 0xEC900C + +#define mmTPC3_CMDQ_GLBL_ERR_ADDR_LO 0xEC9010 + +#define mmTPC3_CMDQ_GLBL_ERR_ADDR_HI 0xEC9014 + +#define mmTPC3_CMDQ_GLBL_ERR_WDATA 0xEC9018 + +#define mmTPC3_CMDQ_GLBL_SECURE_PROPS 0xEC901C + +#define mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS 0xEC9020 + +#define mmTPC3_CMDQ_GLBL_STS0 0xEC9024 + +#define mmTPC3_CMDQ_GLBL_STS1 0xEC9028 + +#define mmTPC3_CMDQ_CQ_CFG0 0xEC90B0 + +#define mmTPC3_CMDQ_CQ_CFG1 0xEC90B4 + +#define mmTPC3_CMDQ_CQ_ARUSER 0xEC90B8 + +#define mmTPC3_CMDQ_CQ_PTR_LO 0xEC90C0 + +#define mmTPC3_CMDQ_CQ_PTR_HI 0xEC90C4 + +#define mmTPC3_CMDQ_CQ_TSIZE 0xEC90C8 + +#define mmTPC3_CMDQ_CQ_CTL 0xEC90CC + +#define mmTPC3_CMDQ_CQ_PTR_LO_STS 0xEC90D4 + +#define mmTPC3_CMDQ_CQ_PTR_HI_STS 0xEC90D8 + +#define mmTPC3_CMDQ_CQ_TSIZE_STS 0xEC90DC + +#define mmTPC3_CMDQ_CQ_CTL_STS 0xEC90E0 + +#define mmTPC3_CMDQ_CQ_STS0 0xEC90E4 + +#define mmTPC3_CMDQ_CQ_STS1 0xEC90E8 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN 0xEC90F0 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xEC90F4 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT 0xEC90F8 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT 0xEC90FC + +#define mmTPC3_CMDQ_CQ_IFIFO_CNT 0xEC9108 + +#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO 0xEC9120 + +#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI 0xEC9124 + +#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO 0xEC9128 + +#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI 0xEC912C + +#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO 0xEC9130 + +#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI 0xEC9134 + +#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO 0xEC9138 + +#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI 0xEC913C + +#define mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET 0xEC9140 + +#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xEC9144 + +#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xEC9148 + +#define mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xEC914C + +#define mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xEC9150 + +#define mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET 0xEC9154 + +#define mmTPC3_CMDQ_CP_FENCE0_RDATA 0xEC9158 + +#define mmTPC3_CMDQ_CP_FENCE1_RDATA 0xEC915C + +#define mmTPC3_CMDQ_CP_FENCE2_RDATA 0xEC9160 + +#define mmTPC3_CMDQ_CP_FENCE3_RDATA 0xEC9164 + +#define mmTPC3_CMDQ_CP_FENCE0_CNT 0xEC9168 + +#define mmTPC3_CMDQ_CP_FENCE1_CNT 0xEC916C + +#define mmTPC3_CMDQ_CP_FENCE2_CNT 0xEC9170 + +#define mmTPC3_CMDQ_CP_FENCE3_CNT 0xEC9174 + +#define mmTPC3_CMDQ_CP_STS 0xEC9178 + +#define mmTPC3_CMDQ_CP_CURRENT_INST_LO 0xEC917C + +#define mmTPC3_CMDQ_CP_CURRENT_INST_HI 0xEC9180 + +#define mmTPC3_CMDQ_CP_BARRIER_CFG 0xEC9184 + +#define mmTPC3_CMDQ_CP_DBG_0 0xEC9188 + +#define mmTPC3_CMDQ_CQ_BUF_ADDR 0xEC9308 + +#define mmTPC3_CMDQ_CQ_BUF_RDATA 0xEC930C + +#endif /* ASIC_REG_TPC3_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h new file mode 100644 index 000000000000..b05b1e18e664 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_QM_REGS_H_ +#define ASIC_REG_TPC3_QM_REGS_H_ + +/* + ***************************************** + * TPC3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC3_QM_GLBL_CFG0 0xEC8000 + +#define mmTPC3_QM_GLBL_CFG1 0xEC8004 + +#define mmTPC3_QM_GLBL_PROT 0xEC8008 + +#define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C + +#define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8010 + +#define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8014 + +#define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8018 + +#define mmTPC3_QM_GLBL_SECURE_PROPS 0xEC801C + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS 0xEC8020 + +#define mmTPC3_QM_GLBL_STS0 0xEC8024 + +#define mmTPC3_QM_GLBL_STS1 0xEC8028 + +#define mmTPC3_QM_PQ_BASE_LO 0xEC8060 + +#define mmTPC3_QM_PQ_BASE_HI 0xEC8064 + +#define mmTPC3_QM_PQ_SIZE 0xEC8068 + +#define mmTPC3_QM_PQ_PI 0xEC806C + +#define mmTPC3_QM_PQ_CI 0xEC8070 + +#define mmTPC3_QM_PQ_CFG0 0xEC8074 + +#define mmTPC3_QM_PQ_CFG1 0xEC8078 + +#define mmTPC3_QM_PQ_ARUSER 0xEC807C + +#define mmTPC3_QM_PQ_PUSH0 0xEC8080 + +#define mmTPC3_QM_PQ_PUSH1 0xEC8084 + +#define mmTPC3_QM_PQ_PUSH2 0xEC8088 + +#define mmTPC3_QM_PQ_PUSH3 0xEC808C + +#define mmTPC3_QM_PQ_STS0 0xEC8090 + +#define mmTPC3_QM_PQ_STS1 0xEC8094 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_EN 0xEC80A0 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xEC80A4 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_SAT 0xEC80A8 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_TOUT 0xEC80AC + +#define mmTPC3_QM_CQ_CFG0 0xEC80B0 + +#define mmTPC3_QM_CQ_CFG1 0xEC80B4 + +#define mmTPC3_QM_CQ_ARUSER 0xEC80B8 + +#define mmTPC3_QM_CQ_PTR_LO 0xEC80C0 + +#define mmTPC3_QM_CQ_PTR_HI 0xEC80C4 + +#define mmTPC3_QM_CQ_TSIZE 0xEC80C8 + +#define mmTPC3_QM_CQ_CTL 0xEC80CC + +#define mmTPC3_QM_CQ_PTR_LO_STS 0xEC80D4 + +#define mmTPC3_QM_CQ_PTR_HI_STS 0xEC80D8 + +#define mmTPC3_QM_CQ_TSIZE_STS 0xEC80DC + +#define mmTPC3_QM_CQ_CTL_STS 0xEC80E0 + +#define mmTPC3_QM_CQ_STS0 0xEC80E4 + +#define mmTPC3_QM_CQ_STS1 0xEC80E8 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_EN 0xEC80F0 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xEC80F4 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_SAT 0xEC80F8 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_TOUT 0xEC80FC + +#define mmTPC3_QM_CQ_IFIFO_CNT 0xEC8108 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO 0xEC8120 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI 0xEC8124 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO 0xEC8128 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI 0xEC812C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO 0xEC8130 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI 0xEC8134 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO 0xEC8138 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI 0xEC813C + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET 0xEC8140 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xEC8144 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xEC8148 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xEC814C + +#define mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xEC8150 + +#define mmTPC3_QM_CP_LDMA_COMMIT_OFFSET 0xEC8154 + +#define mmTPC3_QM_CP_FENCE0_RDATA 0xEC8158 + +#define mmTPC3_QM_CP_FENCE1_RDATA 0xEC815C + +#define mmTPC3_QM_CP_FENCE2_RDATA 0xEC8160 + +#define mmTPC3_QM_CP_FENCE3_RDATA 0xEC8164 + +#define mmTPC3_QM_CP_FENCE0_CNT 0xEC8168 + +#define mmTPC3_QM_CP_FENCE1_CNT 0xEC816C + +#define mmTPC3_QM_CP_FENCE2_CNT 0xEC8170 + +#define mmTPC3_QM_CP_FENCE3_CNT 0xEC8174 + +#define mmTPC3_QM_CP_STS 0xEC8178 + +#define mmTPC3_QM_CP_CURRENT_INST_LO 0xEC817C + +#define mmTPC3_QM_CP_CURRENT_INST_HI 0xEC8180 + +#define mmTPC3_QM_CP_BARRIER_CFG 0xEC8184 + +#define mmTPC3_QM_CP_DBG_0 0xEC8188 + +#define mmTPC3_QM_PQ_BUF_ADDR 0xEC8300 + +#define mmTPC3_QM_PQ_BUF_RDATA 0xEC8304 + +#define mmTPC3_QM_CQ_BUF_ADDR 0xEC8308 + +#define mmTPC3_QM_CQ_BUF_RDATA 0xEC830C + +#endif /* ASIC_REG_TPC3_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h new file mode 100644 index 000000000000..5a2fd7652650 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_RTR_REGS_H_ +#define ASIC_REG_TPC3_RTR_REGS_H_ + +/* + ***************************************** + * TPC3_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC3_RTR_HBW_RD_RQ_E_ARB 0xEC0100 + +#define mmTPC3_RTR_HBW_RD_RQ_W_ARB 0xEC0104 + +#define mmTPC3_RTR_HBW_RD_RQ_N_ARB 0xEC0108 + +#define mmTPC3_RTR_HBW_RD_RQ_S_ARB 0xEC010C + +#define mmTPC3_RTR_HBW_RD_RQ_L_ARB 0xEC0110 + +#define mmTPC3_RTR_HBW_E_ARB_MAX 0xEC0120 + +#define mmTPC3_RTR_HBW_W_ARB_MAX 0xEC0124 + +#define mmTPC3_RTR_HBW_N_ARB_MAX 0xEC0128 + +#define mmTPC3_RTR_HBW_S_ARB_MAX 0xEC012C + +#define mmTPC3_RTR_HBW_L_ARB_MAX 0xEC0130 + +#define mmTPC3_RTR_HBW_RD_RS_E_ARB 0xEC0140 + +#define mmTPC3_RTR_HBW_RD_RS_W_ARB 0xEC0144 + +#define mmTPC3_RTR_HBW_RD_RS_N_ARB 0xEC0148 + +#define mmTPC3_RTR_HBW_RD_RS_S_ARB 0xEC014C + +#define mmTPC3_RTR_HBW_RD_RS_L_ARB 0xEC0150 + +#define mmTPC3_RTR_HBW_WR_RQ_E_ARB 0xEC0170 + +#define mmTPC3_RTR_HBW_WR_RQ_W_ARB 0xEC0174 + +#define mmTPC3_RTR_HBW_WR_RQ_N_ARB 0xEC0178 + +#define mmTPC3_RTR_HBW_WR_RQ_S_ARB 0xEC017C + +#define mmTPC3_RTR_HBW_WR_RQ_L_ARB 0xEC0180 + +#define mmTPC3_RTR_HBW_WR_RS_E_ARB 0xEC0190 + +#define mmTPC3_RTR_HBW_WR_RS_W_ARB 0xEC0194 + +#define mmTPC3_RTR_HBW_WR_RS_N_ARB 0xEC0198 + +#define mmTPC3_RTR_HBW_WR_RS_S_ARB 0xEC019C + +#define mmTPC3_RTR_HBW_WR_RS_L_ARB 0xEC01A0 + +#define mmTPC3_RTR_LBW_RD_RQ_E_ARB 0xEC0200 + +#define mmTPC3_RTR_LBW_RD_RQ_W_ARB 0xEC0204 + +#define mmTPC3_RTR_LBW_RD_RQ_N_ARB 0xEC0208 + +#define mmTPC3_RTR_LBW_RD_RQ_S_ARB 0xEC020C + +#define mmTPC3_RTR_LBW_RD_RQ_L_ARB 0xEC0210 + +#define mmTPC3_RTR_LBW_E_ARB_MAX 0xEC0220 + +#define mmTPC3_RTR_LBW_W_ARB_MAX 0xEC0224 + +#define mmTPC3_RTR_LBW_N_ARB_MAX 0xEC0228 + +#define mmTPC3_RTR_LBW_S_ARB_MAX 0xEC022C + +#define mmTPC3_RTR_LBW_L_ARB_MAX 0xEC0230 + +#define mmTPC3_RTR_LBW_RD_RS_E_ARB 0xEC0250 + +#define mmTPC3_RTR_LBW_RD_RS_W_ARB 0xEC0254 + +#define mmTPC3_RTR_LBW_RD_RS_N_ARB 0xEC0258 + +#define mmTPC3_RTR_LBW_RD_RS_S_ARB 0xEC025C + +#define mmTPC3_RTR_LBW_RD_RS_L_ARB 0xEC0260 + +#define mmTPC3_RTR_LBW_WR_RQ_E_ARB 0xEC0270 + +#define mmTPC3_RTR_LBW_WR_RQ_W_ARB 0xEC0274 + +#define mmTPC3_RTR_LBW_WR_RQ_N_ARB 0xEC0278 + +#define mmTPC3_RTR_LBW_WR_RQ_S_ARB 0xEC027C + +#define mmTPC3_RTR_LBW_WR_RQ_L_ARB 0xEC0280 + +#define mmTPC3_RTR_LBW_WR_RS_E_ARB 0xEC0290 + +#define mmTPC3_RTR_LBW_WR_RS_W_ARB 0xEC0294 + +#define mmTPC3_RTR_LBW_WR_RS_N_ARB 0xEC0298 + +#define mmTPC3_RTR_LBW_WR_RS_S_ARB 0xEC029C + +#define mmTPC3_RTR_LBW_WR_RS_L_ARB 0xEC02A0 + +#define mmTPC3_RTR_DBG_E_ARB 0xEC0300 + +#define mmTPC3_RTR_DBG_W_ARB 0xEC0304 + +#define mmTPC3_RTR_DBG_N_ARB 0xEC0308 + +#define mmTPC3_RTR_DBG_S_ARB 0xEC030C + +#define mmTPC3_RTR_DBG_L_ARB 0xEC0310 + +#define mmTPC3_RTR_DBG_E_ARB_MAX 0xEC0320 + +#define mmTPC3_RTR_DBG_W_ARB_MAX 0xEC0324 + +#define mmTPC3_RTR_DBG_N_ARB_MAX 0xEC0328 + +#define mmTPC3_RTR_DBG_S_ARB_MAX 0xEC032C + +#define mmTPC3_RTR_DBG_L_ARB_MAX 0xEC0330 + +#define mmTPC3_RTR_SPLIT_COEF_0 0xEC0400 + +#define mmTPC3_RTR_SPLIT_COEF_1 0xEC0404 + +#define mmTPC3_RTR_SPLIT_COEF_2 0xEC0408 + +#define mmTPC3_RTR_SPLIT_COEF_3 0xEC040C + +#define mmTPC3_RTR_SPLIT_COEF_4 0xEC0410 + +#define mmTPC3_RTR_SPLIT_COEF_5 0xEC0414 + +#define mmTPC3_RTR_SPLIT_COEF_6 0xEC0418 + +#define mmTPC3_RTR_SPLIT_COEF_7 0xEC041C + +#define mmTPC3_RTR_SPLIT_COEF_8 0xEC0420 + +#define mmTPC3_RTR_SPLIT_COEF_9 0xEC0424 + +#define mmTPC3_RTR_SPLIT_CFG 0xEC0440 + +#define mmTPC3_RTR_SPLIT_RD_SAT 0xEC0444 + +#define mmTPC3_RTR_SPLIT_RD_RST_TOKEN 0xEC0448 + +#define mmTPC3_RTR_SPLIT_RD_TIMEOUT_0 0xEC044C + +#define mmTPC3_RTR_SPLIT_RD_TIMEOUT_1 0xEC0450 + +#define mmTPC3_RTR_SPLIT_WR_SAT 0xEC0454 + +#define mmTPC3_RTR_WPLIT_WR_TST_TOLEN 0xEC0458 + +#define mmTPC3_RTR_SPLIT_WR_TIMEOUT_0 0xEC045C + +#define mmTPC3_RTR_SPLIT_WR_TIMEOUT_1 0xEC0460 + +#define mmTPC3_RTR_HBW_RANGE_HIT 0xEC0470 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_0 0xEC0480 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_1 0xEC0484 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_2 0xEC0488 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_3 0xEC048C + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_4 0xEC0490 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_5 0xEC0494 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_6 0xEC0498 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_7 0xEC049C + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_0 0xEC04A0 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_1 0xEC04A4 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_2 0xEC04A8 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_3 0xEC04AC + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_4 0xEC04B0 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_5 0xEC04B4 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_6 0xEC04B8 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_7 0xEC04BC + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_0 0xEC04C0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_1 0xEC04C4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_2 0xEC04C8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_3 0xEC04CC + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_4 0xEC04D0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_5 0xEC04D4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_6 0xEC04D8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_7 0xEC04DC + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_0 0xEC04E0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_1 0xEC04E4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_2 0xEC04E8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_3 0xEC04EC + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_4 0xEC04F0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_5 0xEC04F4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_6 0xEC04F8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_7 0xEC04FC + +#define mmTPC3_RTR_LBW_RANGE_HIT 0xEC0500 + +#define mmTPC3_RTR_LBW_RANGE_MASK_0 0xEC0510 + +#define mmTPC3_RTR_LBW_RANGE_MASK_1 0xEC0514 + +#define mmTPC3_RTR_LBW_RANGE_MASK_2 0xEC0518 + +#define mmTPC3_RTR_LBW_RANGE_MASK_3 0xEC051C + +#define mmTPC3_RTR_LBW_RANGE_MASK_4 0xEC0520 + +#define mmTPC3_RTR_LBW_RANGE_MASK_5 0xEC0524 + +#define mmTPC3_RTR_LBW_RANGE_MASK_6 0xEC0528 + +#define mmTPC3_RTR_LBW_RANGE_MASK_7 0xEC052C + +#define mmTPC3_RTR_LBW_RANGE_MASK_8 0xEC0530 + +#define mmTPC3_RTR_LBW_RANGE_MASK_9 0xEC0534 + +#define mmTPC3_RTR_LBW_RANGE_MASK_10 0xEC0538 + +#define mmTPC3_RTR_LBW_RANGE_MASK_11 0xEC053C + +#define mmTPC3_RTR_LBW_RANGE_MASK_12 0xEC0540 + +#define mmTPC3_RTR_LBW_RANGE_MASK_13 0xEC0544 + +#define mmTPC3_RTR_LBW_RANGE_MASK_14 0xEC0548 + +#define mmTPC3_RTR_LBW_RANGE_MASK_15 0xEC054C + +#define mmTPC3_RTR_LBW_RANGE_BASE_0 0xEC0550 + +#define mmTPC3_RTR_LBW_RANGE_BASE_1 0xEC0554 + +#define mmTPC3_RTR_LBW_RANGE_BASE_2 0xEC0558 + +#define mmTPC3_RTR_LBW_RANGE_BASE_3 0xEC055C + +#define mmTPC3_RTR_LBW_RANGE_BASE_4 0xEC0560 + +#define mmTPC3_RTR_LBW_RANGE_BASE_5 0xEC0564 + +#define mmTPC3_RTR_LBW_RANGE_BASE_6 0xEC0568 + +#define mmTPC3_RTR_LBW_RANGE_BASE_7 0xEC056C + +#define mmTPC3_RTR_LBW_RANGE_BASE_8 0xEC0570 + +#define mmTPC3_RTR_LBW_RANGE_BASE_9 0xEC0574 + +#define mmTPC3_RTR_LBW_RANGE_BASE_10 0xEC0578 + +#define mmTPC3_RTR_LBW_RANGE_BASE_11 0xEC057C + +#define mmTPC3_RTR_LBW_RANGE_BASE_12 0xEC0580 + +#define mmTPC3_RTR_LBW_RANGE_BASE_13 0xEC0584 + +#define mmTPC3_RTR_LBW_RANGE_BASE_14 0xEC0588 + +#define mmTPC3_RTR_LBW_RANGE_BASE_15 0xEC058C + +#define mmTPC3_RTR_RGLTR 0xEC0590 + +#define mmTPC3_RTR_RGLTR_WR_RESULT 0xEC0594 + +#define mmTPC3_RTR_RGLTR_RD_RESULT 0xEC0598 + +#define mmTPC3_RTR_SCRAMB_EN 0xEC0600 + +#define mmTPC3_RTR_NON_LIN_SCRAMB 0xEC0604 + +#endif /* ASIC_REG_TPC3_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h new file mode 100644 index 000000000000..d64a100075f2 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_CFG_REGS_H_ +#define ASIC_REG_TPC4_CFG_REGS_H_ + +/* + ***************************************** + * TPC4_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF06418 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF0641C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF06420 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF06424 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06428 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF0642C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF06430 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06434 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF06438 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF0643C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06440 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06444 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF06448 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF0644C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF06450 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06454 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06458 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF0645C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF06460 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF06464 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06468 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF0646C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF06470 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06474 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF06478 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF0647C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06480 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06484 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF06488 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF0648C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF06490 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF06494 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06498 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF0649C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF064A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF064A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF064A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF064AC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF064B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF064B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF064B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF064BC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF064C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF064C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF064C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF064CC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF064D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF064D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064DC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF064E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064EC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF064FC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF06500 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF06504 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF06508 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF0650C + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF06510 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF06514 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF06518 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF0651C + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF06520 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF06524 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF06528 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF0652C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF06530 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF06534 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF06538 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF0653C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF06540 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF06544 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF06548 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF0654C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF06550 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF06554 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06558 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF0655C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF06560 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06564 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF06568 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF0656C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06570 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06574 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF06578 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF0657C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF06580 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06584 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06588 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF0658C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF06590 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF06594 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06598 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF0659C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF065A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF065A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF065A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF065AC + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF065B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF065B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF065B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF065BC + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF065C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF065C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF065C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF065CC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF065D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF065D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF065D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF065DC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF065E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF065E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF065E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF065EC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF065F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF065F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF065F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF065FC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF06600 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF06604 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06608 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF0660C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF06610 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06614 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF06618 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF0661C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06620 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06624 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF06628 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF0662C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF06630 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF06634 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF06638 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF0663C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF06640 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF06644 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF06648 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF0664C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF06650 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF06654 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF06658 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF0665C + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06660 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF06664 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06668 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF0666C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06670 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF06674 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF06678 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF0667C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF06680 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF06684 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF06688 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF0668C + +#define mmTPC4_CFG_KERNEL_SRF_0 0xF06690 + +#define mmTPC4_CFG_KERNEL_SRF_1 0xF06694 + +#define mmTPC4_CFG_KERNEL_SRF_2 0xF06698 + +#define mmTPC4_CFG_KERNEL_SRF_3 0xF0669C + +#define mmTPC4_CFG_KERNEL_SRF_4 0xF066A0 + +#define mmTPC4_CFG_KERNEL_SRF_5 0xF066A4 + +#define mmTPC4_CFG_KERNEL_SRF_6 0xF066A8 + +#define mmTPC4_CFG_KERNEL_SRF_7 0xF066AC + +#define mmTPC4_CFG_KERNEL_SRF_8 0xF066B0 + +#define mmTPC4_CFG_KERNEL_SRF_9 0xF066B4 + +#define mmTPC4_CFG_KERNEL_SRF_10 0xF066B8 + +#define mmTPC4_CFG_KERNEL_SRF_11 0xF066BC + +#define mmTPC4_CFG_KERNEL_SRF_12 0xF066C0 + +#define mmTPC4_CFG_KERNEL_SRF_13 0xF066C4 + +#define mmTPC4_CFG_KERNEL_SRF_14 0xF066C8 + +#define mmTPC4_CFG_KERNEL_SRF_15 0xF066CC + +#define mmTPC4_CFG_KERNEL_SRF_16 0xF066D0 + +#define mmTPC4_CFG_KERNEL_SRF_17 0xF066D4 + +#define mmTPC4_CFG_KERNEL_SRF_18 0xF066D8 + +#define mmTPC4_CFG_KERNEL_SRF_19 0xF066DC + +#define mmTPC4_CFG_KERNEL_SRF_20 0xF066E0 + +#define mmTPC4_CFG_KERNEL_SRF_21 0xF066E4 + +#define mmTPC4_CFG_KERNEL_SRF_22 0xF066E8 + +#define mmTPC4_CFG_KERNEL_SRF_23 0xF066EC + +#define mmTPC4_CFG_KERNEL_SRF_24 0xF066F0 + +#define mmTPC4_CFG_KERNEL_SRF_25 0xF066F4 + +#define mmTPC4_CFG_KERNEL_SRF_26 0xF066F8 + +#define mmTPC4_CFG_KERNEL_SRF_27 0xF066FC + +#define mmTPC4_CFG_KERNEL_SRF_28 0xF06700 + +#define mmTPC4_CFG_KERNEL_SRF_29 0xF06704 + +#define mmTPC4_CFG_KERNEL_SRF_30 0xF06708 + +#define mmTPC4_CFG_KERNEL_SRF_31 0xF0670C + +#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF06710 + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06714 + +#define mmTPC4_CFG_RESERVED_DESC_END 0xF06738 + +#define mmTPC4_CFG_ROUND_CSR 0xF067FC + +#define mmTPC4_CFG_TBUF_BASE_ADDR_LOW 0xF06800 + +#define mmTPC4_CFG_TBUF_BASE_ADDR_HIGH 0xF06804 + +#define mmTPC4_CFG_SEMAPHORE 0xF06808 + +#define mmTPC4_CFG_VFLAGS 0xF0680C + +#define mmTPC4_CFG_SFLAGS 0xF06810 + +#define mmTPC4_CFG_LFSR_POLYNOM 0xF06818 + +#define mmTPC4_CFG_STATUS 0xF0681C + +#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06820 + +#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06824 + +#define mmTPC4_CFG_SM_BASE_ADDRESS_LOW 0xF06828 + +#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0682C + +#define mmTPC4_CFG_TPC_CMD 0xF06830 + +#define mmTPC4_CFG_TPC_EXECUTE 0xF06838 + +#define mmTPC4_CFG_TPC_STALL 0xF0683C + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06840 + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06844 + +#define mmTPC4_CFG_MSS_CONFIG 0xF06854 + +#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06858 + +#define mmTPC4_CFG_TPC_INTR_MASK 0xF0685C + +#define mmTPC4_CFG_TSB_CONFIG 0xF06860 + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 + +#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 + +#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF06A18 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A1C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A20 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF06A24 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A28 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A2C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF06A30 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A34 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A38 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF06A3C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A40 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A44 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF06A48 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A4C + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A50 + +#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A54 + +#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A58 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A5C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A60 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF06A64 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A68 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A6C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF06A70 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A74 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A78 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF06A7C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A80 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A84 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF06A88 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A8C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A90 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF06A94 + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A98 + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A9C + +#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06AA0 + +#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06AA4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06AA8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06AAC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF06AB0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06AB4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06AB8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF06ABC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06AC0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06AC4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF06AC8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06ACC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06AD0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF06AD4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AD8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06ADC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF06AE0 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AE4 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AE8 + +#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AEC + +#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AF0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AF4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06AF8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF06AFC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06B00 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06B04 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF06B08 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06B0C + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06B10 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF06B14 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06B18 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06B1C + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF06B20 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06B24 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06B28 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF06B2C + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06B30 + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06B34 + +#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06B38 + +#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06B3C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06B40 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06B44 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF06B48 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06B4C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06B50 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF06B54 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B58 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B5C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF06B60 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B64 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B68 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF06B6C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B70 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B74 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF06B78 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B7C + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B80 + +#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B84 + +#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B88 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B8C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B90 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF06B94 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B98 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B9C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF06BA0 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06BA4 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06BA8 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF06BAC + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06BB0 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06BB4 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF06BB8 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06BBC + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06BC0 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF06BC4 + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06BC8 + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06BCC + +#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06BD0 + +#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06BD4 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06BD8 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06BDC + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF06BE0 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06BE4 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06BE8 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF06BEC + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06BF0 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06BF4 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF06BF8 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06BFC + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06C00 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF06C04 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06C08 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06C0C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF06C10 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06C14 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06C18 + +#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06C1C + +#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06C20 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06C24 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06C28 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF06C2C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06C30 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06C34 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF06C38 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06C3C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06C40 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF06C44 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06C48 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06C4C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF06C50 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06C54 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06C58 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF06C5C + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06C60 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06C64 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06C68 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06C6C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06C70 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06C74 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06C78 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06C7C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06C80 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06C84 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06C88 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06C8C + +#define mmTPC4_CFG_QM_SRF_0 0xF06C90 + +#define mmTPC4_CFG_QM_SRF_1 0xF06C94 + +#define mmTPC4_CFG_QM_SRF_2 0xF06C98 + +#define mmTPC4_CFG_QM_SRF_3 0xF06C9C + +#define mmTPC4_CFG_QM_SRF_4 0xF06CA0 + +#define mmTPC4_CFG_QM_SRF_5 0xF06CA4 + +#define mmTPC4_CFG_QM_SRF_6 0xF06CA8 + +#define mmTPC4_CFG_QM_SRF_7 0xF06CAC + +#define mmTPC4_CFG_QM_SRF_8 0xF06CB0 + +#define mmTPC4_CFG_QM_SRF_9 0xF06CB4 + +#define mmTPC4_CFG_QM_SRF_10 0xF06CB8 + +#define mmTPC4_CFG_QM_SRF_11 0xF06CBC + +#define mmTPC4_CFG_QM_SRF_12 0xF06CC0 + +#define mmTPC4_CFG_QM_SRF_13 0xF06CC4 + +#define mmTPC4_CFG_QM_SRF_14 0xF06CC8 + +#define mmTPC4_CFG_QM_SRF_15 0xF06CCC + +#define mmTPC4_CFG_QM_SRF_16 0xF06CD0 + +#define mmTPC4_CFG_QM_SRF_17 0xF06CD4 + +#define mmTPC4_CFG_QM_SRF_18 0xF06CD8 + +#define mmTPC4_CFG_QM_SRF_19 0xF06CDC + +#define mmTPC4_CFG_QM_SRF_20 0xF06CE0 + +#define mmTPC4_CFG_QM_SRF_21 0xF06CE4 + +#define mmTPC4_CFG_QM_SRF_22 0xF06CE8 + +#define mmTPC4_CFG_QM_SRF_23 0xF06CEC + +#define mmTPC4_CFG_QM_SRF_24 0xF06CF0 + +#define mmTPC4_CFG_QM_SRF_25 0xF06CF4 + +#define mmTPC4_CFG_QM_SRF_26 0xF06CF8 + +#define mmTPC4_CFG_QM_SRF_27 0xF06CFC + +#define mmTPC4_CFG_QM_SRF_28 0xF06D00 + +#define mmTPC4_CFG_QM_SRF_29 0xF06D04 + +#define mmTPC4_CFG_QM_SRF_30 0xF06D08 + +#define mmTPC4_CFG_QM_SRF_31 0xF06D0C + +#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06D10 + +#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D14 + +#define mmTPC4_CFG_ARUSER 0xF06D18 + +#define mmTPC4_CFG_AWUSER 0xF06D1C + +#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF06E00 + +#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF06E04 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF06E08 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF06E0C + +#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF06E10 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF06E14 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF06E18 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF06E1C + +#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF06E20 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF06E24 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF06E28 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF06E2C + +#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h new file mode 100644 index 000000000000..565b42885b0d --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_CMDQ_REGS_H_ +#define ASIC_REG_TPC4_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC4_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC4_CMDQ_GLBL_CFG0 0xF09000 + +#define mmTPC4_CMDQ_GLBL_CFG1 0xF09004 + +#define mmTPC4_CMDQ_GLBL_PROT 0xF09008 + +#define mmTPC4_CMDQ_GLBL_ERR_CFG 0xF0900C + +#define mmTPC4_CMDQ_GLBL_ERR_ADDR_LO 0xF09010 + +#define mmTPC4_CMDQ_GLBL_ERR_ADDR_HI 0xF09014 + +#define mmTPC4_CMDQ_GLBL_ERR_WDATA 0xF09018 + +#define mmTPC4_CMDQ_GLBL_SECURE_PROPS 0xF0901C + +#define mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS 0xF09020 + +#define mmTPC4_CMDQ_GLBL_STS0 0xF09024 + +#define mmTPC4_CMDQ_GLBL_STS1 0xF09028 + +#define mmTPC4_CMDQ_CQ_CFG0 0xF090B0 + +#define mmTPC4_CMDQ_CQ_CFG1 0xF090B4 + +#define mmTPC4_CMDQ_CQ_ARUSER 0xF090B8 + +#define mmTPC4_CMDQ_CQ_PTR_LO 0xF090C0 + +#define mmTPC4_CMDQ_CQ_PTR_HI 0xF090C4 + +#define mmTPC4_CMDQ_CQ_TSIZE 0xF090C8 + +#define mmTPC4_CMDQ_CQ_CTL 0xF090CC + +#define mmTPC4_CMDQ_CQ_PTR_LO_STS 0xF090D4 + +#define mmTPC4_CMDQ_CQ_PTR_HI_STS 0xF090D8 + +#define mmTPC4_CMDQ_CQ_TSIZE_STS 0xF090DC + +#define mmTPC4_CMDQ_CQ_CTL_STS 0xF090E0 + +#define mmTPC4_CMDQ_CQ_STS0 0xF090E4 + +#define mmTPC4_CMDQ_CQ_STS1 0xF090E8 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN 0xF090F0 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF090F4 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT 0xF090F8 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF090FC + +#define mmTPC4_CMDQ_CQ_IFIFO_CNT 0xF09108 + +#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF09120 + +#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF09124 + +#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF09128 + +#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF0912C + +#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF09130 + +#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF09134 + +#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF09138 + +#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF0913C + +#define mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF09140 + +#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF09144 + +#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF09148 + +#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF0914C + +#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF09150 + +#define mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF09154 + +#define mmTPC4_CMDQ_CP_FENCE0_RDATA 0xF09158 + +#define mmTPC4_CMDQ_CP_FENCE1_RDATA 0xF0915C + +#define mmTPC4_CMDQ_CP_FENCE2_RDATA 0xF09160 + +#define mmTPC4_CMDQ_CP_FENCE3_RDATA 0xF09164 + +#define mmTPC4_CMDQ_CP_FENCE0_CNT 0xF09168 + +#define mmTPC4_CMDQ_CP_FENCE1_CNT 0xF0916C + +#define mmTPC4_CMDQ_CP_FENCE2_CNT 0xF09170 + +#define mmTPC4_CMDQ_CP_FENCE3_CNT 0xF09174 + +#define mmTPC4_CMDQ_CP_STS 0xF09178 + +#define mmTPC4_CMDQ_CP_CURRENT_INST_LO 0xF0917C + +#define mmTPC4_CMDQ_CP_CURRENT_INST_HI 0xF09180 + +#define mmTPC4_CMDQ_CP_BARRIER_CFG 0xF09184 + +#define mmTPC4_CMDQ_CP_DBG_0 0xF09188 + +#define mmTPC4_CMDQ_CQ_BUF_ADDR 0xF09308 + +#define mmTPC4_CMDQ_CQ_BUF_RDATA 0xF0930C + +#endif /* ASIC_REG_TPC4_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h new file mode 100644 index 000000000000..196da3f12710 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_QM_REGS_H_ +#define ASIC_REG_TPC4_QM_REGS_H_ + +/* + ***************************************** + * TPC4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC4_QM_GLBL_CFG0 0xF08000 + +#define mmTPC4_QM_GLBL_CFG1 0xF08004 + +#define mmTPC4_QM_GLBL_PROT 0xF08008 + +#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C + +#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08010 + +#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08014 + +#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08018 + +#define mmTPC4_QM_GLBL_SECURE_PROPS 0xF0801C + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS 0xF08020 + +#define mmTPC4_QM_GLBL_STS0 0xF08024 + +#define mmTPC4_QM_GLBL_STS1 0xF08028 + +#define mmTPC4_QM_PQ_BASE_LO 0xF08060 + +#define mmTPC4_QM_PQ_BASE_HI 0xF08064 + +#define mmTPC4_QM_PQ_SIZE 0xF08068 + +#define mmTPC4_QM_PQ_PI 0xF0806C + +#define mmTPC4_QM_PQ_CI 0xF08070 + +#define mmTPC4_QM_PQ_CFG0 0xF08074 + +#define mmTPC4_QM_PQ_CFG1 0xF08078 + +#define mmTPC4_QM_PQ_ARUSER 0xF0807C + +#define mmTPC4_QM_PQ_PUSH0 0xF08080 + +#define mmTPC4_QM_PQ_PUSH1 0xF08084 + +#define mmTPC4_QM_PQ_PUSH2 0xF08088 + +#define mmTPC4_QM_PQ_PUSH3 0xF0808C + +#define mmTPC4_QM_PQ_STS0 0xF08090 + +#define mmTPC4_QM_PQ_STS1 0xF08094 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_EN 0xF080A0 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF080A4 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_SAT 0xF080A8 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_TOUT 0xF080AC + +#define mmTPC4_QM_CQ_CFG0 0xF080B0 + +#define mmTPC4_QM_CQ_CFG1 0xF080B4 + +#define mmTPC4_QM_CQ_ARUSER 0xF080B8 + +#define mmTPC4_QM_CQ_PTR_LO 0xF080C0 + +#define mmTPC4_QM_CQ_PTR_HI 0xF080C4 + +#define mmTPC4_QM_CQ_TSIZE 0xF080C8 + +#define mmTPC4_QM_CQ_CTL 0xF080CC + +#define mmTPC4_QM_CQ_PTR_LO_STS 0xF080D4 + +#define mmTPC4_QM_CQ_PTR_HI_STS 0xF080D8 + +#define mmTPC4_QM_CQ_TSIZE_STS 0xF080DC + +#define mmTPC4_QM_CQ_CTL_STS 0xF080E0 + +#define mmTPC4_QM_CQ_STS0 0xF080E4 + +#define mmTPC4_QM_CQ_STS1 0xF080E8 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_EN 0xF080F0 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF080F4 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_SAT 0xF080F8 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_TOUT 0xF080FC + +#define mmTPC4_QM_CQ_IFIFO_CNT 0xF08108 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO 0xF08120 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI 0xF08124 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO 0xF08128 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI 0xF0812C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO 0xF08130 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI 0xF08134 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO 0xF08138 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI 0xF0813C + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET 0xF08140 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF08144 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF08148 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF0814C + +#define mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF08150 + +#define mmTPC4_QM_CP_LDMA_COMMIT_OFFSET 0xF08154 + +#define mmTPC4_QM_CP_FENCE0_RDATA 0xF08158 + +#define mmTPC4_QM_CP_FENCE1_RDATA 0xF0815C + +#define mmTPC4_QM_CP_FENCE2_RDATA 0xF08160 + +#define mmTPC4_QM_CP_FENCE3_RDATA 0xF08164 + +#define mmTPC4_QM_CP_FENCE0_CNT 0xF08168 + +#define mmTPC4_QM_CP_FENCE1_CNT 0xF0816C + +#define mmTPC4_QM_CP_FENCE2_CNT 0xF08170 + +#define mmTPC4_QM_CP_FENCE3_CNT 0xF08174 + +#define mmTPC4_QM_CP_STS 0xF08178 + +#define mmTPC4_QM_CP_CURRENT_INST_LO 0xF0817C + +#define mmTPC4_QM_CP_CURRENT_INST_HI 0xF08180 + +#define mmTPC4_QM_CP_BARRIER_CFG 0xF08184 + +#define mmTPC4_QM_CP_DBG_0 0xF08188 + +#define mmTPC4_QM_PQ_BUF_ADDR 0xF08300 + +#define mmTPC4_QM_PQ_BUF_RDATA 0xF08304 + +#define mmTPC4_QM_CQ_BUF_ADDR 0xF08308 + +#define mmTPC4_QM_CQ_BUF_RDATA 0xF0830C + +#endif /* ASIC_REG_TPC4_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h new file mode 100644 index 000000000000..8b54041d144a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_RTR_REGS_H_ +#define ASIC_REG_TPC4_RTR_REGS_H_ + +/* + ***************************************** + * TPC4_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC4_RTR_HBW_RD_RQ_E_ARB 0xF00100 + +#define mmTPC4_RTR_HBW_RD_RQ_W_ARB 0xF00104 + +#define mmTPC4_RTR_HBW_RD_RQ_N_ARB 0xF00108 + +#define mmTPC4_RTR_HBW_RD_RQ_S_ARB 0xF0010C + +#define mmTPC4_RTR_HBW_RD_RQ_L_ARB 0xF00110 + +#define mmTPC4_RTR_HBW_E_ARB_MAX 0xF00120 + +#define mmTPC4_RTR_HBW_W_ARB_MAX 0xF00124 + +#define mmTPC4_RTR_HBW_N_ARB_MAX 0xF00128 + +#define mmTPC4_RTR_HBW_S_ARB_MAX 0xF0012C + +#define mmTPC4_RTR_HBW_L_ARB_MAX 0xF00130 + +#define mmTPC4_RTR_HBW_RD_RS_E_ARB 0xF00140 + +#define mmTPC4_RTR_HBW_RD_RS_W_ARB 0xF00144 + +#define mmTPC4_RTR_HBW_RD_RS_N_ARB 0xF00148 + +#define mmTPC4_RTR_HBW_RD_RS_S_ARB 0xF0014C + +#define mmTPC4_RTR_HBW_RD_RS_L_ARB 0xF00150 + +#define mmTPC4_RTR_HBW_WR_RQ_E_ARB 0xF00170 + +#define mmTPC4_RTR_HBW_WR_RQ_W_ARB 0xF00174 + +#define mmTPC4_RTR_HBW_WR_RQ_N_ARB 0xF00178 + +#define mmTPC4_RTR_HBW_WR_RQ_S_ARB 0xF0017C + +#define mmTPC4_RTR_HBW_WR_RQ_L_ARB 0xF00180 + +#define mmTPC4_RTR_HBW_WR_RS_E_ARB 0xF00190 + +#define mmTPC4_RTR_HBW_WR_RS_W_ARB 0xF00194 + +#define mmTPC4_RTR_HBW_WR_RS_N_ARB 0xF00198 + +#define mmTPC4_RTR_HBW_WR_RS_S_ARB 0xF0019C + +#define mmTPC4_RTR_HBW_WR_RS_L_ARB 0xF001A0 + +#define mmTPC4_RTR_LBW_RD_RQ_E_ARB 0xF00200 + +#define mmTPC4_RTR_LBW_RD_RQ_W_ARB 0xF00204 + +#define mmTPC4_RTR_LBW_RD_RQ_N_ARB 0xF00208 + +#define mmTPC4_RTR_LBW_RD_RQ_S_ARB 0xF0020C + +#define mmTPC4_RTR_LBW_RD_RQ_L_ARB 0xF00210 + +#define mmTPC4_RTR_LBW_E_ARB_MAX 0xF00220 + +#define mmTPC4_RTR_LBW_W_ARB_MAX 0xF00224 + +#define mmTPC4_RTR_LBW_N_ARB_MAX 0xF00228 + +#define mmTPC4_RTR_LBW_S_ARB_MAX 0xF0022C + +#define mmTPC4_RTR_LBW_L_ARB_MAX 0xF00230 + +#define mmTPC4_RTR_LBW_RD_RS_E_ARB 0xF00250 + +#define mmTPC4_RTR_LBW_RD_RS_W_ARB 0xF00254 + +#define mmTPC4_RTR_LBW_RD_RS_N_ARB 0xF00258 + +#define mmTPC4_RTR_LBW_RD_RS_S_ARB 0xF0025C + +#define mmTPC4_RTR_LBW_RD_RS_L_ARB 0xF00260 + +#define mmTPC4_RTR_LBW_WR_RQ_E_ARB 0xF00270 + +#define mmTPC4_RTR_LBW_WR_RQ_W_ARB 0xF00274 + +#define mmTPC4_RTR_LBW_WR_RQ_N_ARB 0xF00278 + +#define mmTPC4_RTR_LBW_WR_RQ_S_ARB 0xF0027C + +#define mmTPC4_RTR_LBW_WR_RQ_L_ARB 0xF00280 + +#define mmTPC4_RTR_LBW_WR_RS_E_ARB 0xF00290 + +#define mmTPC4_RTR_LBW_WR_RS_W_ARB 0xF00294 + +#define mmTPC4_RTR_LBW_WR_RS_N_ARB 0xF00298 + +#define mmTPC4_RTR_LBW_WR_RS_S_ARB 0xF0029C + +#define mmTPC4_RTR_LBW_WR_RS_L_ARB 0xF002A0 + +#define mmTPC4_RTR_DBG_E_ARB 0xF00300 + +#define mmTPC4_RTR_DBG_W_ARB 0xF00304 + +#define mmTPC4_RTR_DBG_N_ARB 0xF00308 + +#define mmTPC4_RTR_DBG_S_ARB 0xF0030C + +#define mmTPC4_RTR_DBG_L_ARB 0xF00310 + +#define mmTPC4_RTR_DBG_E_ARB_MAX 0xF00320 + +#define mmTPC4_RTR_DBG_W_ARB_MAX 0xF00324 + +#define mmTPC4_RTR_DBG_N_ARB_MAX 0xF00328 + +#define mmTPC4_RTR_DBG_S_ARB_MAX 0xF0032C + +#define mmTPC4_RTR_DBG_L_ARB_MAX 0xF00330 + +#define mmTPC4_RTR_SPLIT_COEF_0 0xF00400 + +#define mmTPC4_RTR_SPLIT_COEF_1 0xF00404 + +#define mmTPC4_RTR_SPLIT_COEF_2 0xF00408 + +#define mmTPC4_RTR_SPLIT_COEF_3 0xF0040C + +#define mmTPC4_RTR_SPLIT_COEF_4 0xF00410 + +#define mmTPC4_RTR_SPLIT_COEF_5 0xF00414 + +#define mmTPC4_RTR_SPLIT_COEF_6 0xF00418 + +#define mmTPC4_RTR_SPLIT_COEF_7 0xF0041C + +#define mmTPC4_RTR_SPLIT_COEF_8 0xF00420 + +#define mmTPC4_RTR_SPLIT_COEF_9 0xF00424 + +#define mmTPC4_RTR_SPLIT_CFG 0xF00440 + +#define mmTPC4_RTR_SPLIT_RD_SAT 0xF00444 + +#define mmTPC4_RTR_SPLIT_RD_RST_TOKEN 0xF00448 + +#define mmTPC4_RTR_SPLIT_RD_TIMEOUT_0 0xF0044C + +#define mmTPC4_RTR_SPLIT_RD_TIMEOUT_1 0xF00450 + +#define mmTPC4_RTR_SPLIT_WR_SAT 0xF00454 + +#define mmTPC4_RTR_WPLIT_WR_TST_TOLEN 0xF00458 + +#define mmTPC4_RTR_SPLIT_WR_TIMEOUT_0 0xF0045C + +#define mmTPC4_RTR_SPLIT_WR_TIMEOUT_1 0xF00460 + +#define mmTPC4_RTR_HBW_RANGE_HIT 0xF00470 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_0 0xF00480 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_1 0xF00484 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_2 0xF00488 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_3 0xF0048C + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_4 0xF00490 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_5 0xF00494 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_6 0xF00498 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_7 0xF0049C + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_0 0xF004A0 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_1 0xF004A4 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_2 0xF004A8 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_3 0xF004AC + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_4 0xF004B0 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_5 0xF004B4 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_6 0xF004B8 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_7 0xF004BC + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_0 0xF004C0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_1 0xF004C4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_2 0xF004C8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_3 0xF004CC + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_4 0xF004D0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_5 0xF004D4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_6 0xF004D8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_7 0xF004DC + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_0 0xF004E0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_1 0xF004E4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_2 0xF004E8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_3 0xF004EC + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_4 0xF004F0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_5 0xF004F4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_6 0xF004F8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_7 0xF004FC + +#define mmTPC4_RTR_LBW_RANGE_HIT 0xF00500 + +#define mmTPC4_RTR_LBW_RANGE_MASK_0 0xF00510 + +#define mmTPC4_RTR_LBW_RANGE_MASK_1 0xF00514 + +#define mmTPC4_RTR_LBW_RANGE_MASK_2 0xF00518 + +#define mmTPC4_RTR_LBW_RANGE_MASK_3 0xF0051C + +#define mmTPC4_RTR_LBW_RANGE_MASK_4 0xF00520 + +#define mmTPC4_RTR_LBW_RANGE_MASK_5 0xF00524 + +#define mmTPC4_RTR_LBW_RANGE_MASK_6 0xF00528 + +#define mmTPC4_RTR_LBW_RANGE_MASK_7 0xF0052C + +#define mmTPC4_RTR_LBW_RANGE_MASK_8 0xF00530 + +#define mmTPC4_RTR_LBW_RANGE_MASK_9 0xF00534 + +#define mmTPC4_RTR_LBW_RANGE_MASK_10 0xF00538 + +#define mmTPC4_RTR_LBW_RANGE_MASK_11 0xF0053C + +#define mmTPC4_RTR_LBW_RANGE_MASK_12 0xF00540 + +#define mmTPC4_RTR_LBW_RANGE_MASK_13 0xF00544 + +#define mmTPC4_RTR_LBW_RANGE_MASK_14 0xF00548 + +#define mmTPC4_RTR_LBW_RANGE_MASK_15 0xF0054C + +#define mmTPC4_RTR_LBW_RANGE_BASE_0 0xF00550 + +#define mmTPC4_RTR_LBW_RANGE_BASE_1 0xF00554 + +#define mmTPC4_RTR_LBW_RANGE_BASE_2 0xF00558 + +#define mmTPC4_RTR_LBW_RANGE_BASE_3 0xF0055C + +#define mmTPC4_RTR_LBW_RANGE_BASE_4 0xF00560 + +#define mmTPC4_RTR_LBW_RANGE_BASE_5 0xF00564 + +#define mmTPC4_RTR_LBW_RANGE_BASE_6 0xF00568 + +#define mmTPC4_RTR_LBW_RANGE_BASE_7 0xF0056C + +#define mmTPC4_RTR_LBW_RANGE_BASE_8 0xF00570 + +#define mmTPC4_RTR_LBW_RANGE_BASE_9 0xF00574 + +#define mmTPC4_RTR_LBW_RANGE_BASE_10 0xF00578 + +#define mmTPC4_RTR_LBW_RANGE_BASE_11 0xF0057C + +#define mmTPC4_RTR_LBW_RANGE_BASE_12 0xF00580 + +#define mmTPC4_RTR_LBW_RANGE_BASE_13 0xF00584 + +#define mmTPC4_RTR_LBW_RANGE_BASE_14 0xF00588 + +#define mmTPC4_RTR_LBW_RANGE_BASE_15 0xF0058C + +#define mmTPC4_RTR_RGLTR 0xF00590 + +#define mmTPC4_RTR_RGLTR_WR_RESULT 0xF00594 + +#define mmTPC4_RTR_RGLTR_RD_RESULT 0xF00598 + +#define mmTPC4_RTR_SCRAMB_EN 0xF00600 + +#define mmTPC4_RTR_NON_LIN_SCRAMB 0xF00604 + +#endif /* ASIC_REG_TPC4_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h new file mode 100644 index 000000000000..3f00954fcdba --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_CFG_REGS_H_ +#define ASIC_REG_TPC5_CFG_REGS_H_ + +/* + ***************************************** + * TPC5_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF46418 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF4641C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF46420 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF46424 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46428 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF4642C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF46430 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46434 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF46438 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF4643C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46440 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46444 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF46448 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF4644C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF46450 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46454 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46458 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF4645C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF46460 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF46464 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46468 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF4646C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF46470 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46474 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF46478 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF4647C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46480 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46484 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF46488 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF4648C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF46490 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF46494 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46498 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF4649C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF464A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF464A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF464A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF464AC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF464B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF464B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF464B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF464BC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF464C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF464C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF464C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF464CC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF464D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF464D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464DC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF464E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464EC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF464FC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF46500 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF46504 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF46508 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF4650C + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF46510 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF46514 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF46518 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF4651C + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF46520 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF46524 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF46528 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF4652C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF46530 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF46534 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF46538 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF4653C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF46540 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF46544 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF46548 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF4654C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF46550 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF46554 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46558 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF4655C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF46560 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46564 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF46568 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF4656C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46570 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46574 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF46578 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF4657C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF46580 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46584 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46588 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF4658C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF46590 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF46594 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46598 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF4659C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF465A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF465A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF465A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF465AC + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF465B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF465B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF465B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF465BC + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF465C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF465C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF465C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF465CC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF465D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF465D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF465D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF465DC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF465E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF465E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF465E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF465EC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF465F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF465F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF465F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF465FC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF46600 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF46604 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46608 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF4660C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF46610 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46614 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF46618 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF4661C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46620 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46624 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF46628 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF4662C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF46630 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF46634 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF46638 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF4663C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF46640 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF46644 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF46648 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF4664C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF46650 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF46654 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF46658 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF4665C + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46660 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF46664 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46668 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF4666C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46670 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF46674 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF46678 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF4667C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF46680 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF46684 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF46688 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF4668C + +#define mmTPC5_CFG_KERNEL_SRF_0 0xF46690 + +#define mmTPC5_CFG_KERNEL_SRF_1 0xF46694 + +#define mmTPC5_CFG_KERNEL_SRF_2 0xF46698 + +#define mmTPC5_CFG_KERNEL_SRF_3 0xF4669C + +#define mmTPC5_CFG_KERNEL_SRF_4 0xF466A0 + +#define mmTPC5_CFG_KERNEL_SRF_5 0xF466A4 + +#define mmTPC5_CFG_KERNEL_SRF_6 0xF466A8 + +#define mmTPC5_CFG_KERNEL_SRF_7 0xF466AC + +#define mmTPC5_CFG_KERNEL_SRF_8 0xF466B0 + +#define mmTPC5_CFG_KERNEL_SRF_9 0xF466B4 + +#define mmTPC5_CFG_KERNEL_SRF_10 0xF466B8 + +#define mmTPC5_CFG_KERNEL_SRF_11 0xF466BC + +#define mmTPC5_CFG_KERNEL_SRF_12 0xF466C0 + +#define mmTPC5_CFG_KERNEL_SRF_13 0xF466C4 + +#define mmTPC5_CFG_KERNEL_SRF_14 0xF466C8 + +#define mmTPC5_CFG_KERNEL_SRF_15 0xF466CC + +#define mmTPC5_CFG_KERNEL_SRF_16 0xF466D0 + +#define mmTPC5_CFG_KERNEL_SRF_17 0xF466D4 + +#define mmTPC5_CFG_KERNEL_SRF_18 0xF466D8 + +#define mmTPC5_CFG_KERNEL_SRF_19 0xF466DC + +#define mmTPC5_CFG_KERNEL_SRF_20 0xF466E0 + +#define mmTPC5_CFG_KERNEL_SRF_21 0xF466E4 + +#define mmTPC5_CFG_KERNEL_SRF_22 0xF466E8 + +#define mmTPC5_CFG_KERNEL_SRF_23 0xF466EC + +#define mmTPC5_CFG_KERNEL_SRF_24 0xF466F0 + +#define mmTPC5_CFG_KERNEL_SRF_25 0xF466F4 + +#define mmTPC5_CFG_KERNEL_SRF_26 0xF466F8 + +#define mmTPC5_CFG_KERNEL_SRF_27 0xF466FC + +#define mmTPC5_CFG_KERNEL_SRF_28 0xF46700 + +#define mmTPC5_CFG_KERNEL_SRF_29 0xF46704 + +#define mmTPC5_CFG_KERNEL_SRF_30 0xF46708 + +#define mmTPC5_CFG_KERNEL_SRF_31 0xF4670C + +#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF46710 + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46714 + +#define mmTPC5_CFG_RESERVED_DESC_END 0xF46738 + +#define mmTPC5_CFG_ROUND_CSR 0xF467FC + +#define mmTPC5_CFG_TBUF_BASE_ADDR_LOW 0xF46800 + +#define mmTPC5_CFG_TBUF_BASE_ADDR_HIGH 0xF46804 + +#define mmTPC5_CFG_SEMAPHORE 0xF46808 + +#define mmTPC5_CFG_VFLAGS 0xF4680C + +#define mmTPC5_CFG_SFLAGS 0xF46810 + +#define mmTPC5_CFG_LFSR_POLYNOM 0xF46818 + +#define mmTPC5_CFG_STATUS 0xF4681C + +#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46820 + +#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46824 + +#define mmTPC5_CFG_SM_BASE_ADDRESS_LOW 0xF46828 + +#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4682C + +#define mmTPC5_CFG_TPC_CMD 0xF46830 + +#define mmTPC5_CFG_TPC_EXECUTE 0xF46838 + +#define mmTPC5_CFG_TPC_STALL 0xF4683C + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46840 + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46844 + +#define mmTPC5_CFG_MSS_CONFIG 0xF46854 + +#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46858 + +#define mmTPC5_CFG_TPC_INTR_MASK 0xF4685C + +#define mmTPC5_CFG_TSB_CONFIG 0xF46860 + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00 + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04 + +#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08 + +#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF46A18 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A1C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A20 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF46A24 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A28 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A2C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF46A30 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A34 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A38 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF46A3C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A40 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A44 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF46A48 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A4C + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A50 + +#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A54 + +#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A58 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A5C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A60 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF46A64 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A68 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A6C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF46A70 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A74 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A78 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF46A7C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A80 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A84 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF46A88 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A8C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A90 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF46A94 + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A98 + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A9C + +#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46AA0 + +#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46AA4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46AA8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46AAC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF46AB0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46AB4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46AB8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF46ABC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46AC0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46AC4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF46AC8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46ACC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46AD0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF46AD4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AD8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46ADC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF46AE0 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AE4 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AE8 + +#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AEC + +#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AF0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AF4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46AF8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF46AFC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46B00 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46B04 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF46B08 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46B0C + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46B10 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF46B14 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46B18 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46B1C + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF46B20 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46B24 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46B28 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF46B2C + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46B30 + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46B34 + +#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46B38 + +#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46B3C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46B40 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46B44 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF46B48 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46B4C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46B50 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF46B54 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B58 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B5C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF46B60 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B64 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B68 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF46B6C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B70 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B74 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF46B78 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B7C + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B80 + +#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B84 + +#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B88 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B8C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B90 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF46B94 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B98 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B9C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF46BA0 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46BA4 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46BA8 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF46BAC + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46BB0 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46BB4 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF46BB8 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46BBC + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46BC0 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF46BC4 + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46BC8 + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46BCC + +#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46BD0 + +#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46BD4 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46BD8 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46BDC + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF46BE0 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46BE4 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46BE8 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF46BEC + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46BF0 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46BF4 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF46BF8 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46BFC + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46C00 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF46C04 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46C08 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46C0C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF46C10 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46C14 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46C18 + +#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46C1C + +#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46C20 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46C24 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46C28 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF46C2C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46C30 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46C34 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF46C38 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46C3C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46C40 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF46C44 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46C48 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46C4C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF46C50 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46C54 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46C58 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF46C5C + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46C60 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46C64 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46C68 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46C6C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46C70 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46C74 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46C78 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46C7C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46C80 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46C84 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46C88 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46C8C + +#define mmTPC5_CFG_QM_SRF_0 0xF46C90 + +#define mmTPC5_CFG_QM_SRF_1 0xF46C94 + +#define mmTPC5_CFG_QM_SRF_2 0xF46C98 + +#define mmTPC5_CFG_QM_SRF_3 0xF46C9C + +#define mmTPC5_CFG_QM_SRF_4 0xF46CA0 + +#define mmTPC5_CFG_QM_SRF_5 0xF46CA4 + +#define mmTPC5_CFG_QM_SRF_6 0xF46CA8 + +#define mmTPC5_CFG_QM_SRF_7 0xF46CAC + +#define mmTPC5_CFG_QM_SRF_8 0xF46CB0 + +#define mmTPC5_CFG_QM_SRF_9 0xF46CB4 + +#define mmTPC5_CFG_QM_SRF_10 0xF46CB8 + +#define mmTPC5_CFG_QM_SRF_11 0xF46CBC + +#define mmTPC5_CFG_QM_SRF_12 0xF46CC0 + +#define mmTPC5_CFG_QM_SRF_13 0xF46CC4 + +#define mmTPC5_CFG_QM_SRF_14 0xF46CC8 + +#define mmTPC5_CFG_QM_SRF_15 0xF46CCC + +#define mmTPC5_CFG_QM_SRF_16 0xF46CD0 + +#define mmTPC5_CFG_QM_SRF_17 0xF46CD4 + +#define mmTPC5_CFG_QM_SRF_18 0xF46CD8 + +#define mmTPC5_CFG_QM_SRF_19 0xF46CDC + +#define mmTPC5_CFG_QM_SRF_20 0xF46CE0 + +#define mmTPC5_CFG_QM_SRF_21 0xF46CE4 + +#define mmTPC5_CFG_QM_SRF_22 0xF46CE8 + +#define mmTPC5_CFG_QM_SRF_23 0xF46CEC + +#define mmTPC5_CFG_QM_SRF_24 0xF46CF0 + +#define mmTPC5_CFG_QM_SRF_25 0xF46CF4 + +#define mmTPC5_CFG_QM_SRF_26 0xF46CF8 + +#define mmTPC5_CFG_QM_SRF_27 0xF46CFC + +#define mmTPC5_CFG_QM_SRF_28 0xF46D00 + +#define mmTPC5_CFG_QM_SRF_29 0xF46D04 + +#define mmTPC5_CFG_QM_SRF_30 0xF46D08 + +#define mmTPC5_CFG_QM_SRF_31 0xF46D0C + +#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46D10 + +#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D14 + +#define mmTPC5_CFG_ARUSER 0xF46D18 + +#define mmTPC5_CFG_AWUSER 0xF46D1C + +#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF46E00 + +#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF46E04 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF46E08 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF46E0C + +#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF46E10 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF46E14 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF46E18 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF46E1C + +#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF46E20 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF46E24 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF46E28 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF46E2C + +#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h new file mode 100644 index 000000000000..d8e72a8e18d7 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_CMDQ_REGS_H_ +#define ASIC_REG_TPC5_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC5_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC5_CMDQ_GLBL_CFG0 0xF49000 + +#define mmTPC5_CMDQ_GLBL_CFG1 0xF49004 + +#define mmTPC5_CMDQ_GLBL_PROT 0xF49008 + +#define mmTPC5_CMDQ_GLBL_ERR_CFG 0xF4900C + +#define mmTPC5_CMDQ_GLBL_ERR_ADDR_LO 0xF49010 + +#define mmTPC5_CMDQ_GLBL_ERR_ADDR_HI 0xF49014 + +#define mmTPC5_CMDQ_GLBL_ERR_WDATA 0xF49018 + +#define mmTPC5_CMDQ_GLBL_SECURE_PROPS 0xF4901C + +#define mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS 0xF49020 + +#define mmTPC5_CMDQ_GLBL_STS0 0xF49024 + +#define mmTPC5_CMDQ_GLBL_STS1 0xF49028 + +#define mmTPC5_CMDQ_CQ_CFG0 0xF490B0 + +#define mmTPC5_CMDQ_CQ_CFG1 0xF490B4 + +#define mmTPC5_CMDQ_CQ_ARUSER 0xF490B8 + +#define mmTPC5_CMDQ_CQ_PTR_LO 0xF490C0 + +#define mmTPC5_CMDQ_CQ_PTR_HI 0xF490C4 + +#define mmTPC5_CMDQ_CQ_TSIZE 0xF490C8 + +#define mmTPC5_CMDQ_CQ_CTL 0xF490CC + +#define mmTPC5_CMDQ_CQ_PTR_LO_STS 0xF490D4 + +#define mmTPC5_CMDQ_CQ_PTR_HI_STS 0xF490D8 + +#define mmTPC5_CMDQ_CQ_TSIZE_STS 0xF490DC + +#define mmTPC5_CMDQ_CQ_CTL_STS 0xF490E0 + +#define mmTPC5_CMDQ_CQ_STS0 0xF490E4 + +#define mmTPC5_CMDQ_CQ_STS1 0xF490E8 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN 0xF490F0 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF490F4 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT 0xF490F8 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF490FC + +#define mmTPC5_CMDQ_CQ_IFIFO_CNT 0xF49108 + +#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF49120 + +#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF49124 + +#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF49128 + +#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF4912C + +#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF49130 + +#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF49134 + +#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF49138 + +#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF4913C + +#define mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF49140 + +#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF49144 + +#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF49148 + +#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF4914C + +#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF49150 + +#define mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF49154 + +#define mmTPC5_CMDQ_CP_FENCE0_RDATA 0xF49158 + +#define mmTPC5_CMDQ_CP_FENCE1_RDATA 0xF4915C + +#define mmTPC5_CMDQ_CP_FENCE2_RDATA 0xF49160 + +#define mmTPC5_CMDQ_CP_FENCE3_RDATA 0xF49164 + +#define mmTPC5_CMDQ_CP_FENCE0_CNT 0xF49168 + +#define mmTPC5_CMDQ_CP_FENCE1_CNT 0xF4916C + +#define mmTPC5_CMDQ_CP_FENCE2_CNT 0xF49170 + +#define mmTPC5_CMDQ_CP_FENCE3_CNT 0xF49174 + +#define mmTPC5_CMDQ_CP_STS 0xF49178 + +#define mmTPC5_CMDQ_CP_CURRENT_INST_LO 0xF4917C + +#define mmTPC5_CMDQ_CP_CURRENT_INST_HI 0xF49180 + +#define mmTPC5_CMDQ_CP_BARRIER_CFG 0xF49184 + +#define mmTPC5_CMDQ_CP_DBG_0 0xF49188 + +#define mmTPC5_CMDQ_CQ_BUF_ADDR 0xF49308 + +#define mmTPC5_CMDQ_CQ_BUF_RDATA 0xF4930C + +#endif /* ASIC_REG_TPC5_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h new file mode 100644 index 000000000000..be2e68624709 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_QM_REGS_H_ +#define ASIC_REG_TPC5_QM_REGS_H_ + +/* + ***************************************** + * TPC5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC5_QM_GLBL_CFG0 0xF48000 + +#define mmTPC5_QM_GLBL_CFG1 0xF48004 + +#define mmTPC5_QM_GLBL_PROT 0xF48008 + +#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C + +#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48010 + +#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48014 + +#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48018 + +#define mmTPC5_QM_GLBL_SECURE_PROPS 0xF4801C + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS 0xF48020 + +#define mmTPC5_QM_GLBL_STS0 0xF48024 + +#define mmTPC5_QM_GLBL_STS1 0xF48028 + +#define mmTPC5_QM_PQ_BASE_LO 0xF48060 + +#define mmTPC5_QM_PQ_BASE_HI 0xF48064 + +#define mmTPC5_QM_PQ_SIZE 0xF48068 + +#define mmTPC5_QM_PQ_PI 0xF4806C + +#define mmTPC5_QM_PQ_CI 0xF48070 + +#define mmTPC5_QM_PQ_CFG0 0xF48074 + +#define mmTPC5_QM_PQ_CFG1 0xF48078 + +#define mmTPC5_QM_PQ_ARUSER 0xF4807C + +#define mmTPC5_QM_PQ_PUSH0 0xF48080 + +#define mmTPC5_QM_PQ_PUSH1 0xF48084 + +#define mmTPC5_QM_PQ_PUSH2 0xF48088 + +#define mmTPC5_QM_PQ_PUSH3 0xF4808C + +#define mmTPC5_QM_PQ_STS0 0xF48090 + +#define mmTPC5_QM_PQ_STS1 0xF48094 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_EN 0xF480A0 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF480A4 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_SAT 0xF480A8 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_TOUT 0xF480AC + +#define mmTPC5_QM_CQ_CFG0 0xF480B0 + +#define mmTPC5_QM_CQ_CFG1 0xF480B4 + +#define mmTPC5_QM_CQ_ARUSER 0xF480B8 + +#define mmTPC5_QM_CQ_PTR_LO 0xF480C0 + +#define mmTPC5_QM_CQ_PTR_HI 0xF480C4 + +#define mmTPC5_QM_CQ_TSIZE 0xF480C8 + +#define mmTPC5_QM_CQ_CTL 0xF480CC + +#define mmTPC5_QM_CQ_PTR_LO_STS 0xF480D4 + +#define mmTPC5_QM_CQ_PTR_HI_STS 0xF480D8 + +#define mmTPC5_QM_CQ_TSIZE_STS 0xF480DC + +#define mmTPC5_QM_CQ_CTL_STS 0xF480E0 + +#define mmTPC5_QM_CQ_STS0 0xF480E4 + +#define mmTPC5_QM_CQ_STS1 0xF480E8 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_EN 0xF480F0 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF480F4 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_SAT 0xF480F8 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_TOUT 0xF480FC + +#define mmTPC5_QM_CQ_IFIFO_CNT 0xF48108 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO 0xF48120 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI 0xF48124 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO 0xF48128 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI 0xF4812C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO 0xF48130 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI 0xF48134 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO 0xF48138 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI 0xF4813C + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET 0xF48140 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF48144 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF48148 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF4814C + +#define mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF48150 + +#define mmTPC5_QM_CP_LDMA_COMMIT_OFFSET 0xF48154 + +#define mmTPC5_QM_CP_FENCE0_RDATA 0xF48158 + +#define mmTPC5_QM_CP_FENCE1_RDATA 0xF4815C + +#define mmTPC5_QM_CP_FENCE2_RDATA 0xF48160 + +#define mmTPC5_QM_CP_FENCE3_RDATA 0xF48164 + +#define mmTPC5_QM_CP_FENCE0_CNT 0xF48168 + +#define mmTPC5_QM_CP_FENCE1_CNT 0xF4816C + +#define mmTPC5_QM_CP_FENCE2_CNT 0xF48170 + +#define mmTPC5_QM_CP_FENCE3_CNT 0xF48174 + +#define mmTPC5_QM_CP_STS 0xF48178 + +#define mmTPC5_QM_CP_CURRENT_INST_LO 0xF4817C + +#define mmTPC5_QM_CP_CURRENT_INST_HI 0xF48180 + +#define mmTPC5_QM_CP_BARRIER_CFG 0xF48184 + +#define mmTPC5_QM_CP_DBG_0 0xF48188 + +#define mmTPC5_QM_PQ_BUF_ADDR 0xF48300 + +#define mmTPC5_QM_PQ_BUF_RDATA 0xF48304 + +#define mmTPC5_QM_CQ_BUF_ADDR 0xF48308 + +#define mmTPC5_QM_CQ_BUF_RDATA 0xF4830C + +#endif /* ASIC_REG_TPC5_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h new file mode 100644 index 000000000000..6f301c7bbc2f --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_RTR_REGS_H_ +#define ASIC_REG_TPC5_RTR_REGS_H_ + +/* + ***************************************** + * TPC5_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC5_RTR_HBW_RD_RQ_E_ARB 0xF40100 + +#define mmTPC5_RTR_HBW_RD_RQ_W_ARB 0xF40104 + +#define mmTPC5_RTR_HBW_RD_RQ_N_ARB 0xF40108 + +#define mmTPC5_RTR_HBW_RD_RQ_S_ARB 0xF4010C + +#define mmTPC5_RTR_HBW_RD_RQ_L_ARB 0xF40110 + +#define mmTPC5_RTR_HBW_E_ARB_MAX 0xF40120 + +#define mmTPC5_RTR_HBW_W_ARB_MAX 0xF40124 + +#define mmTPC5_RTR_HBW_N_ARB_MAX 0xF40128 + +#define mmTPC5_RTR_HBW_S_ARB_MAX 0xF4012C + +#define mmTPC5_RTR_HBW_L_ARB_MAX 0xF40130 + +#define mmTPC5_RTR_HBW_RD_RS_E_ARB 0xF40140 + +#define mmTPC5_RTR_HBW_RD_RS_W_ARB 0xF40144 + +#define mmTPC5_RTR_HBW_RD_RS_N_ARB 0xF40148 + +#define mmTPC5_RTR_HBW_RD_RS_S_ARB 0xF4014C + +#define mmTPC5_RTR_HBW_RD_RS_L_ARB 0xF40150 + +#define mmTPC5_RTR_HBW_WR_RQ_E_ARB 0xF40170 + +#define mmTPC5_RTR_HBW_WR_RQ_W_ARB 0xF40174 + +#define mmTPC5_RTR_HBW_WR_RQ_N_ARB 0xF40178 + +#define mmTPC5_RTR_HBW_WR_RQ_S_ARB 0xF4017C + +#define mmTPC5_RTR_HBW_WR_RQ_L_ARB 0xF40180 + +#define mmTPC5_RTR_HBW_WR_RS_E_ARB 0xF40190 + +#define mmTPC5_RTR_HBW_WR_RS_W_ARB 0xF40194 + +#define mmTPC5_RTR_HBW_WR_RS_N_ARB 0xF40198 + +#define mmTPC5_RTR_HBW_WR_RS_S_ARB 0xF4019C + +#define mmTPC5_RTR_HBW_WR_RS_L_ARB 0xF401A0 + +#define mmTPC5_RTR_LBW_RD_RQ_E_ARB 0xF40200 + +#define mmTPC5_RTR_LBW_RD_RQ_W_ARB 0xF40204 + +#define mmTPC5_RTR_LBW_RD_RQ_N_ARB 0xF40208 + +#define mmTPC5_RTR_LBW_RD_RQ_S_ARB 0xF4020C + +#define mmTPC5_RTR_LBW_RD_RQ_L_ARB 0xF40210 + +#define mmTPC5_RTR_LBW_E_ARB_MAX 0xF40220 + +#define mmTPC5_RTR_LBW_W_ARB_MAX 0xF40224 + +#define mmTPC5_RTR_LBW_N_ARB_MAX 0xF40228 + +#define mmTPC5_RTR_LBW_S_ARB_MAX 0xF4022C + +#define mmTPC5_RTR_LBW_L_ARB_MAX 0xF40230 + +#define mmTPC5_RTR_LBW_RD_RS_E_ARB 0xF40250 + +#define mmTPC5_RTR_LBW_RD_RS_W_ARB 0xF40254 + +#define mmTPC5_RTR_LBW_RD_RS_N_ARB 0xF40258 + +#define mmTPC5_RTR_LBW_RD_RS_S_ARB 0xF4025C + +#define mmTPC5_RTR_LBW_RD_RS_L_ARB 0xF40260 + +#define mmTPC5_RTR_LBW_WR_RQ_E_ARB 0xF40270 + +#define mmTPC5_RTR_LBW_WR_RQ_W_ARB 0xF40274 + +#define mmTPC5_RTR_LBW_WR_RQ_N_ARB 0xF40278 + +#define mmTPC5_RTR_LBW_WR_RQ_S_ARB 0xF4027C + +#define mmTPC5_RTR_LBW_WR_RQ_L_ARB 0xF40280 + +#define mmTPC5_RTR_LBW_WR_RS_E_ARB 0xF40290 + +#define mmTPC5_RTR_LBW_WR_RS_W_ARB 0xF40294 + +#define mmTPC5_RTR_LBW_WR_RS_N_ARB 0xF40298 + +#define mmTPC5_RTR_LBW_WR_RS_S_ARB 0xF4029C + +#define mmTPC5_RTR_LBW_WR_RS_L_ARB 0xF402A0 + +#define mmTPC5_RTR_DBG_E_ARB 0xF40300 + +#define mmTPC5_RTR_DBG_W_ARB 0xF40304 + +#define mmTPC5_RTR_DBG_N_ARB 0xF40308 + +#define mmTPC5_RTR_DBG_S_ARB 0xF4030C + +#define mmTPC5_RTR_DBG_L_ARB 0xF40310 + +#define mmTPC5_RTR_DBG_E_ARB_MAX 0xF40320 + +#define mmTPC5_RTR_DBG_W_ARB_MAX 0xF40324 + +#define mmTPC5_RTR_DBG_N_ARB_MAX 0xF40328 + +#define mmTPC5_RTR_DBG_S_ARB_MAX 0xF4032C + +#define mmTPC5_RTR_DBG_L_ARB_MAX 0xF40330 + +#define mmTPC5_RTR_SPLIT_COEF_0 0xF40400 + +#define mmTPC5_RTR_SPLIT_COEF_1 0xF40404 + +#define mmTPC5_RTR_SPLIT_COEF_2 0xF40408 + +#define mmTPC5_RTR_SPLIT_COEF_3 0xF4040C + +#define mmTPC5_RTR_SPLIT_COEF_4 0xF40410 + +#define mmTPC5_RTR_SPLIT_COEF_5 0xF40414 + +#define mmTPC5_RTR_SPLIT_COEF_6 0xF40418 + +#define mmTPC5_RTR_SPLIT_COEF_7 0xF4041C + +#define mmTPC5_RTR_SPLIT_COEF_8 0xF40420 + +#define mmTPC5_RTR_SPLIT_COEF_9 0xF40424 + +#define mmTPC5_RTR_SPLIT_CFG 0xF40440 + +#define mmTPC5_RTR_SPLIT_RD_SAT 0xF40444 + +#define mmTPC5_RTR_SPLIT_RD_RST_TOKEN 0xF40448 + +#define mmTPC5_RTR_SPLIT_RD_TIMEOUT_0 0xF4044C + +#define mmTPC5_RTR_SPLIT_RD_TIMEOUT_1 0xF40450 + +#define mmTPC5_RTR_SPLIT_WR_SAT 0xF40454 + +#define mmTPC5_RTR_WPLIT_WR_TST_TOLEN 0xF40458 + +#define mmTPC5_RTR_SPLIT_WR_TIMEOUT_0 0xF4045C + +#define mmTPC5_RTR_SPLIT_WR_TIMEOUT_1 0xF40460 + +#define mmTPC5_RTR_HBW_RANGE_HIT 0xF40470 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_0 0xF40480 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_1 0xF40484 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_2 0xF40488 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_3 0xF4048C + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_4 0xF40490 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_5 0xF40494 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_6 0xF40498 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_7 0xF4049C + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_0 0xF404A0 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_1 0xF404A4 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_2 0xF404A8 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_3 0xF404AC + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_4 0xF404B0 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_5 0xF404B4 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_6 0xF404B8 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_7 0xF404BC + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_0 0xF404C0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_1 0xF404C4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_2 0xF404C8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_3 0xF404CC + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_4 0xF404D0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_5 0xF404D4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_6 0xF404D8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_7 0xF404DC + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_0 0xF404E0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_1 0xF404E4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_2 0xF404E8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_3 0xF404EC + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_4 0xF404F0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_5 0xF404F4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_6 0xF404F8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_7 0xF404FC + +#define mmTPC5_RTR_LBW_RANGE_HIT 0xF40500 + +#define mmTPC5_RTR_LBW_RANGE_MASK_0 0xF40510 + +#define mmTPC5_RTR_LBW_RANGE_MASK_1 0xF40514 + +#define mmTPC5_RTR_LBW_RANGE_MASK_2 0xF40518 + +#define mmTPC5_RTR_LBW_RANGE_MASK_3 0xF4051C + +#define mmTPC5_RTR_LBW_RANGE_MASK_4 0xF40520 + +#define mmTPC5_RTR_LBW_RANGE_MASK_5 0xF40524 + +#define mmTPC5_RTR_LBW_RANGE_MASK_6 0xF40528 + +#define mmTPC5_RTR_LBW_RANGE_MASK_7 0xF4052C + +#define mmTPC5_RTR_LBW_RANGE_MASK_8 0xF40530 + +#define mmTPC5_RTR_LBW_RANGE_MASK_9 0xF40534 + +#define mmTPC5_RTR_LBW_RANGE_MASK_10 0xF40538 + +#define mmTPC5_RTR_LBW_RANGE_MASK_11 0xF4053C + +#define mmTPC5_RTR_LBW_RANGE_MASK_12 0xF40540 + +#define mmTPC5_RTR_LBW_RANGE_MASK_13 0xF40544 + +#define mmTPC5_RTR_LBW_RANGE_MASK_14 0xF40548 + +#define mmTPC5_RTR_LBW_RANGE_MASK_15 0xF4054C + +#define mmTPC5_RTR_LBW_RANGE_BASE_0 0xF40550 + +#define mmTPC5_RTR_LBW_RANGE_BASE_1 0xF40554 + +#define mmTPC5_RTR_LBW_RANGE_BASE_2 0xF40558 + +#define mmTPC5_RTR_LBW_RANGE_BASE_3 0xF4055C + +#define mmTPC5_RTR_LBW_RANGE_BASE_4 0xF40560 + +#define mmTPC5_RTR_LBW_RANGE_BASE_5 0xF40564 + +#define mmTPC5_RTR_LBW_RANGE_BASE_6 0xF40568 + +#define mmTPC5_RTR_LBW_RANGE_BASE_7 0xF4056C + +#define mmTPC5_RTR_LBW_RANGE_BASE_8 0xF40570 + +#define mmTPC5_RTR_LBW_RANGE_BASE_9 0xF40574 + +#define mmTPC5_RTR_LBW_RANGE_BASE_10 0xF40578 + +#define mmTPC5_RTR_LBW_RANGE_BASE_11 0xF4057C + +#define mmTPC5_RTR_LBW_RANGE_BASE_12 0xF40580 + +#define mmTPC5_RTR_LBW_RANGE_BASE_13 0xF40584 + +#define mmTPC5_RTR_LBW_RANGE_BASE_14 0xF40588 + +#define mmTPC5_RTR_LBW_RANGE_BASE_15 0xF4058C + +#define mmTPC5_RTR_RGLTR 0xF40590 + +#define mmTPC5_RTR_RGLTR_WR_RESULT 0xF40594 + +#define mmTPC5_RTR_RGLTR_RD_RESULT 0xF40598 + +#define mmTPC5_RTR_SCRAMB_EN 0xF40600 + +#define mmTPC5_RTR_NON_LIN_SCRAMB 0xF40604 + +#endif /* ASIC_REG_TPC5_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h new file mode 100644 index 000000000000..1e1168601c41 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_CFG_REGS_H_ +#define ASIC_REG_TPC6_CFG_REGS_H_ + +/* + ***************************************** + * TPC6_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF86418 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF8641C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF86420 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF86424 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86428 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF8642C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF86430 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86434 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF86438 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF8643C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86440 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86444 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF86448 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF8644C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF86450 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86454 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86458 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF8645C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF86460 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF86464 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86468 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF8646C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF86470 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86474 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF86478 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF8647C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86480 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86484 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF86488 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF8648C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF86490 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF86494 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86498 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF8649C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF864A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF864A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF864A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF864AC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF864B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF864B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF864B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF864BC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF864C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF864C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF864C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF864CC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF864D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF864D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864DC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF864E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864EC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF864FC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF86500 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF86504 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF86508 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF8650C + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF86510 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF86514 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF86518 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF8651C + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF86520 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF86524 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF86528 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF8652C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF86530 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF86534 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF86538 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF8653C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF86540 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF86544 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF86548 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF8654C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF86550 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF86554 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86558 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF8655C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF86560 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86564 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF86568 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF8656C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86570 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86574 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF86578 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF8657C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF86580 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86584 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86588 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF8658C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF86590 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF86594 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86598 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF8659C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF865A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF865A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF865A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF865AC + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF865B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF865B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF865B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF865BC + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF865C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF865C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF865C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF865CC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF865D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF865D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF865D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF865DC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF865E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF865E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF865E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF865EC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF865F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF865F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF865F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF865FC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF86600 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF86604 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86608 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF8660C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF86610 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86614 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF86618 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF8661C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86620 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86624 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF86628 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF8662C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF86630 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF86634 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF86638 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF8663C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF86640 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF86644 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF86648 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF8664C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF86650 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF86654 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF86658 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF8665C + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86660 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF86664 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86668 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF8666C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86670 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF86674 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF86678 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF8667C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF86680 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF86684 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF86688 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF8668C + +#define mmTPC6_CFG_KERNEL_SRF_0 0xF86690 + +#define mmTPC6_CFG_KERNEL_SRF_1 0xF86694 + +#define mmTPC6_CFG_KERNEL_SRF_2 0xF86698 + +#define mmTPC6_CFG_KERNEL_SRF_3 0xF8669C + +#define mmTPC6_CFG_KERNEL_SRF_4 0xF866A0 + +#define mmTPC6_CFG_KERNEL_SRF_5 0xF866A4 + +#define mmTPC6_CFG_KERNEL_SRF_6 0xF866A8 + +#define mmTPC6_CFG_KERNEL_SRF_7 0xF866AC + +#define mmTPC6_CFG_KERNEL_SRF_8 0xF866B0 + +#define mmTPC6_CFG_KERNEL_SRF_9 0xF866B4 + +#define mmTPC6_CFG_KERNEL_SRF_10 0xF866B8 + +#define mmTPC6_CFG_KERNEL_SRF_11 0xF866BC + +#define mmTPC6_CFG_KERNEL_SRF_12 0xF866C0 + +#define mmTPC6_CFG_KERNEL_SRF_13 0xF866C4 + +#define mmTPC6_CFG_KERNEL_SRF_14 0xF866C8 + +#define mmTPC6_CFG_KERNEL_SRF_15 0xF866CC + +#define mmTPC6_CFG_KERNEL_SRF_16 0xF866D0 + +#define mmTPC6_CFG_KERNEL_SRF_17 0xF866D4 + +#define mmTPC6_CFG_KERNEL_SRF_18 0xF866D8 + +#define mmTPC6_CFG_KERNEL_SRF_19 0xF866DC + +#define mmTPC6_CFG_KERNEL_SRF_20 0xF866E0 + +#define mmTPC6_CFG_KERNEL_SRF_21 0xF866E4 + +#define mmTPC6_CFG_KERNEL_SRF_22 0xF866E8 + +#define mmTPC6_CFG_KERNEL_SRF_23 0xF866EC + +#define mmTPC6_CFG_KERNEL_SRF_24 0xF866F0 + +#define mmTPC6_CFG_KERNEL_SRF_25 0xF866F4 + +#define mmTPC6_CFG_KERNEL_SRF_26 0xF866F8 + +#define mmTPC6_CFG_KERNEL_SRF_27 0xF866FC + +#define mmTPC6_CFG_KERNEL_SRF_28 0xF86700 + +#define mmTPC6_CFG_KERNEL_SRF_29 0xF86704 + +#define mmTPC6_CFG_KERNEL_SRF_30 0xF86708 + +#define mmTPC6_CFG_KERNEL_SRF_31 0xF8670C + +#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF86710 + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86714 + +#define mmTPC6_CFG_RESERVED_DESC_END 0xF86738 + +#define mmTPC6_CFG_ROUND_CSR 0xF867FC + +#define mmTPC6_CFG_TBUF_BASE_ADDR_LOW 0xF86800 + +#define mmTPC6_CFG_TBUF_BASE_ADDR_HIGH 0xF86804 + +#define mmTPC6_CFG_SEMAPHORE 0xF86808 + +#define mmTPC6_CFG_VFLAGS 0xF8680C + +#define mmTPC6_CFG_SFLAGS 0xF86810 + +#define mmTPC6_CFG_LFSR_POLYNOM 0xF86818 + +#define mmTPC6_CFG_STATUS 0xF8681C + +#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86820 + +#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86824 + +#define mmTPC6_CFG_SM_BASE_ADDRESS_LOW 0xF86828 + +#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8682C + +#define mmTPC6_CFG_TPC_CMD 0xF86830 + +#define mmTPC6_CFG_TPC_EXECUTE 0xF86838 + +#define mmTPC6_CFG_TPC_STALL 0xF8683C + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86840 + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86844 + +#define mmTPC6_CFG_MSS_CONFIG 0xF86854 + +#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86858 + +#define mmTPC6_CFG_TPC_INTR_MASK 0xF8685C + +#define mmTPC6_CFG_TSB_CONFIG 0xF86860 + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 + +#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 + +#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF86A18 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A1C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A20 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF86A24 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A28 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A2C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF86A30 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A34 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A38 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF86A3C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A40 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A44 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF86A48 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A4C + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A50 + +#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A54 + +#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A58 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A5C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A60 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF86A64 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A68 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A6C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF86A70 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A74 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A78 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF86A7C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A80 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A84 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF86A88 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A8C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A90 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF86A94 + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A98 + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A9C + +#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86AA0 + +#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86AA4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86AA8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86AAC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF86AB0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86AB4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86AB8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF86ABC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86AC0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86AC4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF86AC8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86ACC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86AD0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF86AD4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AD8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86ADC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF86AE0 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AE4 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AE8 + +#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AEC + +#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AF0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AF4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86AF8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF86AFC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86B00 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86B04 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF86B08 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86B0C + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86B10 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF86B14 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86B18 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86B1C + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF86B20 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86B24 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86B28 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF86B2C + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86B30 + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86B34 + +#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86B38 + +#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86B3C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86B40 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86B44 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF86B48 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86B4C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86B50 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF86B54 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B58 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B5C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF86B60 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B64 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B68 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF86B6C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B70 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B74 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF86B78 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B7C + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B80 + +#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B84 + +#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B88 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B8C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B90 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF86B94 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B98 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B9C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF86BA0 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86BA4 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86BA8 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF86BAC + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86BB0 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86BB4 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF86BB8 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86BBC + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86BC0 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF86BC4 + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86BC8 + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86BCC + +#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86BD0 + +#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86BD4 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86BD8 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86BDC + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF86BE0 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86BE4 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86BE8 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF86BEC + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86BF0 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86BF4 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF86BF8 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86BFC + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86C00 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF86C04 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86C08 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86C0C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF86C10 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86C14 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86C18 + +#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86C1C + +#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86C20 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86C24 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86C28 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF86C2C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86C30 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86C34 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF86C38 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86C3C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86C40 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF86C44 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86C48 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86C4C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF86C50 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86C54 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86C58 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF86C5C + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86C60 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86C64 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86C68 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86C6C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86C70 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86C74 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86C78 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86C7C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86C80 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86C84 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86C88 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86C8C + +#define mmTPC6_CFG_QM_SRF_0 0xF86C90 + +#define mmTPC6_CFG_QM_SRF_1 0xF86C94 + +#define mmTPC6_CFG_QM_SRF_2 0xF86C98 + +#define mmTPC6_CFG_QM_SRF_3 0xF86C9C + +#define mmTPC6_CFG_QM_SRF_4 0xF86CA0 + +#define mmTPC6_CFG_QM_SRF_5 0xF86CA4 + +#define mmTPC6_CFG_QM_SRF_6 0xF86CA8 + +#define mmTPC6_CFG_QM_SRF_7 0xF86CAC + +#define mmTPC6_CFG_QM_SRF_8 0xF86CB0 + +#define mmTPC6_CFG_QM_SRF_9 0xF86CB4 + +#define mmTPC6_CFG_QM_SRF_10 0xF86CB8 + +#define mmTPC6_CFG_QM_SRF_11 0xF86CBC + +#define mmTPC6_CFG_QM_SRF_12 0xF86CC0 + +#define mmTPC6_CFG_QM_SRF_13 0xF86CC4 + +#define mmTPC6_CFG_QM_SRF_14 0xF86CC8 + +#define mmTPC6_CFG_QM_SRF_15 0xF86CCC + +#define mmTPC6_CFG_QM_SRF_16 0xF86CD0 + +#define mmTPC6_CFG_QM_SRF_17 0xF86CD4 + +#define mmTPC6_CFG_QM_SRF_18 0xF86CD8 + +#define mmTPC6_CFG_QM_SRF_19 0xF86CDC + +#define mmTPC6_CFG_QM_SRF_20 0xF86CE0 + +#define mmTPC6_CFG_QM_SRF_21 0xF86CE4 + +#define mmTPC6_CFG_QM_SRF_22 0xF86CE8 + +#define mmTPC6_CFG_QM_SRF_23 0xF86CEC + +#define mmTPC6_CFG_QM_SRF_24 0xF86CF0 + +#define mmTPC6_CFG_QM_SRF_25 0xF86CF4 + +#define mmTPC6_CFG_QM_SRF_26 0xF86CF8 + +#define mmTPC6_CFG_QM_SRF_27 0xF86CFC + +#define mmTPC6_CFG_QM_SRF_28 0xF86D00 + +#define mmTPC6_CFG_QM_SRF_29 0xF86D04 + +#define mmTPC6_CFG_QM_SRF_30 0xF86D08 + +#define mmTPC6_CFG_QM_SRF_31 0xF86D0C + +#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86D10 + +#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D14 + +#define mmTPC6_CFG_ARUSER 0xF86D18 + +#define mmTPC6_CFG_AWUSER 0xF86D1C + +#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF86E00 + +#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF86E04 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF86E08 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF86E0C + +#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF86E10 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF86E14 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF86E18 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF86E1C + +#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF86E20 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF86E24 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF86E28 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF86E2C + +#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h new file mode 100644 index 000000000000..fbca6b47284e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_CMDQ_REGS_H_ +#define ASIC_REG_TPC6_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC6_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC6_CMDQ_GLBL_CFG0 0xF89000 + +#define mmTPC6_CMDQ_GLBL_CFG1 0xF89004 + +#define mmTPC6_CMDQ_GLBL_PROT 0xF89008 + +#define mmTPC6_CMDQ_GLBL_ERR_CFG 0xF8900C + +#define mmTPC6_CMDQ_GLBL_ERR_ADDR_LO 0xF89010 + +#define mmTPC6_CMDQ_GLBL_ERR_ADDR_HI 0xF89014 + +#define mmTPC6_CMDQ_GLBL_ERR_WDATA 0xF89018 + +#define mmTPC6_CMDQ_GLBL_SECURE_PROPS 0xF8901C + +#define mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS 0xF89020 + +#define mmTPC6_CMDQ_GLBL_STS0 0xF89024 + +#define mmTPC6_CMDQ_GLBL_STS1 0xF89028 + +#define mmTPC6_CMDQ_CQ_CFG0 0xF890B0 + +#define mmTPC6_CMDQ_CQ_CFG1 0xF890B4 + +#define mmTPC6_CMDQ_CQ_ARUSER 0xF890B8 + +#define mmTPC6_CMDQ_CQ_PTR_LO 0xF890C0 + +#define mmTPC6_CMDQ_CQ_PTR_HI 0xF890C4 + +#define mmTPC6_CMDQ_CQ_TSIZE 0xF890C8 + +#define mmTPC6_CMDQ_CQ_CTL 0xF890CC + +#define mmTPC6_CMDQ_CQ_PTR_LO_STS 0xF890D4 + +#define mmTPC6_CMDQ_CQ_PTR_HI_STS 0xF890D8 + +#define mmTPC6_CMDQ_CQ_TSIZE_STS 0xF890DC + +#define mmTPC6_CMDQ_CQ_CTL_STS 0xF890E0 + +#define mmTPC6_CMDQ_CQ_STS0 0xF890E4 + +#define mmTPC6_CMDQ_CQ_STS1 0xF890E8 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN 0xF890F0 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF890F4 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT 0xF890F8 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF890FC + +#define mmTPC6_CMDQ_CQ_IFIFO_CNT 0xF89108 + +#define mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF89120 + +#define mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF89124 + +#define mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF89128 + +#define mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF8912C + +#define mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF89130 + +#define mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF89134 + +#define mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF89138 + +#define mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF8913C + +#define mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF89140 + +#define mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF89144 + +#define mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF89148 + +#define mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF8914C + +#define mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF89150 + +#define mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF89154 + +#define mmTPC6_CMDQ_CP_FENCE0_RDATA 0xF89158 + +#define mmTPC6_CMDQ_CP_FENCE1_RDATA 0xF8915C + +#define mmTPC6_CMDQ_CP_FENCE2_RDATA 0xF89160 + +#define mmTPC6_CMDQ_CP_FENCE3_RDATA 0xF89164 + +#define mmTPC6_CMDQ_CP_FENCE0_CNT 0xF89168 + +#define mmTPC6_CMDQ_CP_FENCE1_CNT 0xF8916C + +#define mmTPC6_CMDQ_CP_FENCE2_CNT 0xF89170 + +#define mmTPC6_CMDQ_CP_FENCE3_CNT 0xF89174 + +#define mmTPC6_CMDQ_CP_STS 0xF89178 + +#define mmTPC6_CMDQ_CP_CURRENT_INST_LO 0xF8917C + +#define mmTPC6_CMDQ_CP_CURRENT_INST_HI 0xF89180 + +#define mmTPC6_CMDQ_CP_BARRIER_CFG 0xF89184 + +#define mmTPC6_CMDQ_CP_DBG_0 0xF89188 + +#define mmTPC6_CMDQ_CQ_BUF_ADDR 0xF89308 + +#define mmTPC6_CMDQ_CQ_BUF_RDATA 0xF8930C + +#endif /* ASIC_REG_TPC6_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h new file mode 100644 index 000000000000..bf32465dabcb --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_QM_REGS_H_ +#define ASIC_REG_TPC6_QM_REGS_H_ + +/* + ***************************************** + * TPC6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC6_QM_GLBL_CFG0 0xF88000 + +#define mmTPC6_QM_GLBL_CFG1 0xF88004 + +#define mmTPC6_QM_GLBL_PROT 0xF88008 + +#define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C + +#define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88010 + +#define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88014 + +#define mmTPC6_QM_GLBL_ERR_WDATA 0xF88018 + +#define mmTPC6_QM_GLBL_SECURE_PROPS 0xF8801C + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS 0xF88020 + +#define mmTPC6_QM_GLBL_STS0 0xF88024 + +#define mmTPC6_QM_GLBL_STS1 0xF88028 + +#define mmTPC6_QM_PQ_BASE_LO 0xF88060 + +#define mmTPC6_QM_PQ_BASE_HI 0xF88064 + +#define mmTPC6_QM_PQ_SIZE 0xF88068 + +#define mmTPC6_QM_PQ_PI 0xF8806C + +#define mmTPC6_QM_PQ_CI 0xF88070 + +#define mmTPC6_QM_PQ_CFG0 0xF88074 + +#define mmTPC6_QM_PQ_CFG1 0xF88078 + +#define mmTPC6_QM_PQ_ARUSER 0xF8807C + +#define mmTPC6_QM_PQ_PUSH0 0xF88080 + +#define mmTPC6_QM_PQ_PUSH1 0xF88084 + +#define mmTPC6_QM_PQ_PUSH2 0xF88088 + +#define mmTPC6_QM_PQ_PUSH3 0xF8808C + +#define mmTPC6_QM_PQ_STS0 0xF88090 + +#define mmTPC6_QM_PQ_STS1 0xF88094 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_EN 0xF880A0 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF880A4 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_SAT 0xF880A8 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_TOUT 0xF880AC + +#define mmTPC6_QM_CQ_CFG0 0xF880B0 + +#define mmTPC6_QM_CQ_CFG1 0xF880B4 + +#define mmTPC6_QM_CQ_ARUSER 0xF880B8 + +#define mmTPC6_QM_CQ_PTR_LO 0xF880C0 + +#define mmTPC6_QM_CQ_PTR_HI 0xF880C4 + +#define mmTPC6_QM_CQ_TSIZE 0xF880C8 + +#define mmTPC6_QM_CQ_CTL 0xF880CC + +#define mmTPC6_QM_CQ_PTR_LO_STS 0xF880D4 + +#define mmTPC6_QM_CQ_PTR_HI_STS 0xF880D8 + +#define mmTPC6_QM_CQ_TSIZE_STS 0xF880DC + +#define mmTPC6_QM_CQ_CTL_STS 0xF880E0 + +#define mmTPC6_QM_CQ_STS0 0xF880E4 + +#define mmTPC6_QM_CQ_STS1 0xF880E8 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_EN 0xF880F0 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF880F4 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_SAT 0xF880F8 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_TOUT 0xF880FC + +#define mmTPC6_QM_CQ_IFIFO_CNT 0xF88108 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO 0xF88120 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI 0xF88124 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO 0xF88128 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI 0xF8812C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO 0xF88130 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI 0xF88134 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO 0xF88138 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI 0xF8813C + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET 0xF88140 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF88144 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF88148 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF8814C + +#define mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF88150 + +#define mmTPC6_QM_CP_LDMA_COMMIT_OFFSET 0xF88154 + +#define mmTPC6_QM_CP_FENCE0_RDATA 0xF88158 + +#define mmTPC6_QM_CP_FENCE1_RDATA 0xF8815C + +#define mmTPC6_QM_CP_FENCE2_RDATA 0xF88160 + +#define mmTPC6_QM_CP_FENCE3_RDATA 0xF88164 + +#define mmTPC6_QM_CP_FENCE0_CNT 0xF88168 + +#define mmTPC6_QM_CP_FENCE1_CNT 0xF8816C + +#define mmTPC6_QM_CP_FENCE2_CNT 0xF88170 + +#define mmTPC6_QM_CP_FENCE3_CNT 0xF88174 + +#define mmTPC6_QM_CP_STS 0xF88178 + +#define mmTPC6_QM_CP_CURRENT_INST_LO 0xF8817C + +#define mmTPC6_QM_CP_CURRENT_INST_HI 0xF88180 + +#define mmTPC6_QM_CP_BARRIER_CFG 0xF88184 + +#define mmTPC6_QM_CP_DBG_0 0xF88188 + +#define mmTPC6_QM_PQ_BUF_ADDR 0xF88300 + +#define mmTPC6_QM_PQ_BUF_RDATA 0xF88304 + +#define mmTPC6_QM_CQ_BUF_ADDR 0xF88308 + +#define mmTPC6_QM_CQ_BUF_RDATA 0xF8830C + +#endif /* ASIC_REG_TPC6_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h new file mode 100644 index 000000000000..609bb90e1046 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_RTR_REGS_H_ +#define ASIC_REG_TPC6_RTR_REGS_H_ + +/* + ***************************************** + * TPC6_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC6_RTR_HBW_RD_RQ_E_ARB 0xF80100 + +#define mmTPC6_RTR_HBW_RD_RQ_W_ARB 0xF80104 + +#define mmTPC6_RTR_HBW_RD_RQ_N_ARB 0xF80108 + +#define mmTPC6_RTR_HBW_RD_RQ_S_ARB 0xF8010C + +#define mmTPC6_RTR_HBW_RD_RQ_L_ARB 0xF80110 + +#define mmTPC6_RTR_HBW_E_ARB_MAX 0xF80120 + +#define mmTPC6_RTR_HBW_W_ARB_MAX 0xF80124 + +#define mmTPC6_RTR_HBW_N_ARB_MAX 0xF80128 + +#define mmTPC6_RTR_HBW_S_ARB_MAX 0xF8012C + +#define mmTPC6_RTR_HBW_L_ARB_MAX 0xF80130 + +#define mmTPC6_RTR_HBW_RD_RS_E_ARB 0xF80140 + +#define mmTPC6_RTR_HBW_RD_RS_W_ARB 0xF80144 + +#define mmTPC6_RTR_HBW_RD_RS_N_ARB 0xF80148 + +#define mmTPC6_RTR_HBW_RD_RS_S_ARB 0xF8014C + +#define mmTPC6_RTR_HBW_RD_RS_L_ARB 0xF80150 + +#define mmTPC6_RTR_HBW_WR_RQ_E_ARB 0xF80170 + +#define mmTPC6_RTR_HBW_WR_RQ_W_ARB 0xF80174 + +#define mmTPC6_RTR_HBW_WR_RQ_N_ARB 0xF80178 + +#define mmTPC6_RTR_HBW_WR_RQ_S_ARB 0xF8017C + +#define mmTPC6_RTR_HBW_WR_RQ_L_ARB 0xF80180 + +#define mmTPC6_RTR_HBW_WR_RS_E_ARB 0xF80190 + +#define mmTPC6_RTR_HBW_WR_RS_W_ARB 0xF80194 + +#define mmTPC6_RTR_HBW_WR_RS_N_ARB 0xF80198 + +#define mmTPC6_RTR_HBW_WR_RS_S_ARB 0xF8019C + +#define mmTPC6_RTR_HBW_WR_RS_L_ARB 0xF801A0 + +#define mmTPC6_RTR_LBW_RD_RQ_E_ARB 0xF80200 + +#define mmTPC6_RTR_LBW_RD_RQ_W_ARB 0xF80204 + +#define mmTPC6_RTR_LBW_RD_RQ_N_ARB 0xF80208 + +#define mmTPC6_RTR_LBW_RD_RQ_S_ARB 0xF8020C + +#define mmTPC6_RTR_LBW_RD_RQ_L_ARB 0xF80210 + +#define mmTPC6_RTR_LBW_E_ARB_MAX 0xF80220 + +#define mmTPC6_RTR_LBW_W_ARB_MAX 0xF80224 + +#define mmTPC6_RTR_LBW_N_ARB_MAX 0xF80228 + +#define mmTPC6_RTR_LBW_S_ARB_MAX 0xF8022C + +#define mmTPC6_RTR_LBW_L_ARB_MAX 0xF80230 + +#define mmTPC6_RTR_LBW_RD_RS_E_ARB 0xF80250 + +#define mmTPC6_RTR_LBW_RD_RS_W_ARB 0xF80254 + +#define mmTPC6_RTR_LBW_RD_RS_N_ARB 0xF80258 + +#define mmTPC6_RTR_LBW_RD_RS_S_ARB 0xF8025C + +#define mmTPC6_RTR_LBW_RD_RS_L_ARB 0xF80260 + +#define mmTPC6_RTR_LBW_WR_RQ_E_ARB 0xF80270 + +#define mmTPC6_RTR_LBW_WR_RQ_W_ARB 0xF80274 + +#define mmTPC6_RTR_LBW_WR_RQ_N_ARB 0xF80278 + +#define mmTPC6_RTR_LBW_WR_RQ_S_ARB 0xF8027C + +#define mmTPC6_RTR_LBW_WR_RQ_L_ARB 0xF80280 + +#define mmTPC6_RTR_LBW_WR_RS_E_ARB 0xF80290 + +#define mmTPC6_RTR_LBW_WR_RS_W_ARB 0xF80294 + +#define mmTPC6_RTR_LBW_WR_RS_N_ARB 0xF80298 + +#define mmTPC6_RTR_LBW_WR_RS_S_ARB 0xF8029C + +#define mmTPC6_RTR_LBW_WR_RS_L_ARB 0xF802A0 + +#define mmTPC6_RTR_DBG_E_ARB 0xF80300 + +#define mmTPC6_RTR_DBG_W_ARB 0xF80304 + +#define mmTPC6_RTR_DBG_N_ARB 0xF80308 + +#define mmTPC6_RTR_DBG_S_ARB 0xF8030C + +#define mmTPC6_RTR_DBG_L_ARB 0xF80310 + +#define mmTPC6_RTR_DBG_E_ARB_MAX 0xF80320 + +#define mmTPC6_RTR_DBG_W_ARB_MAX 0xF80324 + +#define mmTPC6_RTR_DBG_N_ARB_MAX 0xF80328 + +#define mmTPC6_RTR_DBG_S_ARB_MAX 0xF8032C + +#define mmTPC6_RTR_DBG_L_ARB_MAX 0xF80330 + +#define mmTPC6_RTR_SPLIT_COEF_0 0xF80400 + +#define mmTPC6_RTR_SPLIT_COEF_1 0xF80404 + +#define mmTPC6_RTR_SPLIT_COEF_2 0xF80408 + +#define mmTPC6_RTR_SPLIT_COEF_3 0xF8040C + +#define mmTPC6_RTR_SPLIT_COEF_4 0xF80410 + +#define mmTPC6_RTR_SPLIT_COEF_5 0xF80414 + +#define mmTPC6_RTR_SPLIT_COEF_6 0xF80418 + +#define mmTPC6_RTR_SPLIT_COEF_7 0xF8041C + +#define mmTPC6_RTR_SPLIT_COEF_8 0xF80420 + +#define mmTPC6_RTR_SPLIT_COEF_9 0xF80424 + +#define mmTPC6_RTR_SPLIT_CFG 0xF80440 + +#define mmTPC6_RTR_SPLIT_RD_SAT 0xF80444 + +#define mmTPC6_RTR_SPLIT_RD_RST_TOKEN 0xF80448 + +#define mmTPC6_RTR_SPLIT_RD_TIMEOUT_0 0xF8044C + +#define mmTPC6_RTR_SPLIT_RD_TIMEOUT_1 0xF80450 + +#define mmTPC6_RTR_SPLIT_WR_SAT 0xF80454 + +#define mmTPC6_RTR_WPLIT_WR_TST_TOLEN 0xF80458 + +#define mmTPC6_RTR_SPLIT_WR_TIMEOUT_0 0xF8045C + +#define mmTPC6_RTR_SPLIT_WR_TIMEOUT_1 0xF80460 + +#define mmTPC6_RTR_HBW_RANGE_HIT 0xF80470 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_0 0xF80480 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_1 0xF80484 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_2 0xF80488 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_3 0xF8048C + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_4 0xF80490 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_5 0xF80494 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_6 0xF80498 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_7 0xF8049C + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_0 0xF804A0 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_1 0xF804A4 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_2 0xF804A8 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_3 0xF804AC + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_4 0xF804B0 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_5 0xF804B4 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_6 0xF804B8 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_7 0xF804BC + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_0 0xF804C0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_1 0xF804C4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_2 0xF804C8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_3 0xF804CC + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_4 0xF804D0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_5 0xF804D4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_6 0xF804D8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_7 0xF804DC + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_0 0xF804E0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_1 0xF804E4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_2 0xF804E8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_3 0xF804EC + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_4 0xF804F0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_5 0xF804F4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_6 0xF804F8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_7 0xF804FC + +#define mmTPC6_RTR_LBW_RANGE_HIT 0xF80500 + +#define mmTPC6_RTR_LBW_RANGE_MASK_0 0xF80510 + +#define mmTPC6_RTR_LBW_RANGE_MASK_1 0xF80514 + +#define mmTPC6_RTR_LBW_RANGE_MASK_2 0xF80518 + +#define mmTPC6_RTR_LBW_RANGE_MASK_3 0xF8051C + +#define mmTPC6_RTR_LBW_RANGE_MASK_4 0xF80520 + +#define mmTPC6_RTR_LBW_RANGE_MASK_5 0xF80524 + +#define mmTPC6_RTR_LBW_RANGE_MASK_6 0xF80528 + +#define mmTPC6_RTR_LBW_RANGE_MASK_7 0xF8052C + +#define mmTPC6_RTR_LBW_RANGE_MASK_8 0xF80530 + +#define mmTPC6_RTR_LBW_RANGE_MASK_9 0xF80534 + +#define mmTPC6_RTR_LBW_RANGE_MASK_10 0xF80538 + +#define mmTPC6_RTR_LBW_RANGE_MASK_11 0xF8053C + +#define mmTPC6_RTR_LBW_RANGE_MASK_12 0xF80540 + +#define mmTPC6_RTR_LBW_RANGE_MASK_13 0xF80544 + +#define mmTPC6_RTR_LBW_RANGE_MASK_14 0xF80548 + +#define mmTPC6_RTR_LBW_RANGE_MASK_15 0xF8054C + +#define mmTPC6_RTR_LBW_RANGE_BASE_0 0xF80550 + +#define mmTPC6_RTR_LBW_RANGE_BASE_1 0xF80554 + +#define mmTPC6_RTR_LBW_RANGE_BASE_2 0xF80558 + +#define mmTPC6_RTR_LBW_RANGE_BASE_3 0xF8055C + +#define mmTPC6_RTR_LBW_RANGE_BASE_4 0xF80560 + +#define mmTPC6_RTR_LBW_RANGE_BASE_5 0xF80564 + +#define mmTPC6_RTR_LBW_RANGE_BASE_6 0xF80568 + +#define mmTPC6_RTR_LBW_RANGE_BASE_7 0xF8056C + +#define mmTPC6_RTR_LBW_RANGE_BASE_8 0xF80570 + +#define mmTPC6_RTR_LBW_RANGE_BASE_9 0xF80574 + +#define mmTPC6_RTR_LBW_RANGE_BASE_10 0xF80578 + +#define mmTPC6_RTR_LBW_RANGE_BASE_11 0xF8057C + +#define mmTPC6_RTR_LBW_RANGE_BASE_12 0xF80580 + +#define mmTPC6_RTR_LBW_RANGE_BASE_13 0xF80584 + +#define mmTPC6_RTR_LBW_RANGE_BASE_14 0xF80588 + +#define mmTPC6_RTR_LBW_RANGE_BASE_15 0xF8058C + +#define mmTPC6_RTR_RGLTR 0xF80590 + +#define mmTPC6_RTR_RGLTR_WR_RESULT 0xF80594 + +#define mmTPC6_RTR_RGLTR_RD_RESULT 0xF80598 + +#define mmTPC6_RTR_SCRAMB_EN 0xF80600 + +#define mmTPC6_RTR_NON_LIN_SCRAMB 0xF80604 + +#endif /* ASIC_REG_TPC6_RTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h new file mode 100644 index 000000000000..bf2fd0f73906 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h @@ -0,0 +1,887 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_CFG_REGS_H_ +#define ASIC_REG_TPC7_CFG_REGS_H_ + +/* + ***************************************** + * TPC7_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xFC6418 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC641C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC6420 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xFC6424 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6428 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC642C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xFC6430 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6434 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC6438 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xFC643C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6440 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6444 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xFC6448 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC644C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC6450 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6454 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6458 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC645C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC6460 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xFC6464 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6468 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC646C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xFC6470 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6474 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC6478 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xFC647C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6480 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6484 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xFC6488 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC648C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC6490 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xFC6494 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6498 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC649C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC64A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC64A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC64A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC64AC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xFC64B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC64B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC64B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xFC64BC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC64C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC64C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xFC64C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC64CC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC64D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xFC64D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64DC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xFC64E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64EC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xFC64FC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC6500 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC6504 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6508 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC650C + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC6510 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6514 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC6518 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC651C + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6520 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC6524 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC6528 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xFC652C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC6530 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC6534 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC6538 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC653C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC6540 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC6544 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6548 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC654C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC6550 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6554 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6558 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC655C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6560 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6564 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC6568 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xFC656C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6570 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6574 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6578 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC657C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC6580 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6584 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6588 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC658C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC6590 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6594 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6598 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC659C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xFC65A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC65A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC65A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xFC65AC + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC65B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC65B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xFC65B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC65BC + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC65C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xFC65C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC65C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC65CC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC65D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC65D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC65D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC65DC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xFC65E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC65E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC65E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xFC65EC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC65F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC65F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xFC65F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC65FC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC6600 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6604 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6608 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC660C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6610 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6614 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC6618 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC661C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6620 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6624 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC6628 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xFC662C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC6630 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC6634 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6638 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC663C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC6640 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6644 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC6648 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC664C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6650 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC6654 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC6658 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xFC665C + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6660 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC6664 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6668 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC666C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6670 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC6674 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC6678 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC667C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC6680 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC6684 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC6688 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC668C + +#define mmTPC7_CFG_KERNEL_SRF_0 0xFC6690 + +#define mmTPC7_CFG_KERNEL_SRF_1 0xFC6694 + +#define mmTPC7_CFG_KERNEL_SRF_2 0xFC6698 + +#define mmTPC7_CFG_KERNEL_SRF_3 0xFC669C + +#define mmTPC7_CFG_KERNEL_SRF_4 0xFC66A0 + +#define mmTPC7_CFG_KERNEL_SRF_5 0xFC66A4 + +#define mmTPC7_CFG_KERNEL_SRF_6 0xFC66A8 + +#define mmTPC7_CFG_KERNEL_SRF_7 0xFC66AC + +#define mmTPC7_CFG_KERNEL_SRF_8 0xFC66B0 + +#define mmTPC7_CFG_KERNEL_SRF_9 0xFC66B4 + +#define mmTPC7_CFG_KERNEL_SRF_10 0xFC66B8 + +#define mmTPC7_CFG_KERNEL_SRF_11 0xFC66BC + +#define mmTPC7_CFG_KERNEL_SRF_12 0xFC66C0 + +#define mmTPC7_CFG_KERNEL_SRF_13 0xFC66C4 + +#define mmTPC7_CFG_KERNEL_SRF_14 0xFC66C8 + +#define mmTPC7_CFG_KERNEL_SRF_15 0xFC66CC + +#define mmTPC7_CFG_KERNEL_SRF_16 0xFC66D0 + +#define mmTPC7_CFG_KERNEL_SRF_17 0xFC66D4 + +#define mmTPC7_CFG_KERNEL_SRF_18 0xFC66D8 + +#define mmTPC7_CFG_KERNEL_SRF_19 0xFC66DC + +#define mmTPC7_CFG_KERNEL_SRF_20 0xFC66E0 + +#define mmTPC7_CFG_KERNEL_SRF_21 0xFC66E4 + +#define mmTPC7_CFG_KERNEL_SRF_22 0xFC66E8 + +#define mmTPC7_CFG_KERNEL_SRF_23 0xFC66EC + +#define mmTPC7_CFG_KERNEL_SRF_24 0xFC66F0 + +#define mmTPC7_CFG_KERNEL_SRF_25 0xFC66F4 + +#define mmTPC7_CFG_KERNEL_SRF_26 0xFC66F8 + +#define mmTPC7_CFG_KERNEL_SRF_27 0xFC66FC + +#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6700 + +#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6704 + +#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6708 + +#define mmTPC7_CFG_KERNEL_SRF_31 0xFC670C + +#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC6710 + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6714 + +#define mmTPC7_CFG_RESERVED_DESC_END 0xFC6738 + +#define mmTPC7_CFG_ROUND_CSR 0xFC67FC + +#define mmTPC7_CFG_TBUF_BASE_ADDR_LOW 0xFC6800 + +#define mmTPC7_CFG_TBUF_BASE_ADDR_HIGH 0xFC6804 + +#define mmTPC7_CFG_SEMAPHORE 0xFC6808 + +#define mmTPC7_CFG_VFLAGS 0xFC680C + +#define mmTPC7_CFG_SFLAGS 0xFC6810 + +#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6818 + +#define mmTPC7_CFG_STATUS 0xFC681C + +#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6820 + +#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6824 + +#define mmTPC7_CFG_SM_BASE_ADDRESS_LOW 0xFC6828 + +#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC682C + +#define mmTPC7_CFG_TPC_CMD 0xFC6830 + +#define mmTPC7_CFG_TPC_EXECUTE 0xFC6838 + +#define mmTPC7_CFG_TPC_STALL 0xFC683C + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6840 + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6844 + +#define mmTPC7_CFG_MSS_CONFIG 0xFC6854 + +#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6858 + +#define mmTPC7_CFG_TPC_INTR_MASK 0xFC685C + +#define mmTPC7_CFG_TSB_CONFIG 0xFC6860 + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00 + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04 + +#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08 + +#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xFC6A18 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A1C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A20 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xFC6A24 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A28 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A2C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xFC6A30 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A34 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A38 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xFC6A3C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A40 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A44 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xFC6A48 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A4C + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A50 + +#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A54 + +#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A58 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A5C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A60 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xFC6A64 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A68 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A6C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xFC6A70 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A74 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A78 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xFC6A7C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A80 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A84 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xFC6A88 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A8C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A90 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xFC6A94 + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A98 + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A9C + +#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6AA0 + +#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6AA4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6AA8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6AAC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xFC6AB0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6AB4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6AB8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xFC6ABC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6AC0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6AC4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xFC6AC8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6ACC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6AD0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xFC6AD4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AD8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6ADC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xFC6AE0 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AE4 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AE8 + +#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AEC + +#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AF0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AF4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6AF8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xFC6AFC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6B00 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6B04 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6B08 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6B0C + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6B10 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6B14 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6B18 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6B1C + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6B20 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6B24 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6B28 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xFC6B2C + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6B30 + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6B34 + +#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6B38 + +#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6B3C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6B40 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6B44 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6B48 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6B4C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6B50 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6B54 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B58 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B5C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6B60 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B64 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B68 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xFC6B6C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B70 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B74 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6B78 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B7C + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B80 + +#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B84 + +#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B88 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B8C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B90 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6B94 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B98 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B9C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xFC6BA0 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6BA4 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6BA8 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xFC6BAC + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6BB0 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6BB4 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xFC6BB8 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6BBC + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6BC0 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xFC6BC4 + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6BC8 + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6BCC + +#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6BD0 + +#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6BD4 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6BD8 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6BDC + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xFC6BE0 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6BE4 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6BE8 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xFC6BEC + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6BF0 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6BF4 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xFC6BF8 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6BFC + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6C00 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6C04 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6C08 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6C0C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6C10 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6C14 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6C18 + +#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6C1C + +#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6C20 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6C24 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6C28 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xFC6C2C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6C30 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6C34 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6C38 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6C3C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6C40 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6C44 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6C48 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6C4C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6C50 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6C54 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6C58 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xFC6C5C + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6C60 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6C64 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6C68 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6C6C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6C70 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6C74 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6C78 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6C7C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6C80 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6C84 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6C88 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6C8C + +#define mmTPC7_CFG_QM_SRF_0 0xFC6C90 + +#define mmTPC7_CFG_QM_SRF_1 0xFC6C94 + +#define mmTPC7_CFG_QM_SRF_2 0xFC6C98 + +#define mmTPC7_CFG_QM_SRF_3 0xFC6C9C + +#define mmTPC7_CFG_QM_SRF_4 0xFC6CA0 + +#define mmTPC7_CFG_QM_SRF_5 0xFC6CA4 + +#define mmTPC7_CFG_QM_SRF_6 0xFC6CA8 + +#define mmTPC7_CFG_QM_SRF_7 0xFC6CAC + +#define mmTPC7_CFG_QM_SRF_8 0xFC6CB0 + +#define mmTPC7_CFG_QM_SRF_9 0xFC6CB4 + +#define mmTPC7_CFG_QM_SRF_10 0xFC6CB8 + +#define mmTPC7_CFG_QM_SRF_11 0xFC6CBC + +#define mmTPC7_CFG_QM_SRF_12 0xFC6CC0 + +#define mmTPC7_CFG_QM_SRF_13 0xFC6CC4 + +#define mmTPC7_CFG_QM_SRF_14 0xFC6CC8 + +#define mmTPC7_CFG_QM_SRF_15 0xFC6CCC + +#define mmTPC7_CFG_QM_SRF_16 0xFC6CD0 + +#define mmTPC7_CFG_QM_SRF_17 0xFC6CD4 + +#define mmTPC7_CFG_QM_SRF_18 0xFC6CD8 + +#define mmTPC7_CFG_QM_SRF_19 0xFC6CDC + +#define mmTPC7_CFG_QM_SRF_20 0xFC6CE0 + +#define mmTPC7_CFG_QM_SRF_21 0xFC6CE4 + +#define mmTPC7_CFG_QM_SRF_22 0xFC6CE8 + +#define mmTPC7_CFG_QM_SRF_23 0xFC6CEC + +#define mmTPC7_CFG_QM_SRF_24 0xFC6CF0 + +#define mmTPC7_CFG_QM_SRF_25 0xFC6CF4 + +#define mmTPC7_CFG_QM_SRF_26 0xFC6CF8 + +#define mmTPC7_CFG_QM_SRF_27 0xFC6CFC + +#define mmTPC7_CFG_QM_SRF_28 0xFC6D00 + +#define mmTPC7_CFG_QM_SRF_29 0xFC6D04 + +#define mmTPC7_CFG_QM_SRF_30 0xFC6D08 + +#define mmTPC7_CFG_QM_SRF_31 0xFC6D0C + +#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6D10 + +#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D14 + +#define mmTPC7_CFG_ARUSER 0xFC6D18 + +#define mmTPC7_CFG_AWUSER 0xFC6D1C + +#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC6E00 + +#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC6E04 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC6E08 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC6E0C + +#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC6E10 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC6E14 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC6E18 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC6E1C + +#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC6E20 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC6E24 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC6E28 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC6E2C + +#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h new file mode 100644 index 000000000000..65d83043bf63 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_CMDQ_REGS_H_ +#define ASIC_REG_TPC7_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC7_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC7_CMDQ_GLBL_CFG0 0xFC9000 + +#define mmTPC7_CMDQ_GLBL_CFG1 0xFC9004 + +#define mmTPC7_CMDQ_GLBL_PROT 0xFC9008 + +#define mmTPC7_CMDQ_GLBL_ERR_CFG 0xFC900C + +#define mmTPC7_CMDQ_GLBL_ERR_ADDR_LO 0xFC9010 + +#define mmTPC7_CMDQ_GLBL_ERR_ADDR_HI 0xFC9014 + +#define mmTPC7_CMDQ_GLBL_ERR_WDATA 0xFC9018 + +#define mmTPC7_CMDQ_GLBL_SECURE_PROPS 0xFC901C + +#define mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS 0xFC9020 + +#define mmTPC7_CMDQ_GLBL_STS0 0xFC9024 + +#define mmTPC7_CMDQ_GLBL_STS1 0xFC9028 + +#define mmTPC7_CMDQ_CQ_CFG0 0xFC90B0 + +#define mmTPC7_CMDQ_CQ_CFG1 0xFC90B4 + +#define mmTPC7_CMDQ_CQ_ARUSER 0xFC90B8 + +#define mmTPC7_CMDQ_CQ_PTR_LO 0xFC90C0 + +#define mmTPC7_CMDQ_CQ_PTR_HI 0xFC90C4 + +#define mmTPC7_CMDQ_CQ_TSIZE 0xFC90C8 + +#define mmTPC7_CMDQ_CQ_CTL 0xFC90CC + +#define mmTPC7_CMDQ_CQ_PTR_LO_STS 0xFC90D4 + +#define mmTPC7_CMDQ_CQ_PTR_HI_STS 0xFC90D8 + +#define mmTPC7_CMDQ_CQ_TSIZE_STS 0xFC90DC + +#define mmTPC7_CMDQ_CQ_CTL_STS 0xFC90E0 + +#define mmTPC7_CMDQ_CQ_STS0 0xFC90E4 + +#define mmTPC7_CMDQ_CQ_STS1 0xFC90E8 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_EN 0xFC90F0 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xFC90F4 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_SAT 0xFC90F8 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_TOUT 0xFC90FC + +#define mmTPC7_CMDQ_CQ_IFIFO_CNT 0xFC9108 + +#define mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_LO 0xFC9120 + +#define mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_HI 0xFC9124 + +#define mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_LO 0xFC9128 + +#define mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_HI 0xFC912C + +#define mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_LO 0xFC9130 + +#define mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_HI 0xFC9134 + +#define mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_LO 0xFC9138 + +#define mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_HI 0xFC913C + +#define mmTPC7_CMDQ_CP_LDMA_TSIZE_OFFSET 0xFC9140 + +#define mmTPC7_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xFC9144 + +#define mmTPC7_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xFC9148 + +#define mmTPC7_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xFC914C + +#define mmTPC7_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xFC9150 + +#define mmTPC7_CMDQ_CP_LDMA_COMMIT_OFFSET 0xFC9154 + +#define mmTPC7_CMDQ_CP_FENCE0_RDATA 0xFC9158 + +#define mmTPC7_CMDQ_CP_FENCE1_RDATA 0xFC915C + +#define mmTPC7_CMDQ_CP_FENCE2_RDATA 0xFC9160 + +#define mmTPC7_CMDQ_CP_FENCE3_RDATA 0xFC9164 + +#define mmTPC7_CMDQ_CP_FENCE0_CNT 0xFC9168 + +#define mmTPC7_CMDQ_CP_FENCE1_CNT 0xFC916C + +#define mmTPC7_CMDQ_CP_FENCE2_CNT 0xFC9170 + +#define mmTPC7_CMDQ_CP_FENCE3_CNT 0xFC9174 + +#define mmTPC7_CMDQ_CP_STS 0xFC9178 + +#define mmTPC7_CMDQ_CP_CURRENT_INST_LO 0xFC917C + +#define mmTPC7_CMDQ_CP_CURRENT_INST_HI 0xFC9180 + +#define mmTPC7_CMDQ_CP_BARRIER_CFG 0xFC9184 + +#define mmTPC7_CMDQ_CP_DBG_0 0xFC9188 + +#define mmTPC7_CMDQ_CQ_BUF_ADDR 0xFC9308 + +#define mmTPC7_CMDQ_CQ_BUF_RDATA 0xFC930C + +#endif /* ASIC_REG_TPC7_CMDQ_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h new file mode 100644 index 000000000000..3d5848d87304 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_NRTR_REGS_H_ +#define ASIC_REG_TPC7_NRTR_REGS_H_ + +/* + ***************************************** + * TPC7_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmTPC7_NRTR_HBW_MAX_CRED 0xFC0100 + +#define mmTPC7_NRTR_LBW_MAX_CRED 0xFC0120 + +#define mmTPC7_NRTR_DBG_E_ARB 0xFC0300 + +#define mmTPC7_NRTR_DBG_W_ARB 0xFC0304 + +#define mmTPC7_NRTR_DBG_N_ARB 0xFC0308 + +#define mmTPC7_NRTR_DBG_S_ARB 0xFC030C + +#define mmTPC7_NRTR_DBG_L_ARB 0xFC0310 + +#define mmTPC7_NRTR_DBG_E_ARB_MAX 0xFC0320 + +#define mmTPC7_NRTR_DBG_W_ARB_MAX 0xFC0324 + +#define mmTPC7_NRTR_DBG_N_ARB_MAX 0xFC0328 + +#define mmTPC7_NRTR_DBG_S_ARB_MAX 0xFC032C + +#define mmTPC7_NRTR_DBG_L_ARB_MAX 0xFC0330 + +#define mmTPC7_NRTR_SPLIT_COEF_0 0xFC0400 + +#define mmTPC7_NRTR_SPLIT_COEF_1 0xFC0404 + +#define mmTPC7_NRTR_SPLIT_COEF_2 0xFC0408 + +#define mmTPC7_NRTR_SPLIT_COEF_3 0xFC040C + +#define mmTPC7_NRTR_SPLIT_COEF_4 0xFC0410 + +#define mmTPC7_NRTR_SPLIT_COEF_5 0xFC0414 + +#define mmTPC7_NRTR_SPLIT_COEF_6 0xFC0418 + +#define mmTPC7_NRTR_SPLIT_COEF_7 0xFC041C + +#define mmTPC7_NRTR_SPLIT_COEF_8 0xFC0420 + +#define mmTPC7_NRTR_SPLIT_COEF_9 0xFC0424 + +#define mmTPC7_NRTR_SPLIT_CFG 0xFC0440 + +#define mmTPC7_NRTR_SPLIT_RD_SAT 0xFC0444 + +#define mmTPC7_NRTR_SPLIT_RD_RST_TOKEN 0xFC0448 + +#define mmTPC7_NRTR_SPLIT_RD_TIMEOUT_0 0xFC044C + +#define mmTPC7_NRTR_SPLIT_RD_TIMEOUT_1 0xFC0450 + +#define mmTPC7_NRTR_SPLIT_WR_SAT 0xFC0454 + +#define mmTPC7_NRTR_WPLIT_WR_TST_TOLEN 0xFC0458 + +#define mmTPC7_NRTR_SPLIT_WR_TIMEOUT_0 0xFC045C + +#define mmTPC7_NRTR_SPLIT_WR_TIMEOUT_1 0xFC0460 + +#define mmTPC7_NRTR_HBW_RANGE_HIT 0xFC0470 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_0 0xFC0480 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_1 0xFC0484 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_2 0xFC0488 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_3 0xFC048C + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_4 0xFC0490 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_5 0xFC0494 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_6 0xFC0498 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_7 0xFC049C + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_0 0xFC04A0 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_1 0xFC04A4 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_2 0xFC04A8 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_3 0xFC04AC + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_4 0xFC04B0 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_5 0xFC04B4 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_6 0xFC04B8 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_7 0xFC04BC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_0 0xFC04C0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_1 0xFC04C4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_2 0xFC04C8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_3 0xFC04CC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_4 0xFC04D0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_5 0xFC04D4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_6 0xFC04D8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_7 0xFC04DC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_0 0xFC04E0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_1 0xFC04E4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_2 0xFC04E8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_3 0xFC04EC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_4 0xFC04F0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_5 0xFC04F4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_6 0xFC04F8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_7 0xFC04FC + +#define mmTPC7_NRTR_LBW_RANGE_HIT 0xFC0500 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_0 0xFC0510 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_1 0xFC0514 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_2 0xFC0518 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_3 0xFC051C + +#define mmTPC7_NRTR_LBW_RANGE_MASK_4 0xFC0520 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_5 0xFC0524 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_6 0xFC0528 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_7 0xFC052C + +#define mmTPC7_NRTR_LBW_RANGE_MASK_8 0xFC0530 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_9 0xFC0534 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_10 0xFC0538 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_11 0xFC053C + +#define mmTPC7_NRTR_LBW_RANGE_MASK_12 0xFC0540 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_13 0xFC0544 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_14 0xFC0548 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_15 0xFC054C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_0 0xFC0550 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_1 0xFC0554 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_2 0xFC0558 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_3 0xFC055C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_4 0xFC0560 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_5 0xFC0564 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_6 0xFC0568 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_7 0xFC056C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_8 0xFC0570 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_9 0xFC0574 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_10 0xFC0578 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_11 0xFC057C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_12 0xFC0580 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_13 0xFC0584 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_14 0xFC0588 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_15 0xFC058C + +#define mmTPC7_NRTR_RGLTR 0xFC0590 + +#define mmTPC7_NRTR_RGLTR_WR_RESULT 0xFC0594 + +#define mmTPC7_NRTR_RGLTR_RD_RESULT 0xFC0598 + +#define mmTPC7_NRTR_SCRAMB_EN 0xFC0600 + +#define mmTPC7_NRTR_NON_LIN_SCRAMB 0xFC0604 + +#endif /* ASIC_REG_TPC7_NRTR_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h new file mode 100644 index 000000000000..25f5095f68fb --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_QM_REGS_H_ +#define ASIC_REG_TPC7_QM_REGS_H_ + +/* + ***************************************** + * TPC7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC7_QM_GLBL_CFG0 0xFC8000 + +#define mmTPC7_QM_GLBL_CFG1 0xFC8004 + +#define mmTPC7_QM_GLBL_PROT 0xFC8008 + +#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C + +#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8010 + +#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8014 + +#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8018 + +#define mmTPC7_QM_GLBL_SECURE_PROPS 0xFC801C + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS 0xFC8020 + +#define mmTPC7_QM_GLBL_STS0 0xFC8024 + +#define mmTPC7_QM_GLBL_STS1 0xFC8028 + +#define mmTPC7_QM_PQ_BASE_LO 0xFC8060 + +#define mmTPC7_QM_PQ_BASE_HI 0xFC8064 + +#define mmTPC7_QM_PQ_SIZE 0xFC8068 + +#define mmTPC7_QM_PQ_PI 0xFC806C + +#define mmTPC7_QM_PQ_CI 0xFC8070 + +#define mmTPC7_QM_PQ_CFG0 0xFC8074 + +#define mmTPC7_QM_PQ_CFG1 0xFC8078 + +#define mmTPC7_QM_PQ_ARUSER 0xFC807C + +#define mmTPC7_QM_PQ_PUSH0 0xFC8080 + +#define mmTPC7_QM_PQ_PUSH1 0xFC8084 + +#define mmTPC7_QM_PQ_PUSH2 0xFC8088 + +#define mmTPC7_QM_PQ_PUSH3 0xFC808C + +#define mmTPC7_QM_PQ_STS0 0xFC8090 + +#define mmTPC7_QM_PQ_STS1 0xFC8094 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_EN 0xFC80A0 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xFC80A4 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_SAT 0xFC80A8 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_TOUT 0xFC80AC + +#define mmTPC7_QM_CQ_CFG0 0xFC80B0 + +#define mmTPC7_QM_CQ_CFG1 0xFC80B4 + +#define mmTPC7_QM_CQ_ARUSER 0xFC80B8 + +#define mmTPC7_QM_CQ_PTR_LO 0xFC80C0 + +#define mmTPC7_QM_CQ_PTR_HI 0xFC80C4 + +#define mmTPC7_QM_CQ_TSIZE 0xFC80C8 + +#define mmTPC7_QM_CQ_CTL 0xFC80CC + +#define mmTPC7_QM_CQ_PTR_LO_STS 0xFC80D4 + +#define mmTPC7_QM_CQ_PTR_HI_STS 0xFC80D8 + +#define mmTPC7_QM_CQ_TSIZE_STS 0xFC80DC + +#define mmTPC7_QM_CQ_CTL_STS 0xFC80E0 + +#define mmTPC7_QM_CQ_STS0 0xFC80E4 + +#define mmTPC7_QM_CQ_STS1 0xFC80E8 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_EN 0xFC80F0 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xFC80F4 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_SAT 0xFC80F8 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_TOUT 0xFC80FC + +#define mmTPC7_QM_CQ_IFIFO_CNT 0xFC8108 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO 0xFC8120 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI 0xFC8124 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO 0xFC8128 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI 0xFC812C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO 0xFC8130 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI 0xFC8134 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO 0xFC8138 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI 0xFC813C + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET 0xFC8140 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xFC8144 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xFC8148 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xFC814C + +#define mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xFC8150 + +#define mmTPC7_QM_CP_LDMA_COMMIT_OFFSET 0xFC8154 + +#define mmTPC7_QM_CP_FENCE0_RDATA 0xFC8158 + +#define mmTPC7_QM_CP_FENCE1_RDATA 0xFC815C + +#define mmTPC7_QM_CP_FENCE2_RDATA 0xFC8160 + +#define mmTPC7_QM_CP_FENCE3_RDATA 0xFC8164 + +#define mmTPC7_QM_CP_FENCE0_CNT 0xFC8168 + +#define mmTPC7_QM_CP_FENCE1_CNT 0xFC816C + +#define mmTPC7_QM_CP_FENCE2_CNT 0xFC8170 + +#define mmTPC7_QM_CP_FENCE3_CNT 0xFC8174 + +#define mmTPC7_QM_CP_STS 0xFC8178 + +#define mmTPC7_QM_CP_CURRENT_INST_LO 0xFC817C + +#define mmTPC7_QM_CP_CURRENT_INST_HI 0xFC8180 + +#define mmTPC7_QM_CP_BARRIER_CFG 0xFC8184 + +#define mmTPC7_QM_CP_DBG_0 0xFC8188 + +#define mmTPC7_QM_PQ_BUF_ADDR 0xFC8300 + +#define mmTPC7_QM_PQ_BUF_RDATA 0xFC8304 + +#define mmTPC7_QM_CQ_BUF_ADDR 0xFC8308 + +#define mmTPC7_QM_CQ_BUF_RDATA 0xFC830C + +#endif /* ASIC_REG_TPC7_QM_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h new file mode 100644 index 000000000000..920231d0afa5 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC_PLL_REGS_H_ +#define ASIC_REG_TPC_PLL_REGS_H_ + +/* + ***************************************** + * TPC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmTPC_PLL_NR 0xE01100 + +#define mmTPC_PLL_NF 0xE01104 + +#define mmTPC_PLL_OD 0xE01108 + +#define mmTPC_PLL_NB 0xE0110C + +#define mmTPC_PLL_CFG 0xE01110 + +#define mmTPC_PLL_LOSE_MASK 0xE01120 + +#define mmTPC_PLL_LOCK_INTR 0xE01128 + +#define mmTPC_PLL_LOCK_BYPASS 0xE0112C + +#define mmTPC_PLL_DATA_CHNG 0xE01130 + +#define mmTPC_PLL_RST 0xE01134 + +#define mmTPC_PLL_SLIP_WD_CNTR 0xE01150 + +#define mmTPC_PLL_DIV_FACTOR_0 0xE01200 + +#define mmTPC_PLL_DIV_FACTOR_1 0xE01204 + +#define mmTPC_PLL_DIV_FACTOR_2 0xE01208 + +#define mmTPC_PLL_DIV_FACTOR_3 0xE0120C + +#define mmTPC_PLL_DIV_FACTOR_CMD_0 0xE01220 + +#define mmTPC_PLL_DIV_FACTOR_CMD_1 0xE01224 + +#define mmTPC_PLL_DIV_FACTOR_CMD_2 0xE01228 + +#define mmTPC_PLL_DIV_FACTOR_CMD_3 0xE0122C + +#define mmTPC_PLL_DIV_SEL_0 0xE01280 + +#define mmTPC_PLL_DIV_SEL_1 0xE01284 + +#define mmTPC_PLL_DIV_SEL_2 0xE01288 + +#define mmTPC_PLL_DIV_SEL_3 0xE0128C + +#define mmTPC_PLL_DIV_EN_0 0xE012A0 + +#define mmTPC_PLL_DIV_EN_1 0xE012A4 + +#define mmTPC_PLL_DIV_EN_2 0xE012A8 + +#define mmTPC_PLL_DIV_EN_3 0xE012AC + +#define mmTPC_PLL_DIV_FACTOR_BUSY_0 0xE012C0 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_1 0xE012C4 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_2 0xE012C8 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_3 0xE012CC + +#define mmTPC_PLL_CLK_GATER 0xE01300 + +#define mmTPC_PLL_CLK_RLX_0 0xE01310 + +#define mmTPC_PLL_CLK_RLX_1 0xE01314 + +#define mmTPC_PLL_CLK_RLX_2 0xE01318 + +#define mmTPC_PLL_CLK_RLX_3 0xE0131C + +#define mmTPC_PLL_REF_CNTR_PERIOD 0xE01400 + +#define mmTPC_PLL_REF_LOW_THRESHOLD 0xE01410 + +#define mmTPC_PLL_REF_HIGH_THRESHOLD 0xE01420 + +#define mmTPC_PLL_PLL_NOT_STABLE 0xE01430 + +#define mmTPC_PLL_FREQ_CALC_EN 0xE01440 + +#endif /* ASIC_REG_TPC_PLL_REGS_H_ */ + diff --git a/drivers/misc/habanalabs/include/goya/goya.h b/drivers/misc/habanalabs/include/goya/goya.h new file mode 100644 index 000000000000..614149efa412 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_H +#define GOYA_H + +#include "asic_reg/goya_regs.h" + +#include <linux/types.h> + +#define SRAM_CFG_BAR_ID 0 +#define MSIX_BAR_ID 2 +#define DDR_BAR_ID 4 + +#define CFG_BAR_SIZE 0x10000000ull /* 256MB */ +#define MSIX_BAR_SIZE 0x1000ull /* 4KB */ + +#define CFG_BASE 0x7FFC000000ull +#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ + +#define SRAM_BASE_ADDR 0x7FF0000000ull +#define SRAM_SIZE 0x32A0000 /* 50.625MB */ + +#define DRAM_PHYS_BASE 0x0ull + +#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ +#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ + +#define GOYA_MSIX_ENTRIES 8 + +#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ + +#define MAX_ASID 1024 + +#define PROT_BITS_OFFS 0xF80 + +#define DMA_MAX_NUM 5 + +#define TPC_MAX_NUM 8 + +#endif /* GOYA_H */ diff --git a/drivers/misc/habanalabs/include/goya/goya_async_events.h b/drivers/misc/habanalabs/include/goya/goya_async_events.h new file mode 100644 index 000000000000..497937a17ee9 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_async_events.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef __GOYA_ASYNC_EVENTS_H_ +#define __GOYA_ASYNC_EVENTS_H_ + +enum goya_async_event_id { + GOYA_ASYNC_EVENT_ID_PCIE_IF = 33, + GOYA_ASYNC_EVENT_ID_TPC0_ECC = 36, + GOYA_ASYNC_EVENT_ID_TPC1_ECC = 39, + GOYA_ASYNC_EVENT_ID_TPC2_ECC = 42, + GOYA_ASYNC_EVENT_ID_TPC3_ECC = 45, + GOYA_ASYNC_EVENT_ID_TPC4_ECC = 48, + GOYA_ASYNC_EVENT_ID_TPC5_ECC = 51, + GOYA_ASYNC_EVENT_ID_TPC6_ECC = 54, + GOYA_ASYNC_EVENT_ID_TPC7_ECC = 57, + GOYA_ASYNC_EVENT_ID_MME_ECC = 60, + GOYA_ASYNC_EVENT_ID_MME_ECC_EXT = 61, + GOYA_ASYNC_EVENT_ID_MMU_ECC = 63, + GOYA_ASYNC_EVENT_ID_DMA_MACRO = 64, + GOYA_ASYNC_EVENT_ID_DMA_ECC = 66, + GOYA_ASYNC_EVENT_ID_CPU_IF_ECC = 75, + GOYA_ASYNC_EVENT_ID_PSOC_MEM = 78, + GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT = 79, + GOYA_ASYNC_EVENT_ID_SRAM0 = 81, + GOYA_ASYNC_EVENT_ID_SRAM1 = 82, + GOYA_ASYNC_EVENT_ID_SRAM2 = 83, + GOYA_ASYNC_EVENT_ID_SRAM3 = 84, + GOYA_ASYNC_EVENT_ID_SRAM4 = 85, + GOYA_ASYNC_EVENT_ID_SRAM5 = 86, + GOYA_ASYNC_EVENT_ID_SRAM6 = 87, + GOYA_ASYNC_EVENT_ID_SRAM7 = 88, + GOYA_ASYNC_EVENT_ID_SRAM8 = 89, + GOYA_ASYNC_EVENT_ID_SRAM9 = 90, + GOYA_ASYNC_EVENT_ID_SRAM10 = 91, + GOYA_ASYNC_EVENT_ID_SRAM11 = 92, + GOYA_ASYNC_EVENT_ID_SRAM12 = 93, + GOYA_ASYNC_EVENT_ID_SRAM13 = 94, + GOYA_ASYNC_EVENT_ID_SRAM14 = 95, + GOYA_ASYNC_EVENT_ID_SRAM15 = 96, + GOYA_ASYNC_EVENT_ID_SRAM16 = 97, + GOYA_ASYNC_EVENT_ID_SRAM17 = 98, + GOYA_ASYNC_EVENT_ID_SRAM18 = 99, + GOYA_ASYNC_EVENT_ID_SRAM19 = 100, + GOYA_ASYNC_EVENT_ID_SRAM20 = 101, + GOYA_ASYNC_EVENT_ID_SRAM21 = 102, + GOYA_ASYNC_EVENT_ID_SRAM22 = 103, + GOYA_ASYNC_EVENT_ID_SRAM23 = 104, + GOYA_ASYNC_EVENT_ID_SRAM24 = 105, + GOYA_ASYNC_EVENT_ID_SRAM25 = 106, + GOYA_ASYNC_EVENT_ID_SRAM26 = 107, + GOYA_ASYNC_EVENT_ID_SRAM27 = 108, + GOYA_ASYNC_EVENT_ID_SRAM28 = 109, + GOYA_ASYNC_EVENT_ID_SRAM29 = 110, + GOYA_ASYNC_EVENT_ID_GIC500 = 112, + GOYA_ASYNC_EVENT_ID_PCIE_DEC = 115, + GOYA_ASYNC_EVENT_ID_TPC0_DEC = 117, + GOYA_ASYNC_EVENT_ID_TPC1_DEC = 120, + GOYA_ASYNC_EVENT_ID_TPC2_DEC = 123, + GOYA_ASYNC_EVENT_ID_TPC3_DEC = 126, + GOYA_ASYNC_EVENT_ID_TPC4_DEC = 129, + GOYA_ASYNC_EVENT_ID_TPC5_DEC = 132, + GOYA_ASYNC_EVENT_ID_TPC6_DEC = 135, + GOYA_ASYNC_EVENT_ID_TPC7_DEC = 138, + GOYA_ASYNC_EVENT_ID_AXI_ECC = 139, + GOYA_ASYNC_EVENT_ID_L2_RAM_ECC = 140, + GOYA_ASYNC_EVENT_ID_MME_WACS = 141, + GOYA_ASYNC_EVENT_ID_MME_WACSD = 142, + GOYA_ASYNC_EVENT_ID_PLL0 = 143, + GOYA_ASYNC_EVENT_ID_PLL1 = 144, + GOYA_ASYNC_EVENT_ID_PLL3 = 146, + GOYA_ASYNC_EVENT_ID_PLL4 = 147, + GOYA_ASYNC_EVENT_ID_PLL5 = 148, + GOYA_ASYNC_EVENT_ID_PLL6 = 149, + GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER = 155, + GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC = 159, + GOYA_ASYNC_EVENT_ID_PSOC = 160, + GOYA_ASYNC_EVENT_ID_PCIE_FLR = 171, + GOYA_ASYNC_EVENT_ID_PCIE_HOT_RESET = 172, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG0 = 174, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG1 = 175, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG2 = 176, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG3 = 177, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG0 = 178, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG1 = 179, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG2 = 180, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG3 = 181, + GOYA_ASYNC_EVENT_ID_PCIE_APB = 182, + GOYA_ASYNC_EVENT_ID_PCIE_QDB = 183, + GOYA_ASYNC_EVENT_ID_PCIE_BM_D_P_WR = 184, + GOYA_ASYNC_EVENT_ID_PCIE_BM_D_RD = 185, + GOYA_ASYNC_EVENT_ID_PCIE_BM_U_P_WR = 186, + GOYA_ASYNC_EVENT_ID_PCIE_BM_U_RD = 187, + GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU = 190, + GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR = 191, + GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU = 200, + GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR = 201, + GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU = 210, + GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR = 211, + GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU = 220, + GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR = 221, + GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU = 230, + GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR = 231, + GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU = 240, + GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR = 241, + GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU = 250, + GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR = 251, + GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU = 260, + GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR = 261, + GOYA_ASYNC_EVENT_ID_MMU_SBA_SPMU0 = 270, + GOYA_ASYNC_EVENT_ID_MMU_SBA_SPMU1 = 271, + GOYA_ASYNC_EVENT_ID_MME_WACS_UP = 272, + GOYA_ASYNC_EVENT_ID_MME_WACS_DOWN = 273, + GOYA_ASYNC_EVENT_ID_MMU_PAGE_FAULT = 280, + GOYA_ASYNC_EVENT_ID_MMU_WR_PERM = 281, + GOYA_ASYNC_EVENT_ID_MMU_DBG_BM = 282, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 = 290, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH1 = 291, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH2 = 292, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH3 = 293, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH4 = 294, + GOYA_ASYNC_EVENT_ID_DDR0_PHY_DFI = 300, + GOYA_ASYNC_EVENT_ID_DDR0_ECC_SCRUB = 301, + GOYA_ASYNC_EVENT_ID_DDR0_DB_ECC = 302, + GOYA_ASYNC_EVENT_ID_DDR0_SB_ECC = 303, + GOYA_ASYNC_EVENT_ID_DDR0_SB_ECC_MC = 304, + GOYA_ASYNC_EVENT_ID_DDR0_AXI_RD = 305, + GOYA_ASYNC_EVENT_ID_DDR0_AXI_WR = 306, + GOYA_ASYNC_EVENT_ID_DDR1_PHY_DFI = 310, + GOYA_ASYNC_EVENT_ID_DDR1_ECC_SCRUB = 311, + GOYA_ASYNC_EVENT_ID_DDR1_DB_ECC = 312, + GOYA_ASYNC_EVENT_ID_DDR1_SB_ECC = 313, + GOYA_ASYNC_EVENT_ID_DDR1_SB_ECC_MC = 314, + GOYA_ASYNC_EVENT_ID_DDR1_AXI_RD = 315, + GOYA_ASYNC_EVENT_ID_DDR1_AXI_WR = 316, + GOYA_ASYNC_EVENT_ID_CPU_BMON = 320, + GOYA_ASYNC_EVENT_ID_TS_EAST = 322, + GOYA_ASYNC_EVENT_ID_TS_WEST = 323, + GOYA_ASYNC_EVENT_ID_TS_NORTH = 324, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_0 = 330, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_1 = 331, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_2 = 332, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET = 356, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT = 361, + GOYA_ASYNC_EVENT_ID_TPC0_CMDQ = 430, + GOYA_ASYNC_EVENT_ID_TPC1_CMDQ = 431, + GOYA_ASYNC_EVENT_ID_TPC2_CMDQ = 432, + GOYA_ASYNC_EVENT_ID_TPC3_CMDQ = 433, + GOYA_ASYNC_EVENT_ID_TPC4_CMDQ = 434, + GOYA_ASYNC_EVENT_ID_TPC5_CMDQ = 435, + GOYA_ASYNC_EVENT_ID_TPC6_CMDQ = 436, + GOYA_ASYNC_EVENT_ID_TPC7_CMDQ = 437, + GOYA_ASYNC_EVENT_ID_TPC0_QM = 438, + GOYA_ASYNC_EVENT_ID_TPC1_QM = 439, + GOYA_ASYNC_EVENT_ID_TPC2_QM = 440, + GOYA_ASYNC_EVENT_ID_TPC3_QM = 441, + GOYA_ASYNC_EVENT_ID_TPC4_QM = 442, + GOYA_ASYNC_EVENT_ID_TPC5_QM = 443, + GOYA_ASYNC_EVENT_ID_TPC6_QM = 444, + GOYA_ASYNC_EVENT_ID_TPC7_QM = 445, + GOYA_ASYNC_EVENT_ID_MME_QM = 447, + GOYA_ASYNC_EVENT_ID_MME_CMDQ = 448, + GOYA_ASYNC_EVENT_ID_DMA0_QM = 449, + GOYA_ASYNC_EVENT_ID_DMA1_QM = 450, + GOYA_ASYNC_EVENT_ID_DMA2_QM = 451, + GOYA_ASYNC_EVENT_ID_DMA3_QM = 452, + GOYA_ASYNC_EVENT_ID_DMA4_QM = 453, + GOYA_ASYNC_EVENT_ID_DMA_ON_HBW = 454, + GOYA_ASYNC_EVENT_ID_DMA0_CH = 455, + GOYA_ASYNC_EVENT_ID_DMA1_CH = 456, + GOYA_ASYNC_EVENT_ID_DMA2_CH = 457, + GOYA_ASYNC_EVENT_ID_DMA3_CH = 458, + GOYA_ASYNC_EVENT_ID_DMA4_CH = 459, + GOYA_ASYNC_EVENT_ID_PI_UPDATE = 484, + GOYA_ASYNC_EVENT_ID_HALT_MACHINE = 485, + GOYA_ASYNC_EVENT_ID_INTS_REGISTER = 486, + GOYA_ASYNC_EVENT_ID_SOFT_RESET = 487, + GOYA_ASYNC_EVENT_ID_LAST_VALID_ID = 1023, + GOYA_ASYNC_EVENT_ID_SIZE +}; + +#endif /* __GOYA_ASYNC_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/goya_fw_if.h b/drivers/misc/habanalabs/include/goya/goya_fw_if.h new file mode 100644 index 000000000000..a9920cb4a07b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_fw_if.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_FW_IF_H +#define GOYA_FW_IF_H + +#define CPU_BOOT_ADDR 0x7FF8040000ull + +#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ +#define LINUX_FW_OFFSET 0x800000 /* 8MB in DDR */ + +enum goya_pll_index { + CPU_PLL = 0, + IC_PLL, + MC_PLL, + MME_PLL, + PCI_PLL, + EMMC_PLL, + TPC_PLL +}; + +#define GOYA_PLL_FREQ_LOW 50000000 /* 50 MHz */ + +#endif /* GOYA_FW_IF_H */ diff --git a/drivers/misc/habanalabs/include/goya/goya_packets.h b/drivers/misc/habanalabs/include/goya/goya_packets.h new file mode 100644 index 000000000000..a14407b975e4 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_packets.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2017-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_PACKETS_H +#define GOYA_PACKETS_H + +#include <linux/types.h> + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull + +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +enum goya_dma_direction { + DMA_HOST_TO_DRAM, + DMA_HOST_TO_SRAM, + DMA_DRAM_TO_SRAM, + DMA_SRAM_TO_DRAM, + DMA_SRAM_TO_HOST, + DMA_DRAM_TO_HOST, + DMA_DRAM_TO_DRAM, + DMA_SRAM_TO_SRAM, + DMA_ENUM_MAX +}; + +#define GOYA_PKT_CTL_OPCODE_SHIFT 24 +#define GOYA_PKT_CTL_OPCODE_MASK 0x1F000000 + +#define GOYA_PKT_CTL_EB_SHIFT 29 +#define GOYA_PKT_CTL_EB_MASK 0x20000000 + +#define GOYA_PKT_CTL_RB_SHIFT 30 +#define GOYA_PKT_CTL_RB_MASK 0x40000000 + +#define GOYA_PKT_CTL_MB_SHIFT 31 +#define GOYA_PKT_CTL_MB_MASK 0x80000000 + +struct packet_nop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_stop { + __le32 reserved; + __le32 ctl; +}; + +#define GOYA_PKT_WREG32_CTL_REG_OFFSET_SHIFT 0 +#define GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK 0x0000FFFF + +struct packet_wreg32 { + __le32 value; + __le32 ctl; +}; + +struct packet_wreg_bulk { + __le32 size64; + __le32 ctl; + __le64 values[0]; /* data starts here */ +}; + +struct packet_msg_long { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +struct packet_msg_short { + __le32 value; + __le32 ctl; +}; + +struct packet_msg_prot { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +struct packet_fence { + __le32 cfg; + __le32 ctl; +}; + +#define GOYA_PKT_LIN_DMA_CTL_WO_SHIFT 0 +#define GOYA_PKT_LIN_DMA_CTL_WO_MASK 0x00000001 + +#define GOYA_PKT_LIN_DMA_CTL_RDCOMP_SHIFT 1 +#define GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK 0x00000002 + +#define GOYA_PKT_LIN_DMA_CTL_WRCOMP_SHIFT 2 +#define GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK 0x00000004 + +#define GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT 6 +#define GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000040 + +#define GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT 20 +#define GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK 0x00700000 + +struct packet_lin_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; + __le64 dst_addr; +}; + +struct packet_cp_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; +}; + +#endif /* GOYA_PACKETS_H */ diff --git a/drivers/misc/habanalabs/include/hl_boot_if.h b/drivers/misc/habanalabs/include/hl_boot_if.h new file mode 100644 index 000000000000..7475732b9996 --- /dev/null +++ b/drivers/misc/habanalabs/include/hl_boot_if.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef HL_BOOT_IF_H +#define HL_BOOT_IF_H + +enum cpu_boot_status { + CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */ + CPU_BOOT_STATUS_IN_WFE, + CPU_BOOT_STATUS_DRAM_RDY, + CPU_BOOT_STATUS_SRAM_AVAIL, + CPU_BOOT_STATUS_IN_BTL, /* BTL is H/W FSM */ + CPU_BOOT_STATUS_IN_PREBOOT, + CPU_BOOT_STATUS_IN_SPL, + CPU_BOOT_STATUS_IN_UBOOT, + CPU_BOOT_STATUS_DRAM_INIT_FAIL, + CPU_BOOT_STATUS_FIT_CORRUPTED +}; + +enum kmd_msg { + KMD_MSG_NA = 0, + KMD_MSG_GOTO_WFE, + KMD_MSG_FIT_RDY +}; + +#endif /* HL_BOOT_IF_H */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h new file mode 100644 index 000000000000..b680052ee3f0 --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_GENERAL_H_ +#define INCLUDE_MMU_GENERAL_H_ + +#define PAGE_SHIFT_4KB 12 +#define PAGE_SHIFT_2MB 21 +#define PAGE_SIZE_2MB (_AC(1, UL) << PAGE_SHIFT_2MB) +#define PAGE_SIZE_4KB (_AC(1, UL) << PAGE_SHIFT_4KB) +#define PAGE_MASK_2MB (~(PAGE_SIZE_2MB - 1)) + +#define PAGE_PRESENT_MASK 0x0000000000001 +#define SWAP_OUT_MASK 0x0000000000004 +#define LAST_MASK 0x0000000000800 +#define PHYS_ADDR_MASK 0x3FFFFFFFFF000ull +#define HOP0_MASK 0x3000000000000ull +#define HOP1_MASK 0x0FF8000000000ull +#define HOP2_MASK 0x0007FC0000000ull +#define HOP3_MASK 0x000003FE00000 +#define HOP4_MASK 0x00000001FF000 +#define OFFSET_MASK 0x0000000000FFF + +#define HOP0_SHIFT 48 +#define HOP1_SHIFT 39 +#define HOP2_SHIFT 30 +#define HOP3_SHIFT 21 +#define HOP4_SHIFT 12 + +#define PTE_PHYS_ADDR_SHIFT 12 +#define PTE_PHYS_ADDR_MASK ~0xFFF + +#define HL_PTE_SIZE sizeof(u64) +#define HOP_TABLE_SIZE PAGE_SIZE_4KB +#define PTE_ENTRIES_IN_HOP (HOP_TABLE_SIZE / HL_PTE_SIZE) +#define HOP0_TABLES_TOTAL_SIZE (HOP_TABLE_SIZE * MAX_ASID) + +#define MMU_HOP0_PA43_12_SHIFT 12 +#define MMU_HOP0_PA49_44_SHIFT (12 + 32) + +#define MMU_CONFIG_TIMEOUT_USEC 2000 /* 2 ms */ + +#endif /* INCLUDE_MMU_GENERAL_H_ */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h new file mode 100644 index 000000000000..8539dd041f2c --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_V1_0_H_ +#define INCLUDE_MMU_V1_0_H_ + +#define MMU_HOP0_PA43_12 0x490004 +#define MMU_HOP0_PA49_44 0x490008 +#define MMU_ASID_BUSY 0x490000 + +#endif /* INCLUDE_MMU_V1_0_H_ */ diff --git a/drivers/misc/habanalabs/include/qman_if.h b/drivers/misc/habanalabs/include/qman_if.h new file mode 100644 index 000000000000..bf59bbe27fdc --- /dev/null +++ b/drivers/misc/habanalabs/include/qman_if.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef QMAN_IF_H +#define QMAN_IF_H + +#include <linux/types.h> + +/* + * PRIMARY QUEUE + */ + +struct hl_bd { + __le64 ptr; + __le32 len; + __le32 ctl; +}; + +#define HL_BD_SIZE sizeof(struct hl_bd) + +/* + * BD_CTL_REPEAT_VALID tells the CP whether the repeat field in the BD CTL is + * valid. 1 means the repeat field is valid, 0 means not-valid, + * i.e. repeat == 1 + */ +#define BD_CTL_REPEAT_VALID_SHIFT 24 +#define BD_CTL_REPEAT_VALID_MASK 0x01000000 + +#define BD_CTL_SHADOW_INDEX_SHIFT 0 +#define BD_CTL_SHADOW_INDEX_MASK 0x00000FFF + +/* + * COMPLETION QUEUE + */ + +struct hl_cq_entry { + __le32 data; +}; + +#define HL_CQ_ENTRY_SIZE sizeof(struct hl_cq_entry) + +#define CQ_ENTRY_READY_SHIFT 31 +#define CQ_ENTRY_READY_MASK 0x80000000 + +#define CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT 30 +#define CQ_ENTRY_SHADOW_INDEX_VALID_MASK 0x40000000 + +#define CQ_ENTRY_SHADOW_INDEX_SHIFT BD_CTL_SHADOW_INDEX_SHIFT +#define CQ_ENTRY_SHADOW_INDEX_MASK BD_CTL_SHADOW_INDEX_MASK + + +#endif /* QMAN_IF_H */ diff --git a/drivers/misc/habanalabs/irq.c b/drivers/misc/habanalabs/irq.c new file mode 100644 index 000000000000..e69a09c10e3f --- /dev/null +++ b/drivers/misc/habanalabs/irq.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#include <linux/slab.h> + +/** + * This structure is used to schedule work of EQ entry and armcp_reset event + * + * @eq_work - workqueue object to run when EQ entry is received + * @hdev - pointer to device structure + * @eq_entry - copy of the EQ entry + */ +struct hl_eqe_work { + struct work_struct eq_work; + struct hl_device *hdev; + struct hl_eq_entry eq_entry; +}; + +/* + * hl_cq_inc_ptr - increment ci or pi of cq + * + * @ptr: the current ci or pi value of the completion queue + * + * Increment ptr by 1. If it reaches the number of completion queue + * entries, set it to 0 + */ +inline u32 hl_cq_inc_ptr(u32 ptr) +{ + ptr++; + if (unlikely(ptr == HL_CQ_LENGTH)) + ptr = 0; + return ptr; +} + +/* + * hl_eq_inc_ptr - increment ci of eq + * + * @ptr: the current ci value of the event queue + * + * Increment ptr by 1. If it reaches the number of event queue + * entries, set it to 0 + */ +inline u32 hl_eq_inc_ptr(u32 ptr) +{ + ptr++; + if (unlikely(ptr == HL_EQ_LENGTH)) + ptr = 0; + return ptr; +} + +static void irq_handle_eqe(struct work_struct *work) +{ + struct hl_eqe_work *eqe_work = container_of(work, struct hl_eqe_work, + eq_work); + struct hl_device *hdev = eqe_work->hdev; + + hdev->asic_funcs->handle_eqe(hdev, &eqe_work->eq_entry); + + kfree(eqe_work); +} + +/* + * hl_irq_handler_cq - irq handler for completion queue + * + * @irq: irq number + * @arg: pointer to completion queue structure + * + */ +irqreturn_t hl_irq_handler_cq(int irq, void *arg) +{ + struct hl_cq *cq = arg; + struct hl_device *hdev = cq->hdev; + struct hl_hw_queue *queue; + struct hl_cs_job *job; + bool shadow_index_valid; + u16 shadow_index; + u32 *cq_entry; + u32 *cq_base; + + if (hdev->disabled) { + dev_dbg(hdev->dev, + "Device disabled but received IRQ %d for CQ %d\n", + irq, cq->hw_queue_id); + return IRQ_HANDLED; + } + + cq_base = (u32 *) (uintptr_t) cq->kernel_address; + + while (1) { + bool entry_ready = ((cq_base[cq->ci] & CQ_ENTRY_READY_MASK) + >> CQ_ENTRY_READY_SHIFT); + + if (!entry_ready) + break; + + cq_entry = (u32 *) &cq_base[cq->ci]; + + /* + * Make sure we read CQ entry contents after we've + * checked the ownership bit. + */ + dma_rmb(); + + shadow_index_valid = + ((*cq_entry & CQ_ENTRY_SHADOW_INDEX_VALID_MASK) + >> CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT); + + shadow_index = (u16) + ((*cq_entry & CQ_ENTRY_SHADOW_INDEX_MASK) + >> CQ_ENTRY_SHADOW_INDEX_SHIFT); + + queue = &hdev->kernel_queues[cq->hw_queue_id]; + + if ((shadow_index_valid) && (!hdev->disabled)) { + job = queue->shadow_queue[hl_pi_2_offset(shadow_index)]; + queue_work(hdev->cq_wq, &job->finish_work); + } + + /* + * Update ci of the context's queue. There is no + * need to protect it with spinlock because this update is + * done only inside IRQ and there is a different IRQ per + * queue + */ + queue->ci = hl_queue_inc_ptr(queue->ci); + + /* Clear CQ entry ready bit */ + cq_base[cq->ci] &= ~CQ_ENTRY_READY_MASK; + + cq->ci = hl_cq_inc_ptr(cq->ci); + + /* Increment free slots */ + atomic_inc(&cq->free_slots_cnt); + } + + return IRQ_HANDLED; +} + +/* + * hl_irq_handler_eq - irq handler for event queue + * + * @irq: irq number + * @arg: pointer to event queue structure + * + */ +irqreturn_t hl_irq_handler_eq(int irq, void *arg) +{ + struct hl_eq *eq = arg; + struct hl_device *hdev = eq->hdev; + struct hl_eq_entry *eq_entry; + struct hl_eq_entry *eq_base; + struct hl_eqe_work *handle_eqe_work; + + eq_base = (struct hl_eq_entry *) (uintptr_t) eq->kernel_address; + + while (1) { + bool entry_ready = + ((__le32_to_cpu(eq_base[eq->ci].hdr.ctl) & + EQ_CTL_READY_MASK) >> EQ_CTL_READY_SHIFT); + + if (!entry_ready) + break; + + eq_entry = &eq_base[eq->ci]; + + /* + * Make sure we read EQ entry contents after we've + * checked the ownership bit. + */ + dma_rmb(); + + if (hdev->disabled) { + dev_warn(hdev->dev, + "Device disabled but received IRQ %d for EQ\n", + irq); + goto skip_irq; + } + + handle_eqe_work = kmalloc(sizeof(*handle_eqe_work), GFP_ATOMIC); + if (handle_eqe_work) { + INIT_WORK(&handle_eqe_work->eq_work, irq_handle_eqe); + handle_eqe_work->hdev = hdev; + + memcpy(&handle_eqe_work->eq_entry, eq_entry, + sizeof(*eq_entry)); + + queue_work(hdev->eq_wq, &handle_eqe_work->eq_work); + } +skip_irq: + /* Clear EQ entry ready bit */ + eq_entry->hdr.ctl = + __cpu_to_le32(__le32_to_cpu(eq_entry->hdr.ctl) & + ~EQ_CTL_READY_MASK); + + eq->ci = hl_eq_inc_ptr(eq->ci); + + hdev->asic_funcs->update_eq_ci(hdev, eq->ci); + } + + return IRQ_HANDLED; +} + +/* + * hl_cq_init - main initialization function for an cq object + * + * @hdev: pointer to device structure + * @q: pointer to cq structure + * @hw_queue_id: The H/W queue ID this completion queue belongs to + * + * Allocate dma-able memory for the completion queue and initialize fields + * Returns 0 on success + */ +int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id) +{ + void *p; + + BUILD_BUG_ON(HL_CQ_SIZE_IN_BYTES > HL_PAGE_SIZE); + + p = hdev->asic_funcs->dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES, + &q->bus_address, GFP_KERNEL | __GFP_ZERO); + if (!p) + return -ENOMEM; + + q->hdev = hdev; + q->kernel_address = (u64) (uintptr_t) p; + q->hw_queue_id = hw_queue_id; + q->ci = 0; + q->pi = 0; + + atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH); + + return 0; +} + +/* + * hl_cq_fini - destroy completion queue + * + * @hdev: pointer to device structure + * @q: pointer to cq structure + * + * Free the completion queue memory + */ +void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q) +{ + hdev->asic_funcs->dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES, + (void *) (uintptr_t) q->kernel_address, q->bus_address); +} + +void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q) +{ + q->ci = 0; + q->pi = 0; + + atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH); + + /* + * It's not enough to just reset the PI/CI because the H/W may have + * written valid completion entries before it was halted and therefore + * we need to clean the actual queues so we won't process old entries + * when the device is operational again + */ + + memset((void *) (uintptr_t) q->kernel_address, 0, HL_CQ_SIZE_IN_BYTES); +} + +/* + * hl_eq_init - main initialization function for an event queue object + * + * @hdev: pointer to device structure + * @q: pointer to eq structure + * + * Allocate dma-able memory for the event queue and initialize fields + * Returns 0 on success + */ +int hl_eq_init(struct hl_device *hdev, struct hl_eq *q) +{ + void *p; + + BUILD_BUG_ON(HL_EQ_SIZE_IN_BYTES > HL_PAGE_SIZE); + + p = hdev->asic_funcs->dma_alloc_coherent(hdev, HL_EQ_SIZE_IN_BYTES, + &q->bus_address, GFP_KERNEL | __GFP_ZERO); + if (!p) + return -ENOMEM; + + q->hdev = hdev; + q->kernel_address = (u64) (uintptr_t) p; + q->ci = 0; + + return 0; +} + +/* + * hl_eq_fini - destroy event queue + * + * @hdev: pointer to device structure + * @q: pointer to eq structure + * + * Free the event queue memory + */ +void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q) +{ + flush_workqueue(hdev->eq_wq); + + hdev->asic_funcs->dma_free_coherent(hdev, HL_EQ_SIZE_IN_BYTES, + (void *) (uintptr_t) q->kernel_address, q->bus_address); +} + +void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q) +{ + q->ci = 0; + + /* + * It's not enough to just reset the PI/CI because the H/W may have + * written valid completion entries before it was halted and therefore + * we need to clean the actual queues so we won't process old entries + * when the device is operational again + */ + + memset((void *) (uintptr_t) q->kernel_address, 0, HL_EQ_SIZE_IN_BYTES); +} diff --git a/drivers/misc/habanalabs/memory.c b/drivers/misc/habanalabs/memory.c new file mode 100644 index 000000000000..3a12fd1a5274 --- /dev/null +++ b/drivers/misc/habanalabs/memory.c @@ -0,0 +1,1723 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include <uapi/misc/habanalabs.h> +#include "habanalabs.h" +#include "include/hw_ip/mmu/mmu_general.h" + +#include <linux/uaccess.h> +#include <linux/slab.h> +#include <linux/genalloc.h> + +#define PGS_IN_2MB_PAGE (PAGE_SIZE_2MB >> PAGE_SHIFT) +#define HL_MMU_DEBUG 0 + +/* + * The va ranges in context object contain a list with the available chunks of + * device virtual memory. + * There is one range for host allocations and one for DRAM allocations. + * + * On initialization each range contains one chunk of all of its available + * virtual range which is a half of the total device virtual range. + * + * On each mapping of physical pages, a suitable virtual range chunk (with a + * minimum size) is selected from the list. If the chunk size equals the + * requested size, the chunk is returned. Otherwise, the chunk is split into + * two chunks - one to return as result and a remainder to stay in the list. + * + * On each Unmapping of a virtual address, the relevant virtual chunk is + * returned to the list. The chunk is added to the list and if its edges match + * the edges of the adjacent chunks (means a contiguous chunk can be created), + * the chunks are merged. + * + * On finish, the list is checked to have only one chunk of all the relevant + * virtual range (which is a half of the device total virtual range). + * If not (means not all mappings were unmapped), a warning is printed. + */ + +/* + * alloc_device_memory - allocate device memory + * + * @ctx : current context + * @args : host parameters containing the requested size + * @ret_handle : result handle + * + * This function does the following: + * - Allocate the requested size rounded up to 2MB pages + * - Return unique handle + */ +static int alloc_device_memory(struct hl_ctx *ctx, struct hl_mem_in *args, + u32 *ret_handle) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm *vm = &hdev->vm; + struct hl_vm_phys_pg_pack *phys_pg_pack; + u64 paddr = 0; + u32 total_size, num_pgs, num_curr_pgs, page_size, page_shift; + int handle, rc, i; + bool contiguous; + + num_curr_pgs = 0; + page_size = hdev->asic_prop.dram_page_size; + page_shift = __ffs(page_size); + num_pgs = (args->alloc.mem_size + (page_size - 1)) >> page_shift; + total_size = num_pgs << page_shift; + + contiguous = args->flags & HL_MEM_CONTIGUOUS; + + if (contiguous) { + paddr = (u64) gen_pool_alloc(vm->dram_pg_pool, total_size); + if (!paddr) { + dev_err(hdev->dev, + "failed to allocate %u huge contiguous pages\n", + num_pgs); + return -ENOMEM; + } + } + + phys_pg_pack = kzalloc(sizeof(*phys_pg_pack), GFP_KERNEL); + if (!phys_pg_pack) { + rc = -ENOMEM; + goto pages_pack_err; + } + + phys_pg_pack->vm_type = VM_TYPE_PHYS_PACK; + phys_pg_pack->asid = ctx->asid; + phys_pg_pack->npages = num_pgs; + phys_pg_pack->page_size = page_size; + phys_pg_pack->total_size = total_size; + phys_pg_pack->flags = args->flags; + phys_pg_pack->contiguous = contiguous; + + phys_pg_pack->pages = kcalloc(num_pgs, sizeof(u64), GFP_KERNEL); + if (!phys_pg_pack->pages) { + rc = -ENOMEM; + goto pages_arr_err; + } + + if (phys_pg_pack->contiguous) { + for (i = 0 ; i < num_pgs ; i++) + phys_pg_pack->pages[i] = paddr + i * page_size; + } else { + for (i = 0 ; i < num_pgs ; i++) { + phys_pg_pack->pages[i] = (u64) gen_pool_alloc( + vm->dram_pg_pool, + page_size); + if (!phys_pg_pack->pages[i]) { + dev_err(hdev->dev, + "ioctl failed to allocate page\n"); + rc = -ENOMEM; + goto page_err; + } + + num_curr_pgs++; + } + } + + spin_lock(&vm->idr_lock); + handle = idr_alloc(&vm->phys_pg_pack_handles, phys_pg_pack, 1, 0, + GFP_ATOMIC); + spin_unlock(&vm->idr_lock); + + if (handle < 0) { + dev_err(hdev->dev, "Failed to get handle for page\n"); + rc = -EFAULT; + goto idr_err; + } + + for (i = 0 ; i < num_pgs ; i++) + kref_get(&vm->dram_pg_pool_refcount); + + phys_pg_pack->handle = handle; + + atomic64_add(phys_pg_pack->total_size, &ctx->dram_phys_mem); + atomic64_add(phys_pg_pack->total_size, &hdev->dram_used_mem); + + *ret_handle = handle; + + return 0; + +idr_err: +page_err: + if (!phys_pg_pack->contiguous) + for (i = 0 ; i < num_curr_pgs ; i++) + gen_pool_free(vm->dram_pg_pool, phys_pg_pack->pages[i], + page_size); + + kfree(phys_pg_pack->pages); +pages_arr_err: + kfree(phys_pg_pack); +pages_pack_err: + if (contiguous) + gen_pool_free(vm->dram_pg_pool, paddr, total_size); + + return rc; +} + +/* + * get_userptr_from_host_va - initialize userptr structure from given host + * virtual address + * + * @hdev : habanalabs device structure + * @args : parameters containing the virtual address and size + * @p_userptr : pointer to result userptr structure + * + * This function does the following: + * - Allocate userptr structure + * - Pin the given host memory using the userptr structure + * - Perform DMA mapping to have the DMA addresses of the pages + */ +static int get_userptr_from_host_va(struct hl_device *hdev, + struct hl_mem_in *args, struct hl_userptr **p_userptr) +{ + struct hl_userptr *userptr; + int rc; + + userptr = kzalloc(sizeof(*userptr), GFP_KERNEL); + if (!userptr) { + rc = -ENOMEM; + goto userptr_err; + } + + rc = hl_pin_host_memory(hdev, args->map_host.host_virt_addr, + args->map_host.mem_size, userptr); + if (rc) { + dev_err(hdev->dev, "Failed to pin host memory\n"); + goto pin_err; + } + + rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl, + userptr->sgt->nents, DMA_BIDIRECTIONAL); + if (rc) { + dev_err(hdev->dev, "failed to map sgt with DMA region\n"); + goto dma_map_err; + } + + userptr->dma_mapped = true; + userptr->dir = DMA_BIDIRECTIONAL; + userptr->vm_type = VM_TYPE_USERPTR; + + *p_userptr = userptr; + + return 0; + +dma_map_err: + hl_unpin_host_memory(hdev, userptr); +pin_err: + kfree(userptr); +userptr_err: + + return rc; +} + +/* + * free_userptr - free userptr structure + * + * @hdev : habanalabs device structure + * @userptr : userptr to free + * + * This function does the following: + * - Unpins the physical pages + * - Frees the userptr structure + */ +static void free_userptr(struct hl_device *hdev, struct hl_userptr *userptr) +{ + hl_unpin_host_memory(hdev, userptr); + kfree(userptr); +} + +/* + * dram_pg_pool_do_release - free DRAM pages pool + * + * @ref : pointer to reference object + * + * This function does the following: + * - Frees the idr structure of physical pages handles + * - Frees the generic pool of DRAM physical pages + */ +static void dram_pg_pool_do_release(struct kref *ref) +{ + struct hl_vm *vm = container_of(ref, struct hl_vm, + dram_pg_pool_refcount); + + /* + * free the idr here as only here we know for sure that there are no + * allocated physical pages and hence there are no handles in use + */ + idr_destroy(&vm->phys_pg_pack_handles); + gen_pool_destroy(vm->dram_pg_pool); +} + +/* + * free_phys_pg_pack - free physical page pack + * + * @hdev : habanalabs device structure + * @phys_pg_pack : physical page pack to free + * + * This function does the following: + * - For DRAM memory only, iterate over the pack and free each physical block + * structure by returning it to the general pool + * - Free the hl_vm_phys_pg_pack structure + */ +static void free_phys_pg_pack(struct hl_device *hdev, + struct hl_vm_phys_pg_pack *phys_pg_pack) +{ + struct hl_vm *vm = &hdev->vm; + int i; + + if (!phys_pg_pack->created_from_userptr) { + if (phys_pg_pack->contiguous) { + gen_pool_free(vm->dram_pg_pool, phys_pg_pack->pages[0], + phys_pg_pack->total_size); + + for (i = 0; i < phys_pg_pack->npages ; i++) + kref_put(&vm->dram_pg_pool_refcount, + dram_pg_pool_do_release); + } else { + for (i = 0 ; i < phys_pg_pack->npages ; i++) { + gen_pool_free(vm->dram_pg_pool, + phys_pg_pack->pages[i], + phys_pg_pack->page_size); + kref_put(&vm->dram_pg_pool_refcount, + dram_pg_pool_do_release); + } + } + } + + kfree(phys_pg_pack->pages); + kfree(phys_pg_pack); +} + +/* + * free_device_memory - free device memory + * + * @ctx : current context + * @handle : handle of the memory chunk to free + * + * This function does the following: + * - Free the device memory related to the given handle + */ +static int free_device_memory(struct hl_ctx *ctx, u32 handle) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm *vm = &hdev->vm; + struct hl_vm_phys_pg_pack *phys_pg_pack; + + spin_lock(&vm->idr_lock); + phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, handle); + if (phys_pg_pack) { + if (atomic_read(&phys_pg_pack->mapping_cnt) > 0) { + dev_err(hdev->dev, "handle %u is mapped, cannot free\n", + handle); + spin_unlock(&vm->idr_lock); + return -EINVAL; + } + + /* + * must remove from idr before the freeing of the physical + * pages as the refcount of the pool is also the trigger of the + * idr destroy + */ + idr_remove(&vm->phys_pg_pack_handles, handle); + spin_unlock(&vm->idr_lock); + + atomic64_sub(phys_pg_pack->total_size, &ctx->dram_phys_mem); + atomic64_sub(phys_pg_pack->total_size, &hdev->dram_used_mem); + + free_phys_pg_pack(hdev, phys_pg_pack); + } else { + spin_unlock(&vm->idr_lock); + dev_err(hdev->dev, + "free device memory failed, no match for handle %u\n", + handle); + return -EINVAL; + } + + return 0; +} + +/* + * clear_va_list_locked - free virtual addresses list + * + * @hdev : habanalabs device structure + * @va_list : list of virtual addresses to free + * + * This function does the following: + * - Iterate over the list and free each virtual addresses block + * + * This function should be called only when va_list lock is taken + */ +static void clear_va_list_locked(struct hl_device *hdev, + struct list_head *va_list) +{ + struct hl_vm_va_block *va_block, *tmp; + + list_for_each_entry_safe(va_block, tmp, va_list, node) { + list_del(&va_block->node); + kfree(va_block); + } +} + +/* + * print_va_list_locked - print virtual addresses list + * + * @hdev : habanalabs device structure + * @va_list : list of virtual addresses to print + * + * This function does the following: + * - Iterate over the list and print each virtual addresses block + * + * This function should be called only when va_list lock is taken + */ +static void print_va_list_locked(struct hl_device *hdev, + struct list_head *va_list) +{ +#if HL_MMU_DEBUG + struct hl_vm_va_block *va_block; + + dev_dbg(hdev->dev, "print va list:\n"); + + list_for_each_entry(va_block, va_list, node) + dev_dbg(hdev->dev, + "va block, start: 0x%llx, end: 0x%llx, size: %llu\n", + va_block->start, va_block->end, va_block->size); +#endif +} + +/* + * merge_va_blocks_locked - merge a virtual block if possible + * + * @hdev : pointer to the habanalabs device structure + * @va_list : pointer to the virtual addresses block list + * @va_block : virtual block to merge with adjacent blocks + * + * This function does the following: + * - Merge the given blocks with the adjacent blocks if their virtual ranges + * create a contiguous virtual range + * + * This Function should be called only when va_list lock is taken + */ +static void merge_va_blocks_locked(struct hl_device *hdev, + struct list_head *va_list, struct hl_vm_va_block *va_block) +{ + struct hl_vm_va_block *prev, *next; + + prev = list_prev_entry(va_block, node); + if (&prev->node != va_list && prev->end + 1 == va_block->start) { + prev->end = va_block->end; + prev->size = prev->end - prev->start; + list_del(&va_block->node); + kfree(va_block); + va_block = prev; + } + + next = list_next_entry(va_block, node); + if (&next->node != va_list && va_block->end + 1 == next->start) { + next->start = va_block->start; + next->size = next->end - next->start; + list_del(&va_block->node); + kfree(va_block); + } +} + +/* + * add_va_block_locked - add a virtual block to the virtual addresses list + * + * @hdev : pointer to the habanalabs device structure + * @va_list : pointer to the virtual addresses block list + * @start : start virtual address + * @end : end virtual address + * + * This function does the following: + * - Add the given block to the virtual blocks list and merge with other + * blocks if a contiguous virtual block can be created + * + * This Function should be called only when va_list lock is taken + */ +static int add_va_block_locked(struct hl_device *hdev, + struct list_head *va_list, u64 start, u64 end) +{ + struct hl_vm_va_block *va_block, *res = NULL; + u64 size = end - start; + + print_va_list_locked(hdev, va_list); + + list_for_each_entry(va_block, va_list, node) { + /* TODO: remove upon matureness */ + if (hl_mem_area_crosses_range(start, size, va_block->start, + va_block->end)) { + dev_err(hdev->dev, + "block crossing ranges at start 0x%llx, end 0x%llx\n", + va_block->start, va_block->end); + return -EINVAL; + } + + if (va_block->end < start) + res = va_block; + } + + va_block = kmalloc(sizeof(*va_block), GFP_KERNEL); + if (!va_block) + return -ENOMEM; + + va_block->start = start; + va_block->end = end; + va_block->size = size; + + if (!res) + list_add(&va_block->node, va_list); + else + list_add(&va_block->node, &res->node); + + merge_va_blocks_locked(hdev, va_list, va_block); + + print_va_list_locked(hdev, va_list); + + return 0; +} + +/* + * add_va_block - wrapper for add_va_block_locked + * + * @hdev : pointer to the habanalabs device structure + * @va_list : pointer to the virtual addresses block list + * @start : start virtual address + * @end : end virtual address + * + * This function does the following: + * - Takes the list lock and calls add_va_block_locked + */ +static inline int add_va_block(struct hl_device *hdev, + struct hl_va_range *va_range, u64 start, u64 end) +{ + int rc; + + mutex_lock(&va_range->lock); + rc = add_va_block_locked(hdev, &va_range->list, start, end); + mutex_unlock(&va_range->lock); + + return rc; +} + +/* + * get_va_block - get a virtual block with the requested size + * + * @hdev : pointer to the habanalabs device structure + * @va_range : pointer to the virtual addresses range + * @size : requested block size + * @hint_addr : hint for request address by the user + * @is_userptr : is host or DRAM memory + * + * This function does the following: + * - Iterate on the virtual block list to find a suitable virtual block for the + * requested size + * - Reserve the requested block and update the list + * - Return the start address of the virtual block + */ +static u64 get_va_block(struct hl_device *hdev, + struct hl_va_range *va_range, u32 size, u64 hint_addr, + bool is_userptr) +{ + struct hl_vm_va_block *va_block, *new_va_block = NULL; + u64 valid_start, valid_size, prev_start, prev_end, page_mask, + res_valid_start = 0, res_valid_size = 0; + u32 page_size; + bool add_prev = false; + + if (is_userptr) { + /* + * We cannot know if the user allocated memory with huge pages + * or not, hence we continue with the biggest possible + * granularity. + */ + page_size = PAGE_SIZE_2MB; + page_mask = PAGE_MASK_2MB; + } else { + page_size = hdev->asic_prop.dram_page_size; + page_mask = ~((u64)page_size - 1); + } + + mutex_lock(&va_range->lock); + + print_va_list_locked(hdev, &va_range->list); + + list_for_each_entry(va_block, &va_range->list, node) { + /* calc the first possible aligned addr */ + valid_start = va_block->start; + + + if (valid_start & (page_size - 1)) { + valid_start &= page_mask; + valid_start += page_size; + if (valid_start > va_block->end) + continue; + } + + valid_size = va_block->end - valid_start; + + if (valid_size >= size && + (!new_va_block || valid_size < res_valid_size)) { + + new_va_block = va_block; + res_valid_start = valid_start; + res_valid_size = valid_size; + } + + if (hint_addr && hint_addr >= valid_start && + ((hint_addr + size) <= va_block->end)) { + new_va_block = va_block; + res_valid_start = hint_addr; + res_valid_size = valid_size; + break; + } + } + + if (!new_va_block) { + dev_err(hdev->dev, "no available va block for size %u\n", size); + goto out; + } + + if (res_valid_start > new_va_block->start) { + prev_start = new_va_block->start; + prev_end = res_valid_start - 1; + + new_va_block->start = res_valid_start; + new_va_block->size = res_valid_size; + + add_prev = true; + } + + if (new_va_block->size > size) { + new_va_block->start += size; + new_va_block->size = new_va_block->end - new_va_block->start; + } else { + list_del(&new_va_block->node); + kfree(new_va_block); + } + + if (add_prev) + add_va_block_locked(hdev, &va_range->list, prev_start, + prev_end); + + print_va_list_locked(hdev, &va_range->list); +out: + mutex_unlock(&va_range->lock); + + return res_valid_start; +} + +/* + * get_sg_info - get number of pages and the DMA address from SG list + * + * @sg : the SG list + * @dma_addr : pointer to DMA address to return + * + * Calculate the number of consecutive pages described by the SG list. Take the + * offset of the address in the first page, add to it the length and round it up + * to the number of needed pages. + */ +static u32 get_sg_info(struct scatterlist *sg, dma_addr_t *dma_addr) +{ + *dma_addr = sg_dma_address(sg); + + return ((((*dma_addr) & (PAGE_SIZE - 1)) + sg_dma_len(sg)) + + (PAGE_SIZE - 1)) >> PAGE_SHIFT; +} + +/* + * init_phys_pg_pack_from_userptr - initialize physical page pack from host + * memory + * + * @ctx : current context + * @userptr : userptr to initialize from + * @pphys_pg_pack : res pointer + * + * This function does the following: + * - Pin the physical pages related to the given virtual block + * - Create a physical page pack from the physical pages related to the given + * virtual block + */ +static int init_phys_pg_pack_from_userptr(struct hl_ctx *ctx, + struct hl_userptr *userptr, + struct hl_vm_phys_pg_pack **pphys_pg_pack) +{ + struct hl_vm_phys_pg_pack *phys_pg_pack; + struct scatterlist *sg; + dma_addr_t dma_addr; + u64 page_mask; + u32 npages, total_npages, page_size = PAGE_SIZE; + bool first = true, is_huge_page_opt = true; + int rc, i, j; + + phys_pg_pack = kzalloc(sizeof(*phys_pg_pack), GFP_KERNEL); + if (!phys_pg_pack) + return -ENOMEM; + + phys_pg_pack->vm_type = userptr->vm_type; + phys_pg_pack->created_from_userptr = true; + phys_pg_pack->asid = ctx->asid; + atomic_set(&phys_pg_pack->mapping_cnt, 1); + + /* Only if all dma_addrs are aligned to 2MB and their + * sizes is at least 2MB, we can use huge page mapping. + * We limit the 2MB optimization to this condition, + * since later on we acquire the related VA range as one + * consecutive block. + */ + total_npages = 0; + for_each_sg(userptr->sgt->sgl, sg, userptr->sgt->nents, i) { + npages = get_sg_info(sg, &dma_addr); + + total_npages += npages; + + if (first) { + first = false; + dma_addr &= PAGE_MASK_2MB; + } + + if ((npages % PGS_IN_2MB_PAGE) || + (dma_addr & (PAGE_SIZE_2MB - 1))) + is_huge_page_opt = false; + } + + if (is_huge_page_opt) { + page_size = PAGE_SIZE_2MB; + total_npages /= PGS_IN_2MB_PAGE; + } + + page_mask = ~(((u64) page_size) - 1); + + phys_pg_pack->pages = kcalloc(total_npages, sizeof(u64), GFP_KERNEL); + if (!phys_pg_pack->pages) { + rc = -ENOMEM; + goto page_pack_arr_mem_err; + } + + phys_pg_pack->npages = total_npages; + phys_pg_pack->page_size = page_size; + phys_pg_pack->total_size = total_npages * page_size; + + j = 0; + first = true; + for_each_sg(userptr->sgt->sgl, sg, userptr->sgt->nents, i) { + npages = get_sg_info(sg, &dma_addr); + + /* align down to physical page size and save the offset */ + if (first) { + first = false; + phys_pg_pack->offset = dma_addr & (page_size - 1); + dma_addr &= page_mask; + } + + while (npages) { + phys_pg_pack->pages[j++] = dma_addr; + dma_addr += page_size; + + if (is_huge_page_opt) + npages -= PGS_IN_2MB_PAGE; + else + npages--; + } + } + + *pphys_pg_pack = phys_pg_pack; + + return 0; + +page_pack_arr_mem_err: + kfree(phys_pg_pack); + + return rc; +} + +/* + * map_phys_page_pack - maps the physical page pack + * + * @ctx : current context + * @vaddr : start address of the virtual area to map from + * @phys_pg_pack : the pack of physical pages to map to + * + * This function does the following: + * - Maps each chunk of virtual memory to matching physical chunk + * - Stores number of successful mappings in the given argument + * - Returns 0 on success, error code otherwise. + */ +static int map_phys_page_pack(struct hl_ctx *ctx, u64 vaddr, + struct hl_vm_phys_pg_pack *phys_pg_pack) +{ + struct hl_device *hdev = ctx->hdev; + u64 next_vaddr = vaddr, paddr; + u32 page_size = phys_pg_pack->page_size; + int i, rc = 0, mapped_pg_cnt = 0; + + for (i = 0 ; i < phys_pg_pack->npages ; i++) { + paddr = phys_pg_pack->pages[i]; + + /* For accessing the host we need to turn on bit 39 */ + if (phys_pg_pack->created_from_userptr) + paddr += hdev->asic_prop.host_phys_base_address; + + rc = hl_mmu_map(ctx, next_vaddr, paddr, page_size); + if (rc) { + dev_err(hdev->dev, + "map failed for handle %u, npages: %d, mapped: %d", + phys_pg_pack->handle, phys_pg_pack->npages, + mapped_pg_cnt); + goto err; + } + + mapped_pg_cnt++; + next_vaddr += page_size; + } + + return 0; + +err: + next_vaddr = vaddr; + for (i = 0 ; i < mapped_pg_cnt ; i++) { + if (hl_mmu_unmap(ctx, next_vaddr, page_size)) + dev_warn_ratelimited(hdev->dev, + "failed to unmap handle %u, va: 0x%llx, pa: 0x%llx, page size: %u\n", + phys_pg_pack->handle, next_vaddr, + phys_pg_pack->pages[i], page_size); + + next_vaddr += page_size; + } + + return rc; +} + +static int get_paddr_from_handle(struct hl_ctx *ctx, struct hl_mem_in *args, + u64 *paddr) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm *vm = &hdev->vm; + struct hl_vm_phys_pg_pack *phys_pg_pack; + u32 handle; + + handle = lower_32_bits(args->map_device.handle); + spin_lock(&vm->idr_lock); + phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, handle); + if (!phys_pg_pack) { + spin_unlock(&vm->idr_lock); + dev_err(hdev->dev, "no match for handle %u\n", handle); + return -EINVAL; + } + + *paddr = phys_pg_pack->pages[0]; + + spin_unlock(&vm->idr_lock); + + return 0; +} + +/* + * map_device_va - map the given memory + * + * @ctx : current context + * @args : host parameters with handle/host virtual address + * @device_addr : pointer to result device virtual address + * + * This function does the following: + * - If given a physical device memory handle, map to a device virtual block + * and return the start address of this block + * - If given a host virtual address and size, find the related physical pages, + * map a device virtual block to this pages and return the start address of + * this block + */ +static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, + u64 *device_addr) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm *vm = &hdev->vm; + struct hl_vm_phys_pg_pack *phys_pg_pack; + struct hl_userptr *userptr = NULL; + struct hl_vm_hash_node *hnode; + enum vm_type_t *vm_type; + u64 ret_vaddr, hint_addr; + u32 handle = 0; + int rc; + bool is_userptr = args->flags & HL_MEM_USERPTR; + + /* Assume failure */ + *device_addr = 0; + + if (is_userptr) { + rc = get_userptr_from_host_va(hdev, args, &userptr); + if (rc) { + dev_err(hdev->dev, "failed to get userptr from va\n"); + return rc; + } + + rc = init_phys_pg_pack_from_userptr(ctx, userptr, + &phys_pg_pack); + if (rc) { + dev_err(hdev->dev, + "unable to init page pack for vaddr 0x%llx\n", + args->map_host.host_virt_addr); + goto init_page_pack_err; + } + + vm_type = (enum vm_type_t *) userptr; + hint_addr = args->map_host.hint_addr; + } else { + handle = lower_32_bits(args->map_device.handle); + + spin_lock(&vm->idr_lock); + phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, handle); + if (!phys_pg_pack) { + spin_unlock(&vm->idr_lock); + dev_err(hdev->dev, + "no match for handle %u\n", handle); + return -EINVAL; + } + + /* increment now to avoid freeing device memory while mapping */ + atomic_inc(&phys_pg_pack->mapping_cnt); + + spin_unlock(&vm->idr_lock); + + vm_type = (enum vm_type_t *) phys_pg_pack; + + hint_addr = args->map_device.hint_addr; + } + + /* + * relevant for mapping device physical memory only, as host memory is + * implicitly shared + */ + if (!is_userptr && !(phys_pg_pack->flags & HL_MEM_SHARED) && + phys_pg_pack->asid != ctx->asid) { + dev_err(hdev->dev, + "Failed to map memory, handle %u is not shared\n", + handle); + rc = -EPERM; + goto shared_err; + } + + hnode = kzalloc(sizeof(*hnode), GFP_KERNEL); + if (!hnode) { + rc = -ENOMEM; + goto hnode_err; + } + + ret_vaddr = get_va_block(hdev, + is_userptr ? &ctx->host_va_range : &ctx->dram_va_range, + phys_pg_pack->total_size, hint_addr, is_userptr); + if (!ret_vaddr) { + dev_err(hdev->dev, "no available va block for handle %u\n", + handle); + rc = -ENOMEM; + goto va_block_err; + } + + mutex_lock(&ctx->mmu_lock); + + rc = map_phys_page_pack(ctx, ret_vaddr, phys_pg_pack); + if (rc) { + mutex_unlock(&ctx->mmu_lock); + dev_err(hdev->dev, "mapping page pack failed for handle %u\n", + handle); + goto map_err; + } + + hdev->asic_funcs->mmu_invalidate_cache(hdev, false); + + mutex_unlock(&ctx->mmu_lock); + + ret_vaddr += phys_pg_pack->offset; + + hnode->ptr = vm_type; + hnode->vaddr = ret_vaddr; + + mutex_lock(&ctx->mem_hash_lock); + hash_add(ctx->mem_hash, &hnode->node, ret_vaddr); + mutex_unlock(&ctx->mem_hash_lock); + + *device_addr = ret_vaddr; + + if (is_userptr) + free_phys_pg_pack(hdev, phys_pg_pack); + + return 0; + +map_err: + if (add_va_block(hdev, + is_userptr ? &ctx->host_va_range : &ctx->dram_va_range, + ret_vaddr, + ret_vaddr + phys_pg_pack->total_size - 1)) + dev_warn(hdev->dev, + "release va block failed for handle 0x%x, vaddr: 0x%llx\n", + handle, ret_vaddr); + +va_block_err: + kfree(hnode); +hnode_err: +shared_err: + atomic_dec(&phys_pg_pack->mapping_cnt); + if (is_userptr) + free_phys_pg_pack(hdev, phys_pg_pack); +init_page_pack_err: + if (is_userptr) + free_userptr(hdev, userptr); + + return rc; +} + +/* + * unmap_device_va - unmap the given device virtual address + * + * @ctx : current context + * @vaddr : device virtual address to unmap + * + * This function does the following: + * - Unmap the physical pages related to the given virtual address + * - return the device virtual block to the virtual block list + */ +static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm_phys_pg_pack *phys_pg_pack = NULL; + struct hl_vm_hash_node *hnode = NULL; + struct hl_userptr *userptr = NULL; + enum vm_type_t *vm_type; + u64 next_vaddr; + u32 page_size; + bool is_userptr; + int i, rc; + + /* protect from double entrance */ + mutex_lock(&ctx->mem_hash_lock); + hash_for_each_possible(ctx->mem_hash, hnode, node, (unsigned long)vaddr) + if (vaddr == hnode->vaddr) + break; + + if (!hnode) { + mutex_unlock(&ctx->mem_hash_lock); + dev_err(hdev->dev, + "unmap failed, no mem hnode for vaddr 0x%llx\n", + vaddr); + return -EINVAL; + } + + hash_del(&hnode->node); + mutex_unlock(&ctx->mem_hash_lock); + + vm_type = hnode->ptr; + + if (*vm_type == VM_TYPE_USERPTR) { + is_userptr = true; + userptr = hnode->ptr; + rc = init_phys_pg_pack_from_userptr(ctx, userptr, + &phys_pg_pack); + if (rc) { + dev_err(hdev->dev, + "unable to init page pack for vaddr 0x%llx\n", + vaddr); + goto vm_type_err; + } + } else if (*vm_type == VM_TYPE_PHYS_PACK) { + is_userptr = false; + phys_pg_pack = hnode->ptr; + } else { + dev_warn(hdev->dev, + "unmap failed, unknown vm desc for vaddr 0x%llx\n", + vaddr); + rc = -EFAULT; + goto vm_type_err; + } + + if (atomic_read(&phys_pg_pack->mapping_cnt) == 0) { + dev_err(hdev->dev, "vaddr 0x%llx is not mapped\n", vaddr); + rc = -EINVAL; + goto mapping_cnt_err; + } + + page_size = phys_pg_pack->page_size; + vaddr &= ~(((u64) page_size) - 1); + + next_vaddr = vaddr; + + mutex_lock(&ctx->mmu_lock); + + for (i = 0 ; i < phys_pg_pack->npages ; i++, next_vaddr += page_size) + if (hl_mmu_unmap(ctx, next_vaddr, page_size)) + dev_warn_ratelimited(hdev->dev, + "unmap failed for vaddr: 0x%llx\n", next_vaddr); + + hdev->asic_funcs->mmu_invalidate_cache(hdev, true); + + mutex_unlock(&ctx->mmu_lock); + + if (add_va_block(hdev, + is_userptr ? &ctx->host_va_range : &ctx->dram_va_range, + vaddr, + vaddr + phys_pg_pack->total_size - 1)) + dev_warn(hdev->dev, "add va block failed for vaddr: 0x%llx\n", + vaddr); + + atomic_dec(&phys_pg_pack->mapping_cnt); + kfree(hnode); + + if (is_userptr) { + free_phys_pg_pack(hdev, phys_pg_pack); + free_userptr(hdev, userptr); + } + + return 0; + +mapping_cnt_err: + if (is_userptr) + free_phys_pg_pack(hdev, phys_pg_pack); +vm_type_err: + mutex_lock(&ctx->mem_hash_lock); + hash_add(ctx->mem_hash, &hnode->node, vaddr); + mutex_unlock(&ctx->mem_hash_lock); + + return rc; +} + +int hl_mem_ioctl(struct hl_fpriv *hpriv, void *data) +{ + union hl_mem_args *args = data; + struct hl_device *hdev = hpriv->hdev; + struct hl_ctx *ctx = hpriv->ctx; + u64 device_addr = 0; + u32 handle = 0; + int rc; + + if (hl_device_disabled_or_in_reset(hdev)) { + dev_warn_ratelimited(hdev->dev, + "Device is disabled or in reset. Can't execute memory IOCTL\n"); + return -EBUSY; + } + + if (hdev->mmu_enable) { + switch (args->in.op) { + case HL_MEM_OP_ALLOC: + if (!hdev->dram_supports_virtual_memory) { + dev_err(hdev->dev, + "DRAM alloc is not supported\n"); + rc = -EINVAL; + goto out; + } + if (args->in.alloc.mem_size == 0) { + dev_err(hdev->dev, + "alloc size must be larger than 0\n"); + rc = -EINVAL; + goto out; + } + rc = alloc_device_memory(ctx, &args->in, &handle); + + memset(args, 0, sizeof(*args)); + args->out.handle = (__u64) handle; + break; + + case HL_MEM_OP_FREE: + if (!hdev->dram_supports_virtual_memory) { + dev_err(hdev->dev, + "DRAM free is not supported\n"); + rc = -EINVAL; + goto out; + } + rc = free_device_memory(ctx, args->in.free.handle); + break; + + case HL_MEM_OP_MAP: + rc = map_device_va(ctx, &args->in, &device_addr); + + memset(args, 0, sizeof(*args)); + args->out.device_virt_addr = device_addr; + break; + + case HL_MEM_OP_UNMAP: + rc = unmap_device_va(ctx, + args->in.unmap.device_virt_addr); + break; + + default: + dev_err(hdev->dev, "Unknown opcode for memory IOCTL\n"); + rc = -ENOTTY; + break; + } + } else { + switch (args->in.op) { + case HL_MEM_OP_ALLOC: + if (args->in.alloc.mem_size == 0) { + dev_err(hdev->dev, + "alloc size must be larger than 0\n"); + rc = -EINVAL; + goto out; + } + + /* Force contiguous as there are no real MMU + * translations to overcome physical memory gaps + */ + args->in.flags |= HL_MEM_CONTIGUOUS; + rc = alloc_device_memory(ctx, &args->in, &handle); + + memset(args, 0, sizeof(*args)); + args->out.handle = (__u64) handle; + break; + + case HL_MEM_OP_FREE: + rc = free_device_memory(ctx, args->in.free.handle); + break; + + case HL_MEM_OP_MAP: + if (args->in.flags & HL_MEM_USERPTR) { + device_addr = args->in.map_host.host_virt_addr; + rc = 0; + } else { + rc = get_paddr_from_handle(ctx, &args->in, + &device_addr); + } + + memset(args, 0, sizeof(*args)); + args->out.device_virt_addr = device_addr; + break; + + case HL_MEM_OP_UNMAP: + rc = 0; + break; + + default: + dev_err(hdev->dev, "Unknown opcode for memory IOCTL\n"); + rc = -ENOTTY; + break; + } + } + +out: + return rc; +} + +/* + * hl_pin_host_memory - pins a chunk of host memory + * + * @hdev : pointer to the habanalabs device structure + * @addr : the user-space virtual address of the memory area + * @size : the size of the memory area + * @userptr : pointer to hl_userptr structure + * + * This function does the following: + * - Pins the physical pages + * - Create a SG list from those pages + */ +int hl_pin_host_memory(struct hl_device *hdev, u64 addr, u64 size, + struct hl_userptr *userptr) +{ + u64 start, end; + u32 npages, offset; + int rc; + + if (!size) { + dev_err(hdev->dev, "size to pin is invalid - %llu\n", size); + return -EINVAL; + } + + if (!access_ok((void __user *) (uintptr_t) addr, size)) { + dev_err(hdev->dev, "user pointer is invalid - 0x%llx\n", addr); + return -EFAULT; + } + + /* + * If the combination of the address and size requested for this memory + * region causes an integer overflow, return error. + */ + if (((addr + size) < addr) || + PAGE_ALIGN(addr + size) < (addr + size)) { + dev_err(hdev->dev, + "user pointer 0x%llx + %llu causes integer overflow\n", + addr, size); + return -EINVAL; + } + + start = addr & PAGE_MASK; + offset = addr & ~PAGE_MASK; + end = PAGE_ALIGN(addr + size); + npages = (end - start) >> PAGE_SHIFT; + + userptr->size = size; + userptr->addr = addr; + userptr->dma_mapped = false; + INIT_LIST_HEAD(&userptr->job_node); + + userptr->vec = frame_vector_create(npages); + if (!userptr->vec) { + dev_err(hdev->dev, "Failed to create frame vector\n"); + return -ENOMEM; + } + + rc = get_vaddr_frames(start, npages, FOLL_FORCE | FOLL_WRITE, + userptr->vec); + + if (rc != npages) { + dev_err(hdev->dev, + "Failed to map host memory, user ptr probably wrong\n"); + if (rc < 0) + goto destroy_framevec; + rc = -EFAULT; + goto put_framevec; + } + + if (frame_vector_to_pages(userptr->vec) < 0) { + dev_err(hdev->dev, + "Failed to translate frame vector to pages\n"); + rc = -EFAULT; + goto put_framevec; + } + + userptr->sgt = kzalloc(sizeof(*userptr->sgt), GFP_ATOMIC); + if (!userptr->sgt) { + rc = -ENOMEM; + goto put_framevec; + } + + rc = sg_alloc_table_from_pages(userptr->sgt, + frame_vector_pages(userptr->vec), + npages, offset, size, GFP_ATOMIC); + if (rc < 0) { + dev_err(hdev->dev, "failed to create SG table from pages\n"); + goto free_sgt; + } + + hl_debugfs_add_userptr(hdev, userptr); + + return 0; + +free_sgt: + kfree(userptr->sgt); +put_framevec: + put_vaddr_frames(userptr->vec); +destroy_framevec: + frame_vector_destroy(userptr->vec); + return rc; +} + +/* + * hl_unpin_host_memory - unpins a chunk of host memory + * + * @hdev : pointer to the habanalabs device structure + * @userptr : pointer to hl_userptr structure + * + * This function does the following: + * - Unpins the physical pages related to the host memory + * - Free the SG list + */ +int hl_unpin_host_memory(struct hl_device *hdev, struct hl_userptr *userptr) +{ + struct page **pages; + + hl_debugfs_remove_userptr(hdev, userptr); + + if (userptr->dma_mapped) + hdev->asic_funcs->hl_dma_unmap_sg(hdev, + userptr->sgt->sgl, + userptr->sgt->nents, + userptr->dir); + + pages = frame_vector_pages(userptr->vec); + if (!IS_ERR(pages)) { + int i; + + for (i = 0; i < frame_vector_count(userptr->vec); i++) + set_page_dirty_lock(pages[i]); + } + put_vaddr_frames(userptr->vec); + frame_vector_destroy(userptr->vec); + + list_del(&userptr->job_node); + + sg_free_table(userptr->sgt); + kfree(userptr->sgt); + + return 0; +} + +/* + * hl_userptr_delete_list - clear userptr list + * + * @hdev : pointer to the habanalabs device structure + * @userptr_list : pointer to the list to clear + * + * This function does the following: + * - Iterates over the list and unpins the host memory and frees the userptr + * structure. + */ +void hl_userptr_delete_list(struct hl_device *hdev, + struct list_head *userptr_list) +{ + struct hl_userptr *userptr, *tmp; + + list_for_each_entry_safe(userptr, tmp, userptr_list, job_node) { + hl_unpin_host_memory(hdev, userptr); + kfree(userptr); + } + + INIT_LIST_HEAD(userptr_list); +} + +/* + * hl_userptr_is_pinned - returns whether the given userptr is pinned + * + * @hdev : pointer to the habanalabs device structure + * @userptr_list : pointer to the list to clear + * @userptr : pointer to userptr to check + * + * This function does the following: + * - Iterates over the list and checks if the given userptr is in it, means is + * pinned. If so, returns true, otherwise returns false. + */ +bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, + u32 size, struct list_head *userptr_list, + struct hl_userptr **userptr) +{ + list_for_each_entry((*userptr), userptr_list, job_node) { + if ((addr == (*userptr)->addr) && (size == (*userptr)->size)) + return true; + } + + return false; +} + +/* + * hl_va_range_init - initialize virtual addresses range + * + * @hdev : pointer to the habanalabs device structure + * @va_range : pointer to the range to initialize + * @start : range start address + * @end : range end address + * + * This function does the following: + * - Initializes the virtual addresses list of the given range with the given + * addresses. + */ +static int hl_va_range_init(struct hl_device *hdev, + struct hl_va_range *va_range, u64 start, u64 end) +{ + int rc; + + INIT_LIST_HEAD(&va_range->list); + + /* PAGE_SIZE alignment */ + + if (start & (PAGE_SIZE - 1)) { + start &= PAGE_MASK; + start += PAGE_SIZE; + } + + if (end & (PAGE_SIZE - 1)) + end &= PAGE_MASK; + + if (start >= end) { + dev_err(hdev->dev, "too small vm range for va list\n"); + return -EFAULT; + } + + rc = add_va_block(hdev, va_range, start, end); + + if (rc) { + dev_err(hdev->dev, "Failed to init host va list\n"); + return rc; + } + + va_range->start_addr = start; + va_range->end_addr = end; + + return 0; +} + +/* + * hl_vm_ctx_init_with_ranges - initialize virtual memory for context + * + * @ctx : pointer to the habanalabs context structure + * @host_range_start : host virtual addresses range start + * @host_range_end : host virtual addresses range end + * @dram_range_start : dram virtual addresses range start + * @dram_range_end : dram virtual addresses range end + * + * This function initializes the following: + * - MMU for context + * - Virtual address to area descriptor hashtable + * - Virtual block list of available virtual memory + */ +static int hl_vm_ctx_init_with_ranges(struct hl_ctx *ctx, u64 host_range_start, + u64 host_range_end, u64 dram_range_start, + u64 dram_range_end) +{ + struct hl_device *hdev = ctx->hdev; + int rc; + + rc = hl_mmu_ctx_init(ctx); + if (rc) { + dev_err(hdev->dev, "failed to init context %d\n", ctx->asid); + return rc; + } + + mutex_init(&ctx->mem_hash_lock); + hash_init(ctx->mem_hash); + + mutex_init(&ctx->host_va_range.lock); + + rc = hl_va_range_init(hdev, &ctx->host_va_range, host_range_start, + host_range_end); + if (rc) { + dev_err(hdev->dev, "failed to init host vm range\n"); + goto host_vm_err; + } + + mutex_init(&ctx->dram_va_range.lock); + + rc = hl_va_range_init(hdev, &ctx->dram_va_range, dram_range_start, + dram_range_end); + if (rc) { + dev_err(hdev->dev, "failed to init dram vm range\n"); + goto dram_vm_err; + } + + hl_debugfs_add_ctx_mem_hash(hdev, ctx); + + return 0; + +dram_vm_err: + mutex_destroy(&ctx->dram_va_range.lock); + + mutex_lock(&ctx->host_va_range.lock); + clear_va_list_locked(hdev, &ctx->host_va_range.list); + mutex_unlock(&ctx->host_va_range.lock); +host_vm_err: + mutex_destroy(&ctx->host_va_range.lock); + mutex_destroy(&ctx->mem_hash_lock); + hl_mmu_ctx_fini(ctx); + + return rc; +} + +int hl_vm_ctx_init(struct hl_ctx *ctx) +{ + struct asic_fixed_properties *prop = &ctx->hdev->asic_prop; + u64 host_range_start, host_range_end, dram_range_start, + dram_range_end; + + atomic64_set(&ctx->dram_phys_mem, 0); + + /* + * - If MMU is enabled, init the ranges as usual. + * - If MMU is disabled, in case of host mapping, the returned address + * is the given one. + * In case of DRAM mapping, the returned address is the physical + * address of the memory related to the given handle. + */ + if (ctx->hdev->mmu_enable) { + dram_range_start = prop->va_space_dram_start_address; + dram_range_end = prop->va_space_dram_end_address; + host_range_start = prop->va_space_host_start_address; + host_range_end = prop->va_space_host_end_address; + } else { + dram_range_start = prop->dram_user_base_address; + dram_range_end = prop->dram_end_address; + host_range_start = prop->dram_user_base_address; + host_range_end = prop->dram_end_address; + } + + return hl_vm_ctx_init_with_ranges(ctx, host_range_start, host_range_end, + dram_range_start, dram_range_end); +} + +/* + * hl_va_range_fini - clear a virtual addresses range + * + * @hdev : pointer to the habanalabs structure + * va_range : pointer to virtual addresses range + * + * This function initializes the following: + * - Checks that the given range contains the whole initial range + * - Frees the virtual addresses block list and its lock + */ +static void hl_va_range_fini(struct hl_device *hdev, + struct hl_va_range *va_range) +{ + struct hl_vm_va_block *va_block; + + if (list_empty(&va_range->list)) { + dev_warn(hdev->dev, + "va list should not be empty on cleanup!\n"); + goto out; + } + + if (!list_is_singular(&va_range->list)) { + dev_warn(hdev->dev, + "va list should not contain multiple blocks on cleanup!\n"); + goto free_va_list; + } + + va_block = list_first_entry(&va_range->list, typeof(*va_block), node); + + if (va_block->start != va_range->start_addr || + va_block->end != va_range->end_addr) { + dev_warn(hdev->dev, + "wrong va block on cleanup, from 0x%llx to 0x%llx\n", + va_block->start, va_block->end); + goto free_va_list; + } + +free_va_list: + mutex_lock(&va_range->lock); + clear_va_list_locked(hdev, &va_range->list); + mutex_unlock(&va_range->lock); + +out: + mutex_destroy(&va_range->lock); +} + +/* + * hl_vm_ctx_fini - virtual memory teardown of context + * + * @ctx : pointer to the habanalabs context structure + * + * This function perform teardown the following: + * - Virtual block list of available virtual memory + * - Virtual address to area descriptor hashtable + * - MMU for context + * + * In addition this function does the following: + * - Unmaps the existing hashtable nodes if the hashtable is not empty. The + * hashtable should be empty as no valid mappings should exist at this + * point. + * - Frees any existing physical page list from the idr which relates to the + * current context asid. + * - This function checks the virtual block list for correctness. At this point + * the list should contain one element which describes the whole virtual + * memory range of the context. Otherwise, a warning is printed. + */ +void hl_vm_ctx_fini(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm *vm = &hdev->vm; + struct hl_vm_phys_pg_pack *phys_pg_list; + struct hl_vm_hash_node *hnode; + struct hlist_node *tmp_node; + int i; + + hl_debugfs_remove_ctx_mem_hash(hdev, ctx); + + if (!hash_empty(ctx->mem_hash)) + dev_notice(hdev->dev, "ctx is freed while it has va in use\n"); + + hash_for_each_safe(ctx->mem_hash, i, tmp_node, hnode, node) { + dev_dbg(hdev->dev, + "hl_mem_hash_node of vaddr 0x%llx of asid %d is still alive\n", + hnode->vaddr, ctx->asid); + unmap_device_va(ctx, hnode->vaddr); + } + + spin_lock(&vm->idr_lock); + idr_for_each_entry(&vm->phys_pg_pack_handles, phys_pg_list, i) + if (phys_pg_list->asid == ctx->asid) { + dev_dbg(hdev->dev, + "page list 0x%p of asid %d is still alive\n", + phys_pg_list, ctx->asid); + free_phys_pg_pack(hdev, phys_pg_list); + idr_remove(&vm->phys_pg_pack_handles, i); + } + spin_unlock(&vm->idr_lock); + + hl_va_range_fini(hdev, &ctx->dram_va_range); + hl_va_range_fini(hdev, &ctx->host_va_range); + + mutex_destroy(&ctx->mem_hash_lock); + hl_mmu_ctx_fini(ctx); +} + +/* + * hl_vm_init - initialize virtual memory module + * + * @hdev : pointer to the habanalabs device structure + * + * This function initializes the following: + * - MMU module + * - DRAM physical pages pool of 2MB + * - Idr for device memory allocation handles + */ +int hl_vm_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_vm *vm = &hdev->vm; + int rc; + + rc = hl_mmu_init(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to init MMU\n"); + return rc; + } + + vm->dram_pg_pool = gen_pool_create(__ffs(prop->dram_page_size), -1); + if (!vm->dram_pg_pool) { + dev_err(hdev->dev, "Failed to create dram page pool\n"); + rc = -ENOMEM; + goto pool_create_err; + } + + kref_init(&vm->dram_pg_pool_refcount); + + rc = gen_pool_add(vm->dram_pg_pool, prop->dram_user_base_address, + prop->dram_end_address - prop->dram_user_base_address, + -1); + + if (rc) { + dev_err(hdev->dev, + "Failed to add memory to dram page pool %d\n", rc); + goto pool_add_err; + } + + spin_lock_init(&vm->idr_lock); + idr_init(&vm->phys_pg_pack_handles); + + atomic64_set(&hdev->dram_used_mem, 0); + + vm->init_done = true; + + return 0; + +pool_add_err: + gen_pool_destroy(vm->dram_pg_pool); +pool_create_err: + hl_mmu_fini(hdev); + + return rc; +} + +/* + * hl_vm_fini - virtual memory module teardown + * + * @hdev : pointer to the habanalabs device structure + * + * This function perform teardown to the following: + * - Idr for device memory allocation handles + * - DRAM physical pages pool of 2MB + * - MMU module + */ +void hl_vm_fini(struct hl_device *hdev) +{ + struct hl_vm *vm = &hdev->vm; + + if (!vm->init_done) + return; + + /* + * At this point all the contexts should be freed and hence no DRAM + * memory should be in use. Hence the DRAM pool should be freed here. + */ + if (kref_put(&vm->dram_pg_pool_refcount, dram_pg_pool_do_release) != 1) + dev_warn(hdev->dev, "dram_pg_pool was not destroyed on %s\n", + __func__); + + hl_mmu_fini(hdev); + + vm->init_done = false; +} diff --git a/drivers/misc/habanalabs/mmu.c b/drivers/misc/habanalabs/mmu.c new file mode 100644 index 000000000000..2f2e99cb2743 --- /dev/null +++ b/drivers/misc/habanalabs/mmu.c @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" +#include "include/hw_ip/mmu/mmu_general.h" + +#include <linux/genalloc.h> +#include <linux/slab.h> + +static struct pgt_info *get_pgt_info(struct hl_ctx *ctx, u64 addr) +{ + struct pgt_info *pgt_info = NULL; + + hash_for_each_possible(ctx->mmu_hash, pgt_info, node, + (unsigned long) addr) + if (addr == pgt_info->addr) + break; + + return pgt_info; +} + +static void free_hop(struct hl_ctx *ctx, u64 hop_addr) +{ + struct pgt_info *pgt_info = get_pgt_info(ctx, hop_addr); + + gen_pool_free(pgt_info->ctx->hdev->mmu_pgt_pool, pgt_info->addr, + ctx->hdev->asic_prop.mmu_hop_table_size); + hash_del(&pgt_info->node); + + kfree(pgt_info); +} + +static u64 alloc_hop(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct pgt_info *pgt_info; + u64 addr; + + pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL); + if (!pgt_info) + return ULLONG_MAX; + + addr = (u64) gen_pool_alloc(hdev->mmu_pgt_pool, + hdev->asic_prop.mmu_hop_table_size); + if (!addr) { + dev_err(hdev->dev, "failed to allocate page\n"); + kfree(pgt_info); + return ULLONG_MAX; + } + + pgt_info->addr = addr; + pgt_info->ctx = ctx; + pgt_info->num_of_ptes = 0; + hash_add(ctx->mmu_hash, &pgt_info->node, addr); + + return addr; +} + +static inline void clear_pte(struct hl_device *hdev, u64 pte_addr) +{ + /* clear the last and present bits */ + hdev->asic_funcs->write_pte(hdev, pte_addr, 0); +} + +static inline void get_pte(struct hl_ctx *ctx, u64 hop_addr) +{ + get_pgt_info(ctx, hop_addr)->num_of_ptes++; +} + +/* + * put_pte - decrement the num of ptes and free the hop if possible + * + * @ctx: pointer to the context structure + * @hop_addr: addr of the hop + * + * This function returns the number of ptes left on this hop. If the number is + * 0, it means the pte was freed. + */ +static inline int put_pte(struct hl_ctx *ctx, u64 hop_addr) +{ + struct pgt_info *pgt_info = get_pgt_info(ctx, hop_addr); + int num_of_ptes_left; + + pgt_info->num_of_ptes--; + + /* + * Need to save the number of ptes left because free_hop might free + * the pgt_info + */ + num_of_ptes_left = pgt_info->num_of_ptes; + if (!num_of_ptes_left) + free_hop(ctx, hop_addr); + + return num_of_ptes_left; +} + +static inline u64 get_hop0_addr(struct hl_ctx *ctx) +{ + return ctx->hdev->asic_prop.mmu_pgt_addr + + (ctx->asid * ctx->hdev->asic_prop.mmu_hop_table_size); +} + +static inline u64 get_hopN_pte_addr(struct hl_ctx *ctx, u64 hop_addr, + u64 virt_addr, u64 mask, u64 shift) +{ + return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * + ((virt_addr & mask) >> shift); +} + +static inline u64 get_hop0_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr) +{ + return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP0_MASK, HOP0_SHIFT); +} + +static inline u64 get_hop1_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr) +{ + return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP1_MASK, HOP1_SHIFT); +} + +static inline u64 get_hop2_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr) +{ + return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP2_MASK, HOP2_SHIFT); +} + +static inline u64 get_hop3_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr) +{ + return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP3_MASK, HOP3_SHIFT); +} + +static inline u64 get_hop4_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr) +{ + return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP4_MASK, HOP4_SHIFT); +} + +static inline u64 get_next_hop_addr(u64 curr_pte) +{ + if (curr_pte & PAGE_PRESENT_MASK) + return curr_pte & PHYS_ADDR_MASK; + else + return ULLONG_MAX; +} + +static inline u64 get_alloc_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte, + bool *is_new_hop) +{ + u64 hop_addr = get_next_hop_addr(curr_pte); + + if (hop_addr == ULLONG_MAX) { + hop_addr = alloc_hop(ctx); + *is_new_hop = (hop_addr != ULLONG_MAX); + } + + return hop_addr; +} + +/* + * hl_mmu_init - init the mmu module + * + * @hdev: pointer to the habanalabs device structure + * + * This function does the following: + * - Allocate max_asid zeroed hop0 pgts so no mapping is available + * - Enable mmu in hw + * - Invalidate the mmu cache + * - Create a pool of pages for pgts + * - Returns 0 on success + * + * This function depends on DMA QMAN to be working! + */ +int hl_mmu_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc; + + if (!hdev->mmu_enable) + return 0; + + /* MMU HW init was already done in device hw_init() */ + + mutex_init(&hdev->mmu_cache_lock); + + hdev->mmu_pgt_pool = + gen_pool_create(__ffs(prop->mmu_hop_table_size), -1); + + if (!hdev->mmu_pgt_pool) { + dev_err(hdev->dev, "Failed to create page gen pool\n"); + rc = -ENOMEM; + goto err_pool_create; + } + + rc = gen_pool_add(hdev->mmu_pgt_pool, prop->mmu_pgt_addr + + prop->mmu_hop0_tables_total_size, + prop->mmu_pgt_size - prop->mmu_hop0_tables_total_size, + -1); + if (rc) { + dev_err(hdev->dev, "Failed to add memory to page gen pool\n"); + goto err_pool_add; + } + + return 0; + +err_pool_add: + gen_pool_destroy(hdev->mmu_pgt_pool); +err_pool_create: + mutex_destroy(&hdev->mmu_cache_lock); + + return rc; +} + +/* + * hl_mmu_fini - release the mmu module. + * + * @hdev: pointer to the habanalabs device structure + * + * This function does the following: + * - Disable mmu in hw + * - free the pgts pool + * + * All ctxs should be freed before calling this func + */ +void hl_mmu_fini(struct hl_device *hdev) +{ + if (!hdev->mmu_enable) + return; + + gen_pool_destroy(hdev->mmu_pgt_pool); + + mutex_destroy(&hdev->mmu_cache_lock); + + /* MMU HW fini will be done in device hw_fini() */ +} + +/** + * hl_mmu_ctx_init() - initialize a context for using the MMU module. + * @ctx: pointer to the context structure to initialize. + * + * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all + * page tables hops related to this context and an optional DRAM default page + * mapping. + * Return: 0 on success, non-zero otherwise. + */ +int hl_mmu_ctx_init(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 num_of_hop3, total_hops, hop1_addr, hop2_addr, hop2_pte_addr, + hop3_pte_addr, pte_val; + int rc, i, j, hop3_allocated = 0; + + if (!hdev->mmu_enable) + return 0; + + mutex_init(&ctx->mmu_lock); + hash_init(ctx->mmu_hash); + + if (!hdev->dram_supports_virtual_memory || + !hdev->dram_default_page_mapping) + return 0; + + num_of_hop3 = prop->dram_size_for_default_page_mapping; + do_div(num_of_hop3, prop->dram_page_size); + do_div(num_of_hop3, PTE_ENTRIES_IN_HOP); + + /* add hop1 and hop2 */ + total_hops = num_of_hop3 + 2; + + ctx->dram_default_hops = kzalloc(HL_PTE_SIZE * total_hops, GFP_KERNEL); + if (!ctx->dram_default_hops) { + rc = -ENOMEM; + goto alloc_err; + } + + hop1_addr = alloc_hop(ctx); + if (hop1_addr == ULLONG_MAX) { + dev_err(hdev->dev, "failed to alloc hop 1\n"); + rc = -ENOMEM; + goto hop1_err; + } + + ctx->dram_default_hops[total_hops - 1] = hop1_addr; + + hop2_addr = alloc_hop(ctx); + if (hop2_addr == ULLONG_MAX) { + dev_err(hdev->dev, "failed to alloc hop 2\n"); + rc = -ENOMEM; + goto hop2_err; + } + + ctx->dram_default_hops[total_hops - 2] = hop2_addr; + + for (i = 0 ; i < num_of_hop3 ; i++) { + ctx->dram_default_hops[i] = alloc_hop(ctx); + if (ctx->dram_default_hops[i] == ULLONG_MAX) { + dev_err(hdev->dev, "failed to alloc hop 3, i: %d\n", i); + rc = -ENOMEM; + goto hop3_err; + } + hop3_allocated++; + } + + /* need only pte 0 in hops 0 and 1 */ + pte_val = (hop1_addr & PTE_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK; + hdev->asic_funcs->write_pte(hdev, get_hop0_addr(ctx), pte_val); + + pte_val = (hop2_addr & PTE_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK; + hdev->asic_funcs->write_pte(hdev, hop1_addr, pte_val); + get_pte(ctx, hop1_addr); + + hop2_pte_addr = hop2_addr; + for (i = 0 ; i < num_of_hop3 ; i++) { + pte_val = (ctx->dram_default_hops[i] & PTE_PHYS_ADDR_MASK) | + PAGE_PRESENT_MASK; + hdev->asic_funcs->write_pte(hdev, hop2_pte_addr, pte_val); + get_pte(ctx, hop2_addr); + hop2_pte_addr += HL_PTE_SIZE; + } + + pte_val = (prop->mmu_dram_default_page_addr & PTE_PHYS_ADDR_MASK) | + LAST_MASK | PAGE_PRESENT_MASK; + + for (i = 0 ; i < num_of_hop3 ; i++) { + hop3_pte_addr = ctx->dram_default_hops[i]; + for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) { + hdev->asic_funcs->write_pte(hdev, hop3_pte_addr, + pte_val); + get_pte(ctx, ctx->dram_default_hops[i]); + hop3_pte_addr += HL_PTE_SIZE; + } + } + + /* flush all writes to reach PCI */ + mb(); + hdev->asic_funcs->read_pte(hdev, hop2_addr); + + return 0; + +hop3_err: + for (i = 0 ; i < hop3_allocated ; i++) + free_hop(ctx, ctx->dram_default_hops[i]); + free_hop(ctx, hop2_addr); +hop2_err: + free_hop(ctx, hop1_addr); +hop1_err: + kfree(ctx->dram_default_hops); +alloc_err: + mutex_destroy(&ctx->mmu_lock); + + return rc; +} + +/* + * hl_mmu_ctx_fini - disable a ctx from using the mmu module + * + * @ctx: pointer to the context structure + * + * This function does the following: + * - Free any pgts which were not freed yet + * - Free the mutex + * - Free DRAM default page mapping hops + */ +void hl_mmu_ctx_fini(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct pgt_info *pgt_info; + struct hlist_node *tmp; + u64 num_of_hop3, total_hops, hop1_addr, hop2_addr, hop2_pte_addr, + hop3_pte_addr; + int i, j; + + if (!ctx->hdev->mmu_enable) + return; + + if (hdev->dram_supports_virtual_memory && + hdev->dram_default_page_mapping) { + + num_of_hop3 = prop->dram_size_for_default_page_mapping; + do_div(num_of_hop3, prop->dram_page_size); + do_div(num_of_hop3, PTE_ENTRIES_IN_HOP); + + /* add hop1 and hop2 */ + total_hops = num_of_hop3 + 2; + hop1_addr = ctx->dram_default_hops[total_hops - 1]; + hop2_addr = ctx->dram_default_hops[total_hops - 2]; + + for (i = 0 ; i < num_of_hop3 ; i++) { + hop3_pte_addr = ctx->dram_default_hops[i]; + for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) { + clear_pte(hdev, hop3_pte_addr); + put_pte(ctx, ctx->dram_default_hops[i]); + hop3_pte_addr += HL_PTE_SIZE; + } + } + + hop2_pte_addr = hop2_addr; + for (i = 0 ; i < num_of_hop3 ; i++) { + clear_pte(hdev, hop2_pte_addr); + put_pte(ctx, hop2_addr); + hop2_pte_addr += HL_PTE_SIZE; + } + + clear_pte(hdev, hop1_addr); + put_pte(ctx, hop1_addr); + clear_pte(hdev, get_hop0_addr(ctx)); + + kfree(ctx->dram_default_hops); + + /* flush all writes to reach PCI */ + mb(); + hdev->asic_funcs->read_pte(hdev, hop2_addr); + } + + if (!hash_empty(ctx->mmu_hash)) + dev_err(hdev->dev, "ctx is freed while it has pgts in use\n"); + + hash_for_each_safe(ctx->mmu_hash, i, tmp, pgt_info, node) { + dev_err(hdev->dev, + "pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n", + pgt_info->addr, ctx->asid, pgt_info->num_of_ptes); + free_hop(ctx, pgt_info->addr); + } + + mutex_destroy(&ctx->mmu_lock); +} + +static int _hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 hop0_addr = 0, hop0_pte_addr = 0, + hop1_addr = 0, hop1_pte_addr = 0, + hop2_addr = 0, hop2_pte_addr = 0, + hop3_addr = 0, hop3_pte_addr = 0, + hop4_addr = 0, hop4_pte_addr = 0, + curr_pte; + int clear_hop3 = 1; + bool is_dram_addr, is_huge, is_dram_default_page_mapping; + + is_dram_addr = hl_mem_area_inside_range(virt_addr, PAGE_SIZE_2MB, + prop->va_space_dram_start_address, + prop->va_space_dram_end_address); + + hop0_addr = get_hop0_addr(ctx); + + hop0_pte_addr = get_hop0_pte_addr(ctx, hop0_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop0_pte_addr); + + hop1_addr = get_next_hop_addr(curr_pte); + + if (hop1_addr == ULLONG_MAX) + goto not_mapped; + + hop1_pte_addr = get_hop1_pte_addr(ctx, hop1_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop1_pte_addr); + + hop2_addr = get_next_hop_addr(curr_pte); + + if (hop2_addr == ULLONG_MAX) + goto not_mapped; + + hop2_pte_addr = get_hop2_pte_addr(ctx, hop2_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop2_pte_addr); + + hop3_addr = get_next_hop_addr(curr_pte); + + if (hop3_addr == ULLONG_MAX) + goto not_mapped; + + hop3_pte_addr = get_hop3_pte_addr(ctx, hop3_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop3_pte_addr); + + is_huge = curr_pte & LAST_MASK; + + if (is_dram_addr && !is_huge) { + dev_err(hdev->dev, + "DRAM unmapping should use huge pages only\n"); + return -EFAULT; + } + + is_dram_default_page_mapping = + hdev->dram_default_page_mapping && is_dram_addr; + + if (!is_huge) { + hop4_addr = get_next_hop_addr(curr_pte); + + if (hop4_addr == ULLONG_MAX) + goto not_mapped; + + hop4_pte_addr = get_hop4_pte_addr(ctx, hop4_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop4_pte_addr); + + clear_hop3 = 0; + } + + if (is_dram_default_page_mapping) { + u64 zero_pte = (prop->mmu_dram_default_page_addr & + PTE_PHYS_ADDR_MASK) | LAST_MASK | + PAGE_PRESENT_MASK; + if (curr_pte == zero_pte) { + dev_err(hdev->dev, + "DRAM: hop3 PTE points to zero page, can't unmap, va: 0x%llx\n", + virt_addr); + goto not_mapped; + } + + if (!(curr_pte & PAGE_PRESENT_MASK)) { + dev_err(hdev->dev, + "DRAM: hop3 PTE is cleared! can't unmap, va: 0x%llx\n", + virt_addr); + goto not_mapped; + } + + hdev->asic_funcs->write_pte(hdev, hop3_pte_addr, zero_pte); + put_pte(ctx, hop3_addr); + } else { + if (!(curr_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + + clear_pte(hdev, hop4_addr ? hop4_pte_addr : hop3_pte_addr); + + if (hop4_addr && !put_pte(ctx, hop4_addr)) + clear_hop3 = 1; + + if (!clear_hop3) + goto flush; + clear_pte(hdev, hop3_pte_addr); + + if (put_pte(ctx, hop3_addr)) + goto flush; + clear_pte(hdev, hop2_pte_addr); + + if (put_pte(ctx, hop2_addr)) + goto flush; + clear_pte(hdev, hop1_pte_addr); + + if (put_pte(ctx, hop1_addr)) + goto flush; + clear_pte(hdev, hop0_pte_addr); + } + +flush: + /* flush all writes from all cores to reach PCI */ + mb(); + + hdev->asic_funcs->read_pte(hdev, + hop4_addr ? hop4_pte_addr : hop3_pte_addr); + + return 0; + +not_mapped: + dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n", + virt_addr); + + return -EINVAL; +} + +/* + * hl_mmu_unmap - unmaps a virtual addr + * + * @ctx: pointer to the context structure + * @virt_addr: virt addr to map from + * @page_size: size of the page to unmap + * + * This function does the following: + * - Check that the virt addr is mapped + * - Unmap the virt addr and frees pgts if possible + * - Returns 0 on success, -EINVAL if the given addr is not mapped + * + * Because this function changes the page tables in the device and because it + * changes the MMU hash, it must be protected by a lock. + * However, because it maps only a single page, the lock should be implemented + * in a higher level in order to protect the entire mapping of the memory area + */ +int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size) +{ + struct hl_device *hdev = ctx->hdev; + u64 real_virt_addr; + u32 real_page_size, npages; + int i, rc; + + if (!hdev->mmu_enable) + return 0; + + /* + * The H/W handles mapping of 4KB/2MB page. Hence if the host page size + * is bigger, we break it to sub-pages and unmap them separately. + */ + if ((page_size % PAGE_SIZE_2MB) == 0) { + real_page_size = PAGE_SIZE_2MB; + } else if ((page_size % PAGE_SIZE_4KB) == 0) { + real_page_size = PAGE_SIZE_4KB; + } else { + dev_err(hdev->dev, + "page size of %u is not 4KB nor 2MB aligned, can't unmap\n", + page_size); + + return -EFAULT; + } + + npages = page_size / real_page_size; + real_virt_addr = virt_addr; + + for (i = 0 ; i < npages ; i++) { + rc = _hl_mmu_unmap(ctx, real_virt_addr); + if (rc) + return rc; + + real_virt_addr += real_page_size; + } + + return 0; +} + +static int _hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, + u32 page_size) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 hop0_addr = 0, hop0_pte_addr = 0, + hop1_addr = 0, hop1_pte_addr = 0, + hop2_addr = 0, hop2_pte_addr = 0, + hop3_addr = 0, hop3_pte_addr = 0, + hop4_addr = 0, hop4_pte_addr = 0, + curr_pte = 0; + bool hop1_new = false, hop2_new = false, hop3_new = false, + hop4_new = false, is_huge, is_dram_addr, + is_dram_default_page_mapping; + int rc = -ENOMEM; + + /* + * This mapping function can map a 4KB/2MB page. For 2MB page there are + * only 3 hops rather than 4. Currently the DRAM allocation uses 2MB + * pages only but user memory could have been allocated with one of the + * two page sizes. Since this is a common code for all the three cases, + * we need this hugs page check. + */ + is_huge = page_size == PAGE_SIZE_2MB; + + is_dram_addr = hl_mem_area_inside_range(virt_addr, page_size, + prop->va_space_dram_start_address, + prop->va_space_dram_end_address); + + if (is_dram_addr && !is_huge) { + dev_err(hdev->dev, "DRAM mapping should use huge pages only\n"); + return -EFAULT; + } + + is_dram_default_page_mapping = + hdev->dram_default_page_mapping && is_dram_addr; + + hop0_addr = get_hop0_addr(ctx); + + hop0_pte_addr = get_hop0_pte_addr(ctx, hop0_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop0_pte_addr); + + hop1_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop1_new); + + if (hop1_addr == ULLONG_MAX) + goto err; + + hop1_pte_addr = get_hop1_pte_addr(ctx, hop1_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop1_pte_addr); + + hop2_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop2_new); + + if (hop2_addr == ULLONG_MAX) + goto err; + + hop2_pte_addr = get_hop2_pte_addr(ctx, hop2_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop2_pte_addr); + + hop3_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop3_new); + + if (hop3_addr == ULLONG_MAX) + goto err; + + hop3_pte_addr = get_hop3_pte_addr(ctx, hop3_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop3_pte_addr); + + if (!is_huge) { + hop4_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop4_new); + + if (hop4_addr == ULLONG_MAX) + goto err; + + hop4_pte_addr = get_hop4_pte_addr(ctx, hop4_addr, virt_addr); + + curr_pte = hdev->asic_funcs->read_pte(hdev, hop4_pte_addr); + } + + if (is_dram_default_page_mapping) { + u64 zero_pte = (prop->mmu_dram_default_page_addr & + PTE_PHYS_ADDR_MASK) | LAST_MASK | + PAGE_PRESENT_MASK; + + if (curr_pte != zero_pte) { + dev_err(hdev->dev, + "DRAM: mapping already exists for virt_addr 0x%llx\n", + virt_addr); + rc = -EINVAL; + goto err; + } + + if (hop1_new || hop2_new || hop3_new || hop4_new) { + dev_err(hdev->dev, + "DRAM mapping should not allocate more hops\n"); + rc = -EFAULT; + goto err; + } + } else if (curr_pte & PAGE_PRESENT_MASK) { + dev_err(hdev->dev, + "mapping already exists for virt_addr 0x%llx\n", + virt_addr); + + dev_dbg(hdev->dev, "hop0 pte: 0x%llx (0x%llx)\n", + hdev->asic_funcs->read_pte(hdev, hop0_pte_addr), + hop0_pte_addr); + dev_dbg(hdev->dev, "hop1 pte: 0x%llx (0x%llx)\n", + hdev->asic_funcs->read_pte(hdev, hop1_pte_addr), + hop1_pte_addr); + dev_dbg(hdev->dev, "hop2 pte: 0x%llx (0x%llx)\n", + hdev->asic_funcs->read_pte(hdev, hop2_pte_addr), + hop2_pte_addr); + dev_dbg(hdev->dev, "hop3 pte: 0x%llx (0x%llx)\n", + hdev->asic_funcs->read_pte(hdev, hop3_pte_addr), + hop3_pte_addr); + + if (!is_huge) + dev_dbg(hdev->dev, "hop4 pte: 0x%llx (0x%llx)\n", + hdev->asic_funcs->read_pte(hdev, + hop4_pte_addr), + hop4_pte_addr); + + rc = -EINVAL; + goto err; + } + + curr_pte = (phys_addr & PTE_PHYS_ADDR_MASK) | LAST_MASK + | PAGE_PRESENT_MASK; + + hdev->asic_funcs->write_pte(hdev, + is_huge ? hop3_pte_addr : hop4_pte_addr, + curr_pte); + + if (hop1_new) { + curr_pte = (hop1_addr & PTE_PHYS_ADDR_MASK) | + PAGE_PRESENT_MASK; + ctx->hdev->asic_funcs->write_pte(ctx->hdev, hop0_pte_addr, + curr_pte); + } + if (hop2_new) { + curr_pte = (hop2_addr & PTE_PHYS_ADDR_MASK) | + PAGE_PRESENT_MASK; + ctx->hdev->asic_funcs->write_pte(ctx->hdev, hop1_pte_addr, + curr_pte); + get_pte(ctx, hop1_addr); + } + if (hop3_new) { + curr_pte = (hop3_addr & PTE_PHYS_ADDR_MASK) | + PAGE_PRESENT_MASK; + ctx->hdev->asic_funcs->write_pte(ctx->hdev, hop2_pte_addr, + curr_pte); + get_pte(ctx, hop2_addr); + } + + if (!is_huge) { + if (hop4_new) { + curr_pte = (hop4_addr & PTE_PHYS_ADDR_MASK) | + PAGE_PRESENT_MASK; + ctx->hdev->asic_funcs->write_pte(ctx->hdev, + hop3_pte_addr, curr_pte); + get_pte(ctx, hop3_addr); + } + + get_pte(ctx, hop4_addr); + } else { + get_pte(ctx, hop3_addr); + } + + /* flush all writes from all cores to reach PCI */ + mb(); + + hdev->asic_funcs->read_pte(hdev, + is_huge ? hop3_pte_addr : hop4_pte_addr); + + return 0; + +err: + if (hop4_new) + free_hop(ctx, hop4_addr); + if (hop3_new) + free_hop(ctx, hop3_addr); + if (hop2_new) + free_hop(ctx, hop2_addr); + if (hop1_new) + free_hop(ctx, hop1_addr); + + return rc; +} + +/* + * hl_mmu_map - maps a virtual addr to physical addr + * + * @ctx: pointer to the context structure + * @virt_addr: virt addr to map from + * @phys_addr: phys addr to map to + * @page_size: physical page size + * + * This function does the following: + * - Check that the virt addr is not mapped + * - Allocate pgts as necessary in order to map the virt addr to the phys + * - Returns 0 on success, -EINVAL if addr is already mapped, or -ENOMEM. + * + * Because this function changes the page tables in the device and because it + * changes the MMU hash, it must be protected by a lock. + * However, because it maps only a single page, the lock should be implemented + * in a higher level in order to protect the entire mapping of the memory area + */ +int hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size) +{ + struct hl_device *hdev = ctx->hdev; + u64 real_virt_addr; + u32 real_page_size, npages; + int i, rc, mapped_cnt = 0; + + if (!hdev->mmu_enable) + return 0; + + /* + * The H/W handles mapping of 4KB/2MB page. Hence if the host page size + * is bigger, we break it to sub-pages and map them separately. + */ + if ((page_size % PAGE_SIZE_2MB) == 0) { + real_page_size = PAGE_SIZE_2MB; + } else if ((page_size % PAGE_SIZE_4KB) == 0) { + real_page_size = PAGE_SIZE_4KB; + } else { + dev_err(hdev->dev, + "page size of %u is not 4KB nor 2MB aligned, can't map\n", + page_size); + + return -EFAULT; + } + + npages = page_size / real_page_size; + real_virt_addr = virt_addr; + + for (i = 0 ; i < npages ; i++) { + rc = _hl_mmu_map(ctx, real_virt_addr, phys_addr, + real_page_size); + if (rc) + goto err; + + real_virt_addr += real_page_size; + mapped_cnt++; + } + + return 0; + +err: + real_virt_addr = virt_addr; + for (i = 0 ; i < mapped_cnt ; i++) { + if (_hl_mmu_unmap(ctx, real_virt_addr)) + dev_warn_ratelimited(hdev->dev, + "failed to unmap va: 0x%llx\n", real_virt_addr); + + real_virt_addr += real_page_size; + } + + return rc; +} + +/* + * hl_mmu_swap_out - marks all mapping of the given ctx as swapped out + * + * @ctx: pointer to the context structure + * + */ +void hl_mmu_swap_out(struct hl_ctx *ctx) +{ + +} + +/* + * hl_mmu_swap_in - marks all mapping of the given ctx as swapped in + * + * @ctx: pointer to the context structure + * + */ +void hl_mmu_swap_in(struct hl_ctx *ctx) +{ + +} diff --git a/drivers/misc/habanalabs/sysfs.c b/drivers/misc/habanalabs/sysfs.c new file mode 100644 index 000000000000..c900ab15cceb --- /dev/null +++ b/drivers/misc/habanalabs/sysfs.c @@ -0,0 +1,539 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#include <linux/pci.h> + +#define SET_CLK_PKT_TIMEOUT 1000000 /* 1s */ +#define SET_PWR_PKT_TIMEOUT 1000000 /* 1s */ + +long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + if (curr) + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_FREQUENCY_CURR_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + else + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_FREQUENCY_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.pll_index = __cpu_to_le32(pll_index); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SET_CLK_PKT_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, + "Failed to get frequency of PLL %d, error %d\n", + pll_index, rc); + result = rc; + } + + return result; +} + +void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq) +{ + struct armcp_packet pkt; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_FREQUENCY_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.pll_index = __cpu_to_le32(pll_index); + pkt.value = __cpu_to_le64(freq); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SET_CLK_PKT_TIMEOUT, NULL); + + if (rc) + dev_err(hdev->dev, + "Failed to set frequency to PLL %d, error %d\n", + pll_index, rc); +} + +u64 hl_get_max_power(struct hl_device *hdev) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_MAX_POWER_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SET_PWR_PKT_TIMEOUT, &result); + + if (rc) { + dev_err(hdev->dev, "Failed to get max power, error %d\n", rc); + result = rc; + } + + return result; +} + +void hl_set_max_power(struct hl_device *hdev, u64 value) +{ + struct armcp_packet pkt; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = __cpu_to_le32(ARMCP_PACKET_MAX_POWER_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.value = __cpu_to_le64(value); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SET_PWR_PKT_TIMEOUT, NULL); + + if (rc) + dev_err(hdev->dev, "Failed to set max power, error %d\n", rc); +} + +static ssize_t pm_mng_profile_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + return sprintf(buf, "%s\n", + (hdev->pm_mng_profile == PM_AUTO) ? "auto" : + (hdev->pm_mng_profile == PM_MANUAL) ? "manual" : + "unknown"); +} + +static ssize_t pm_mng_profile_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto out; + } + + mutex_lock(&hdev->fd_open_cnt_lock); + + if (atomic_read(&hdev->fd_open_cnt) > 0) { + dev_err(hdev->dev, + "Can't change PM profile while user process is opened on the device\n"); + count = -EPERM; + goto unlock_mutex; + } + + if (strncmp("auto", buf, strlen("auto")) == 0) { + /* Make sure we are in LOW PLL when changing modes */ + if (hdev->pm_mng_profile == PM_MANUAL) { + atomic_set(&hdev->curr_pll_profile, PLL_HIGH); + hl_device_set_frequency(hdev, PLL_LOW); + hdev->pm_mng_profile = PM_AUTO; + } + } else if (strncmp("manual", buf, strlen("manual")) == 0) { + /* Make sure we are in LOW PLL when changing modes */ + if (hdev->pm_mng_profile == PM_AUTO) { + flush_delayed_work(&hdev->work_freq); + hdev->pm_mng_profile = PM_MANUAL; + } + } else { + dev_err(hdev->dev, "value should be auto or manual\n"); + count = -EINVAL; + goto unlock_mutex; + } + +unlock_mutex: + mutex_unlock(&hdev->fd_open_cnt_lock); +out: + return count; +} + +static ssize_t high_pll_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + return sprintf(buf, "%u\n", hdev->high_pll); +} + +static ssize_t high_pll_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + int rc; + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto out; + } + + rc = kstrtoul(buf, 0, &value); + + if (rc) { + count = -EINVAL; + goto out; + } + + hdev->high_pll = value; + +out: + return count; +} + +static ssize_t uboot_ver_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", hdev->asic_prop.uboot_ver); +} + +static ssize_t armcp_kernel_ver_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s", hdev->asic_prop.armcp_info.kernel_version); +} + +static ssize_t armcp_ver_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", hdev->asic_prop.armcp_info.armcp_version); +} + +static ssize_t cpld_ver_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "0x%08x\n", + hdev->asic_prop.armcp_info.cpld_version); +} + +static ssize_t infineon_ver_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "0x%04x\n", + hdev->asic_prop.armcp_info.infineon_version); +} + +static ssize_t fuse_ver_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", hdev->asic_prop.armcp_info.fuse_version); +} + +static ssize_t thermal_ver_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s", hdev->asic_prop.armcp_info.thermal_version); +} + +static ssize_t preboot_btl_ver_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", hdev->asic_prop.preboot_ver); +} + +static ssize_t soft_reset_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + int rc; + + rc = kstrtoul(buf, 0, &value); + + if (rc) { + count = -EINVAL; + goto out; + } + + hl_device_reset(hdev, false, false); + +out: + return count; +} + +static ssize_t hard_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + int rc; + + rc = kstrtoul(buf, 0, &value); + + if (rc) { + count = -EINVAL; + goto out; + } + + hl_device_reset(hdev, true, false); + +out: + return count; +} + +static ssize_t device_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + char *str; + + switch (hdev->asic_type) { + case ASIC_GOYA: + str = "GOYA"; + break; + default: + dev_err(hdev->dev, "Unrecognized ASIC type %d\n", + hdev->asic_type); + return -EINVAL; + } + + return sprintf(buf, "%s\n", str); +} + +static ssize_t pci_addr_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + /* Use dummy, fixed address for simulator */ + if (!hdev->pdev) + return sprintf(buf, "0000:%02d:00.0\n", hdev->id); + + return sprintf(buf, "%04x:%02x:%02x.%x\n", + pci_domain_nr(hdev->pdev->bus), + hdev->pdev->bus->number, + PCI_SLOT(hdev->pdev->devfn), + PCI_FUNC(hdev->pdev->devfn)); +} + +static ssize_t status_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + char *str; + + if (atomic_read(&hdev->in_reset)) + str = "In reset"; + else if (hdev->disabled) + str = "Malfunction"; + else + str = "Operational"; + + return sprintf(buf, "%s\n", str); +} + +static ssize_t write_open_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", hdev->user_ctx ? 1 : 0); +} + +static ssize_t soft_reset_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", hdev->soft_reset_cnt); +} + +static ssize_t hard_reset_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", hdev->hard_reset_cnt); +} + +static ssize_t max_power_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long val; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + val = hl_get_max_power(hdev); + + return sprintf(buf, "%lu\n", val); +} + +static ssize_t max_power_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + unsigned long value; + int rc; + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto out; + } + + rc = kstrtoul(buf, 0, &value); + + if (rc) { + count = -EINVAL; + goto out; + } + + hdev->max_power = value; + hl_set_max_power(hdev, value); + +out: + return count; +} + +static ssize_t eeprom_read_handler(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, loff_t offset, + size_t max_size) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct hl_device *hdev = dev_get_drvdata(dev); + char *data; + int rc; + + if (!max_size) + return -EINVAL; + + data = kzalloc(max_size, GFP_KERNEL); + if (!data) + return -ENOMEM; + + rc = hdev->asic_funcs->get_eeprom_data(hdev, data, max_size); + if (rc) + goto out; + + memcpy(buf, data, max_size); + +out: + kfree(data); + + return max_size; +} + +static DEVICE_ATTR_RO(armcp_kernel_ver); +static DEVICE_ATTR_RO(armcp_ver); +static DEVICE_ATTR_RO(cpld_ver); +static DEVICE_ATTR_RO(device_type); +static DEVICE_ATTR_RO(fuse_ver); +static DEVICE_ATTR_WO(hard_reset); +static DEVICE_ATTR_RO(hard_reset_cnt); +static DEVICE_ATTR_RW(high_pll); +static DEVICE_ATTR_RO(infineon_ver); +static DEVICE_ATTR_RW(max_power); +static DEVICE_ATTR_RO(pci_addr); +static DEVICE_ATTR_RW(pm_mng_profile); +static DEVICE_ATTR_RO(preboot_btl_ver); +static DEVICE_ATTR_WO(soft_reset); +static DEVICE_ATTR_RO(soft_reset_cnt); +static DEVICE_ATTR_RO(status); +static DEVICE_ATTR_RO(thermal_ver); +static DEVICE_ATTR_RO(uboot_ver); +static DEVICE_ATTR_RO(write_open_cnt); + +static struct bin_attribute bin_attr_eeprom = { + .attr = {.name = "eeprom", .mode = (0444)}, + .size = PAGE_SIZE, + .read = eeprom_read_handler +}; + +static struct attribute *hl_dev_attrs[] = { + &dev_attr_armcp_kernel_ver.attr, + &dev_attr_armcp_ver.attr, + &dev_attr_cpld_ver.attr, + &dev_attr_device_type.attr, + &dev_attr_fuse_ver.attr, + &dev_attr_hard_reset.attr, + &dev_attr_hard_reset_cnt.attr, + &dev_attr_high_pll.attr, + &dev_attr_infineon_ver.attr, + &dev_attr_max_power.attr, + &dev_attr_pci_addr.attr, + &dev_attr_pm_mng_profile.attr, + &dev_attr_preboot_btl_ver.attr, + &dev_attr_soft_reset.attr, + &dev_attr_soft_reset_cnt.attr, + &dev_attr_status.attr, + &dev_attr_thermal_ver.attr, + &dev_attr_uboot_ver.attr, + &dev_attr_write_open_cnt.attr, + NULL, +}; + +static struct bin_attribute *hl_dev_bin_attrs[] = { + &bin_attr_eeprom, + NULL +}; + +static struct attribute_group hl_dev_attr_group = { + .attrs = hl_dev_attrs, + .bin_attrs = hl_dev_bin_attrs, +}; + +static struct attribute_group hl_dev_clks_attr_group; + +static const struct attribute_group *hl_dev_attr_groups[] = { + &hl_dev_attr_group, + &hl_dev_clks_attr_group, + NULL, +}; + +int hl_sysfs_init(struct hl_device *hdev) +{ + int rc; + + hdev->pm_mng_profile = PM_AUTO; + hdev->max_power = hdev->asic_prop.max_power_default; + + hdev->asic_funcs->add_device_attr(hdev, &hl_dev_clks_attr_group); + + rc = device_add_groups(hdev->dev, hl_dev_attr_groups); + if (rc) { + dev_err(hdev->dev, + "Failed to add groups to device, error %d\n", rc); + return rc; + } + + return 0; +} + +void hl_sysfs_fini(struct hl_device *hdev) +{ + device_remove_groups(hdev->dev, hl_dev_attr_groups); +} |