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path: root/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
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Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rvu.h')
-rw-r--r--drivers/net/ethernet/marvell/octeontx2/af/rvu.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 4a4b0ad2454a..e2c54d0e1102 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -11,6 +11,8 @@
#ifndef RVU_H
#define RVU_H
+#include "rvu_struct.h"
+
/* PCI device IDs */
#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
@@ -21,11 +23,46 @@
#define NAME_SIZE 32
+struct rvu_block {
+ bool implemented;
+};
+
+struct rvu_hwinfo {
+ struct rvu_block block[BLK_COUNT]; /* Block info */
+};
+
struct rvu {
void __iomem *afreg_base;
void __iomem *pfreg_base;
struct pci_dev *pdev;
struct device *dev;
+ struct rvu_hwinfo *hw;
};
+static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
+{
+ writeq(val, rvu->afreg_base + ((block << 28) | offset));
+}
+
+static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
+{
+ return readq(rvu->afreg_base + ((block << 28) | offset));
+}
+
+static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
+{
+ writeq(val, rvu->pfreg_base + offset);
+}
+
+static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
+{
+ return readq(rvu->pfreg_base + offset);
+}
+
+/* Function Prototypes
+ * RVU
+ */
+
+int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
+
#endif /* RVU_H */